diff options
71 files changed, 3223 insertions, 3198 deletions
diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini index 96720c6a8..3b349d2ff 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini @@ -452,7 +452,7 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=X86LocalApic -clock=500 +clock=8000 int_latency=1000 pio_addr=2305843009213693952 pio_latency=100000 @@ -503,6 +503,7 @@ type=CoherentBus block_size=64 clock=500 header_cycles=1 +system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side @@ -535,6 +536,7 @@ type=CoherentBus block_size=64 clock=1000 header_cycles=1 +system=system use_default_range=false width=8 master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave @@ -542,25 +544,28 @@ slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_m [system.physmem] type=SimpleDRAM +activation_limit=4 addr_mapping=openmap banks_per_rank=8 +channels=1 clock=1000 conf_table_reported=false in_addr_map=true -lines_per_rowbuffer=64 -mem_sched_policy=fcfs +lines_per_rowbuffer=32 +mem_sched_policy=frfcfs null=false page_policy=open range=0:134217727 ranks_per_channel=2 read_buffer_size=32 -tBURST=4000 -tCL=14000 -tRCD=14000 +tBURST=5000 +tCL=13750 +tRCD=13750 tREFI=7800000 tRFC=300000 -tRP=14000 -tWTR=1000 +tRP=13750 +tWTR=7500 +tXAW=40000 write_buffer_size=32 write_thresh_perc=70 zero=false diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simerr b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simerr index f5691fd64..e45cd058f 100755 --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simerr +++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simerr @@ -1,3 +1,2 @@ warn: Sockets disabled, not accepting gdb connections -warn: instruction 'fldcw_Mw' unimplemented hack: be nice to actually delete the event here diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout index a29e79bee..0f028aec2 100755 --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout @@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing/si gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 16:30:44 -gem5 started Jan 23 2013 18:48:34 +gem5 compiled Mar 11 2013 13:21:48 +gem5 started Mar 11 2013 13:30:24 gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -42,4 +42,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 607445544000 because target called exit() +Exiting @ tick 607412415000 because target called exit() diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt index 6ca2fc4f2..a8d281c59 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt @@ -1,61 +1,61 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.607292 # Number of seconds simulated -sim_ticks 607292111000 # Number of ticks simulated -final_tick 607292111000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.607412 # Number of seconds simulated +sim_ticks 607412415000 # Number of ticks simulated +final_tick 607412415000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 88731 # Simulator instruction rate (inst/s) -host_op_rate 163492 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 61232046 # Simulator tick rate (ticks/s) -host_mem_usage 248756 # Number of bytes of host memory used -host_seconds 9917.88 # Real time elapsed on the host +host_inst_rate 59004 # Simulator instruction rate (inst/s) +host_op_rate 108719 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 40726098 # Simulator tick rate (ticks/s) +host_mem_usage 295644 # Number of bytes of host memory used +host_seconds 14914.57 # Real time elapsed on the host sim_insts 880025277 # Number of instructions simulated -sim_ops 1621493926 # Number of ops (including micro ops) simulated +sim_ops 1621493927 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 57664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1693184 # Number of bytes read from this memory -system.physmem.bytes_read::total 1750848 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1693248 # Number of bytes read from this memory +system.physmem.bytes_read::total 1750912 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 57664 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 57664 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 162176 # Number of bytes written to this memory system.physmem.bytes_written::total 162176 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 901 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 26456 # Number of read requests responded to by this memory -system.physmem.num_reads::total 27357 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 26457 # Number of read requests responded to by this memory +system.physmem.num_reads::total 27358 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 2534 # Number of write requests responded to by this memory system.physmem.num_writes::total 2534 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 94953 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2788088 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2883041 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 94953 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 94953 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 267048 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 267048 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 267048 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 94953 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2788088 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3150089 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 27359 # Total number of read requests seen +system.physmem.bw_read::cpu.inst 94934 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2787641 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2882575 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 94934 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 94934 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 266995 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 266995 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 266995 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 94934 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2787641 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3149570 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 27360 # Total number of read requests seen system.physmem.writeReqs 2534 # Total number of write requests seen -system.physmem.cpureqs 29893 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 1750848 # Total number of bytes read from memory +system.physmem.cpureqs 29894 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 1750912 # Total number of bytes read from memory system.physmem.bytesWritten 162176 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 1750848 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 1750912 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 162176 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 1742 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 1741 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 1719 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 1712 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 1711 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 1642 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 1655 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 1657 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 1654 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 1714 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 1713 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 1701 # Track reads on a per bank basis system.physmem.perBankRdReqs::8 1712 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1708 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 1711 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 1718 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 1730 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 1739 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 1738 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 1728 # Track reads on a per bank basis system.physmem.perBankRdReqs::14 1750 # Track reads on a per bank basis system.physmem.perBankRdReqs::15 1735 # Track reads on a per bank basis @@ -77,14 +77,14 @@ system.physmem.perBankWrReqs::14 164 # Tr system.physmem.perBankWrReqs::15 159 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 607292095000 # Total gap between requests +system.physmem.totGap 607412402000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 27359 # Categorize read packet sizes +system.physmem.readPktSize::6 27360 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes @@ -92,9 +92,9 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 2534 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 26892 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 344 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 100 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 26889 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 351 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 97 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 21 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -156,14 +156,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 90421500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 895535250 # Sum of mem lat for all requests -system.physmem.totBusLat 136795000 # Total cycles spent in databus access -system.physmem.totBankLat 668318750 # Total cycles spent in bank access -system.physmem.avgQLat 3305.00 # Average queueing delay per request -system.physmem.avgBankLat 24427.75 # Average bank access latency per request +system.physmem.totQLat 88987000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 893982000 # Sum of mem lat for all requests +system.physmem.totBusLat 136800000 # Total cycles spent in databus access +system.physmem.totBankLat 668195000 # Total cycles spent in bank access +system.physmem.avgQLat 3252.45 # Average queueing delay per request +system.physmem.avgBankLat 24422.33 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 32732.75 # Average memory access latency +system.physmem.avgMemAccLat 32674.78 # Average memory access latency system.physmem.avgRdBW 2.88 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.27 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 2.88 # Average consumed read bandwidth in MB/s @@ -171,144 +171,144 @@ system.physmem.avgConsumedWrBW 0.27 # Av system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 6.24 # Average write queue length over time -system.physmem.readRowHits 16426 # Number of row buffer hits during reads -system.physmem.writeRowHits 1032 # Number of row buffer hits during writes +system.physmem.avgWrQLen 13.09 # Average write queue length over time +system.physmem.readRowHits 16427 # Number of row buffer hits during reads +system.physmem.writeRowHits 1022 # Number of row buffer hits during writes system.physmem.readRowHitRate 60.04 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 40.73 # Row buffer hit rate for writes -system.physmem.avgGap 20315528.55 # Average gap between requests -system.cpu.branchPred.lookups 158482804 # Number of BP lookups -system.cpu.branchPred.condPredicted 158482804 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 26384558 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 84639114 # Number of BTB lookups -system.cpu.branchPred.BTBHits 84422216 # Number of BTB hits +system.physmem.writeRowHitRate 40.33 # Row buffer hit rate for writes +system.physmem.avgGap 20318873.42 # Average gap between requests +system.cpu.branchPred.lookups 158382296 # Number of BP lookups +system.cpu.branchPred.condPredicted 158382296 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 26387252 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 83381183 # Number of BTB lookups +system.cpu.branchPred.BTBHits 83179505 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.743738 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 99.758125 # BTB Hit Percentage system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 1214584223 # number of cpu cycles simulated +system.cpu.numCycles 1214824831 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 179034165 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1457747721 # Number of instructions fetch has processed -system.cpu.fetch.Branches 158482804 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 84422216 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 399024262 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 88084887 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 574618713 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 47 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 378 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 188004827 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 11985682 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1214221440 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.059311 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.252911 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 179163349 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1457867613 # Number of instructions fetch has processed +system.cpu.fetch.Branches 158382296 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 83179505 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 399005833 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 88132062 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 574704368 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 43 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 361 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 186835049 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 10712979 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1214462855 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.059159 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.252870 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 822415344 67.73% 67.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 26978129 2.22% 69.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 13144140 1.08% 71.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 20617690 1.70% 72.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 26634807 2.19% 74.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 18232650 1.50% 76.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 31447933 2.59% 79.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 39056021 3.22% 82.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 215694726 17.76% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 822674810 67.74% 67.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 26926688 2.22% 69.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 13135389 1.08% 71.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 20566511 1.69% 72.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 26637257 2.19% 74.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 18247973 1.50% 76.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 31504454 2.59% 79.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 39098170 3.22% 82.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 215671603 17.76% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1214221440 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.130483 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.200203 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 288175297 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 497913615 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 274106209 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 92482444 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 61543875 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2343534245 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 61543875 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 336850046 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 124204658 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 2567 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 303948666 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 387671628 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2247678746 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 360 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 242705531 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 120202926 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2618040036 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5722358621 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 5722353197 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 5424 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1886895258 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 731144778 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 87 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 87 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 731406444 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 531670409 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 219217246 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 342048419 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 144614487 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1993488562 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 286 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1783952231 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 274040 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 371594187 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 759078017 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 237 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1214221440 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.469215 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.421905 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 1214462855 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.130375 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.200064 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 288324734 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 497934423 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 274040429 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 92574368 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 61588901 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2343698812 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 61588901 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 336957337 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 124218348 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 2659 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 304046563 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 387649047 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2248109589 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 354 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 242721119 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 120169480 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2618670353 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5724257672 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 5724251768 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 5904 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1886895260 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 731775093 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 91 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 91 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 731348064 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 531825278 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 219280996 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 342077982 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 144753457 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1993869707 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 294 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1783892793 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 265772 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 371981386 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 760150327 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 245 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1214462855 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.468874 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.421634 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 360233765 29.67% 29.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 364161190 29.99% 59.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 234288875 19.30% 78.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 141409873 11.65% 90.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 60623190 4.99% 95.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 39782570 3.28% 98.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 11078669 0.91% 99.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 2040416 0.17% 99.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 602892 0.05% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 360357006 29.67% 29.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 364326915 30.00% 59.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 234272776 19.29% 78.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 141367539 11.64% 90.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 60718828 5.00% 95.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 39723200 3.27% 98.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 11050512 0.91% 99.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 2045307 0.17% 99.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 600772 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1214221440 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1214462855 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 459684 15.86% 15.86% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 15.86% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 15.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 15.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 15.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 15.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 15.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 15.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 15.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 15.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 15.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 15.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 15.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 15.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 15.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 15.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 15.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 15.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 15.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 15.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 15.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 15.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 15.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 15.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 15.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 15.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 15.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 15.86% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2241246 77.33% 93.20% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 197213 6.80% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 450048 15.52% 15.52% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 15.52% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 15.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 15.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 15.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 15.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 15.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 15.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 15.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 15.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 15.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 15.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 15.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 15.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 15.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 15.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 15.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 15.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 15.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 15.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 15.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 15.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 15.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 15.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 15.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 15.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 15.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 15.52% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2249912 77.59% 93.11% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 199796 6.89% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 46812327 2.62% 2.62% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1065713813 59.74% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 46812279 2.62% 2.62% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1065698440 59.74% 62.36% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 62.36% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.36% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.36% # Type of FU issued @@ -337,282 +337,283 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.36% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.36% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.36% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 478893732 26.84% 89.21% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 192532359 10.79% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 478836274 26.84% 89.21% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 192545800 10.79% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1783952231 # Type of FU issued -system.cpu.iq.rate 1.468776 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2898143 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001625 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4785297542 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2365259636 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1724635094 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 543 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1776 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 123 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1740037802 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 245 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 210029946 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1783892793 # Type of FU issued +system.cpu.iq.rate 1.468436 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2899756 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001626 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4785413585 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2366027132 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1724688067 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 384 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1824 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 99 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1739980085 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 185 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 209981192 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 112628288 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 39424 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 182684 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 31031188 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 112783156 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 38868 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 181899 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 31094938 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2402 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 58 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2165 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 66 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 61543875 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1219448 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 109755 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1993488848 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 63065998 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 531670409 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 219217246 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 81 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 52970 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 2883 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 182684 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 2045175 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 24468993 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 26514168 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1766143547 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 474612951 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 17808684 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 61588901 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1215520 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 110006 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1993870001 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 63340037 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 531825278 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 219280996 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 84 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 53594 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 2844 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 181899 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 2045614 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 24471458 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 26517072 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1766151616 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 474571020 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 17741177 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 666319153 # number of memory reference insts executed -system.cpu.iew.exec_branches 110355146 # Number of branches executed -system.cpu.iew.exec_stores 191706202 # Number of stores executed -system.cpu.iew.exec_rate 1.454114 # Inst execution rate -system.cpu.iew.wb_sent 1725748007 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1724635217 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1267063011 # num instructions producing a value -system.cpu.iew.wb_consumers 1828799692 # num instructions consuming a value +system.cpu.iew.exec_refs 666290065 # number of memory reference insts executed +system.cpu.iew.exec_branches 110357109 # Number of branches executed +system.cpu.iew.exec_stores 191719045 # Number of stores executed +system.cpu.iew.exec_rate 1.453832 # Inst execution rate +system.cpu.iew.wb_sent 1725806864 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1724688166 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1267103836 # num instructions producing a value +system.cpu.iew.wb_consumers 1828916065 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.419939 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.692839 # average fanout of values written-back +system.cpu.iew.wb_rate 1.419701 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.692817 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 371996186 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 372377336 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 49 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 26384610 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1152677565 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.406719 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.830300 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 26387302 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1152873954 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.406480 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.829955 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 418027879 36.27% 36.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 415124601 36.01% 72.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 86915055 7.54% 79.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 122122398 10.59% 90.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 24176868 2.10% 92.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 25399940 2.20% 94.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 16385768 1.42% 96.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 12050207 1.05% 97.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 32474849 2.82% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 418181253 36.27% 36.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 415089887 36.00% 72.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 86977349 7.54% 79.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 122167535 10.60% 90.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 24171647 2.10% 92.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 25387316 2.20% 94.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 16411129 1.42% 96.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 12045909 1.04% 97.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 32441929 2.81% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1152677565 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1152873954 # Number of insts commited each cycle system.cpu.commit.committedInsts 880025277 # Number of instructions committed -system.cpu.commit.committedOps 1621493926 # Number of ops (including micro ops) committed +system.cpu.commit.committedOps 1621493927 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 607228179 # Number of memory references committed -system.cpu.commit.loads 419042121 # Number of loads committed +system.cpu.commit.refs 607228180 # Number of memory references committed +system.cpu.commit.loads 419042122 # Number of loads committed system.cpu.commit.membars 0 # Number of memory barriers committed system.cpu.commit.branches 107161574 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1621354437 # Number of committed integer instructions. +system.cpu.commit.int_insts 1621354439 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 32474849 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 32441929 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3113692828 # The number of ROB reads -system.cpu.rob.rob_writes 4048559892 # The number of ROB writes -system.cpu.timesIdled 59027 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 362783 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3114303288 # The number of ROB reads +system.cpu.rob.rob_writes 4049366814 # The number of ROB writes +system.cpu.timesIdled 58967 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 361976 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 880025277 # Number of Instructions Simulated -system.cpu.committedOps 1621493926 # Number of Ops (including micro ops) Simulated +system.cpu.committedOps 1621493927 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 880025277 # Number of Instructions Simulated -system.cpu.cpi 1.380170 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.380170 # CPI: Total CPI of All Threads -system.cpu.ipc 0.724549 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.724549 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3542852942 # number of integer regfile reads -system.cpu.int_regfile_writes 1974486988 # number of integer regfile writes -system.cpu.fp_regfile_reads 123 # number of floating regfile reads -system.cpu.misc_regfile_reads 910772207 # number of misc regfile reads +system.cpu.cpi 1.380443 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.380443 # CPI: Total CPI of All Threads +system.cpu.ipc 0.724405 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.724405 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3542727713 # number of integer regfile reads +system.cpu.int_regfile_writes 1974483700 # number of integer regfile writes +system.cpu.fp_regfile_reads 99 # number of floating regfile reads +system.cpu.misc_regfile_reads 910779890 # number of misc regfile reads +system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 25 # number of replacements -system.cpu.icache.tagsinuse 816.669933 # Cycle average of tags in use -system.cpu.icache.total_refs 188003443 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 814.738585 # Cycle average of tags in use +system.cpu.icache.total_refs 186833677 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 918 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 204796.778867 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 203522.523965 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 816.669933 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.398765 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.398765 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 188003447 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 188003447 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 188003447 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 188003447 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 188003447 # number of overall hits -system.cpu.icache.overall_hits::total 188003447 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1380 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1380 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1380 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1380 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1380 # number of overall misses -system.cpu.icache.overall_misses::total 1380 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 65047500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 65047500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 65047500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 65047500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 65047500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 65047500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 188004827 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 188004827 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 188004827 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 188004827 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 188004827 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 188004827 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 814.738585 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.397822 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.397822 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 186833682 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 186833682 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 186833682 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 186833682 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 186833682 # number of overall hits +system.cpu.icache.overall_hits::total 186833682 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1367 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1367 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1367 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1367 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1367 # number of overall misses +system.cpu.icache.overall_misses::total 1367 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 65166500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 65166500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 65166500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 65166500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 65166500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 65166500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 186835049 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 186835049 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 186835049 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 186835049 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 186835049 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 186835049 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000007 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000007 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000007 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000007 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000007 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000007 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 47135.869565 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 47135.869565 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 47135.869565 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 47135.869565 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 47135.869565 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 47135.869565 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 171 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 47671.177762 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 47671.177762 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 47671.177762 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 47671.177762 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 47671.177762 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 47671.177762 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 146 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 34.200000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 29.200000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 455 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 455 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 455 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 455 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 455 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 455 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 925 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 925 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 925 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 925 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 925 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 925 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 47382000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 47382000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 47382000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 47382000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 47382000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 47382000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 444 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 444 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 444 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 444 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 444 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 444 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 923 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 923 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 923 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 923 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 923 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 923 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 47626500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 47626500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 47626500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 47626500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 47626500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 47626500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000005 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000005 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000005 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51223.783784 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51223.783784 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51223.783784 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 51223.783784 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51223.783784 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 51223.783784 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51599.674973 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51599.674973 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51599.674973 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 51599.674973 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51599.674973 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 51599.674973 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 2556 # number of replacements -system.cpu.l2cache.tagsinuse 22259.325739 # Cycle average of tags in use -system.cpu.l2cache.total_refs 531319 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 22259.918849 # Cycle average of tags in use +system.cpu.l2cache.total_refs 531250 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 24190 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 21.964407 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 21.961554 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 20781.078407 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 799.480926 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 678.766407 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.634188 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.024398 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.020714 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.679301 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 20782.874819 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 797.549554 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 679.494476 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.634243 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.024339 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.020737 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.679319 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 17 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 199250 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 199267 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 429018 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 429018 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 7 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 7 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 224476 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 224476 # number of ReadExReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 199226 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 199243 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 428982 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 428982 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 5 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 5 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 224442 # 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miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.981481 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.058772 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.060649 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51352.386238 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72403.968428 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68931.343830 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 51832.853816 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 51832.853816 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 51352.386238 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55379.034697 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 55246.427135 # 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average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55301.787671 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 55180.939327 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51632.075472 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55301.787671 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 55180.939327 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -624,141 +625,141 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks::writebacks 2534 # number of writebacks system.cpu.l2cache.writebacks::total 2534 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 901 # 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average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42796.890091 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38937.273030 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42928.325384 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42796.890091 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.058781 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.060659 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39217.792453 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59918.479386 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56503.112434 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39306.343669 # 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number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 457736 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 457736 # number of overall misses -system.cpu.dcache.overall_misses::total 457736 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3022618500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3022618500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4119768500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4119768500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7142387000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7142387000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7142387000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7142387000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 264579649 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 264579649 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_hits::cpu.data 264375496 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 264375496 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 187939628 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 187939628 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 452315124 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 452315124 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 452315124 # number of overall hits +system.cpu.dcache.overall_hits::total 452315124 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 211166 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 211166 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 246430 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 246430 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 457596 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 457596 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 457596 # number of overall misses +system.cpu.dcache.overall_misses::total 457596 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3021463500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3021463500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4117356500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4117356500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7138820000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7138820000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7138820000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7138820000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 264586662 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 264586662 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 188186058 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 188186058 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 452765707 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 452765707 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 452765707 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 452765707 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000799 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000799 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 452772720 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 452772720 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 452772720 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 452772720 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000798 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000798 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001310 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.001310 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.001011 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.001011 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.001011 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.001011 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14306.153890 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14306.153890 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16716.108417 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 16716.108417 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 15603.725728 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 15603.725728 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 15603.725728 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 15603.725728 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 365 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14308.475323 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14308.475323 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16708.016475 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 16708.016475 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 15600.704552 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 15600.704552 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 15600.704552 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 15600.704552 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 398 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 40 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 38 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.125000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.473684 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 429018 # number of writebacks -system.cpu.dcache.writebacks::total 429018 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7464 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 7464 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 81 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 81 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7545 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7545 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7545 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7545 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 203817 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 203817 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 246374 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 246374 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 450191 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 450191 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 450191 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 450191 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2528414500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2528414500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3626222000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3626222000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6154636500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6154636500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6154636500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6154636500 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 428982 # number of writebacks +system.cpu.dcache.writebacks::total 428982 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7377 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 7377 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 87 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 87 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 7464 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7464 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7464 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7464 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 203789 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 203789 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 246343 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 246343 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 450132 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 450132 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 450132 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 450132 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2528052500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2528052500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3623861000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3623861000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6151913500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6151913500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6151913500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6151913500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000770 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000770 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001309 # mshr miss rate for WriteReq accesses @@ -767,14 +768,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000994 system.cpu.dcache.demand_mshr_miss_rate::total 0.000994 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000994 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000994 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12405.317025 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12405.317025 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14718.363139 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14718.363139 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13671.167349 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13671.167349 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13671.167349 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13671.167349 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12405.245131 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12405.245131 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14710.631112 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14710.631112 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13666.909929 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13666.909929 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13666.909929 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13666.909929 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini index 8a8a24651..417d7cc9b 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini @@ -77,7 +77,7 @@ port=system.membus.slave[4] [system.cpu.interrupts] type=X86LocalApic -clock=500 +clock=8000 int_latency=1000 pio_addr=2305843009213693952 pio_latency=100000 @@ -128,6 +128,7 @@ type=CoherentBus block_size=64 clock=1000 header_cycles=1 +system=system use_default_range=false width=8 master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simerr b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simerr index f5691fd64..e45cd058f 100755 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simerr +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simerr @@ -1,3 +1,2 @@ warn: Sockets disabled, not accepting gdb connections -warn: instruction 'fldcw_Mw' unimplemented hack: be nice to actually delete the event here diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout index 6792b9773..34476ffed 100755 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout @@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-atomi gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 16:30:44 -gem5 started Jan 23 2013 18:52:14 +gem5 compiled Mar 11 2013 13:21:48 +gem5 started Mar 11 2013 13:30:35 gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second @@ -41,4 +41,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 963992671500 because target called exit() +Exiting @ tick 963992672000 because target called exit() diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt index a1cb93ee9..da1003d0f 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt @@ -1,59 +1,59 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.963993 # Number of seconds simulated -sim_ticks 963992671500 # Number of ticks simulated -final_tick 963992671500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 963992672000 # Number of ticks simulated +final_tick 963992672000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 911190 # Simulator instruction rate (inst/s) -host_op_rate 1678916 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 998130396 # Simulator tick rate (ticks/s) -host_mem_usage 284224 # Number of bytes of host memory used -host_seconds 965.80 # Real time elapsed on the host +host_inst_rate 595979 # Simulator instruction rate (inst/s) +host_op_rate 1098124 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 652844357 # Simulator tick rate (ticks/s) +host_mem_usage 283988 # Number of bytes of host memory used +host_seconds 1476.60 # Real time elapsed on the host sim_insts 880025278 # Number of instructions simulated -sim_ops 1621493927 # Number of ops (including micro ops) simulated +sim_ops 1621493928 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 9492133560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1842452909 # Number of bytes read from this memory -system.physmem.bytes_read::total 11334586469 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1842452911 # Number of bytes read from this memory +system.physmem.bytes_read::total 11334586471 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 9492133560 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 9492133560 # Number of instructions bytes read from this memory system.physmem.bytes_written::cpu.data 864451002 # Number of bytes written to this memory system.physmem.bytes_written::total 864451002 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 1186516695 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 419042121 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1605558816 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 419042122 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1605558817 # Number of read requests responded to by this memory system.physmem.num_writes::cpu.data 188186058 # Number of write requests responded to by this memory system.physmem.num_writes::total 188186058 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 9846686433 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1911272734 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 11757959167 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 9846686433 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 9846686433 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 896740222 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 896740222 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 9846686433 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2808012956 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 12654699389 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 9846686428 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1911272735 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 11757959163 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 9846686428 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 9846686428 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 896740221 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 896740221 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 9846686428 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2808012957 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 12654699384 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 1927985344 # number of cpu cycles simulated +system.cpu.numCycles 1927985345 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 880025278 # Number of instructions committed -system.cpu.committedOps 1621493927 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1621354438 # Number of integer alu accesses +system.cpu.committedOps 1621493928 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 1621354440 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured system.cpu.num_conditional_control_insts 99478856 # number of instructions that are conditional controls -system.cpu.num_int_insts 1621354438 # number of integer instructions +system.cpu.num_int_insts 1621354440 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 4204103512 # number of times the integer registers were read -system.cpu.num_int_register_writes 1886895258 # number of times the integer registers were written +system.cpu.num_int_register_reads 4204103517 # number of times the integer registers were read +system.cpu.num_int_register_writes 1886895260 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 607228179 # number of memory refs -system.cpu.num_load_insts 419042121 # Number of load instructions +system.cpu.num_mem_refs 607228180 # number of memory refs +system.cpu.num_load_insts 419042122 # Number of load instructions system.cpu.num_store_insts 188186058 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1927985344 # Number of busy cycles +system.cpu.num_busy_cycles 1927985345 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini index 5736b9341..cec3db95e 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini @@ -117,7 +117,7 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=X86LocalApic -clock=500 +clock=8000 int_latency=1000 pio_addr=2305843009213693952 pio_latency=100000 @@ -168,6 +168,7 @@ type=CoherentBus block_size=64 clock=500 header_cycles=1 +system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side @@ -200,6 +201,7 @@ type=CoherentBus block_size=64 clock=1000 header_cycles=1 +system=system use_default_range=false width=8 master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simerr b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simerr index f5691fd64..e45cd058f 100755 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simerr +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simerr @@ -1,3 +1,2 @@ warn: Sockets disabled, not accepting gdb connections -warn: instruction 'fldcw_Mw' unimplemented hack: be nice to actually delete the event here diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout index 5f5879b0d..01addadef 100755 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout @@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timin gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 16:30:44 -gem5 started Jan 23 2013 18:22:44 +gem5 compiled Mar 11 2013 13:21:48 +gem5 started Mar 11 2013 13:30:24 gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second @@ -41,4 +41,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 1800193397000 because target called exit() +Exiting @ tick 1800193398000 because target called exit() diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt index 088aad8da..2279afb65 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 1.800193 # Number of seconds simulated -sim_ticks 1800193397000 # Number of ticks simulated -final_tick 1800193397000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 1800193398000 # Number of ticks simulated +final_tick 1800193398000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 575805 # Simulator instruction rate (inst/s) -host_op_rate 1060952 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1177876462 # Simulator tick rate (ticks/s) -host_mem_usage 292800 # Number of bytes of host memory used -host_seconds 1528.34 # Real time elapsed on the host +host_inst_rate 392596 # Simulator instruction rate (inst/s) +host_op_rate 723379 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 803099848 # Simulator tick rate (ticks/s) +host_mem_usage 292568 # Number of bytes of host memory used +host_seconds 2241.56 # Real time elapsed on the host sim_insts 880025278 # Number of instructions simulated -sim_ops 1621493927 # Number of ops (including micro ops) simulated +sim_ops 1621493928 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 46208 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 1682368 # Number of bytes read from this memory system.physmem.bytes_read::total 1728576 # Number of bytes read from this memory @@ -35,35 +35,35 @@ system.physmem.bw_total::cpu.inst 25668 # To system.physmem.bw_total::cpu.data 934548 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 1049487 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 3600386794 # number of cpu cycles simulated +system.cpu.numCycles 3600386796 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 880025278 # Number of instructions committed -system.cpu.committedOps 1621493927 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1621354438 # Number of integer alu accesses +system.cpu.committedOps 1621493928 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 1621354440 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured system.cpu.num_conditional_control_insts 99478856 # number of instructions that are conditional controls -system.cpu.num_int_insts 1621354438 # number of integer instructions +system.cpu.num_int_insts 1621354440 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 4204103512 # number of times the integer registers were read -system.cpu.num_int_register_writes 1886895258 # number of times the integer registers were written +system.cpu.num_int_register_reads 4204103517 # number of times the integer registers were read +system.cpu.num_int_register_writes 1886895260 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 607228179 # number of memory refs -system.cpu.num_load_insts 419042121 # Number of load instructions +system.cpu.num_mem_refs 607228180 # number of memory refs +system.cpu.num_load_insts 419042122 # Number of load instructions system.cpu.num_store_insts 188186058 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 3600386794 # Number of busy cycles +system.cpu.num_busy_cycles 3600386796 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 4 # number of replacements -system.cpu.icache.tagsinuse 660.197306 # Cycle average of tags in use +system.cpu.icache.tagsinuse 660.197305 # Cycle average of tags in use system.cpu.icache.total_refs 1186515974 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 722 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 1643373.925208 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 660.197306 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 660.197305 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.322362 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.322362 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1186515974 # number of ReadReq hits @@ -136,12 +136,12 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53002.770083 system.cpu.icache.overall_avg_mshr_miss_latency::total 53002.770083 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 2532 # number of replacements -system.cpu.l2cache.tagsinuse 22211.029327 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 22211.029315 # Cycle average of tags in use system.cpu.l2cache.total_refs 519268 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 23832 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 21.788687 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21021.301355 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 21021.301343 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.inst 643.199216 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.data 546.528756 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.641519 # Average percentage of cache occupancy @@ -271,22 +271,22 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40034.351581 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40033.507349 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 437952 # number of replacements -system.cpu.dcache.tagsinuse 4094.905742 # Cycle average of tags in use -system.cpu.dcache.total_refs 606786131 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4094.905740 # Cycle average of tags in use +system.cpu.dcache.total_refs 606786132 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 442048 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 1372.670233 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 771787000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.905742 # Average occupied blocks per requestor +system.cpu.dcache.avg_refs 1372.670235 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 771788000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4094.905740 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999733 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999733 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 418844795 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 418844795 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 418844796 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 418844796 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 187941336 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 187941336 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 606786131 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 606786131 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 606786131 # number of overall hits -system.cpu.dcache.overall_hits::total 606786131 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 606786132 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 606786132 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 606786132 # number of overall hits +system.cpu.dcache.overall_hits::total 606786132 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 197326 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 197326 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 244722 # number of WriteReq misses @@ -303,14 +303,14 @@ system.cpu.dcache.demand_miss_latency::cpu.data 6851581000 system.cpu.dcache.demand_miss_latency::total 6851581000 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 6851581000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 6851581000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 419042121 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 419042121 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 419042122 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 419042122 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 188186058 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 188186058 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 607228179 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 607228179 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 607228179 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 607228179 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 607228180 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 607228180 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 607228180 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 607228180 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000471 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000471 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001300 # miss rate for WriteReq accesses diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini index c87784f11..4e8c5ef6c 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini @@ -452,7 +452,7 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=X86LocalApic -clock=500 +clock=8000 int_latency=1000 pio_addr=2305843009213693952 pio_latency=100000 @@ -503,6 +503,7 @@ type=CoherentBus block_size=64 clock=500 header_cycles=1 +system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side @@ -535,6 +536,7 @@ type=CoherentBus block_size=64 clock=1000 header_cycles=1 +system=system use_default_range=false width=8 master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave @@ -542,25 +544,28 @@ slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_m [system.physmem] type=SimpleDRAM +activation_limit=4 addr_mapping=openmap banks_per_rank=8 +channels=1 clock=1000 conf_table_reported=false in_addr_map=true -lines_per_rowbuffer=64 -mem_sched_policy=fcfs +lines_per_rowbuffer=32 +mem_sched_policy=frfcfs null=false page_policy=open range=0:268435455 ranks_per_channel=2 read_buffer_size=32 -tBURST=4000 -tCL=14000 -tRCD=14000 +tBURST=5000 +tCL=13750 +tRCD=13750 tREFI=7800000 tRFC=300000 -tRP=14000 -tWTR=1000 +tRP=13750 +tWTR=7500 +tXAW=40000 write_buffer_size=32 write_thresh_perc=70 zero=false diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simerr b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simerr index f5691fd64..e45cd058f 100755 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simerr +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simerr @@ -1,3 +1,2 @@ warn: Sockets disabled, not accepting gdb connections -warn: instruction 'fldcw_Mw' unimplemented hack: be nice to actually delete the event here diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout index 3f08953e4..57123b5c9 100755 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout @@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing/sim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 16:30:44 -gem5 started Jan 23 2013 16:36:34 +gem5 compiled Mar 11 2013 13:21:48 +gem5 started Mar 11 2013 13:30:24 gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -25,4 +25,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 65982862500 because target called exit() +Exiting @ tick 66030660000 because target called exit() diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index c14a5bb89..e747d6c9e 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -1,101 +1,101 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.066022 # Number of seconds simulated -sim_ticks 66021796500 # Number of ticks simulated -final_tick 66021796500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.066031 # Number of seconds simulated +sim_ticks 66030660000 # Number of ticks simulated +final_tick 66030660000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 92381 # Simulator instruction rate (inst/s) -host_op_rate 162668 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 38604948 # Simulator tick rate (ticks/s) -host_mem_usage 384888 # Number of bytes of host memory used -host_seconds 1710.19 # Real time elapsed on the host +host_inst_rate 55728 # Simulator instruction rate (inst/s) +host_op_rate 98128 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 23291229 # Simulator tick rate (ticks/s) +host_mem_usage 430752 # Number of bytes of host memory used +host_seconds 2835.00 # Real time elapsed on the host sim_insts 157988547 # Number of instructions simulated -sim_ops 278192463 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 64832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1881664 # Number of bytes read from this memory -system.physmem.bytes_read::total 1946496 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 64832 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 64832 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9856 # Number of bytes written to this memory -system.physmem.bytes_written::total 9856 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1013 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 29401 # Number of read requests responded to by this memory -system.physmem.num_reads::total 30414 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 154 # Number of write requests responded to by this memory -system.physmem.num_writes::total 154 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 981979 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 28500648 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 29482627 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 981979 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 981979 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 149284 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 149284 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 149284 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 981979 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 28500648 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 29631911 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 30416 # Total number of read requests seen -system.physmem.writeReqs 154 # Total number of write requests seen -system.physmem.cpureqs 30571 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 1946496 # Total number of bytes read from memory -system.physmem.bytesWritten 9856 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 1946496 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 9856 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 46 # Number of read reqs serviced by write Q +sim_ops 278192464 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 64768 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1881920 # Number of bytes read from this memory +system.physmem.bytes_read::total 1946688 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 64768 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 64768 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 10176 # Number of bytes written to this memory +system.physmem.bytes_written::total 10176 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1012 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 29405 # Number of read requests responded to by this memory +system.physmem.num_reads::total 30417 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 159 # Number of write requests responded to by this memory +system.physmem.num_writes::total 159 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 980878 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 28500700 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 29481577 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 980878 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 980878 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 154110 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 154110 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 154110 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 980878 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 28500700 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 29635687 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 30419 # Total number of read requests seen +system.physmem.writeReqs 159 # Total number of write requests seen +system.physmem.cpureqs 30579 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 1946688 # Total number of bytes read from memory +system.physmem.bytesWritten 10176 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 1946688 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 10176 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 38 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 1 # Reqs where no action is needed system.physmem.perBankRdReqs::0 1928 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 1906 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 1909 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 1973 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 1961 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 1879 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 1864 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 1880 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 1865 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 1928 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 1952 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 1951 # Track reads on a per bank basis system.physmem.perBankRdReqs::8 1931 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1939 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 1941 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 1872 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 1873 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 1845 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1890 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 1874 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 1846 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 1894 # Track reads on a per bank basis system.physmem.perBankRdReqs::14 1830 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 1799 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 1798 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 6 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 61 # Track writes on a per bank basis system.physmem.perBankWrReqs::3 39 # Track writes on a per bank basis system.physmem.perBankWrReqs::4 7 # Track writes on a per bank basis system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::6 2 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 7 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 4 # Track writes on a per bank basis system.physmem.perBankWrReqs::8 3 # Track writes on a per bank basis system.physmem.perBankWrReqs::9 8 # Track writes on a per bank basis system.physmem.perBankWrReqs::10 6 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 5 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 3 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 6 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 4 # Track writes on a per bank basis system.physmem.perBankWrReqs::13 13 # Track writes on a per bank basis system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 66021783500 # Total gap between requests +system.physmem.totGap 66030647000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 30416 # Categorize read packet sizes +system.physmem.readPktSize::6 30419 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 154 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 29836 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 402 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 97 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 28 # What read queue length does an incoming req see +system.physmem.writePktSize::6 159 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 29848 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 401 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 96 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 29 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -140,11 +140,11 @@ system.physmem.wrQLenPdf::12 7 # Wh system.physmem.wrQLenPdf::13 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 6 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 6 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see @@ -156,14 +156,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 12785750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 610218250 # Sum of mem lat for all requests -system.physmem.totBusLat 151850000 # Total cycles spent in databus access -system.physmem.totBankLat 445582500 # Total cycles spent in bank access -system.physmem.avgQLat 421.00 # Average queueing delay per request -system.physmem.avgBankLat 14671.80 # Average bank access latency per request +system.physmem.totQLat 12950000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 610712500 # Sum of mem lat for all requests +system.physmem.totBusLat 151905000 # Total cycles spent in databus access +system.physmem.totBankLat 445857500 # Total cycles spent in bank access +system.physmem.avgQLat 426.25 # Average queueing delay per request +system.physmem.avgBankLat 14675.54 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 20092.80 # Average memory access latency +system.physmem.avgMemAccLat 20101.79 # Average memory access latency system.physmem.avgRdBW 29.48 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.15 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 29.48 # Average consumed read bandwidth in MB/s @@ -171,324 +171,325 @@ system.physmem.avgConsumedWrBW 0.15 # Av system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.23 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 1.30 # Average write queue length over time -system.physmem.readRowHits 29116 # Number of row buffer hits during reads -system.physmem.writeRowHits 69 # Number of row buffer hits during writes -system.physmem.readRowHitRate 95.87 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 44.81 # Row buffer hit rate for writes -system.physmem.avgGap 2159691.97 # Average gap between requests -system.cpu.branchPred.lookups 34555739 # Number of BP lookups -system.cpu.branchPred.condPredicted 34555739 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 911751 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 24769004 # Number of BTB lookups -system.cpu.branchPred.BTBHits 24665056 # Number of BTB hits +system.physmem.avgWrQLen 9.37 # Average write queue length over time +system.physmem.readRowHits 29124 # Number of row buffer hits during reads +system.physmem.writeRowHits 74 # Number of row buffer hits during writes +system.physmem.readRowHitRate 95.86 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 46.54 # Row buffer hit rate for writes +system.physmem.avgGap 2159416.80 # Average gap between requests +system.cpu.branchPred.lookups 34530822 # Number of BP lookups +system.cpu.branchPred.condPredicted 34530822 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 911360 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 24729253 # Number of BTB lookups +system.cpu.branchPred.BTBHits 24630321 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.580330 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 99.599939 # BTB Hit Percentage system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.numCycles 132043594 # number of cpu cycles simulated +system.cpu.numCycles 132061321 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 26598616 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 185589305 # Number of instructions fetch has processed -system.cpu.fetch.Branches 34555739 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 24665056 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 56508781 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6124933 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 43680261 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 26 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 134 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 25951098 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 190273 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 131964855 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.484572 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.326415 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 26640465 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 185644154 # Number of instructions fetch has processed +system.cpu.fetch.Branches 34530822 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 24630321 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 56512430 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6116130 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 43661882 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 28 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 168 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 25987124 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 190736 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 131984046 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.483688 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.326165 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 78003722 59.11% 59.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1996961 1.51% 60.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2955104 2.24% 62.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3922098 2.97% 65.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 7793741 5.91% 71.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4759235 3.61% 75.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2730671 2.07% 77.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1579089 1.20% 78.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 28224234 21.39% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 78029555 59.12% 59.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1995729 1.51% 60.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2956074 2.24% 62.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3928612 2.98% 65.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 7800232 5.91% 71.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4757812 3.60% 75.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2739309 2.08% 77.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1526136 1.16% 78.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 28250587 21.40% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 131964855 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.261699 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.405515 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 37438024 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 35931161 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 44761152 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 8657481 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 5177037 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 324625052 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 5177037 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 42998776 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 8560534 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 9611 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 47593573 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 27625324 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 320243292 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 235 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 57194 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 25761475 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 370 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 322250586 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 849328812 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 849326947 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1865 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 279212745 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 43037841 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 469 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 463 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 62395647 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 102574673 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 35240496 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 39587079 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 6070451 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 315904307 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1659 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 302190238 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 114769 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 37077809 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 54333314 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1214 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 131964855 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.289930 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.700500 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 131984046 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.261476 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.405742 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 37482972 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 35916557 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 44772529 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 8642915 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 5169073 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 324582822 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 5169073 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 43046448 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 8564916 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 9080 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 47588733 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 27605796 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 320159922 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 237 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 45758 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 25753634 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 369 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 322185741 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 849178580 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 849176902 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1678 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 279212747 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 42972994 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 471 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 465 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 62311011 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 102521831 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 35289955 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 39590581 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5948018 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 315836203 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1692 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 302241523 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 114427 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 37009178 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 54193553 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1247 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 131984046 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.289985 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.700189 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 24574614 18.62% 18.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 23238985 17.61% 36.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 25913680 19.64% 55.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 25803819 19.55% 75.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 18917522 14.34% 89.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 8297062 6.29% 96.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 4140134 3.14% 99.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 916078 0.69% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 162961 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 24578568 18.62% 18.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 23258852 17.62% 36.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 25861899 19.59% 55.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 25827751 19.57% 75.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 18939781 14.35% 89.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 8317897 6.30% 96.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 4131388 3.13% 99.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 904597 0.69% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 163313 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 131964855 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 131984046 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 38351 1.96% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1834339 93.53% 95.49% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 88449 4.51% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 38531 1.97% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1832245 93.51% 95.48% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 88531 4.52% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 31282 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 171161474 56.64% 56.65% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 56.65% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 56.65% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 29 0.00% 56.65% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.65% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.65% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.65% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.65% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.65% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 97761295 32.35% 89.00% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 33236158 11.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 31281 0.01% 0.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 171212053 56.65% 56.66% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 56.66% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 56.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 31 0.00% 56.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.66% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 97762843 32.35% 89.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 33235315 11.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 302190238 # Type of FU issued -system.cpu.iq.rate 2.288564 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1961139 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006490 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 738420696 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 353016005 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 299545946 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 543 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 861 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 154 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 304119846 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 249 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 53994204 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 302241523 # Type of FU issued +system.cpu.iq.rate 2.288645 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1959307 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006483 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 738540324 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 352878782 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 299597425 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 502 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 804 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 148 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 304169320 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 229 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 54003142 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 11795289 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 26124 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 34117 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 3800744 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 11742446 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 27574 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 33469 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 3850203 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3243 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 8488 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3240 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 8493 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 5177037 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1758271 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 159446 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 315905966 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 197291 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 102574673 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 35240496 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 464 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3186 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 73305 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 34117 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 522582 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 446237 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 968819 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 300569422 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 97293064 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1620816 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 5169073 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1760712 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 159375 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 315837895 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 196193 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 102521831 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 35289955 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 465 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 3161 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 73375 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 33469 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 522333 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 446338 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 968671 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 300624260 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 97295381 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1617263 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 130310023 # number of memory reference insts executed -system.cpu.iew.exec_branches 30888402 # Number of branches executed -system.cpu.iew.exec_stores 33016959 # Number of stores executed -system.cpu.iew.exec_rate 2.276289 # Inst execution rate -system.cpu.iew.wb_sent 299975987 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 299546100 # cumulative count of insts written-back -system.cpu.iew.wb_producers 219510783 # num instructions producing a value -system.cpu.iew.wb_consumers 298009836 # num instructions consuming a value +system.cpu.iew.exec_refs 130311532 # number of memory reference insts executed +system.cpu.iew.exec_branches 30892471 # Number of branches executed +system.cpu.iew.exec_stores 33016151 # Number of stores executed +system.cpu.iew.exec_rate 2.276399 # Inst execution rate +system.cpu.iew.wb_sent 300027844 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 299597573 # cumulative count of insts written-back +system.cpu.iew.wb_producers 219555050 # num instructions producing a value +system.cpu.iew.wb_consumers 298061824 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.268539 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.736589 # average fanout of values written-back +system.cpu.iew.wb_rate 2.268625 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.736609 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 37726716 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 37658416 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 911770 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 126787818 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.194158 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.965410 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 911380 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 126814973 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.193688 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.964855 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 58221604 45.92% 45.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 19287083 15.21% 61.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 11808302 9.31% 70.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9592177 7.57% 78.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1746716 1.38% 79.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2074829 1.64% 81.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1294024 1.02% 82.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 717572 0.57% 82.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 22045511 17.39% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 58216662 45.91% 45.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 19288284 15.21% 61.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 11866550 9.36% 70.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9593635 7.57% 78.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1717867 1.35% 79.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2074758 1.64% 81.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1297787 1.02% 82.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 717245 0.57% 82.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 22042185 17.38% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 126787818 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 126814973 # Number of insts commited each cycle system.cpu.commit.committedInsts 157988547 # Number of instructions committed -system.cpu.commit.committedOps 278192463 # Number of ops (including micro ops) committed +system.cpu.commit.committedOps 278192464 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 122219136 # Number of memory references committed -system.cpu.commit.loads 90779384 # Number of loads committed +system.cpu.commit.refs 122219137 # Number of memory references committed +system.cpu.commit.loads 90779385 # Number of loads committed system.cpu.commit.membars 0 # Number of memory barriers committed system.cpu.commit.branches 29309705 # Number of branches committed system.cpu.commit.fp_insts 40 # Number of committed floating point instructions. -system.cpu.commit.int_insts 278186172 # Number of committed integer instructions. +system.cpu.commit.int_insts 278186174 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 22045511 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 22042185 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 420661486 # The number of ROB reads -system.cpu.rob.rob_writes 637020452 # The number of ROB writes -system.cpu.timesIdled 13945 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 78739 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 420623668 # The number of ROB reads +system.cpu.rob.rob_writes 636875907 # The number of ROB writes +system.cpu.timesIdled 13847 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 77275 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 157988547 # Number of Instructions Simulated -system.cpu.committedOps 278192463 # Number of Ops (including micro ops) Simulated +system.cpu.committedOps 278192464 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 157988547 # Number of Instructions Simulated -system.cpu.cpi 0.835780 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.835780 # CPI: Total CPI of All Threads -system.cpu.ipc 1.196488 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.196488 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 592874208 # number of integer regfile reads -system.cpu.int_regfile_writes 300213863 # number of integer regfile writes +system.cpu.cpi 0.835892 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.835892 # CPI: Total CPI of All Threads +system.cpu.ipc 1.196327 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.196327 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 592882448 # number of integer regfile reads +system.cpu.int_regfile_writes 300260228 # number of integer regfile writes system.cpu.fp_regfile_reads 139 # number of floating regfile reads -system.cpu.fp_regfile_writes 70 # number of floating regfile writes -system.cpu.misc_regfile_reads 192707426 # number of misc regfile reads +system.cpu.fp_regfile_writes 69 # number of floating regfile writes +system.cpu.misc_regfile_reads 192732445 # number of misc regfile reads +system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 62 # number of replacements -system.cpu.icache.tagsinuse 835.762840 # Cycle average of tags in use -system.cpu.icache.total_refs 25949757 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 833.765098 # Cycle average of tags in use +system.cpu.icache.total_refs 25985776 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 1029 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 25218.422741 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 25253.426628 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 835.762840 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.408087 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.408087 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 25949757 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25949757 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25949757 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25949757 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25949757 # number of overall hits -system.cpu.icache.overall_hits::total 25949757 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1341 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1341 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1341 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1341 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1341 # number of overall misses -system.cpu.icache.overall_misses::total 1341 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 65663000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 65663000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 65663000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 65663000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 65663000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 65663000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 25951098 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 25951098 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 25951098 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 25951098 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 25951098 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 25951098 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 833.765098 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.407112 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.407112 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 25985776 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 25985776 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 25985776 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 25985776 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 25985776 # number of overall hits +system.cpu.icache.overall_hits::total 25985776 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1348 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1348 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1348 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1348 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1348 # number of overall misses +system.cpu.icache.overall_misses::total 1348 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 66423500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 66423500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 66423500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 66423500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 66423500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 66423500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 25987124 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 25987124 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 25987124 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 25987124 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 25987124 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 25987124 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000052 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000052 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000052 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000052 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000052 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000052 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48965.697241 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 48965.697241 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 48965.697241 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 48965.697241 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 48965.697241 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 48965.697241 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49275.593472 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 49275.593472 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 49275.593472 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 49275.593472 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 49275.593472 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 49275.593472 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 133 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked @@ -497,126 +498,126 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 26.600000 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 311 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 311 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 311 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 311 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 311 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 311 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 318 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 318 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 318 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 318 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 318 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 318 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1030 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 1030 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 1030 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 1030 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 1030 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 1030 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 51831000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 51831000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 51831000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 51831000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 51831000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 51831000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 51809000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 51809000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 51809000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 51809000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 51809000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 51809000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000040 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50321.359223 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50321.359223 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50321.359223 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 50321.359223 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50321.359223 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 50321.359223 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50300 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50300 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50300 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 50300 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50300 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 50300 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 462 # number of replacements -system.cpu.l2cache.tagsinuse 20805.290602 # Cycle average of tags in use -system.cpu.l2cache.total_refs 4028325 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 30393 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 132.541210 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 466 # number of replacements +system.cpu.l2cache.tagsinuse 20794.050693 # Cycle average of tags in use +system.cpu.l2cache.total_refs 4028842 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 30396 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 132.545138 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 19869.756423 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 689.265972 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 246.268207 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.606377 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.021035 # 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number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2110180998 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2110180998 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 33438807498 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 33438807498 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 33438807498 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 33438807498 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 43246672 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 43246672 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 74692970 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 74692970 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 74692970 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 74692970 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.060698 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.060698 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 74686424 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 74686424 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 74686424 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 74686424 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.060720 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.060720 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003126 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.003126 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.036465 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.036465 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.036465 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.036465 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11928.992296 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11928.992296 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21457.621591 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 21457.621591 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 12272.867425 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 12272.867425 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 12272.867425 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 12272.867425 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 31969 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.036475 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.036475 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036475 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036475 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11930.483512 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11930.483512 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21470.894659 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 21470.894659 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 12274.671537 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 12274.671537 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 12274.671537 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 12274.671537 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 32091 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 9433 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 9458 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 3.389060 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 3.393001 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2066038 # number of writebacks -system.cpu.dcache.writebacks::total 2066038 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 631383 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 631383 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16146 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16146 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 647529 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 647529 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 647529 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 647529 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1993980 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1993980 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82147 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 82147 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2076127 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2076127 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2076127 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2076127 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21982224500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 21982224500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1833925499 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1833925499 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23816149999 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 23816149999 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23816149999 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 23816149999 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046100 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046100 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 2066502 # number of writebacks +system.cpu.dcache.writebacks::total 2066502 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 631907 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 631907 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16126 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16126 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 648033 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 648033 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 648033 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 648033 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994024 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1994024 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82155 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 82155 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2076179 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2076179 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2076179 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2076179 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21982252000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 21982252000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1835038498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1835038498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23817290498 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 23817290498 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23817290498 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 23817290498 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046108 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046108 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002613 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002613 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027795 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.027795 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027795 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.027795 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11024.295379 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11024.295379 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22324.923600 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22324.923600 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11471.432142 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11471.432142 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11471.432142 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11471.432142 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027799 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.027799 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027799 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.027799 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11024.065909 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11024.065909 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22336.297219 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22336.297219 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11471.694155 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11471.694155 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11471.694155 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11471.694155 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini index 059376b69..4a41d87f1 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini @@ -77,7 +77,7 @@ port=system.membus.slave[4] [system.cpu.interrupts] type=X86LocalApic -clock=500 +clock=8000 int_latency=1000 pio_addr=2305843009213693952 pio_latency=100000 @@ -128,6 +128,7 @@ type=CoherentBus block_size=64 clock=1000 header_cycles=1 +system=system use_default_range=false width=8 master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simerr b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simerr index f5691fd64..e45cd058f 100755 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simerr +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simerr @@ -1,3 +1,2 @@ warn: Sockets disabled, not accepting gdb connections -warn: instruction 'fldcw_Mw' unimplemented hack: be nice to actually delete the event here diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout index b60097676..b233b4d5d 100755 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout @@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 16:30:44 -gem5 started Jan 23 2013 18:49:17 +gem5 compiled Mar 11 2013 13:21:48 +gem5 started Mar 11 2013 13:30:24 gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second @@ -25,4 +25,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 168950039500 because target called exit() +Exiting @ tick 168950040000 because target called exit() diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt index 3345429f2..f4ab1803f 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt @@ -1,59 +1,59 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.168950 # Number of seconds simulated -sim_ticks 168950039500 # Number of ticks simulated -final_tick 168950039500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 168950040000 # Number of ticks simulated +final_tick 168950040000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 951900 # Simulator instruction rate (inst/s) -host_op_rate 1676143 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1017943887 # Simulator tick rate (ticks/s) -host_mem_usage 420484 # Number of bytes of host memory used -host_seconds 165.97 # Real time elapsed on the host +host_inst_rate 540700 # Simulator instruction rate (inst/s) +host_op_rate 952086 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 578214744 # Simulator tick rate (ticks/s) +host_mem_usage 420252 # Number of bytes of host memory used +host_seconds 292.19 # Real time elapsed on the host sim_insts 157988548 # Number of instructions simulated -sim_ops 278192464 # Number of ops (including micro ops) simulated +sim_ops 278192465 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 1741569312 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 717246011 # Number of bytes read from this memory -system.physmem.bytes_read::total 2458815323 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 717246013 # Number of bytes read from this memory +system.physmem.bytes_read::total 2458815325 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 1741569312 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 1741569312 # Number of instructions bytes read from this memory system.physmem.bytes_written::cpu.data 243173117 # Number of bytes written to this memory system.physmem.bytes_written::total 243173117 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 217696164 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 90779446 # Number of read requests responded to by this memory -system.physmem.num_reads::total 308475610 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 90779447 # Number of read requests responded to by this memory +system.physmem.num_reads::total 308475611 # Number of read requests responded to by this memory system.physmem.num_writes::cpu.data 31439752 # Number of write requests responded to by this memory system.physmem.num_writes::total 31439752 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 10308191209 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 4245314255 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14553505464 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 10308191209 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 10308191209 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1439319681 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1439319681 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 10308191209 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5684633936 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 15992825145 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 10308191179 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 4245314254 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14553505433 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 10308191179 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 10308191179 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1439319677 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1439319677 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 10308191179 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5684633931 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 15992825110 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.numCycles 337900080 # number of cpu cycles simulated +system.cpu.numCycles 337900081 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 157988548 # Number of instructions committed -system.cpu.committedOps 278192464 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 278186173 # Number of integer alu accesses +system.cpu.committedOps 278192465 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 278186175 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured system.cpu.num_conditional_control_insts 18628007 # number of instructions that are conditional controls -system.cpu.num_int_insts 278186173 # number of integer instructions +system.cpu.num_int_insts 278186175 # number of integer instructions system.cpu.num_fp_insts 40 # number of float instructions -system.cpu.num_int_register_reads 739519998 # number of times the integer registers were read -system.cpu.num_int_register_writes 279212719 # number of times the integer registers were written +system.cpu.num_int_register_reads 739520003 # number of times the integer registers were read +system.cpu.num_int_register_writes 279212721 # number of times the integer registers were written system.cpu.num_fp_register_reads 40 # number of times the floating registers were read system.cpu.num_fp_register_writes 26 # number of times the floating registers were written -system.cpu.num_mem_refs 122219136 # number of memory refs -system.cpu.num_load_insts 90779384 # Number of load instructions +system.cpu.num_mem_refs 122219137 # number of memory refs +system.cpu.num_load_insts 90779385 # Number of load instructions system.cpu.num_store_insts 31439752 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 337900080 # Number of busy cycles +system.cpu.num_busy_cycles 337900081 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini index edae4b0b1..5da614d68 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini @@ -117,7 +117,7 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=X86LocalApic -clock=500 +clock=8000 int_latency=1000 pio_addr=2305843009213693952 pio_latency=100000 @@ -168,6 +168,7 @@ type=CoherentBus block_size=64 clock=500 header_cycles=1 +system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side @@ -200,6 +201,7 @@ type=CoherentBus block_size=64 clock=1000 header_cycles=1 +system=system use_default_range=false width=8 master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simerr b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simerr index f5691fd64..e45cd058f 100755 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simerr +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simerr @@ -1,3 +1,2 @@ warn: Sockets disabled, not accepting gdb connections -warn: instruction 'fldcw_Mw' unimplemented hack: be nice to actually delete the event here diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout index 3eb41b894..5ba351c70 100755 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout @@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 16:30:44 -gem5 started Jan 23 2013 16:31:05 +gem5 compiled Mar 11 2013 13:21:48 +gem5 started Mar 11 2013 13:30:24 gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second @@ -25,4 +25,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 365989064000 because target called exit() +Exiting @ tick 365989065000 because target called exit() diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt index d5a162335..ac797fce6 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.365989 # Number of seconds simulated -sim_ticks 365989064000 # Number of ticks simulated -final_tick 365989064000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 365989065000 # Number of ticks simulated +final_tick 365989065000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 496442 # Simulator instruction rate (inst/s) -host_op_rate 874155 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1150035399 # Simulator tick rate (ticks/s) -host_mem_usage 428932 # Number of bytes of host memory used -host_seconds 318.24 # Real time elapsed on the host +host_inst_rate 284823 # Simulator instruction rate (inst/s) +host_op_rate 501527 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 659807143 # Simulator tick rate (ticks/s) +host_mem_usage 428704 # Number of bytes of host memory used +host_seconds 554.69 # Real time elapsed on the host sim_insts 157988548 # Number of instructions simulated -sim_ops 278192464 # Number of ops (including micro ops) simulated +sim_ops 278192465 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 51392 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 1871744 # Number of bytes read from this memory system.physmem.bytes_read::total 1923136 # Number of bytes read from this memory @@ -35,35 +35,35 @@ system.physmem.bw_total::cpu.inst 140419 # To system.physmem.bw_total::cpu.data 5114207 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 5272114 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.numCycles 731978128 # number of cpu cycles simulated +system.cpu.numCycles 731978130 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 157988548 # Number of instructions committed -system.cpu.committedOps 278192464 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 278186173 # Number of integer alu accesses +system.cpu.committedOps 278192465 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 278186175 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured system.cpu.num_conditional_control_insts 18628007 # number of instructions that are conditional controls -system.cpu.num_int_insts 278186173 # number of integer instructions +system.cpu.num_int_insts 278186175 # number of integer instructions system.cpu.num_fp_insts 40 # number of float instructions -system.cpu.num_int_register_reads 739519998 # number of times the integer registers were read -system.cpu.num_int_register_writes 279212719 # number of times the integer registers were written +system.cpu.num_int_register_reads 739520003 # number of times the integer registers were read +system.cpu.num_int_register_writes 279212721 # number of times the integer registers were written system.cpu.num_fp_register_reads 40 # number of times the floating registers were read system.cpu.num_fp_register_writes 26 # number of times the floating registers were written -system.cpu.num_mem_refs 122219136 # number of memory refs -system.cpu.num_load_insts 90779384 # Number of load instructions +system.cpu.num_mem_refs 122219137 # number of memory refs +system.cpu.num_load_insts 90779385 # Number of load instructions system.cpu.num_store_insts 31439752 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 731978128 # Number of busy cycles +system.cpu.num_busy_cycles 731978130 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 24 # number of replacements -system.cpu.icache.tagsinuse 665.632509 # Cycle average of tags in use +system.cpu.icache.tagsinuse 665.632508 # Cycle average of tags in use system.cpu.icache.total_refs 217695357 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 808 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 269424.946782 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 665.632509 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 665.632508 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.325016 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.325016 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 217695357 # number of ReadReq hits @@ -136,14 +136,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52740.099010 system.cpu.icache.overall_avg_mshr_miss_latency::total 52740.099010 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 318 # number of replacements -system.cpu.l2cache.tagsinuse 20041.899820 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 20041.899765 # Cycle average of tags in use system.cpu.l2cache.total_refs 3992419 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 30026 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 132.965397 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 19330.353217 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 557.646383 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 153.900220 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 19330.353164 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 557.646382 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 153.900219 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.589916 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.017018 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.004697 # Average percentage of cache occupancy @@ -274,22 +274,22 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 2062733 # number of replacements -system.cpu.dcache.tagsinuse 4076.488630 # Cycle average of tags in use -system.cpu.dcache.total_refs 120152369 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4076.488619 # Cycle average of tags in use +system.cpu.dcache.total_refs 120152370 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 2066829 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 58.133677 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 126079700000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4076.488630 # Average occupied blocks per requestor +system.cpu.dcache.warmup_cycle 126079701000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4076.488619 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.995236 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.995236 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 88818726 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 88818726 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 88818727 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 88818727 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 31333643 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 31333643 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 120152369 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 120152369 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 120152369 # number of overall hits -system.cpu.dcache.overall_hits::total 120152369 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 120152370 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 120152370 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 120152370 # number of overall hits +system.cpu.dcache.overall_hits::total 120152370 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 1960720 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 1960720 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 106109 # number of WriteReq misses @@ -306,14 +306,14 @@ system.cpu.dcache.demand_miss_latency::cpu.data 28097140000 system.cpu.dcache.demand_miss_latency::total 28097140000 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 28097140000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 28097140000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 90779446 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 90779446 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 90779447 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 90779447 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 122219198 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 122219198 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 122219198 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 122219198 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 122219199 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 122219199 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 122219199 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 122219199 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021599 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.021599 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003375 # miss rate for WriteReq accesses diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini index ab5e0012f..448cff052 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini @@ -452,7 +452,7 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=X86LocalApic -clock=500 +clock=8000 int_latency=1000 pio_addr=2305843009213693952 pio_latency=100000 @@ -503,6 +503,7 @@ type=CoherentBus block_size=64 clock=500 header_cycles=1 +system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side @@ -535,6 +536,7 @@ type=CoherentBus block_size=64 clock=1000 header_cycles=1 +system=system use_default_range=false width=8 master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave @@ -542,25 +544,28 @@ slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_m [system.physmem] type=SimpleDRAM +activation_limit=4 addr_mapping=openmap banks_per_rank=8 +channels=1 clock=1000 conf_table_reported=false in_addr_map=true -lines_per_rowbuffer=64 -mem_sched_policy=fcfs +lines_per_rowbuffer=32 +mem_sched_policy=frfcfs null=false page_policy=open range=0:134217727 ranks_per_channel=2 read_buffer_size=32 -tBURST=4000 -tCL=14000 -tRCD=14000 +tBURST=5000 +tCL=13750 +tRCD=13750 tREFI=7800000 tRFC=300000 -tRP=14000 -tWTR=1000 +tRP=13750 +tWTR=7500 +tXAW=40000 write_buffer_size=32 write_thresh_perc=70 zero=false diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simerr b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simerr index f5691fd64..e45cd058f 100755 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simerr +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simerr @@ -1,3 +1,2 @@ warn: Sockets disabled, not accepting gdb connections -warn: instruction 'fldcw_Mw' unimplemented hack: be nice to actually delete the event here diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout index c205806bb..527df912e 100755 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout @@ -3,14 +3,15 @@ Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing/ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 16:30:44 -gem5 started Jan 23 2013 16:49:19 +gem5 compiled Mar 11 2013 13:21:48 +gem5 started Mar 11 2013 13:30:24 gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Reading the dictionary files: *********info: Increasing stack size by one page. +info: Increasing stack size by one page. **************************************** 58924 words stored in 3784810 bytes @@ -24,7 +25,6 @@ Processing sentences in batch mode Echoing of input sentence turned on. * as had expected the party to be a success , it was a success info: Increasing stack size by one page. -info: Increasing stack size by one page. * do you know where John 's * he said that , finding that it was impossible to get work as a waiter , he would work as a janitor info: Increasing stack size by one page. @@ -81,4 +81,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 434474519000 because target called exit() +Exiting @ tick 434778577000 because target called exit() diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index 1e537017c..44aca7e96 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,104 +1,104 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.434431 # Number of seconds simulated -sim_ticks 434430920500 # Number of ticks simulated -final_tick 434430920500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.434779 # Number of seconds simulated +sim_ticks 434778577000 # Number of ticks simulated +final_tick 434778577000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 103951 # Simulator instruction rate (inst/s) -host_op_rate 192218 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 54614710 # Simulator tick rate (ticks/s) -host_mem_usage 421552 # Number of bytes of host memory used -host_seconds 7954.47 # Real time elapsed on the host +host_inst_rate 65958 # Simulator instruction rate (inst/s) +host_op_rate 121963 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 34681028 # Simulator tick rate (ticks/s) +host_mem_usage 469672 # Number of bytes of host memory used +host_seconds 12536.50 # Real time elapsed on the host sim_insts 826877109 # Number of instructions simulated -sim_ops 1528988700 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 206656 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24473856 # Number of bytes read from this memory -system.physmem.bytes_read::total 24680512 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 206656 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 206656 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18792192 # Number of bytes written to this memory -system.physmem.bytes_written::total 18792192 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3229 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 382404 # Number of read requests responded to by this memory -system.physmem.num_reads::total 385633 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 293628 # Number of write requests responded to by this memory -system.physmem.num_writes::total 293628 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 475694 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 56335438 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 56811131 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 475694 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 475694 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 43257031 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 43257031 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 43257031 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 475694 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 56335438 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 100068163 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 385635 # Total number of read requests seen -system.physmem.writeReqs 293628 # Total number of write requests seen -system.physmem.cpureqs 897306 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 24680512 # Total number of bytes read from memory -system.physmem.bytesWritten 18792192 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 24680512 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 18792192 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 135 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 215167 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 23200 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 24440 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 23926 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 22603 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 23455 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 24726 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 24470 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 24228 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 24367 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 24672 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 24294 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 24362 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 24487 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 23459 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 24852 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 23959 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 17796 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 18805 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 18324 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 17566 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 18019 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 18653 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 18315 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 18311 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 18728 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 18743 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 18429 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 18564 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 18552 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 17863 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 18856 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 18104 # Track writes on a per bank basis +sim_ops 1528988701 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 207616 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24480192 # Number of bytes read from this memory +system.physmem.bytes_read::total 24687808 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 207616 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 207616 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18793792 # Number of bytes written to this memory +system.physmem.bytes_written::total 18793792 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3244 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 382503 # Number of read requests responded to by this memory +system.physmem.num_reads::total 385747 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 293653 # Number of write requests responded to by this memory +system.physmem.num_writes::total 293653 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 477521 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 56304964 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 56782485 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 477521 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 477521 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 43226122 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 43226122 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 43226122 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 477521 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 56304964 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 100008607 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 385749 # Total number of read requests seen +system.physmem.writeReqs 293653 # Total number of write requests seen +system.physmem.cpureqs 898439 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 24687808 # Total number of bytes read from memory +system.physmem.bytesWritten 18793792 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 24687808 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 18793792 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 166 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 215914 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 23310 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 24517 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 23767 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 22579 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 23602 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 24804 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 24363 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 24233 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 24554 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 24709 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 24156 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 24303 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 24582 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 23494 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 24683 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 23927 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 17803 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 18810 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 18279 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 17552 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 18029 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 18664 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 18318 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 18338 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 18780 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 18770 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 18402 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 18539 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 18562 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 17888 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 18802 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 18117 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 2876 # Number of times wr buffer was full causing retry -system.physmem.totGap 434430903500 # Total gap between requests +system.physmem.numWrRetry 3123 # Number of times wr buffer was full causing retry +system.physmem.totGap 434778560000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 385635 # Categorize read packet sizes +system.physmem.readPktSize::6 385749 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 293628 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 380797 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4262 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 378 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 58 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 293653 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 380888 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4255 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 362 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 63 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -124,197 +124,197 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 12709 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 12719 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 12720 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 12722 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 12725 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 12729 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 12733 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 12739 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 12741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 12767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 12766 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 12766 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 12766 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 12766 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 12766 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 12766 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 12766 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 12766 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 12766 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 12766 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 12766 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 12766 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 12766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 12710 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 12723 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 12724 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 12726 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 12730 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 12731 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 12734 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 12734 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 12736 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 12768 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 12768 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 12768 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 12767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 12767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 12767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 12767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 12767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 12767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 12767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 12767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 12767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 12767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 12767 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 48 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 47 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 37 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 34 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 26 # What write queue length does an incoming req see -system.physmem.totQLat 3409479750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11997177250 # Sum of mem lat for all requests -system.physmem.totBusLat 1927500000 # Total cycles spent in databus access -system.physmem.totBankLat 6660197500 # Total cycles spent in bank access -system.physmem.avgQLat 8844.31 # Average queueing delay per request -system.physmem.avgBankLat 17276.78 # Average bank access latency per request +system.physmem.wrQLenPdf::30 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 32 # What write queue length does an incoming req see +system.physmem.totQLat 3433767500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 12026720000 # Sum of mem lat for all requests +system.physmem.totBusLat 1927915000 # Total cycles spent in databus access +system.physmem.totBankLat 6665037500 # Total cycles spent in bank access +system.physmem.avgQLat 8905.39 # Average queueing delay per request +system.physmem.avgBankLat 17285.61 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 31121.08 # Average memory access latency -system.physmem.avgRdBW 56.81 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 43.26 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 56.81 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 43.26 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 31191.00 # Average memory access latency +system.physmem.avgRdBW 56.78 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 43.23 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 56.78 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 43.23 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.78 # Data bus utilization in percentage system.physmem.avgRdQLen 0.03 # Average read queue length over time -system.physmem.avgWrQLen 9.17 # Average write queue length over time -system.physmem.readRowHits 331860 # Number of row buffer hits during reads -system.physmem.writeRowHits 191798 # Number of row buffer hits during writes -system.physmem.readRowHitRate 86.09 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 65.32 # Row buffer hit rate for writes -system.physmem.avgGap 639562.15 # Average gap between requests -system.cpu.branchPred.lookups 214905339 # Number of BP lookups -system.cpu.branchPred.condPredicted 214905339 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 13127433 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 150477516 # Number of BTB lookups -system.cpu.branchPred.BTBHits 147823689 # Number of BTB hits +system.physmem.avgWrQLen 9.96 # Average write queue length over time +system.physmem.readRowHits 331863 # Number of row buffer hits during reads +system.physmem.writeRowHits 191855 # Number of row buffer hits during writes +system.physmem.readRowHitRate 86.07 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 65.33 # Row buffer hit rate for writes +system.physmem.avgGap 639943.01 # Average gap between requests +system.cpu.branchPred.lookups 214994146 # Number of BP lookups +system.cpu.branchPred.condPredicted 214994146 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 13135298 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 150584792 # Number of BTB lookups +system.cpu.branchPred.BTBHits 147887338 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.236396 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 98.208681 # BTB Hit Percentage system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 868861842 # number of cpu cycles simulated +system.cpu.numCycles 869557155 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 180577504 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1192973241 # Number of instructions fetch has processed -system.cpu.fetch.Branches 214905339 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 147823689 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 371150852 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 83341611 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 231393952 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 33171 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 324598 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 87 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 173446874 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 3818726 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 853436670 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.595518 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.389389 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 180620519 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1193264599 # Number of instructions fetch has processed +system.cpu.fetch.Branches 214994146 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 147887338 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 371275147 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 83409102 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 231974123 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 33791 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 326928 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 55 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 173497134 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 3845609 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 854248204 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.593680 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.388732 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 486691437 57.03% 57.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 24707790 2.90% 59.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 27346098 3.20% 63.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 28808795 3.38% 66.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 18459850 2.16% 68.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 24598509 2.88% 71.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 30642263 3.59% 75.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 28856964 3.38% 78.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 183324964 21.48% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 487377953 57.05% 57.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 24712671 2.89% 59.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 27340185 3.20% 63.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 28885218 3.38% 66.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 18461820 2.16% 68.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 24636038 2.88% 71.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 30640475 3.59% 75.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 28823425 3.37% 78.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 183370419 21.47% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 853436670 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.247341 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.373030 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 237036597 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 187932241 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 313348177 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 45163149 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 69956506 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2166370172 # Number of instructions handled by decode +system.cpu.fetch.rateDist::total 854248204 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.247246 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.372267 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 237078092 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 188537109 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 313423018 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 45192344 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 70017641 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2166915251 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 6 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 69956506 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 270406129 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 53950609 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 16000 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 322641702 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 136465724 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2119600897 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 32452 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 20939189 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 101244294 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 109 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2216054849 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5354933162 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 5354796739 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 136423 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1614040852 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 602013997 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1381 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1341 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 329887917 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 512569621 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 204871608 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 196009794 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 55366102 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2033547368 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 23672 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1807958991 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 824800 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 499056334 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 817700270 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 23120 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 853436670 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.118445 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.887633 # Number of insts issued each cycle +system.cpu.rename.SquashCycles 70017641 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 270505809 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 54166582 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 16246 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 322705449 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 136836477 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2120054204 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 31988 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 21457173 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 101130762 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 79 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2216502453 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5356043513 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 5355912931 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 130582 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 602461599 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1415 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1390 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 330161364 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 512694390 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 204951429 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 196255090 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 55443674 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2034023079 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 23697 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1808317213 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 841556 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 499552115 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 818199817 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 23145 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 854248204 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.116852 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.887224 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 233342895 27.34% 27.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 145008680 16.99% 44.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 138353825 16.21% 60.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 133057886 15.59% 76.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 96025914 11.25% 87.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 58740201 6.88% 94.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 34984970 4.10% 98.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 12023870 1.41% 99.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1898429 0.22% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 233580311 27.34% 27.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 145624549 17.05% 44.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 138385021 16.20% 60.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 133093921 15.58% 76.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 95894144 11.23% 87.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 58820201 6.89% 94.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 34887177 4.08% 98.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 12062824 1.41% 99.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1900056 0.22% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 853436670 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 854248204 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 4945296 32.31% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 7774785 50.79% 83.10% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2587375 16.90% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 4959094 32.46% 32.46% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 32.46% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 32.46% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.46% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.46% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.46% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 32.46% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.46% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 32.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 32.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.46% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 7752013 50.74% 83.20% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2567167 16.80% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2719757 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1190688442 65.86% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2720919 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1190891827 65.86% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.01% # Type of FU issued @@ -340,291 +340,292 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.01% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 438864121 24.27% 90.28% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 175686671 9.72% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 438957859 24.27% 90.28% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 175746607 9.72% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1807958991 # Type of FU issued -system.cpu.iq.rate 2.080836 # Inst issue rate -system.cpu.iq.fu_busy_cnt 15307456 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.008467 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4485463564 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2532842226 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1768511816 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23344 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 44056 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 5298 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1820535825 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 10865 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 170531860 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1808317213 # Type of FU issued +system.cpu.iq.rate 2.079584 # Inst issue rate +system.cpu.iq.fu_busy_cnt 15278274 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.008449 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4486980237 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2533813283 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1768843031 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 22223 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 42394 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 5084 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1820864137 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 10431 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 170575963 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 128467465 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 477996 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 270600 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 55711763 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 128592233 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 466094 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 268512 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 55791476 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 12158 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 637 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 12353 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 585 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 69956506 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 16270481 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2882420 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2033571040 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 2388116 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 512569621 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 204871949 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 6204 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1819124 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 76761 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 270600 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 9107192 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4485988 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 13593180 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1780284053 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 431339374 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 27674938 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 70017641 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 16317048 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2892217 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2034046776 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 2393263 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 512694390 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 204951662 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 6140 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1820618 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 76746 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 268512 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 9116558 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4489858 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 13606416 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1780627625 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 431426006 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 27689588 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 602039294 # number of memory reference insts executed -system.cpu.iew.exec_branches 169246967 # Number of branches executed -system.cpu.iew.exec_stores 170699920 # Number of stores executed -system.cpu.iew.exec_rate 2.048984 # Inst execution rate -system.cpu.iew.wb_sent 1775206038 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1768517114 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1341481369 # num instructions producing a value -system.cpu.iew.wb_consumers 1964281102 # num instructions consuming a value +system.cpu.iew.exec_refs 602161774 # number of memory reference insts executed +system.cpu.iew.exec_branches 169273752 # Number of branches executed +system.cpu.iew.exec_stores 170735768 # Number of stores executed +system.cpu.iew.exec_rate 2.047741 # Inst execution rate +system.cpu.iew.wb_sent 1775545178 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1768848115 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1341672434 # num instructions producing a value +system.cpu.iew.wb_consumers 1964743040 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.035441 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.682938 # average fanout of values written-back +system.cpu.iew.wb_rate 2.034194 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.682874 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 504616245 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 505092905 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 13160386 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 783480164 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.951535 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.459630 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 13168881 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 784230563 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.949667 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.458347 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 290390176 37.06% 37.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 195527314 24.96% 62.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 61904118 7.90% 69.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 92200524 11.77% 81.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 25009746 3.19% 84.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 28276907 3.61% 88.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 9452853 1.21% 89.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10837267 1.38% 91.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 69881259 8.92% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 290802586 37.08% 37.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 195769482 24.96% 62.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 62065599 7.91% 69.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 92211558 11.76% 81.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 25071827 3.20% 84.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 28246222 3.60% 88.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 9385684 1.20% 89.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10800015 1.38% 91.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 69877590 8.91% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 783480164 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 784230563 # Number of insts commited each cycle system.cpu.commit.committedInsts 826877109 # Number of instructions committed -system.cpu.commit.committedOps 1528988700 # Number of ops (including micro ops) committed +system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 533262342 # Number of memory references committed -system.cpu.commit.loads 384102156 # Number of loads committed +system.cpu.commit.refs 533262343 # Number of memory references committed +system.cpu.commit.loads 384102157 # Number of loads committed system.cpu.commit.membars 0 # Number of memory barriers committed system.cpu.commit.branches 149758583 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1528317559 # Number of committed integer instructions. +system.cpu.commit.int_insts 1528317561 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 69881259 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 69877590 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2747203850 # The number of ROB reads -system.cpu.rob.rob_writes 4137345189 # The number of ROB writes -system.cpu.timesIdled 333192 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 15425172 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2748434579 # The number of ROB reads +system.cpu.rob.rob_writes 4138359582 # The number of ROB writes +system.cpu.timesIdled 322597 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 15308951 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826877109 # Number of Instructions Simulated -system.cpu.committedOps 1528988700 # Number of Ops (including micro ops) Simulated +system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 826877109 # Number of Instructions Simulated -system.cpu.cpi 1.050775 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.050775 # CPI: Total CPI of All Threads -system.cpu.ipc 0.951678 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.951678 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3357185623 # number of integer regfile reads -system.cpu.int_regfile_writes 1848288300 # number of integer regfile writes -system.cpu.fp_regfile_reads 5295 # number of floating regfile reads -system.cpu.fp_regfile_writes 3 # number of floating regfile writes -system.cpu.misc_regfile_reads 980095444 # number of misc regfile reads -system.cpu.icache.replacements 5498 # number of replacements -system.cpu.icache.tagsinuse 1034.775539 # Cycle average of tags in use -system.cpu.icache.total_refs 173205275 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 7087 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 24439.858191 # Average number of references to valid blocks. +system.cpu.cpi 1.051616 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.051616 # CPI: Total CPI of All Threads +system.cpu.ipc 0.950917 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.950917 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3357648579 # number of integer regfile reads +system.cpu.int_regfile_writes 1848573449 # number of integer regfile writes +system.cpu.fp_regfile_reads 5079 # number of floating regfile reads +system.cpu.fp_regfile_writes 8 # number of floating regfile writes +system.cpu.misc_regfile_reads 980313786 # number of misc regfile reads +system.cpu.misc_regfile_writes 1 # number of misc regfile writes +system.cpu.icache.replacements 5514 # number of replacements +system.cpu.icache.tagsinuse 1036.209327 # Cycle average of tags in use +system.cpu.icache.total_refs 173254328 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 7112 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 24360.844769 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1034.775539 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.505261 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.505261 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 173220667 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 173220667 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 173220667 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 173220667 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 173220667 # number of overall hits -system.cpu.icache.overall_hits::total 173220667 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 226207 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 226207 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 226207 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 226207 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 226207 # number of overall misses -system.cpu.icache.overall_misses::total 226207 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1445018998 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1445018998 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1445018998 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1445018998 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1445018998 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1445018998 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 173446874 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 173446874 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 173446874 # 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number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 223791 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 223791 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 223791 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 223791 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 223791 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 223791 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 922806998 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 922806998 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 922806998 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 922806998 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 922806998 # 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average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 57716.709453 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 57794.413123 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 34.243085 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 34.243085 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50139.855101 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50139.855101 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 62003.389831 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53621.354471 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 53691.860029 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 62003.389831 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53621.354471 # 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number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3907599 # number of overall misses -system.cpu.dcache.overall_misses::total 3907599 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 51581963000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 51581963000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 23867126500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 23867126500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 75449089500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 75449089500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 75449089500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 75449089500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 259464493 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 259464493 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 2529656 # number of replacements +system.cpu.dcache.tagsinuse 4087.796251 # Cycle average of tags in use +system.cpu.dcache.total_refs 405349896 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2533752 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 159.980099 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 1794571000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4087.796251 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.997997 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.997997 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 256610011 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 256610011 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148154878 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148154878 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 404764889 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 404764889 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 404764889 # number of overall hits +system.cpu.dcache.overall_hits::total 404764889 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2895327 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2895327 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1005324 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1005324 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3900651 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3900651 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3900651 # number of overall misses +system.cpu.dcache.overall_misses::total 3900651 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 51401791500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 51401791500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 23898482499 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 23898482499 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 75300273999 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 75300273999 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 75300273999 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 75300273999 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 259505338 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 259505338 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 408624695 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 408624695 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 408624695 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 408624695 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011189 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.011189 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006735 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.006735 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009563 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009563 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009563 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009563 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17768.245516 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17768.245516 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23758.857387 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 23758.857387 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 19308.298907 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 19308.298907 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 19308.298907 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 19308.298907 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 6217 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 408665540 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 408665540 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 408665540 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 408665540 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011157 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.011157 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006740 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006740 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009545 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009545 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009545 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009545 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17753.363092 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17753.363092 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23771.920793 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 23771.920793 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 19304.540191 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 19304.540191 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 19304.540191 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 19304.540191 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 6530 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 681 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 642 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.129222 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.171340 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2331083 # number of writebacks -system.cpu.dcache.writebacks::total 2331083 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1140525 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1140525 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16809 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16809 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1157334 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1157334 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1157334 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1157334 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762517 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1762517 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 987748 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 987748 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2750265 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2750265 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2750265 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2750265 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27791691500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 27791691500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 21690054500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 21690054500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 49481746000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 49481746000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 49481746000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 49481746000 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 2331136 # number of writebacks +system.cpu.dcache.writebacks::total 2331136 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1132617 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1132617 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16869 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16869 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1149486 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1149486 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1149486 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1149486 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762710 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1762710 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 988455 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 988455 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2751165 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2751165 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2751165 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2751165 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27811279500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 27811279500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 21719252000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 21719252000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 49530531500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 49530531500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 49530531500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 49530531500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006793 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006793 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006622 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006622 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006731 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006731 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006731 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006731 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15768.183513 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15768.183513 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 21959.097361 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 21959.097361 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17991.628443 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 17991.628443 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17991.628443 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 17991.628443 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006627 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006627 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006732 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006732 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006732 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006732 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15777.569481 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15777.569481 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 21972.929471 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 21972.929471 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18003.475437 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 18003.475437 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18003.475437 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 18003.475437 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini index 43e0511db..3ae684a0d 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini @@ -77,7 +77,7 @@ port=system.membus.slave[4] [system.cpu.interrupts] type=X86LocalApic -clock=500 +clock=8000 int_latency=1000 pio_addr=2305843009213693952 pio_latency=100000 @@ -128,6 +128,7 @@ type=CoherentBus block_size=64 clock=1000 header_cycles=1 +system=system use_default_range=false width=8 master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simerr b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simerr index f5691fd64..e45cd058f 100755 --- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simerr +++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simerr @@ -1,3 +1,2 @@ warn: Sockets disabled, not accepting gdb connections -warn: instruction 'fldcw_Mw' unimplemented hack: be nice to actually delete the event here diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout index 5586bce3b..1169e7228 100755 --- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout +++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout @@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/simple-ato gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 16:30:44 -gem5 started Jan 23 2013 16:35:03 +gem5 compiled Mar 11 2013 13:21:48 +gem5 started Mar 11 2013 13:30:24 gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second @@ -71,4 +71,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 885229327500 because target called exit() +Exiting @ tick 885229328000 because target called exit() diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt index c7a71973c..cadafb39e 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt @@ -1,59 +1,59 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.885229 # Number of seconds simulated -sim_ticks 885229327500 # Number of ticks simulated -final_tick 885229327500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 885229328000 # Number of ticks simulated +final_tick 885229328000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 978383 # Simulator instruction rate (inst/s) -host_op_rate 1809140 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1047426540 # Simulator tick rate (ticks/s) -host_mem_usage 293648 # Number of bytes of host memory used -host_seconds 845.15 # Real time elapsed on the host +host_inst_rate 607816 # Simulator instruction rate (inst/s) +host_op_rate 1123920 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 650709398 # Simulator tick rate (ticks/s) +host_mem_usage 293412 # Number of bytes of host memory used +host_seconds 1360.41 # Real time elapsed on the host sim_insts 826877110 # Number of instructions simulated -sim_ops 1528988701 # Number of ops (including micro ops) simulated +sim_ops 1528988702 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 8546776520 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 2285655656 # Number of bytes read from this memory -system.physmem.bytes_read::total 10832432176 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 2285655658 # Number of bytes read from this memory +system.physmem.bytes_read::total 10832432178 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 8546776520 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 8546776520 # Number of instructions bytes read from this memory system.physmem.bytes_written::cpu.data 991849462 # Number of bytes written to this memory system.physmem.bytes_written::total 991849462 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 1068347065 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 384102185 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1452449250 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 384102186 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1452449251 # Number of read requests responded to by this memory system.physmem.num_writes::cpu.data 149160202 # Number of write requests responded to by this memory system.physmem.num_writes::total 149160202 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 9654872760 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2581992694 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 12236865453 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 9654872760 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 9654872760 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1120443518 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1120443518 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 9654872760 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 9654872754 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2581992695 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 12236865449 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 9654872754 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 9654872754 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1120443517 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1120443517 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 9654872754 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3702436212 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 13357308971 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 13357308966 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 1770458656 # number of cpu cycles simulated +system.cpu.numCycles 1770458657 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 826877110 # Number of instructions committed -system.cpu.committedOps 1528988701 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1528317560 # Number of integer alu accesses +system.cpu.committedOps 1528988702 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 1528317562 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured system.cpu.num_conditional_control_insts 92658795 # number of instructions that are conditional controls -system.cpu.num_int_insts 1528317560 # number of integer instructions +system.cpu.num_int_insts 1528317562 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 3855106255 # number of times the integer registers were read -system.cpu.num_int_register_writes 1614040852 # number of times the integer registers were written +system.cpu.num_int_register_reads 3855106260 # number of times the integer registers were read +system.cpu.num_int_register_writes 1614040854 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 533262342 # number of memory refs -system.cpu.num_load_insts 384102156 # Number of load instructions +system.cpu.num_mem_refs 533262343 # number of memory refs +system.cpu.num_load_insts 384102157 # Number of load instructions system.cpu.num_store_insts 149160186 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1770458656 # Number of busy cycles +system.cpu.num_busy_cycles 1770458657 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini index 32281f28e..e9b7f5ea7 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini @@ -117,7 +117,7 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=X86LocalApic -clock=500 +clock=8000 int_latency=1000 pio_addr=2305843009213693952 pio_latency=100000 @@ -168,6 +168,7 @@ type=CoherentBus block_size=64 clock=500 header_cycles=1 +system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side @@ -200,6 +201,7 @@ type=CoherentBus block_size=64 clock=1000 header_cycles=1 +system=system use_default_range=false width=8 master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simerr b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simerr index f5691fd64..e45cd058f 100755 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simerr +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simerr @@ -1,3 +1,2 @@ warn: Sockets disabled, not accepting gdb connections -warn: instruction 'fldcw_Mw' unimplemented hack: be nice to actually delete the event here diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout index f781a0970..d05acb658 100755 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout @@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/simple-tim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 16:30:44 -gem5 started Jan 23 2013 18:08:30 +gem5 compiled Mar 11 2013 13:21:48 +gem5 started Mar 11 2013 13:30:24 gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second @@ -71,4 +71,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 1647872848000 because target called exit() +Exiting @ tick 1647872849000 because target called exit() diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt index 532eed382..c3c3c6909 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 1.647873 # Number of seconds simulated -sim_ticks 1647872848000 # Number of ticks simulated -final_tick 1647872848000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 1647872849000 # Number of ticks simulated +final_tick 1647872849000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 579757 # Simulator instruction rate (inst/s) -host_op_rate 1072035 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1155389699 # Simulator tick rate (ticks/s) -host_mem_usage 301076 # Number of bytes of host memory used -host_seconds 1426.25 # Real time elapsed on the host +host_inst_rate 379189 # Simulator instruction rate (inst/s) +host_op_rate 701163 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 755680972 # Simulator tick rate (ticks/s) +host_mem_usage 300836 # Number of bytes of host memory used +host_seconds 2180.65 # Real time elapsed on the host sim_insts 826877110 # Number of instructions simulated -sim_ops 1528988701 # Number of ops (including micro ops) simulated +sim_ops 1528988702 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 120704 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 24272448 # Number of bytes read from this memory system.physmem.bytes_read::total 24393152 # Number of bytes read from this memory @@ -35,26 +35,26 @@ system.physmem.bw_total::cpu.inst 73248 # To system.physmem.bw_total::cpu.data 14729564 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 26154600 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 3295745696 # number of cpu cycles simulated +system.cpu.numCycles 3295745698 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 826877110 # Number of instructions committed -system.cpu.committedOps 1528988701 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1528317560 # Number of integer alu accesses +system.cpu.committedOps 1528988702 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 1528317562 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured system.cpu.num_conditional_control_insts 92658795 # number of instructions that are conditional controls -system.cpu.num_int_insts 1528317560 # number of integer instructions +system.cpu.num_int_insts 1528317562 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 3855106255 # number of times the integer registers were read -system.cpu.num_int_register_writes 1614040852 # number of times the integer registers were written +system.cpu.num_int_register_reads 3855106260 # number of times the integer registers were read +system.cpu.num_int_register_writes 1614040854 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 533262342 # number of memory refs -system.cpu.num_load_insts 384102156 # Number of load instructions +system.cpu.num_mem_refs 533262343 # number of memory refs +system.cpu.num_load_insts 384102157 # Number of load instructions system.cpu.num_store_insts 149160186 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 3295745696 # Number of busy cycles +system.cpu.num_busy_cycles 3295745698 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 1253 # number of replacements @@ -136,14 +136,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39153.518124 system.cpu.icache.overall_avg_mshr_miss_latency::total 39153.518124 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 348459 # number of replacements -system.cpu.l2cache.tagsinuse 29286.402681 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 29286.402664 # Cycle average of tags in use system.cpu.l2cache.total_refs 3655011 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 380814 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 9.597890 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 755936430000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21041.299350 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 139.758520 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 8105.344812 # Average occupied blocks per requestor +system.cpu.l2cache.warmup_cycle 755936431000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 21041.299337 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 139.758519 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 8105.344807 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.642129 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.004265 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.247355 # Average percentage of cache occupancy @@ -274,22 +274,22 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.324318 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.354198 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 2514362 # number of replacements -system.cpu.dcache.tagsinuse 4086.415786 # Cycle average of tags in use -system.cpu.dcache.total_refs 530743929 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4086.415783 # Cycle average of tags in use +system.cpu.dcache.total_refs 530743930 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 2518458 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 210.741624 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 8211723000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4086.415786 # Average occupied blocks per requestor +system.cpu.dcache.warmup_cycle 8211724000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4086.415783 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.997660 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.997660 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 382374771 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 382374771 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 382374772 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 382374772 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 148369158 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 148369158 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 530743929 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 530743929 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 530743929 # number of overall hits -system.cpu.dcache.overall_hits::total 530743929 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 530743930 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 530743930 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 530743930 # number of overall hits +system.cpu.dcache.overall_hits::total 530743930 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 1727414 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 1727414 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 791044 # number of WriteReq misses @@ -306,14 +306,14 @@ system.cpu.dcache.demand_miss_latency::cpu.data 48668884500 system.cpu.dcache.demand_miss_latency::total 48668884500 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 48668884500 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 48668884500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 384102185 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 384102185 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 384102186 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 384102186 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 533262387 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 533262387 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 533262387 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 533262387 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 533262388 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 533262388 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 533262388 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 533262388 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004497 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.004497 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005303 # miss rate for WriteReq accesses diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini index e5390bdb7..64ac15724 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini @@ -77,7 +77,7 @@ port=system.membus.slave[4] [system.cpu.interrupts] type=X86LocalApic -clock=500 +clock=8000 int_latency=1000 pio_addr=2305843009213693952 pio_latency=100000 @@ -128,6 +128,7 @@ type=CoherentBus block_size=64 clock=1000 header_cycles=1 +system=system use_default_range=false width=8 master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simerr b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simerr index f5691fd64..e45cd058f 100755 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simerr +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simerr @@ -1,3 +1,2 @@ warn: Sockets disabled, not accepting gdb connections -warn: instruction 'fldcw_Mw' unimplemented hack: be nice to actually delete the event here diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout index 2b9587722..654ed6b82 100755 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout @@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atom gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 16:30:44 -gem5 started Jan 23 2013 17:13:04 +gem5 compiled Mar 11 2013 13:21:48 +gem5 started Mar 11 2013 13:30:24 gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second @@ -26,4 +26,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 2846007227000 because target called exit() +Exiting @ tick 2846007227500 because target called exit() diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt index b864f8ff9..7cb3ea1a2 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt @@ -1,59 +1,59 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 2.846007 # Number of seconds simulated -sim_ticks 2846007227000 # Number of ticks simulated -final_tick 2846007227000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 2846007227500 # Number of ticks simulated +final_tick 2846007227500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1019064 # Simulator instruction rate (inst/s) -host_op_rate 1587794 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 964157561 # Simulator tick rate (ticks/s) -host_mem_usage 283172 # Number of bytes of host memory used -host_seconds 2951.81 # Real time elapsed on the host +host_inst_rate 922936 # Simulator instruction rate (inst/s) +host_op_rate 1438019 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 873209138 # Simulator tick rate (ticks/s) +host_mem_usage 283960 # Number of bytes of host memory used +host_seconds 3259.25 # Real time elapsed on the host sim_insts 3008081022 # Number of instructions simulated -sim_ops 4686862595 # Number of ops (including micro ops) simulated +sim_ops 4686862596 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 32105863056 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 5023868343 # Number of bytes read from this memory -system.physmem.bytes_read::total 37129731399 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 5023868345 # Number of bytes read from this memory +system.physmem.bytes_read::total 37129731401 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 32105863056 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 32105863056 # Number of instructions bytes read from this memory system.physmem.bytes_written::cpu.data 1544656792 # Number of bytes written to this memory system.physmem.bytes_written::total 1544656792 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 4013232882 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1239184745 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5252417627 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1239184746 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5252417628 # Number of read requests responded to by this memory system.physmem.num_writes::cpu.data 438528338 # Number of write requests responded to by this memory system.physmem.num_writes::total 438528338 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 11281019511 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 11281019509 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 1765233867 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13046253378 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 11281019511 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 11281019511 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13046253376 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 11281019509 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 11281019509 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 542745211 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 542745211 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 11281019511 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 11281019509 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2307979078 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 13588998589 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 13588998587 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 5692014455 # number of cpu cycles simulated +system.cpu.numCycles 5692014456 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 3008081022 # Number of instructions committed -system.cpu.committedOps 4686862595 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 4686862525 # Number of integer alu accesses +system.cpu.committedOps 4686862596 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 4686862527 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured system.cpu.num_conditional_control_insts 182173300 # number of instructions that are conditional controls -system.cpu.num_int_insts 4686862525 # number of integer instructions +system.cpu.num_int_insts 4686862527 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 11915474423 # number of times the integer registers were read -system.cpu.num_int_register_writes 5355771936 # number of times the integer registers were written +system.cpu.num_int_register_reads 11915474428 # number of times the integer registers were read +system.cpu.num_int_register_writes 5355771938 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 1677713083 # number of memory refs -system.cpu.num_load_insts 1239184745 # Number of load instructions +system.cpu.num_mem_refs 1677713084 # number of memory refs +system.cpu.num_load_insts 1239184746 # Number of load instructions system.cpu.num_store_insts 438528338 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 5692014455 # Number of busy cycles +system.cpu.num_busy_cycles 5692014456 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini index 55b9fc1a9..dfbf80a27 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini @@ -117,7 +117,7 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=X86LocalApic -clock=500 +clock=8000 int_latency=1000 pio_addr=2305843009213693952 pio_latency=100000 @@ -168,6 +168,7 @@ type=CoherentBus block_size=64 clock=500 header_cycles=1 +system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side @@ -200,6 +201,7 @@ type=CoherentBus block_size=64 clock=1000 header_cycles=1 +system=system use_default_range=false width=8 master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simerr b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simerr index f5691fd64..e45cd058f 100755 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simerr +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simerr @@ -1,3 +1,2 @@ warn: Sockets disabled, not accepting gdb connections -warn: instruction 'fldcw_Mw' unimplemented hack: be nice to actually delete the event here diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout index b6532688b..88a0bc2fc 100755 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout @@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timi gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 16:30:44 -gem5 started Jan 23 2013 18:35:45 +gem5 compiled Mar 11 2013 13:21:48 +gem5 started Mar 11 2013 13:30:24 gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second @@ -26,4 +26,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 5882580525000 because target called exit() +Exiting @ tick 5882580526000 because target called exit() diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt index 790f1ac3e..914311460 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 5.882581 # Number of seconds simulated -sim_ticks 5882580525000 # Number of ticks simulated -final_tick 5882580525000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 5882580526000 # Number of ticks simulated +final_tick 5882580526000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 639726 # Simulator instruction rate (inst/s) -host_op_rate 996751 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1251043124 # Simulator tick rate (ticks/s) -host_mem_usage 291744 # Number of bytes of host memory used -host_seconds 4702.14 # Real time elapsed on the host +host_inst_rate 579739 # Simulator instruction rate (inst/s) +host_op_rate 903286 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1133733281 # Simulator tick rate (ticks/s) +host_mem_usage 291512 # Number of bytes of host memory used +host_seconds 5188.68 # Real time elapsed on the host sim_insts 3008081022 # Number of instructions simulated -sim_ops 4686862595 # Number of ops (including micro ops) simulated +sim_ops 4686862596 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 43200 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 125326976 # Number of bytes read from this memory system.physmem.bytes_read::total 125370176 # Number of bytes read from this memory @@ -35,26 +35,26 @@ system.physmem.bw_total::cpu.inst 7344 # To system.physmem.bw_total::cpu.data 21304762 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 32392097 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 11765161050 # number of cpu cycles simulated +system.cpu.numCycles 11765161052 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 3008081022 # Number of instructions committed -system.cpu.committedOps 4686862595 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 4686862525 # Number of integer alu accesses +system.cpu.committedOps 4686862596 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 4686862527 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured system.cpu.num_conditional_control_insts 182173300 # number of instructions that are conditional controls -system.cpu.num_int_insts 4686862525 # number of integer instructions +system.cpu.num_int_insts 4686862527 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 11915474423 # number of times the integer registers were read -system.cpu.num_int_register_writes 5355771936 # number of times the integer registers were written +system.cpu.num_int_register_reads 11915474428 # number of times the integer registers were read +system.cpu.num_int_register_writes 5355771938 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 1677713083 # number of memory refs -system.cpu.num_load_insts 1239184745 # Number of load instructions +system.cpu.num_mem_refs 1677713084 # number of memory refs +system.cpu.num_load_insts 1239184746 # Number of load instructions system.cpu.num_store_insts 438528338 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 11765161050 # Number of busy cycles +system.cpu.num_busy_cycles 11765161052 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 10 # number of replacements @@ -136,14 +136,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53045.925926 system.cpu.icache.overall_avg_mshr_miss_latency::total 53045.925926 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 1926197 # number of replacements -system.cpu.l2cache.tagsinuse 31136.249384 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 31136.249379 # Cycle average of tags in use system.cpu.l2cache.total_refs 8965026 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 1955980 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 4.583393 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 340768634000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 15396.795536 # Average occupied blocks per requestor +system.cpu.l2cache.warmup_cycle 340768635000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 15396.795533 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.inst 25.641016 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 15713.812833 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 15713.812830 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.469873 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.000783 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.479548 # Average percentage of cache occupancy @@ -271,22 +271,22 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.064854 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.080657 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 9108581 # number of replacements -system.cpu.dcache.tagsinuse 4084.587031 # Cycle average of tags in use -system.cpu.dcache.total_refs 1668600406 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4084.587030 # Cycle average of tags in use +system.cpu.dcache.total_refs 1668600407 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 9112677 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 183.107599 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 58853921000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4084.587031 # Average occupied blocks per requestor +system.cpu.dcache.warmup_cycle 58853922000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4084.587030 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.997214 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.997214 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1231961895 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1231961895 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 1231961896 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1231961896 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 436638511 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 436638511 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1668600406 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1668600406 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1668600406 # number of overall hits -system.cpu.dcache.overall_hits::total 1668600406 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 1668600407 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1668600407 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1668600407 # number of overall hits +system.cpu.dcache.overall_hits::total 1668600407 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 7222850 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 7222850 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 1889827 # number of WriteReq misses @@ -303,14 +303,14 @@ system.cpu.dcache.demand_miss_latency::cpu.data 200710756000 system.cpu.dcache.demand_miss_latency::total 200710756000 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 200710756000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 200710756000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1239184745 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1239184745 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 1239184746 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1239184746 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 438528338 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 438528338 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 1677713083 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 1677713083 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 1677713083 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 1677713083 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 1677713084 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 1677713084 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 1677713084 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 1677713084 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.005829 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.005829 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.004309 # miss rate for WriteReq accesses diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini index c97d77597..32480c302 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini @@ -452,7 +452,7 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=X86LocalApic -clock=500 +clock=8000 int_latency=1000 pio_addr=2305843009213693952 pio_latency=100000 @@ -503,6 +503,7 @@ type=CoherentBus block_size=64 clock=500 header_cycles=1 +system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side @@ -535,6 +536,7 @@ type=CoherentBus block_size=64 clock=1000 header_cycles=1 +system=system use_default_range=false width=8 master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave @@ -542,25 +544,28 @@ slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_m [system.physmem] type=SimpleDRAM +activation_limit=4 addr_mapping=openmap banks_per_rank=8 +channels=1 clock=1000 conf_table_reported=false in_addr_map=true -lines_per_rowbuffer=64 -mem_sched_policy=fcfs +lines_per_rowbuffer=32 +mem_sched_policy=frfcfs null=false page_policy=open range=0:134217727 ranks_per_channel=2 read_buffer_size=32 -tBURST=4000 -tCL=14000 -tRCD=14000 +tBURST=5000 +tCL=13750 +tRCD=13750 tREFI=7800000 tRFC=300000 -tRP=14000 -tWTR=1000 +tRP=13750 +tWTR=7500 +tXAW=40000 write_buffer_size=32 write_thresh_perc=70 zero=false diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simerr b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simerr index f5691fd64..e45cd058f 100755 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simerr +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simerr @@ -1,3 +1,2 @@ warn: Sockets disabled, not accepting gdb connections -warn: instruction 'fldcw_Mw' unimplemented hack: be nice to actually delete the event here diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout index 617f03c25..5fce4f36f 100755 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout @@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/s gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 16:30:44 -gem5 started Jan 23 2013 19:08:30 +gem5 compiled Mar 11 2013 13:21:48 +gem5 started Mar 11 2013 13:30:24 gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sav @@ -26,4 +26,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 82648140000 because target called exit() +122 123 124 Exiting @ tick 82877188500 because target called exit() diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index f1f025306..7c1ec7886 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,55 +1,55 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.082836 # Number of seconds simulated -sim_ticks 82836235000 # Number of ticks simulated -final_tick 82836235000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.082877 # Number of seconds simulated +sim_ticks 82877188500 # Number of ticks simulated +final_tick 82877188500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 70076 # Simulator instruction rate (inst/s) -host_op_rate 117454 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 43952394 # Simulator tick rate (ticks/s) -host_mem_usage 275820 # Number of bytes of host memory used -host_seconds 1884.68 # Real time elapsed on the host +host_inst_rate 45467 # Simulator instruction rate (inst/s) +host_op_rate 76207 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 28531656 # Simulator tick rate (ticks/s) +host_mem_usage 321540 # Number of bytes of host memory used +host_seconds 2904.75 # Real time elapsed on the host sim_insts 132071192 # Number of instructions simulated -sim_ops 221362961 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 218368 # Number of bytes read from this memory +sim_ops 221362962 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 218496 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 124544 # Number of bytes read from this memory -system.physmem.bytes_read::total 342912 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 218368 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 218368 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3412 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 343040 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 218496 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 218496 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3414 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 1946 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5358 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2636141 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1503497 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4139638 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2636141 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2636141 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2636141 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1503497 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4139638 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::total 5360 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2636383 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1502754 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4139137 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2636383 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2636383 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2636383 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1502754 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4139137 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 5362 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 5515 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 342912 # Total number of bytes read from memory +system.physmem.cpureqs 5519 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 343040 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 342912 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 343040 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 153 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 275 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 290 # Track reads on a per bank basis +system.physmem.neitherReadNorWrite 157 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 274 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 293 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 321 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 274 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 310 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 367 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 377 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 379 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 273 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 309 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 368 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 378 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 381 # Track reads on a per bank basis system.physmem.perBankRdReqs::8 371 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 376 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 374 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 367 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 353 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 361 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 338 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 358 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 339 # Track reads on a per bank basis system.physmem.perBankRdReqs::14 355 # Track reads on a per bank basis system.physmem.perBankRdReqs::15 248 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 82836206000 # Total gap between requests +system.physmem.totGap 82877158000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -86,9 +86,9 @@ system.physmem.writePktSize::4 0 # Ca system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes system.physmem.rdQLenPdf::0 4169 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 943 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 199 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 43 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 940 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 206 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 39 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -149,14 +149,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 15721750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 132180500 # Sum of mem lat for all requests -system.physmem.totBusLat 26795000 # Total cycles spent in databus access -system.physmem.totBankLat 89663750 # Total cycles spent in bank access -system.physmem.avgQLat 2932.07 # Average queueing delay per request -system.physmem.avgBankLat 16722.07 # Average bank access latency per request -system.physmem.avgBusLat 4997.20 # Average bus latency per request -system.physmem.avgMemAccLat 24651.34 # Average memory access latency +system.physmem.totQLat 16751250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 133128750 # Sum of mem lat for all requests +system.physmem.totBusLat 26810000 # Total cycles spent in databus access +system.physmem.totBankLat 89567500 # Total cycles spent in bank access +system.physmem.avgQLat 3124.07 # Average queueing delay per request +system.physmem.avgBankLat 16704.12 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 24828.19 # Average memory access latency system.physmem.avgRdBW 4.14 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 4.14 # Average consumed read bandwidth in MB/s @@ -165,453 +165,455 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 4538 # Number of row buffer hits during reads +system.physmem.readRowHits 4540 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 84.63 # Row buffer hit rate for reads +system.physmem.readRowHitRate 84.67 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 15448751.59 # Average gap between requests -system.cpu.branchPred.lookups 19976706 # Number of BP lookups -system.cpu.branchPred.condPredicted 19976706 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 2014402 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 13812152 # Number of BTB lookups -system.cpu.branchPred.BTBHits 13105283 # Number of BTB hits +system.physmem.avgGap 15456389.03 # Average gap between requests +system.cpu.branchPred.lookups 19990631 # Number of BP lookups +system.cpu.branchPred.condPredicted 19990631 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 2016236 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 13900591 # Number of BTB lookups +system.cpu.branchPred.BTBHits 13121041 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.882267 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 94.391965 # BTB Hit Percentage system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 165672471 # number of cpu cycles simulated +system.cpu.numCycles 165754378 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 25870668 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 219126869 # Number of instructions fetch has processed -system.cpu.fetch.Branches 19976706 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 13105283 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 57628355 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 17696017 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 66630701 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 278 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 2007 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 114 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 24475842 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 426793 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 165546176 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.187647 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.326502 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 25900956 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 219294156 # Number of instructions fetch has processed +system.cpu.fetch.Branches 19990631 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 13121041 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 57660261 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 17705629 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 66643848 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 251 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1767 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 87 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 24505830 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 429319 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 165627301 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.187204 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.326012 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 109520431 66.16% 66.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3059143 1.85% 68.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2383042 1.44% 69.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2888379 1.74% 71.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 3450462 2.08% 73.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 3573116 2.16% 75.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 4323051 2.61% 78.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 2727876 1.65% 79.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 33620676 20.31% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 109570790 66.16% 66.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3065879 1.85% 68.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2385245 1.44% 69.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2897287 1.75% 71.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 3451303 2.08% 73.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 3579914 2.16% 75.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4327523 2.61% 78.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 2732307 1.65% 79.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 33617053 20.30% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 165546176 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.120580 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.322651 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 38775408 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 56644846 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 44737695 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9974174 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 15414053 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 354047911 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 15414053 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 46255302 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 14979465 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 23344 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 46561207 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 42312805 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 345686471 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 102 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 18031828 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 22149425 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 50 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 399403706 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 962076305 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 952204922 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 9871383 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 259428604 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 139975102 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1676 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1665 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 90583210 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 86793756 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 31811808 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 57862174 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 18818230 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 334054188 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 3459 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 267584091 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 253989 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 112238541 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 231222254 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 2214 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 165546176 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.616371 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.504250 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 165627301 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.120604 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.323007 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 38796677 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 56675107 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 44775430 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9959956 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 15420131 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 354106901 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 15420131 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 46276497 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 14977058 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 23177 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 46586117 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 42344321 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 345709417 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 99 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 18016892 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 22216647 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 104 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 399350509 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 961743278 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 951847615 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 9895663 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 259428606 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 139921903 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1677 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1668 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 90545817 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 86819200 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 31825632 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 57864226 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 18806791 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 334068514 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 3610 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 267647923 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 253259 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 112254554 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 230842120 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 2365 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 165627301 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.615965 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.504012 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 45159771 27.28% 27.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 46666031 28.19% 55.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 32872103 19.86% 75.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 19858979 12.00% 87.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 13194353 7.97% 95.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4779249 2.89% 98.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2330620 1.41% 99.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 541020 0.33% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 144050 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 45188875 27.28% 27.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 46699909 28.20% 55.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 32907630 19.87% 75.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 19828708 11.97% 87.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 13197780 7.97% 95.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4795004 2.90% 98.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2328707 1.41% 99.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 537256 0.32% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 143432 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 165546176 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 165627301 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 132244 4.97% 4.97% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.97% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.97% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2258982 84.96% 89.93% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 267651 10.07% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 131307 4.94% 4.94% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.94% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.94% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.94% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.94% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.94% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.94% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.94% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.94% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2258473 85.02% 89.96% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 266681 10.04% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1212144 0.45% 0.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 174232004 65.11% 65.57% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 1212174 0.45% 0.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 174292551 65.12% 65.57% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.57% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1599138 0.60% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 67256463 25.13% 91.30% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 23284342 8.70% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1599486 0.60% 66.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.17% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 67254766 25.13% 91.30% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 23288946 8.70% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 267584091 # Type of FU issued -system.cpu.iq.rate 1.615139 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2658877 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.009937 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 698266747 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 441935949 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 260335869 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 5360477 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 4651988 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 2579879 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 266334819 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2696005 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 19019917 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 267647923 # Type of FU issued +system.cpu.iq.rate 1.614726 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2656461 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.009925 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 698473214 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 441941062 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 260395422 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 5359653 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 4679108 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 2580004 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 266396647 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2695563 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 19008282 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 30144170 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 29191 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 297029 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 11296091 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 30169613 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 29317 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 298845 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 11309915 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 49411 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 7 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 49334 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 12 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 15414053 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 584332 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 268197 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 334057647 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 187603 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 86793756 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 31811808 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1663 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 154006 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 31822 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 297029 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1177472 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 918811 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 2096283 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 264704604 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 66268952 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2879487 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 15420131 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 575337 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 259825 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 334072124 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 191879 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 86819200 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 31825632 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1661 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 148151 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 27876 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 298845 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1178996 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 920787 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 2099783 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 264757229 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 66265318 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2890694 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 89158933 # number of memory reference insts executed -system.cpu.iew.exec_branches 14605846 # Number of branches executed -system.cpu.iew.exec_stores 22889981 # Number of stores executed -system.cpu.iew.exec_rate 1.597759 # Inst execution rate -system.cpu.iew.wb_sent 263752937 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 262915748 # cumulative count of insts written-back -system.cpu.iew.wb_producers 212158955 # num instructions producing a value -system.cpu.iew.wb_consumers 375269860 # num instructions consuming a value +system.cpu.iew.exec_refs 89162320 # number of memory reference insts executed +system.cpu.iew.exec_branches 14609733 # Number of branches executed +system.cpu.iew.exec_stores 22897002 # Number of stores executed +system.cpu.iew.exec_rate 1.597286 # Inst execution rate +system.cpu.iew.wb_sent 263814551 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 262975426 # cumulative count of insts written-back +system.cpu.iew.wb_producers 212208096 # num instructions producing a value +system.cpu.iew.wb_consumers 375332869 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.586961 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.565350 # average fanout of values written-back +system.cpu.iew.wb_rate 1.586537 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.565386 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 112734910 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 112746099 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2014608 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 150132123 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.474454 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.942401 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 2016423 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 150207170 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.473718 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.941598 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 50871002 33.88% 33.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 57276171 38.15% 72.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13824598 9.21% 81.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 12056402 8.03% 89.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4136994 2.76% 92.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2958422 1.97% 94.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1072501 0.71% 94.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 994968 0.66% 95.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6941065 4.62% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 50947202 33.92% 33.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 57273647 38.13% 72.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13797241 9.19% 81.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 12067854 8.03% 89.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4154161 2.77% 92.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2974218 1.98% 94.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1064553 0.71% 94.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1010133 0.67% 95.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6918161 4.61% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 150132123 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 150207170 # Number of insts commited each cycle system.cpu.commit.committedInsts 132071192 # Number of instructions committed -system.cpu.commit.committedOps 221362961 # Number of ops (including micro ops) committed +system.cpu.commit.committedOps 221362962 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 77165303 # Number of memory references committed -system.cpu.commit.loads 56649586 # Number of loads committed +system.cpu.commit.refs 77165304 # Number of memory references committed +system.cpu.commit.loads 56649587 # Number of loads committed system.cpu.commit.membars 0 # Number of memory barriers committed system.cpu.commit.branches 12326938 # Number of branches committed system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. -system.cpu.commit.int_insts 220339551 # Number of committed integer instructions. +system.cpu.commit.int_insts 220339553 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6941065 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6918161 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 477288929 # The number of ROB reads -system.cpu.rob.rob_writes 683644230 # The number of ROB writes -system.cpu.timesIdled 2956 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 126295 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 477398070 # The number of ROB reads +system.cpu.rob.rob_writes 683673273 # The number of ROB writes +system.cpu.timesIdled 2993 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 127077 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 132071192 # Number of Instructions Simulated -system.cpu.committedOps 221362961 # Number of Ops (including micro ops) Simulated +system.cpu.committedOps 221362962 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 132071192 # Number of Instructions Simulated -system.cpu.cpi 1.254418 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.254418 # CPI: Total CPI of All Threads -system.cpu.ipc 0.797182 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.797182 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 562757952 # number of integer regfile reads -system.cpu.int_regfile_writes 298813122 # number of integer regfile writes -system.cpu.fp_regfile_reads 3531630 # number of floating regfile reads -system.cpu.fp_regfile_writes 2237821 # number of floating regfile writes -system.cpu.misc_regfile_reads 137110805 # number of misc regfile reads -system.cpu.misc_regfile_writes 844 # number of misc regfile writes -system.cpu.icache.replacements 4901 # number of replacements -system.cpu.icache.tagsinuse 1627.835837 # Cycle average of tags in use -system.cpu.icache.total_refs 24466683 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 6871 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 3560.862029 # Average number of references to valid blocks. +system.cpu.cpi 1.255038 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.255038 # CPI: Total CPI of All Threads +system.cpu.ipc 0.796789 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.796789 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 562793335 # number of integer regfile reads +system.cpu.int_regfile_writes 298868750 # number of integer regfile writes +system.cpu.fp_regfile_reads 3530164 # number of floating regfile reads +system.cpu.fp_regfile_writes 2239527 # number of floating regfile writes +system.cpu.misc_regfile_reads 137140339 # number of misc regfile reads +system.cpu.misc_regfile_writes 845 # number of misc regfile writes +system.cpu.icache.replacements 4944 # number of replacements +system.cpu.icache.tagsinuse 1623.744998 # Cycle average of tags in use +system.cpu.icache.total_refs 24496606 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 6912 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 3544.069155 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1627.835837 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.794842 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.794842 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 24466683 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 24466683 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 24466683 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 24466683 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 24466683 # number of overall hits -system.cpu.icache.overall_hits::total 24466683 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 9159 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 9159 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 9159 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 9159 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 9159 # number of overall misses -system.cpu.icache.overall_misses::total 9159 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 269675497 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 269675497 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 269675497 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 269675497 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 269675497 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 269675497 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 24475842 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 24475842 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 24475842 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 24475842 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 24475842 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 24475842 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000374 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000374 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000374 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000374 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000374 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000374 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29443.770827 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 29443.770827 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 29443.770827 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 29443.770827 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 29443.770827 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 29443.770827 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 864 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1623.744998 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.792844 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.792844 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 24496606 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 24496606 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 24496606 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 24496606 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 24496606 # number of overall hits +system.cpu.icache.overall_hits::total 24496606 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 9224 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 9224 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 9224 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 9224 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 9224 # number of overall misses +system.cpu.icache.overall_misses::total 9224 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 273910997 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 273910997 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 273910997 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 273910997 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 273910997 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 273910997 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 24505830 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 24505830 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 24505830 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 24505830 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 24505830 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 24505830 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000376 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000376 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000376 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000376 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000376 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000376 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29695.468018 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 29695.468018 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 29695.468018 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 29695.468018 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 29695.468018 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 29695.468018 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 837 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 26 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 27 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 33.230769 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 31 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2133 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2133 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2133 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2133 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2133 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2133 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7026 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 7026 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 7026 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 7026 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 7026 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 7026 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 205371497 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 205371497 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 205371497 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 205371497 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 205371497 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 205371497 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000287 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000287 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000287 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000287 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000287 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000287 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 29230.215912 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 29230.215912 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 29230.215912 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 29230.215912 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 29230.215912 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 29230.215912 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2153 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2153 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2153 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2153 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2153 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2153 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7071 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 7071 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 7071 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 7071 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 7071 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 7071 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 206824497 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 206824497 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 206824497 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 206824497 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 206824497 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 206824497 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000289 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000289 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000289 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000289 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000289 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000289 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 29249.681375 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 29249.681375 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 29249.681375 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 29249.681375 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 29249.681375 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 29249.681375 # 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Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 283.750928 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.000044 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.068560 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.008659 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.077263 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 3460 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 30 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 3490 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 13 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 13 # number of Writeback hits +system.cpu.l2cache.occ_blocks::writebacks 1.684861 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2246.789003 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 282.609466 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.000051 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.068567 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.008625 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.077243 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 3499 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 29 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 3528 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 14 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 14 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits system.cpu.l2cache.ReadExReq_hits::cpu.data 7 # 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average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37117.537047 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31666.239228 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31666.239228 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35530.483739 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34831.356080 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 35276.362178 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35530.483739 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34831.356080 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 35276.362178 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31509.320694 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31509.320694 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35812.400703 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34925.212012 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 35490.087467 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35812.400703 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34925.212012 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 35490.087467 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 56 # number of replacements -system.cpu.dcache.tagsinuse 1416.460930 # Cycle average of tags in use -system.cpu.dcache.total_refs 67604390 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1983 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 34091.976803 # Average number of references to valid blocks. +system.cpu.dcache.replacements 55 # number of replacements +system.cpu.dcache.tagsinuse 1413.084187 # Cycle average of tags in use +system.cpu.dcache.total_refs 67612398 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1982 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 34113.217962 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1416.460930 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.345816 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.345816 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 47090189 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 47090189 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 20514015 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 20514015 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 67604204 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 67604204 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 67604204 # number of overall hits -system.cpu.dcache.overall_hits::total 67604204 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 791 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 791 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1716 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1716 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2507 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2507 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2507 # number of overall misses -system.cpu.dcache.overall_misses::total 2507 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 39751500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 39751500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 77402500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 77402500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 117154000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 117154000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 117154000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 117154000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 47090980 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 47090980 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::cpu.data 1413.084187 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.344991 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.344991 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 47098181 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 47098181 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20514009 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20514009 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 67612190 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 67612190 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 67612190 # number of overall hits +system.cpu.dcache.overall_hits::total 67612190 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 831 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 831 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1722 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1722 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2553 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2553 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2553 # number of overall misses +system.cpu.dcache.overall_misses::total 2553 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 41843000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 41843000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 77380000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 77380000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 119223000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 119223000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 119223000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 119223000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 47099012 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 47099012 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 67606711 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 67606711 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 67606711 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 67606711 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000017 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 67614743 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 67614743 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 67614743 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 67614743 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000018 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000018 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000084 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.000084 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000037 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000037 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000037 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000037 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50254.740834 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 50254.740834 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45106.351981 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 45106.351981 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 46730.753889 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 46730.753889 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 46730.753889 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 46730.753889 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 35 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.000038 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000038 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000038 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000038 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50352.587244 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 50352.587244 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44936.120790 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 44936.120790 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 46699.177438 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 46699.177438 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 46699.177438 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 46699.177438 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 70 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 17.500000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 23.333333 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 13 # number of writebacks -system.cpu.dcache.writebacks::total 13 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 367 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 367 # number of ReadReq MSHR hits +system.cpu.dcache.writebacks::writebacks 14 # number of writebacks +system.cpu.dcache.writebacks::total 14 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 410 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 410 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 1 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 368 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 368 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 368 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 368 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 424 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 424 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1715 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1715 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2139 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2139 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2139 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2139 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24221500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 24221500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 73937000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 73937000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 98158500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 98158500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 98158500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 98158500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 411 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 411 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 411 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 411 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 421 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 421 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1721 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1721 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2142 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2142 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2142 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2142 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24554500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 24554500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 73902500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 73902500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 98457000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 98457000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 98457000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 98457000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for WriteReq accesses @@ -772,14 +774,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000032 system.cpu.dcache.demand_mshr_miss_rate::total 0.000032 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000032 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 57126.179245 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 57126.179245 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43111.953353 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43111.953353 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45889.901823 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 45889.901823 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45889.901823 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 45889.901823 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 58324.228029 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 58324.228029 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42941.603719 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42941.603719 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45964.985994 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 45964.985994 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45964.985994 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 45964.985994 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini index 222b14efd..ce16e921c 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini @@ -77,7 +77,7 @@ port=system.membus.slave[4] [system.cpu.interrupts] type=X86LocalApic -clock=500 +clock=8000 int_latency=1000 pio_addr=2305843009213693952 pio_latency=100000 @@ -128,6 +128,7 @@ type=CoherentBus block_size=64 clock=1000 header_cycles=1 +system=system use_default_range=false width=8 master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simerr b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simerr index f5691fd64..e45cd058f 100755 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simerr +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simerr @@ -1,3 +1,2 @@ warn: Sockets disabled, not accepting gdb connections -warn: instruction 'fldcw_Mw' unimplemented hack: be nice to actually delete the event here diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout index 7bcffd6bf..0a35f8c74 100755 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout @@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atom gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 16:30:44 -gem5 started Jan 23 2013 18:05:52 +gem5 compiled Mar 11 2013 13:21:48 +gem5 started Mar 11 2013 13:30:35 gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic/smred.sav @@ -26,4 +26,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 131393067500 because target called exit() +122 123 124 Exiting @ tick 131393068000 because target called exit() diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt index 4c14b976b..bb0c7510f 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt @@ -1,59 +1,59 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.131393 # Number of seconds simulated -sim_ticks 131393067500 # Number of ticks simulated -final_tick 131393067500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 131393068000 # Number of ticks simulated +final_tick 131393068000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 897941 # Simulator instruction rate (inst/s) -host_op_rate 1505028 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 893330062 # Simulator tick rate (ticks/s) -host_mem_usage 308196 # Number of bytes of host memory used -host_seconds 147.08 # Real time elapsed on the host +host_inst_rate 538543 # Simulator instruction rate (inst/s) +host_op_rate 902645 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 535777601 # Simulator tick rate (ticks/s) +host_mem_usage 308992 # Number of bytes of host memory used +host_seconds 245.24 # Real time elapsed on the host sim_insts 132071193 # Number of instructions simulated -sim_ops 221362962 # Number of ops (including micro ops) simulated +sim_ops 221362963 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 1387954936 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 310423750 # Number of bytes read from this memory -system.physmem.bytes_read::total 1698378686 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 310423752 # Number of bytes read from this memory +system.physmem.bytes_read::total 1698378688 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 1387954936 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 1387954936 # Number of instructions bytes read from this memory system.physmem.bytes_written::cpu.data 99822191 # Number of bytes written to this memory system.physmem.bytes_written::total 99822191 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 173494367 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 56682004 # Number of read requests responded to by this memory -system.physmem.num_reads::total 230176371 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 56682005 # Number of read requests responded to by this memory +system.physmem.num_reads::total 230176372 # Number of read requests responded to by this memory system.physmem.num_writes::cpu.data 20515731 # Number of write requests responded to by this memory system.physmem.num_writes::total 20515731 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 10563380264 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2362558055 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 12925938319 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 10563380264 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 10563380264 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 759721901 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 759721901 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 10563380264 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3122279956 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 13685660219 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 10563380223 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2362558061 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 12925938285 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 10563380223 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 10563380223 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 759721898 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 759721898 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 10563380223 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3122279959 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 13685660183 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 262786136 # number of cpu cycles simulated +system.cpu.numCycles 262786137 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 132071193 # Number of instructions committed -system.cpu.committedOps 221362962 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 220339552 # Number of integer alu accesses +system.cpu.committedOps 221362963 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 220339554 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured system.cpu.num_conditional_control_insts 8268466 # number of instructions that are conditional controls -system.cpu.num_int_insts 220339552 # number of integer instructions +system.cpu.num_int_insts 220339554 # number of integer instructions system.cpu.num_fp_insts 2162459 # number of float instructions -system.cpu.num_int_register_reads 616958553 # number of times the integer registers were read -system.cpu.num_int_register_writes 257597201 # number of times the integer registers were written +system.cpu.num_int_register_reads 616958558 # number of times the integer registers were read +system.cpu.num_int_register_writes 257597203 # number of times the integer registers were written system.cpu.num_fp_register_reads 3037165 # number of times the floating registers were read system.cpu.num_fp_register_writes 1831403 # number of times the floating registers were written -system.cpu.num_mem_refs 77165303 # number of memory refs -system.cpu.num_load_insts 56649586 # Number of load instructions +system.cpu.num_mem_refs 77165304 # number of memory refs +system.cpu.num_load_insts 56649587 # Number of load instructions system.cpu.num_store_insts 20515717 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 262786136 # Number of busy cycles +system.cpu.num_busy_cycles 262786137 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini index 368cbf930..93ab42722 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini @@ -117,7 +117,7 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=X86LocalApic -clock=500 +clock=8000 int_latency=1000 pio_addr=2305843009213693952 pio_latency=100000 @@ -168,6 +168,7 @@ type=CoherentBus block_size=64 clock=500 header_cycles=1 +system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side @@ -200,6 +201,7 @@ type=CoherentBus block_size=64 clock=1000 header_cycles=1 +system=system use_default_range=false width=8 master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simerr b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simerr index f5691fd64..e45cd058f 100755 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simerr +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simerr @@ -1,3 +1,2 @@ warn: Sockets disabled, not accepting gdb connections -warn: instruction 'fldcw_Mw' unimplemented hack: be nice to actually delete the event here diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout index ff40493ec..4e4920ac0 100755 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout @@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timi gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 16:30:44 -gem5 started Jan 23 2013 16:30:54 +gem5 compiled Mar 11 2013 13:21:48 +gem5 started Mar 11 2013 13:30:24 gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing/smred.sav @@ -26,4 +26,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 250953956000 because target called exit() +122 123 124 Exiting @ tick 250953957000 because target called exit() diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt index 004f7b9ea..1372cb624 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.250954 # Number of seconds simulated -sim_ticks 250953956000 # Number of ticks simulated -final_tick 250953956000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 250953957000 # Number of ticks simulated +final_tick 250953957000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 580885 # Simulator instruction rate (inst/s) -host_op_rate 973614 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1103763503 # Simulator tick rate (ticks/s) -host_mem_usage 316652 # Number of bytes of host memory used -host_seconds 227.36 # Real time elapsed on the host +host_inst_rate 308460 # Simulator instruction rate (inst/s) +host_op_rate 517006 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 586117013 # Simulator tick rate (ticks/s) +host_mem_usage 316420 # Number of bytes of host memory used +host_seconds 428.16 # Real time elapsed on the host sim_insts 132071193 # Number of instructions simulated -sim_ops 221362962 # Number of ops (including micro ops) simulated +sim_ops 221362963 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 181760 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 121280 # Number of bytes read from this memory system.physmem.bytes_read::total 303040 # Number of bytes read from this memory @@ -28,35 +28,35 @@ system.physmem.bw_total::cpu.inst 724276 # To system.physmem.bw_total::cpu.data 483276 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 1207552 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 501907912 # number of cpu cycles simulated +system.cpu.numCycles 501907914 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 132071193 # Number of instructions committed -system.cpu.committedOps 221362962 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 220339552 # Number of integer alu accesses +system.cpu.committedOps 221362963 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 220339554 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured system.cpu.num_conditional_control_insts 8268466 # number of instructions that are conditional controls -system.cpu.num_int_insts 220339552 # number of integer instructions +system.cpu.num_int_insts 220339554 # number of integer instructions system.cpu.num_fp_insts 2162459 # number of float instructions -system.cpu.num_int_register_reads 616958553 # number of times the integer registers were read -system.cpu.num_int_register_writes 257597201 # number of times the integer registers were written +system.cpu.num_int_register_reads 616958558 # number of times the integer registers were read +system.cpu.num_int_register_writes 257597203 # number of times the integer registers were written system.cpu.num_fp_register_reads 3037165 # number of times the floating registers were read system.cpu.num_fp_register_writes 1831403 # number of times the floating registers were written -system.cpu.num_mem_refs 77165303 # number of memory refs -system.cpu.num_load_insts 56649586 # Number of load instructions +system.cpu.num_mem_refs 77165304 # number of memory refs +system.cpu.num_load_insts 56649587 # Number of load instructions system.cpu.num_store_insts 20515717 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 501907912 # Number of busy cycles +system.cpu.num_busy_cycles 501907914 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 2836 # number of replacements -system.cpu.icache.tagsinuse 1455.296648 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1455.296642 # Cycle average of tags in use system.cpu.icache.total_refs 173489674 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 4694 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 36959.879421 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1455.296648 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 1455.296642 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.710594 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.710594 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 173489674 # number of ReadReq hits @@ -129,14 +129,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36414.784832 system.cpu.icache.overall_avg_mshr_miss_latency::total 36414.784832 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2058.178694 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 2058.178686 # Cycle average of tags in use system.cpu.l2cache.total_refs 1862 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 3164 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.588496 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.occ_blocks::writebacks 0.021744 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1829.978587 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 228.178363 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1829.978580 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 228.178362 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.000001 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.055847 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.006963 # Average percentage of cache occupancy @@ -265,22 +265,22 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 41 # number of replacements -system.cpu.dcache.tagsinuse 1363.457576 # Cycle average of tags in use -system.cpu.dcache.total_refs 77195830 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 1363.457571 # Cycle average of tags in use +system.cpu.dcache.total_refs 77195831 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 1905 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 40522.745407 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 40522.745932 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1363.457576 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 1363.457571 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.332875 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.332875 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 56681677 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 56681677 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 56681678 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 56681678 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 20514153 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 20514153 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 77195830 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 77195830 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 77195830 # number of overall hits -system.cpu.dcache.overall_hits::total 77195830 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 77195831 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 77195831 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 77195831 # number of overall hits +system.cpu.dcache.overall_hits::total 77195831 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 327 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 327 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 1578 # number of WriteReq misses @@ -297,14 +297,14 @@ system.cpu.dcache.demand_miss_latency::cpu.data 104356500 system.cpu.dcache.demand_miss_latency::total 104356500 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 104356500 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 104356500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 56682004 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 56682004 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 56682005 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 56682005 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 77197735 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 77197735 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 77197735 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 77197735 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 77197736 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 77197736 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 77197736 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 77197736 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000006 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000006 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000077 # miss rate for WriteReq accesses diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simerr b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simerr index f5691fd64..e45cd058f 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simerr +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simerr @@ -1,3 +1,2 @@ warn: Sockets disabled, not accepting gdb connections -warn: instruction 'fldcw_Mw' unimplemented hack: be nice to actually delete the event here diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout index 7ce584d65..745f3a55b 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout @@ -3,11 +3,11 @@ Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing/ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 16:30:44 -gem5 started Jan 23 2013 18:48:24 +gem5 compiled Mar 11 2013 13:21:48 +gem5 started Mar 11 2013 13:21:58 gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 15014000 because target called exit() +Exiting @ tick 15471000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index 03f9c34cb..50eb0a35f 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000015 # Number of seconds simulated -sim_ticks 15468000 # Number of ticks simulated -final_tick 15468000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 15471000 # Number of ticks simulated +final_tick 15471000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 31901 # Simulator instruction rate (inst/s) -host_op_rate 57781 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 91692634 # Simulator tick rate (ticks/s) -host_mem_usage 241568 # Number of bytes of host memory used -host_seconds 0.17 # Real time elapsed on the host +host_inst_rate 25126 # Simulator instruction rate (inst/s) +host_op_rate 45518 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 72243012 # Simulator tick rate (ticks/s) +host_mem_usage 287412 # Number of bytes of host memory used +host_seconds 0.21 # Real time elapsed on the host sim_insts 5380 # Number of instructions simulated -sim_ops 9746 # Number of ops (including micro ops) simulated +sim_ops 9747 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 19392 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 9344 # Number of bytes read from this memory system.physmem.bytes_read::total 28736 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 19392 # Nu system.physmem.num_reads::cpu.inst 303 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 146 # Number of read requests responded to by this memory system.physmem.num_reads::total 449 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1253685027 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 604085855 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1857770882 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1253685027 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1253685027 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1253685027 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 604085855 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1857770882 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1253441924 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 603968716 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1857410639 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1253441924 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1253441924 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1253441924 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 603968716 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1857410639 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 451 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 451 # Reqs generatd by CPU via cache - shady @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 15452000 # Total gap between requests +system.physmem.totGap 15455000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -85,8 +85,8 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 231 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 151 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 230 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 152 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 58 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see @@ -157,9 +157,9 @@ system.physmem.avgQLat 4211.75 # Av system.physmem.avgBankLat 19969.51 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request system.physmem.avgMemAccLat 29181.26 # Average memory access latency -system.physmem.avgRdBW 1857.77 # Average achieved read bandwidth in MB/s +system.physmem.avgRdBW 1857.41 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1857.77 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1857.41 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 14.51 # Data bus utilization in percentage @@ -169,318 +169,319 @@ system.physmem.readRowHits 333 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 73.84 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 34261.64 # Average gap between requests -system.cpu.branchPred.lookups 2995 # Number of BP lookups -system.cpu.branchPred.condPredicted 2995 # Number of conditional branches predicted +system.physmem.avgGap 34268.29 # Average gap between requests +system.cpu.branchPred.lookups 2992 # Number of BP lookups +system.cpu.branchPred.condPredicted 2992 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 546 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2485 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 2482 # Number of BTB lookups system.cpu.branchPred.BTBHits 793 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 31.911469 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 31.950040 # BTB Hit Percentage system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 30937 # number of cpu cycles simulated +system.cpu.numCycles 30943 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 8904 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 14405 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2995 # Number of branches that fetch encountered +system.cpu.fetch.icacheStallCycles 8896 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 14387 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2992 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 793 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 3911 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2416 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 3684 # Number of cycles fetch has spent blocked +system.cpu.fetch.Cycles 3908 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2410 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 3707 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 34 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 178 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 18 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 1874 # Number of cache lines fetched +system.cpu.fetch.CacheLines 1872 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 285 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 18552 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.371173 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.873073 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 18558 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.369490 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.871739 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 14740 79.45% 79.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 189 1.02% 80.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 154 0.83% 81.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 193 1.04% 82.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 163 0.88% 83.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 168 0.91% 84.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 265 1.43% 85.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 160 0.86% 86.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2520 13.58% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 14749 79.48% 79.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 190 1.02% 80.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 153 0.82% 81.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 193 1.04% 82.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 163 0.88% 83.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 168 0.91% 84.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 264 1.42% 85.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 160 0.86% 86.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2518 13.57% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 18552 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.096810 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.465624 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 9434 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 3628 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3523 # Number of cycles decode is running +system.cpu.fetch.rateDist::total 18558 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.096694 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.464952 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 9433 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 3646 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 3518 # Number of cycles decode is running system.cpu.decode.UnblockCycles 144 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1823 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 24308 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1823 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 9778 # Number of cycles rename is idle +system.cpu.decode.SquashCycles 1817 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 24275 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1817 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 9777 # Number of cycles rename is idle system.cpu.rename.BlockCycles 2398 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 477 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 3309 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 767 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 22819 # Number of instructions processed by rename +system.cpu.rename.serializeStallCycles 497 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 3304 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 765 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 22769 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 7 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 39 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 651 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 24896 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 54742 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 54726 # Number of integer rename lookups +system.cpu.rename.LSQFullEvents 649 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 24875 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 54688 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 54672 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 11061 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 13835 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 31 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 31 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 2054 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2204 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1750 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.CommittedMaps 11063 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 13812 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 34 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 34 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 2061 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2202 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1748 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 11 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 7 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 20351 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 35 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 17307 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 209 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 9863 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 13657 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 23 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 18552 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.932891 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.792260 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 20301 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 36 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 17266 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 205 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 9813 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 13640 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 24 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 18558 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.930380 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.788216 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 13164 70.96% 70.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1399 7.54% 78.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1053 5.68% 84.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 693 3.74% 87.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 728 3.92% 91.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 621 3.35% 95.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 594 3.20% 98.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 258 1.39% 99.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 13171 70.97% 70.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1403 7.56% 78.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1055 5.68% 84.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 693 3.73% 87.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 728 3.92% 91.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 621 3.35% 95.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 594 3.20% 98.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 251 1.35% 99.77% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 42 0.23% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 18552 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 18558 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 134 76.57% 76.57% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 76.57% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 76.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 76.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 76.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 76.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 76.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 76.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 76.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 76.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 76.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 76.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 76.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 76.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 76.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 76.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 76.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 76.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 76.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 76.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 76.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 76.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 76.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 76.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 76.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 76.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 76.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 76.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 76.57% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 20 11.43% 88.00% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 21 12.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 132 76.30% 76.30% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 76.30% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 76.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 76.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 76.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 76.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 76.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 76.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 76.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 76.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 76.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 76.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 76.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 76.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 76.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 76.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 76.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 76.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 76.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 76.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 76.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 76.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 76.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 76.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 76.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 76.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 76.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 76.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 76.30% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 20 11.56% 87.86% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 21 12.14% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 4 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 13916 80.41% 80.43% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.43% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.43% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1905 11.01% 91.44% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1482 8.56% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 3 0.02% 0.02% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 13880 80.39% 80.41% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.41% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.41% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1903 11.02% 91.43% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1480 8.57% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 17307 # Type of FU issued -system.cpu.iq.rate 0.559427 # Inst issue rate -system.cpu.iq.fu_busy_cnt 175 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010112 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 53542 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 30256 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 15949 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 17266 # Type of FU issued +system.cpu.iq.rate 0.557994 # Inst issue rate +system.cpu.iq.fu_busy_cnt 173 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010020 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 53460 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 30157 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 15915 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 17474 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 17432 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 160 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 159 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1152 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1149 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 14 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 815 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 813 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 13 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1823 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 1817 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 1705 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 33 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 20386 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 20337 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 33 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2204 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1750 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 31 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispLoadInsts 2202 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1748 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 32 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 56 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 607 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 663 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 16378 # Number of executed instructions +system.cpu.iew.predictedNotTakenIncorrect 606 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 662 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 16344 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 1780 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 929 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecSquashedInsts 922 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3145 # number of memory reference insts executed -system.cpu.iew.exec_branches 1625 # Number of branches executed -system.cpu.iew.exec_stores 1365 # Number of stores executed -system.cpu.iew.exec_rate 0.529398 # Inst execution rate -system.cpu.iew.wb_sent 16147 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 15953 # cumulative count of insts written-back -system.cpu.iew.wb_producers 10136 # num instructions producing a value -system.cpu.iew.wb_consumers 15661 # num instructions consuming a value +system.cpu.iew.exec_refs 3142 # number of memory reference insts executed +system.cpu.iew.exec_branches 1619 # Number of branches executed +system.cpu.iew.exec_stores 1362 # Number of stores executed +system.cpu.iew.exec_rate 0.528197 # Inst execution rate +system.cpu.iew.wb_sent 16113 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 15919 # cumulative count of insts written-back +system.cpu.iew.wb_producers 10115 # num instructions producing a value +system.cpu.iew.wb_consumers 15622 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.515661 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.647213 # average fanout of values written-back +system.cpu.iew.wb_rate 0.514462 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.647484 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 10639 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 10589 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 572 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 16729 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.582581 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.458500 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 16741 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.582223 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.458057 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 13195 78.88% 78.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1327 7.93% 86.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 13206 78.88% 78.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1328 7.93% 86.82% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 594 3.55% 90.36% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 704 4.21% 94.57% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::4 355 2.12% 96.69% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 141 0.84% 97.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 118 0.71% 98.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 118 0.70% 98.24% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::7 74 0.44% 98.68% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 221 1.32% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 16729 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 16741 # Number of insts commited each cycle system.cpu.commit.committedInsts 5380 # Number of instructions committed -system.cpu.commit.committedOps 9746 # Number of ops (including micro ops) committed +system.cpu.commit.committedOps 9747 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 1987 # Number of memory references committed -system.cpu.commit.loads 1052 # Number of loads committed +system.cpu.commit.refs 1988 # Number of memory references committed +system.cpu.commit.loads 1053 # Number of loads committed system.cpu.commit.membars 0 # Number of memory barriers committed system.cpu.commit.branches 1208 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 9652 # Number of committed integer instructions. +system.cpu.commit.int_insts 9654 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. system.cpu.commit.bw_lim_events 221 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 36893 # The number of ROB reads -system.cpu.rob.rob_writes 42622 # The number of ROB writes +system.cpu.rob.rob_reads 36856 # The number of ROB reads +system.cpu.rob.rob_writes 42518 # The number of ROB writes system.cpu.timesIdled 155 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 12385 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5380 # Number of Instructions Simulated -system.cpu.committedOps 9746 # Number of Ops (including micro ops) Simulated +system.cpu.committedOps 9747 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5380 # Number of Instructions Simulated -system.cpu.cpi 5.750372 # CPI: Cycles Per Instruction -system.cpu.cpi_total 5.750372 # CPI: Total CPI of All Threads -system.cpu.ipc 0.173902 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.173902 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 28821 # number of integer regfile reads -system.cpu.int_regfile_writes 17168 # number of integer regfile writes +system.cpu.cpi 5.751487 # CPI: Cycles Per Instruction +system.cpu.cpi_total 5.751487 # CPI: Total CPI of All Threads +system.cpu.ipc 0.173868 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.173868 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 28772 # number of integer regfile reads +system.cpu.int_regfile_writes 17143 # number of integer regfile writes system.cpu.fp_regfile_reads 4 # number of floating regfile reads -system.cpu.misc_regfile_reads 7143 # number of misc regfile reads +system.cpu.misc_regfile_reads 7129 # number of misc regfile reads +system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 144.824422 # Cycle average of tags in use -system.cpu.icache.total_refs 1475 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 144.801510 # Cycle average of tags in use +system.cpu.icache.total_refs 1474 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 304 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4.851974 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 4.848684 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 144.824422 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.070715 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.070715 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1475 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1475 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1475 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1475 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1475 # number of overall hits -system.cpu.icache.overall_hits::total 1475 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 399 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 399 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 399 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 399 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 399 # number of overall misses -system.cpu.icache.overall_misses::total 399 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 20611500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 20611500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 20611500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 20611500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 20611500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 20611500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1874 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1874 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1874 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1874 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1874 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1874 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.212914 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.212914 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.212914 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.212914 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.212914 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.212914 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 51657.894737 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 51657.894737 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 51657.894737 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 51657.894737 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 51657.894737 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 51657.894737 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 144.801510 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.070704 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.070704 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1474 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1474 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1474 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1474 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1474 # number of overall hits +system.cpu.icache.overall_hits::total 1474 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 398 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 398 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 398 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 398 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 398 # number of overall misses +system.cpu.icache.overall_misses::total 398 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 20575500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 20575500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 20575500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 20575500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 20575500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 20575500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1872 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1872 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1872 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1872 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1872 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1872 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.212607 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.212607 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.212607 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.212607 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.212607 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.212607 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 51697.236181 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 51697.236181 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 51697.236181 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 51697.236181 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 51697.236181 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 51697.236181 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 312 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 7 # number of cycles access was blocked @@ -489,12 +490,12 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 44.571429 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 95 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 95 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 95 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 95 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 95 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 95 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 94 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 94 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 94 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 94 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 94 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 94 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 304 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 304 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 304 # number of demand (read+write) MSHR misses @@ -507,12 +508,12 @@ system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16157000 system.cpu.icache.demand_mshr_miss_latency::total 16157000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16157000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 16157000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.162220 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.162220 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.162220 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.162220 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.162220 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.162220 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.162393 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.162393 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.162393 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.162393 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.162393 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.162393 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53148.026316 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53148.026316 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53148.026316 # average overall mshr miss latency @@ -521,16 +522,16 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53148.026316 system.cpu.icache.overall_avg_mshr_miss_latency::total 53148.026316 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 177.982459 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 177.956413 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 373 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.002681 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 144.961610 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 33.020849 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004424 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 144.938671 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 33.017743 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004423 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.001008 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005432 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005431 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits @@ -646,22 +647,22 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41135.790541 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40310.594235 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 83.496642 # Cycle average of tags in use -system.cpu.dcache.total_refs 2284 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 83.486269 # Cycle average of tags in use +system.cpu.dcache.total_refs 2285 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 15.643836 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 15.650685 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 83.496642 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.020385 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.020385 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1425 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1425 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 83.486269 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.020382 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.020382 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1426 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1426 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 859 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 859 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2284 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2284 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2284 # number of overall hits -system.cpu.dcache.overall_hits::total 2284 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 2285 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2285 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2285 # number of overall hits +system.cpu.dcache.overall_hits::total 2285 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 127 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 127 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 76 # number of WriteReq misses @@ -678,22 +679,22 @@ system.cpu.dcache.demand_miss_latency::cpu.data 10866500 system.cpu.dcache.demand_miss_latency::total 10866500 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 10866500 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 10866500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1552 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1552 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 1553 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1553 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2487 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2487 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2487 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2487 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081830 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.081830 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2488 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2488 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2488 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2488 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081777 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.081777 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081283 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.081283 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.081624 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.081624 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.081624 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.081624 # miss rate for overall accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.081592 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.081592 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.081592 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.081592 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 52346.456693 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 52346.456693 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55506.578947 # average WriteReq miss latency @@ -732,14 +733,14 @@ system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8029000 system.cpu.dcache.demand_mshr_miss_latency::total 8029000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8029000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 8029000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046392 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046392 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046362 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046362 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081283 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081283 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059509 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.059509 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.059509 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.059509 # mshr miss rate for overall accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059486 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.059486 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.059486 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.059486 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 55034.722222 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 55034.722222 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53506.578947 # average WriteReq mshr miss latency diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini index f7b3c0261..7de6f390d 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini @@ -77,7 +77,7 @@ port=system.membus.slave[4] [system.cpu.interrupts] type=X86LocalApic -clock=500 +clock=8000 int_latency=1000 pio_addr=2305843009213693952 pio_latency=100000 @@ -128,6 +128,7 @@ type=CoherentBus block_size=64 clock=1000 header_cycles=1 +system=system use_default_range=false width=8 master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simerr b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simerr index f5691fd64..e45cd058f 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simerr +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simerr @@ -1,3 +1,2 @@ warn: Sockets disabled, not accepting gdb connections -warn: instruction 'fldcw_Mw' unimplemented hack: be nice to actually delete the event here diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout index 463bf7a2c..41b657a83 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout @@ -3,11 +3,11 @@ Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-ato gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 16:30:44 -gem5 started Jan 23 2013 16:30:54 +gem5 compiled Mar 11 2013 13:21:48 +gem5 started Mar 11 2013 13:21:58 gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 5614500 because target called exit() +Exiting @ tick 5615000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt index bc4bb0d66..f6427353a 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt @@ -1,59 +1,59 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000006 # Number of seconds simulated -sim_ticks 5614500 # Number of ticks simulated -final_tick 5614500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 5615000 # Number of ticks simulated +final_tick 5615000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 59484 # Simulator instruction rate (inst/s) -host_op_rate 107725 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 62039506 # Simulator tick rate (ticks/s) -host_mem_usage 277020 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host +host_inst_rate 54091 # Simulator instruction rate (inst/s) +host_op_rate 97967 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 56419373 # Simulator tick rate (ticks/s) +host_mem_usage 276792 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host sim_insts 5381 # Number of instructions simulated -sim_ops 9747 # Number of ops (including micro ops) simulated +sim_ops 9748 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 54912 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7064 # Number of bytes read from this memory -system.physmem.bytes_read::total 61976 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7066 # Number of bytes read from this memory +system.physmem.bytes_read::total 61978 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 54912 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 54912 # Number of instructions bytes read from this memory system.physmem.bytes_written::cpu.data 7112 # Number of bytes written to this memory system.physmem.bytes_written::total 7112 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 6864 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1052 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7916 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1053 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7917 # Number of read requests responded to by this memory system.physmem.num_writes::cpu.data 935 # Number of write requests responded to by this memory system.physmem.num_writes::total 935 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 9780390061 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1258170808 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 11038560869 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 9780390061 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 9780390061 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1266720100 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1266720100 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 9780390061 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2524890907 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 12305280969 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 9779519145 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1258414960 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 11037934105 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 9779519145 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 9779519145 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1266607302 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1266607302 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 9779519145 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2525022262 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 12304541407 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 11230 # number of cpu cycles simulated +system.cpu.numCycles 11231 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5381 # Number of instructions committed -system.cpu.committedOps 9747 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 9653 # Number of integer alu accesses +system.cpu.committedOps 9748 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 9655 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured system.cpu.num_conditional_control_insts 899 # number of instructions that are conditional controls -system.cpu.num_int_insts 9653 # number of integer instructions +system.cpu.num_int_insts 9655 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 24817 # number of times the integer registers were read -system.cpu.num_int_register_writes 11061 # number of times the integer registers were written +system.cpu.num_int_register_reads 24822 # number of times the integer registers were read +system.cpu.num_int_register_writes 11063 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 1987 # number of memory refs -system.cpu.num_load_insts 1052 # Number of load instructions +system.cpu.num_mem_refs 1988 # number of memory refs +system.cpu.num_load_insts 1053 # Number of load instructions system.cpu.num_store_insts 935 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 11230 # Number of busy cycles +system.cpu.num_busy_cycles 11231 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats index 5e5659352..3bdc04678 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats @@ -1,24 +1,24 @@ -Real time: Jan/23/2013 16:34:52 +Real time: Mar/11/2013 13:21:59 Profiler Stats -------------- -Elapsed_time_in_seconds: 0 -Elapsed_time_in_minutes: 0 -Elapsed_time_in_hours: 0 -Elapsed_time_in_days: 0 +Elapsed_time_in_seconds: 1 +Elapsed_time_in_minutes: 0.0166667 +Elapsed_time_in_hours: 0.000277778 +Elapsed_time_in_days: 1.15741e-05 -Virtual_time_in_seconds: 0.54 -Virtual_time_in_minutes: 0.009 -Virtual_time_in_hours: 0.00015 -Virtual_time_in_days: 6.25e-06 +Virtual_time_in_seconds: 0.6 +Virtual_time_in_minutes: 0.01 +Virtual_time_in_hours: 0.000166667 +Virtual_time_in_days: 6.94444e-06 Ruby_current_time: 121759 Ruby_start_time: 0 Ruby_cycles: 121759 -mbytes_resident: 66.3984 -mbytes_total: 290.648 -resident_ratio: 0.22849 +mbytes_resident: 66.582 +mbytes_total: 163.426 +resident_ratio: 0.407486 ruby_cycles_executed: [ 121760 ] @@ -29,17 +29,17 @@ Directory-0:0 Busy Bank Count:0 -sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8852 average: 1 | standard deviation: 0 | 0 8852 ] +sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8853 average: 1 | standard deviation: 0 | 0 8853 ] All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- -miss_latency: [binsize: 1 max: 125 count: 8851 average: 12.7565 | standard deviation: 22.8681 | 0 0 0 7474 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 1 0 10 4 313 433 492 10 6 5 9 6 11 0 1 1 1 0 0 0 1 1 0 0 1 0 0 1 0 0 0 9 16 39 0 0 2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] -miss_latency_LD: [binsize: 1 max: 101 count: 1044 average: 33.113 | standard deviation: 31.8551 | 0 0 0 545 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 5 2 97 201 150 1 3 2 0 1 1 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 3 5 22 0 0 1 0 0 0 0 0 1 ] -miss_latency_ST: [binsize: 1 max: 92 count: 935 average: 20.0877 | standard deviation: 28.194 | 0 0 0 681 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 59 62 106 3 0 0 2 0 3 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 2 3 9 ] -miss_latency_IFETCH: [binsize: 1 max: 125 count: 6864 average: 8.66404 | standard deviation: 18.01 | 0 0 0 6241 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 4 1 157 170 235 6 3 3 7 5 7 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 4 8 8 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency: [binsize: 1 max: 125 count: 8852 average: 12.755 | standard deviation: 22.8655 | 0 0 0 7475 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 1 0 10 4 312 432 494 10 6 5 9 7 11 0 1 0 1 0 0 0 1 1 0 0 1 0 0 1 0 0 0 9 16 40 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_LD: [binsize: 1 max: 101 count: 1045 average: 33.0842 | standard deviation: 31.8534 | 0 0 0 546 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 5 2 97 201 150 1 3 2 0 1 1 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 3 5 22 0 0 1 0 0 0 0 0 1 ] +miss_latency_ST: [binsize: 1 max: 92 count: 935 average: 20.0845 | standard deviation: 28.1878 | 0 0 0 681 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 59 61 107 3 0 0 2 1 3 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 2 3 9 ] +miss_latency_IFETCH: [binsize: 1 max: 125 count: 6864 average: 8.6639 | standard deviation: 18.0088 | 0 0 0 6241 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 4 1 156 170 236 6 3 3 7 5 7 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 4 8 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] miss_latency_RMW_Read: [binsize: 1 max: 65 count: 8 average: 10.75 | standard deviation: 21.9219 | 0 0 0 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] -miss_latency_L1Cache: [binsize: 1 max: 3 count: 7474 average: 3 | standard deviation: 0 | 0 0 0 7474 ] -miss_latency_Directory: [binsize: 1 max: 125 count: 1377 average: 65.7124 | standard deviation: 6.32886 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 1 0 10 4 313 433 492 10 6 5 9 6 11 0 1 1 1 0 0 0 1 1 0 0 1 0 0 1 0 0 0 9 16 39 0 0 2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_L1Cache: [binsize: 1 max: 3 count: 7475 average: 3 | standard deviation: 0 | 0 0 0 7475 ] +miss_latency_Directory: [binsize: 1 max: 125 count: 1377 average: 65.7095 | standard deviation: 6.31582 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 1 0 10 4 312 432 494 10 6 5 9 7 11 0 1 0 1 0 0 0 1 1 0 0 1 0 0 1 0 0 0 9 16 40 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] @@ -50,12 +50,12 @@ miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 1 average: miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] miss_latency_dir_first_response_to_completion: [binsize: 1 max: 61 count: 1 average: 61 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] imcomplete_dir_Times: 1376 -miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 545 average: 3 | standard deviation: 0 | 0 0 0 545 ] +miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 546 average: 3 | standard deviation: 0 | 0 0 0 546 ] miss_latency_LD_Directory: [binsize: 1 max: 101 count: 499 average: 66.002 | standard deviation: 7.00186 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 5 2 97 201 150 1 3 2 0 1 1 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 3 5 22 0 0 1 0 0 0 0 0 1 ] miss_latency_ST_L1Cache: [binsize: 1 max: 3 count: 681 average: 3 | standard deviation: 0 | 0 0 0 681 ] -miss_latency_ST_Directory: [binsize: 1 max: 92 count: 254 average: 65.9016 | standard deviation: 6.43269 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 59 62 106 3 0 0 2 0 3 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 2 3 9 ] +miss_latency_ST_Directory: [binsize: 1 max: 92 count: 254 average: 65.8898 | standard deviation: 6.41669 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 59 61 107 3 0 0 2 1 3 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 2 3 9 ] miss_latency_IFETCH_L1Cache: [binsize: 1 max: 3 count: 6241 average: 3 | standard deviation: 0 | 0 0 0 6241 ] -miss_latency_IFETCH_Directory: [binsize: 1 max: 125 count: 623 average: 65.4045 | standard deviation: 5.68761 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 4 1 157 170 235 6 3 3 7 5 7 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 4 8 8 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_IFETCH_Directory: [binsize: 1 max: 125 count: 623 average: 65.4029 | standard deviation: 5.66282 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 4 1 156 170 236 6 3 3 7 5 7 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 4 8 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] miss_latency_RMW_Read_L1Cache: [binsize: 1 max: 3 count: 7 average: 3 | standard deviation: 0 | 0 0 0 7 ] miss_latency_RMW_Read_Directory: [binsize: 1 max: 65 count: 1 average: 65 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] @@ -72,7 +72,6 @@ filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN Message Delayed Cycles ---------------------- Total_delay_cycles: [binsize: 1 max: 0 count: 2750 average: 0 | standard deviation: 0 | 2750 ] -Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 2750 average: 0 | standard deviation: 0 | 2750 ] virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 1377 average: 0 | standard deviation: 0 | 1377 ] virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 1373 average: 0 | standard deviation: 0 | 1373 ] @@ -89,7 +88,7 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 13733 +page_reclaims: 14769 page_faults: 0 swaps: 0 block_inputs: 0 @@ -152,7 +151,7 @@ Cache Stats: system.ruby.l1_cntrl0.cacheMemory --- L1Cache --- - Event Counts - -Load [1044 ] 1044 +Load [1045 ] 1045 Ifetch [6864 ] 6864 Store [943 ] 943 Data [1377 ] 1377 @@ -171,7 +170,7 @@ I Replacement [0 ] 0 II Writeback_Nack [0 ] 0 -M Load [545 ] 545 +M Load [546 ] 546 M Ifetch [6241 ] 6241 M Store [688 ] 688 M Fwd_GETX [0 ] 0 @@ -194,18 +193,18 @@ Memory controller: system.ruby.dir_cntrl0.memBuffer: memory_reads: 1377 memory_writes: 1373 memory_refreshes: 846 - memory_total_request_delays: 1964 - memory_delays_per_request: 0.714182 + memory_total_request_delays: 1968 + memory_delays_per_request: 0.715636 memory_delays_in_input_queue: 0 - memory_delays_behind_head_of_bank_queue: 4 - memory_delays_stalled_at_head_of_bank_queue: 1960 - memory_stalls_for_bank_busy: 826 + memory_delays_behind_head_of_bank_queue: 3 + memory_delays_stalled_at_head_of_bank_queue: 1965 + memory_stalls_for_bank_busy: 823 memory_stalls_for_random_busy: 0 memory_stalls_for_anti_starvation: 0 - memory_stalls_for_arbitration: 62 - memory_stalls_for_bus: 1041 + memory_stalls_for_arbitration: 65 + memory_stalls_for_bus: 1044 memory_stalls_for_tfaw: 0 - memory_stalls_for_read_write_turnaround: 31 + memory_stalls_for_read_write_turnaround: 33 memory_stalls_for_read_read_turnaround: 0 accesses_per_bank: 160 144 210 146 196 96 66 38 22 20 184 297 71 124 60 18 84 6 8 14 92 56 14 60 34 58 84 66 42 122 104 54 diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simerr b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simerr index 723b3760f..bbc0c797e 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simerr +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simerr @@ -1,7 +1,6 @@ -Warning: rounding error > tolerance +warn: rounding error > tolerance 0.072760 rounded to 0 -Warning: rounding error > tolerance +warn: rounding error > tolerance 0.072760 rounded to 0 warn: Sockets disabled, not accepting gdb connections -warn: instruction 'fldcw_Mw' unimplemented hack: be nice to actually delete the event here diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout index 931a144eb..8c2cd3936 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout @@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-tim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 16:30:44 -gem5 started Jan 23 2013 16:34:52 +gem5 compiled Mar 11 2013 13:21:48 +gem5 started Mar 11 2013 13:21:58 gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby Global frequency set at 1000000000 ticks per second diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt index 4a0d16755..e2571982e 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt @@ -4,13 +4,13 @@ sim_seconds 0.000122 # Nu sim_ticks 121759 # Number of ticks simulated final_tick 121759 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 20307 # Simulator instruction rate (inst/s) -host_op_rate 36781 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 459428 # Simulator tick rate (ticks/s) -host_mem_usage 167176 # Number of bytes of host memory used -host_seconds 0.27 # Real time elapsed on the host +host_inst_rate 25458 # Simulator instruction rate (inst/s) +host_op_rate 46114 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 575943 # Simulator tick rate (ticks/s) +host_mem_usage 167352 # Number of bytes of host memory used +host_seconds 0.21 # Real time elapsed on the host sim_insts 5381 # Number of instructions simulated -sim_ops 9747 # Number of ops (including micro ops) simulated +sim_ops 9748 # Number of ops (including micro ops) simulated system.ruby.l1_cntrl0.cacheMemory.num_data_array_reads 0 # number of data array reads system.ruby.l1_cntrl0.cacheMemory.num_data_array_writes 0 # number of data array writes system.ruby.l1_cntrl0.cacheMemory.num_tag_array_reads 0 # number of tag array reads @@ -22,19 +22,19 @@ system.cpu.numCycles 121759 # nu system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5381 # Number of instructions committed -system.cpu.committedOps 9747 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 9653 # Number of integer alu accesses +system.cpu.committedOps 9748 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 9655 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured system.cpu.num_conditional_control_insts 899 # number of instructions that are conditional controls -system.cpu.num_int_insts 9653 # number of integer instructions +system.cpu.num_int_insts 9655 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 24817 # number of times the integer registers were read -system.cpu.num_int_register_writes 11061 # number of times the integer registers were written +system.cpu.num_int_register_reads 24822 # number of times the integer registers were read +system.cpu.num_int_register_writes 11063 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 1987 # number of memory refs -system.cpu.num_load_insts 1052 # Number of load instructions +system.cpu.num_mem_refs 1988 # number of memory refs +system.cpu.num_load_insts 1053 # Number of load instructions system.cpu.num_store_insts 935 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_busy_cycles 121759 # Number of busy cycles diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini index 46354ed27..4f3f120ab 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini @@ -117,7 +117,7 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=X86LocalApic -clock=500 +clock=8000 int_latency=1000 pio_addr=2305843009213693952 pio_latency=100000 @@ -168,6 +168,7 @@ type=CoherentBus block_size=64 clock=500 header_cycles=1 +system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side @@ -200,6 +201,7 @@ type=CoherentBus block_size=64 clock=1000 header_cycles=1 +system=system use_default_range=false width=8 master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simerr b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simerr index f5691fd64..e45cd058f 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simerr +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simerr @@ -1,3 +1,2 @@ warn: Sockets disabled, not accepting gdb connections -warn: instruction 'fldcw_Mw' unimplemented hack: be nice to actually delete the event here diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout index 9b198f409..e6d8615da 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout @@ -3,11 +3,11 @@ Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-tim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 16:30:44 -gem5 started Jan 23 2013 19:18:31 +gem5 compiled Mar 11 2013 13:21:48 +gem5 started Mar 11 2013 13:21:58 gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 28357000 because target called exit() +Exiting @ tick 28358000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt index 30a2c344a..84cd243cf 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000028 # Number of seconds simulated -sim_ticks 28357000 # Number of ticks simulated -final_tick 28357000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 28358000 # Number of ticks simulated +final_tick 28358000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 55225 # Simulator instruction rate (inst/s) -host_op_rate 100013 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 290910277 # Simulator tick rate (ticks/s) -host_mem_usage 285604 # Number of bytes of host memory used -host_seconds 0.10 # Real time elapsed on the host +host_inst_rate 48918 # Simulator instruction rate (inst/s) +host_op_rate 88604 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 257715326 # Simulator tick rate (ticks/s) +host_mem_usage 285372 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host sim_insts 5381 # Number of instructions simulated -sim_ops 9747 # Number of ops (including micro ops) simulated +sim_ops 9748 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 14528 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 8576 # Number of bytes read from this memory system.physmem.bytes_read::total 23104 # Number of bytes read from this memory @@ -19,46 +19,46 @@ system.physmem.bytes_inst_read::total 14528 # Nu system.physmem.num_reads::cpu.inst 227 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory system.physmem.num_reads::total 361 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 512324999 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 302429735 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 814754734 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 512324999 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 512324999 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 512324999 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 302429735 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 814754734 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 512306933 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 302419070 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 814726003 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 512306933 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 512306933 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 512306933 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 302419070 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 814726003 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 56714 # number of cpu cycles simulated +system.cpu.numCycles 56716 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5381 # Number of instructions committed -system.cpu.committedOps 9747 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 9653 # Number of integer alu accesses +system.cpu.committedOps 9748 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 9655 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured system.cpu.num_conditional_control_insts 899 # number of instructions that are conditional controls -system.cpu.num_int_insts 9653 # number of integer instructions +system.cpu.num_int_insts 9655 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 24817 # number of times the integer registers were read -system.cpu.num_int_register_writes 11061 # number of times the integer registers were written +system.cpu.num_int_register_reads 24822 # number of times the integer registers were read +system.cpu.num_int_register_writes 11063 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 1987 # number of memory refs -system.cpu.num_load_insts 1052 # Number of load instructions +system.cpu.num_mem_refs 1988 # number of memory refs +system.cpu.num_load_insts 1053 # Number of load instructions system.cpu.num_store_insts 935 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 56714 # Number of busy cycles +system.cpu.num_busy_cycles 56716 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 105.553131 # Cycle average of tags in use +system.cpu.icache.tagsinuse 105.550219 # Cycle average of tags in use system.cpu.icache.total_refs 6637 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 228 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 29.109649 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 105.553131 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.051540 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.051540 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 105.550219 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.051538 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.051538 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 6637 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 6637 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 6637 # number of demand (read+write) hits @@ -129,16 +129,16 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52815.789474 system.cpu.icache.overall_avg_mshr_miss_latency::total 52815.789474 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 134.037527 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 134.034140 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 282 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.003546 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 105.561241 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 28.476285 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 105.558330 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 28.475810 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::cpu.inst 0.003221 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.000869 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.004091 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.004090 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits @@ -254,22 +254,22 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 80.799099 # Cycle average of tags in use -system.cpu.dcache.total_refs 1853 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 80.797237 # Cycle average of tags in use +system.cpu.dcache.total_refs 1854 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 134 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 13.828358 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 13.835821 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 80.799099 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 80.797237 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.019726 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.019726 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 997 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 997 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 998 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 998 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 856 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 856 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1853 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1853 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1853 # number of overall hits -system.cpu.dcache.overall_hits::total 1853 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 1854 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1854 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1854 # number of overall hits +system.cpu.dcache.overall_hits::total 1854 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 55 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 55 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 79 # number of WriteReq misses @@ -286,22 +286,22 @@ system.cpu.dcache.demand_miss_latency::cpu.data 7370000 system.cpu.dcache.demand_miss_latency::total 7370000 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 7370000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 7370000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1052 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1052 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 1053 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1053 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 1987 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 1987 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 1987 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 1987 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052281 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.052281 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 1988 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 1988 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 1988 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 1988 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052232 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.052232 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084492 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.084492 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.067438 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.067438 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.067438 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.067438 # miss rate for overall accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.067404 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.067404 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.067404 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.067404 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency @@ -334,14 +334,14 @@ system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7102000 system.cpu.dcache.demand_mshr_miss_latency::total 7102000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7102000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 7102000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052281 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052281 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052232 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052232 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084492 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084492 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067438 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.067438 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067438 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.067438 # mshr miss rate for overall accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067404 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.067404 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067404 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.067404 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency |