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-rw-r--r--src/mem/bridge.cc4
-rw-r--r--src/mem/cache/mshr.cc2
-rw-r--r--src/mem/cache/prefetch/queued.cc2
-rw-r--r--src/mem/packet_queue.cc6
-rw-r--r--src/mem/simple_mem.cc2
5 files changed, 8 insertions, 8 deletions
diff --git a/src/mem/bridge.cc b/src/mem/bridge.cc
index 6bc8c18f2..ecaf6de04 100644
--- a/src/mem/bridge.cc
+++ b/src/mem/bridge.cc
@@ -217,7 +217,7 @@ Bridge::BridgeMasterPort::schedTimingReq(PacketPtr pkt, Tick when)
assert(transmitList.size() != reqQueueLimit);
- transmitList.emplace_back(DeferredPacket(pkt, when));
+ transmitList.emplace_back(pkt, when);
}
@@ -232,7 +232,7 @@ Bridge::BridgeSlavePort::schedTimingResp(PacketPtr pkt, Tick when)
bridge.schedule(sendEvent, when);
}
- transmitList.emplace_back(DeferredPacket(pkt, when));
+ transmitList.emplace_back(pkt, when);
}
void
diff --git a/src/mem/cache/mshr.cc b/src/mem/cache/mshr.cc
index 78900ed4e..5b7eb0c06 100644
--- a/src/mem/cache/mshr.cc
+++ b/src/mem/cache/mshr.cc
@@ -104,7 +104,7 @@ MSHR::TargetList::add(PacketPtr pkt, Tick readyTime,
}
}
- emplace_back(Target(pkt, readyTime, order, source, markPending));
+ emplace_back(pkt, readyTime, order, source, markPending);
}
diff --git a/src/mem/cache/prefetch/queued.cc b/src/mem/cache/prefetch/queued.cc
index 97ea4eee6..58b33a4ae 100644
--- a/src/mem/cache/prefetch/queued.cc
+++ b/src/mem/cache/prefetch/queued.cc
@@ -149,7 +149,7 @@ QueuedPrefetcher::notify(const PacketPtr &pkt)
DPRINTF(HWPrefetch, "Prefetch queued. "
"addr:%#x tick:%lld.\n", pf_addr, pf_time);
- pfq.emplace_back(DeferredPacket(pf_time, pf_pkt));
+ pfq.emplace_back(pf_time, pf_pkt);
}
}
diff --git a/src/mem/packet_queue.cc b/src/mem/packet_queue.cc
index ff248d388..e7ad1cc47 100644
--- a/src/mem/packet_queue.cc
+++ b/src/mem/packet_queue.cc
@@ -142,7 +142,7 @@ PacketQueue::schedSendTiming(PacketPtr pkt, Tick when, bool force_order)
// note that currently we ignore a potentially outstanding retry
// and could in theory put a new packet at the head of the
// transmit list before retrying the existing packet
- transmitList.emplace_front(DeferredPacket(when, pkt));
+ transmitList.emplace_front(when, pkt);
schedSendEvent(when);
return;
}
@@ -157,7 +157,7 @@ PacketQueue::schedSendTiming(PacketPtr pkt, Tick when, bool force_order)
// list is non-empty and this belongs at the end
if (when >= transmitList.back().tick) {
- transmitList.emplace_back(DeferredPacket(when, pkt));
+ transmitList.emplace_back(when, pkt);
return;
}
@@ -169,7 +169,7 @@ PacketQueue::schedSendTiming(PacketPtr pkt, Tick when, bool force_order)
++i; // already checked for insertion at front
while (i != transmitList.end() && when >= i->tick)
++i;
- transmitList.emplace(i, DeferredPacket(when, pkt));
+ transmitList.emplace(i, when, pkt);
}
void
diff --git a/src/mem/simple_mem.cc b/src/mem/simple_mem.cc
index 8938b2a55..f68066e75 100644
--- a/src/mem/simple_mem.cc
+++ b/src/mem/simple_mem.cc
@@ -161,7 +161,7 @@ SimpleMemory::recvTimingReq(PacketPtr pkt)
// to keep things simple (and in order), we put the packet at
// the end even if the latency suggests it should be sent
// before the packet(s) before it
- packetQueue.emplace_back(DeferredPacket(pkt, curTick() + getLatency()));
+ packetQueue.emplace_back(pkt, curTick() + getLatency());
if (!retryResp && !dequeueEvent.scheduled())
schedule(dequeueEvent, packetQueue.back().tick);
} else {