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-rw-r--r--src/arch/x86/isa/decoder/two_byte_opcodes.isa2
-rw-r--r--src/arch/x86/isa/insts/general_purpose/rotate_and_shift/shift.py47
2 files changed, 30 insertions, 19 deletions
diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
index c47fb5184..dbde17964 100644
--- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
@@ -831,7 +831,7 @@
0x2: rsm_smm();
0x3: Inst::BTS(Ev,Gv);
0x4: Inst::SHRD(Ev,Gv,Ib);
- 0x5: shrd_Ev_Gv_rCl();
+ 0x5: Inst::SHRD(Ev,Gv);
//0x6: group16();
0x6: decode MODRM_REG {
0x0: fxsave();
diff --git a/src/arch/x86/isa/insts/general_purpose/rotate_and_shift/shift.py b/src/arch/x86/isa/insts/general_purpose/rotate_and_shift/shift.py
index d2a579ecb..092fb4213 100644
--- a/src/arch/x86/isa/insts/general_purpose/rotate_and_shift/shift.py
+++ b/src/arch/x86/isa/insts/general_purpose/rotate_and_shift/shift.py
@@ -220,38 +220,49 @@ def macroop SHR_P_R
st t1, seg, riprel, disp
};
-# SHRD will not set OF correctly when the shift count is 1.
+def macroop SHRD_R_R
+{
+ mdbi regm, 0
+ srd reg, reg, rcx, flags=(CF,OF,SF,ZF,PF)
+};
+
+def macroop SHRD_M_R
+{
+ ldst t1, seg, sib, disp
+ mdbi reg, 0
+ srd t1, t1, rcx, flags=(CF,OF,SF,ZF,PF)
+ st t1, seg, sib, disp
+};
+
+def macroop SHRD_P_R
+{
+ rdip t7
+ ldst t1, seg, riprel, disp
+ mdbi reg, 0
+ srd t1, t1, rcx, flags=(CF,OF,SF,ZF,PF)
+ st t1, seg, riprel, disp
+};
+
def macroop SHRD_R_R_I
{
- srli t1, reg, imm, flags=(CF,)
- rori t2, regm, imm
- srli t3, regm, imm
- xor t2, t2, t3
- or reg, t1, t2
+ mdbi regm, 0
+ srdi reg, reg, imm, flags=(CF,OF,SF,ZF,PF)
};
-# SHRD will not set OF correctly when the shift count is 1.
def macroop SHRD_M_R_I
{
ldst t1, seg, sib, disp
- srli t1, t1, imm, flags=(CF,)
- rori t2, reg, imm
- srli t3, reg, imm
- xor t2, t2, t3
- or t1, t1, t2
+ mdbi reg, 0
+ srdi t1, t1, imm, flags=(CF,OF,SF,ZF,PF)
st t1, seg, sib, disp
};
-# SHRD will not set OF correctly when the shift count is 1.
def macroop SHRD_P_R_I
{
rdip t7
ldst t1, seg, riprel, disp
- srli t1, t1, imm, flags=(CF,)
- rori t2, reg, imm
- srli t3, reg, imm
- xor t2, t2, t3
- or t1, t1, t2
+ mdbi reg, 0
+ srdi t1, t1, imm, flags=(CF,OF,SF,ZF,PF)
st t1, seg, riprel, disp
};