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-rwxr-xr-xsrc/arch/isa_parser.py4
-rw-r--r--src/arch/sparc/miscregfile.cc4
-rw-r--r--src/arch/sparc/miscregfile.hh5
-rw-r--r--src/arch/sparc/ua2005.cc5
-rw-r--r--src/cpu/o3/alpha/dyn_inst.hh8
-rw-r--r--src/cpu/o3/sparc/dyn_inst.hh8
-rw-r--r--src/cpu/simple/base.hh8
7 files changed, 20 insertions, 22 deletions
diff --git a/src/arch/isa_parser.py b/src/arch/isa_parser.py
index 9b63c8842..21860a2e1 100755
--- a/src/arch/isa_parser.py
+++ b/src/arch/isa_parser.py
@@ -1368,7 +1368,7 @@ class ControlRegOperand(Operand):
bit_select = 0
if (self.ctype == 'float' or self.ctype == 'double'):
error(0, 'Attempt to read control register as FP')
- base = 'xc->readMiscRegOperandWithEffect(this, %s)' % self.src_reg_idx
+ base = 'xc->readMiscRegOperand(this, %s)' % self.src_reg_idx
if self.size == self.dflt_size:
return '%s = %s;\n' % (self.base_name, base)
else:
@@ -1378,7 +1378,7 @@ class ControlRegOperand(Operand):
def makeWrite(self):
if (self.ctype == 'float' or self.ctype == 'double'):
error(0, 'Attempt to write control register as FP')
- wb = 'xc->setMiscRegOperandWithEffect(this, %s, %s);\n' % \
+ wb = 'xc->setMiscRegOperand(this, %s, %s);\n' % \
(self.dest_reg_idx, self.base_name)
wb += 'if (traceData) { traceData->setData(%s); }' % \
self.base_name
diff --git a/src/arch/sparc/miscregfile.cc b/src/arch/sparc/miscregfile.cc
index e7b866e6f..20bc4ae5d 100644
--- a/src/arch/sparc/miscregfile.cc
+++ b/src/arch/sparc/miscregfile.cc
@@ -374,7 +374,7 @@ MiscReg MiscRegFile::readReg(int miscReg, ThreadContext * tc)
case MISCREG_QUEUE_NRES_ERROR_TAIL:
#if FULL_SYSTEM
case MISCREG_HPSTATE:
- return readFSRegWithEffect(miscReg, tc);
+ return readFSReg(miscReg, tc);
#else
case MISCREG_HPSTATE:
//HPSTATE is special because because sometimes in privilege checks for instructions
@@ -682,7 +682,7 @@ void MiscRegFile::setReg(int miscReg,
case MISCREG_QUEUE_NRES_ERROR_TAIL:
#if FULL_SYSTEM
case MISCREG_HPSTATE:
- setFSRegWithEffect(miscReg, val, tc);
+ setFSReg(miscReg, val, tc);
return;
#else
case MISCREG_HPSTATE:
diff --git a/src/arch/sparc/miscregfile.hh b/src/arch/sparc/miscregfile.hh
index cb46eb2aa..6063c21c8 100644
--- a/src/arch/sparc/miscregfile.hh
+++ b/src/arch/sparc/miscregfile.hh
@@ -257,9 +257,8 @@ namespace SparcISA
// These need to check the int_dis field and if 0 then
// set appropriate bit in softint and checkinterrutps on the cpu
#if FULL_SYSTEM
- void setFSRegWithEffect(int miscReg, const MiscReg &val,
- ThreadContext *tc);
- MiscReg readFSRegWithEffect(int miscReg, ThreadContext * tc);
+ void setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc);
+ MiscReg readFSReg(int miscReg, ThreadContext * tc);
// Update interrupt state on softint or pil change
void checkSoftInt(ThreadContext *tc);
diff --git a/src/arch/sparc/ua2005.cc b/src/arch/sparc/ua2005.cc
index 7a16dc352..6c8a987fe 100644
--- a/src/arch/sparc/ua2005.cc
+++ b/src/arch/sparc/ua2005.cc
@@ -59,8 +59,7 @@ MiscRegFile::checkSoftInt(ThreadContext *tc)
void
-MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
- ThreadContext *tc)
+MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
{
int64_t time;
switch (miscReg) {
@@ -196,7 +195,7 @@ MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
}
MiscReg
-MiscRegFile::readFSRegWithEffect(int miscReg, ThreadContext * tc)
+MiscRegFile::readFSReg(int miscReg, ThreadContext * tc)
{
switch (miscReg) {
/* Privileged registers. */
diff --git a/src/cpu/o3/alpha/dyn_inst.hh b/src/cpu/o3/alpha/dyn_inst.hh
index 6c27e890a..20759d849 100644
--- a/src/cpu/o3/alpha/dyn_inst.hh
+++ b/src/cpu/o3/alpha/dyn_inst.hh
@@ -125,7 +125,7 @@ class AlphaDynInst : public BaseDynInst<Impl>
}
/** Reads a miscellaneous register. */
- TheISA::MiscReg readMiscRegOperand(const StaticInst *si, int idx)
+ TheISA::MiscReg readMiscRegOperandNoEffect(const StaticInst *si, int idx)
{
return this->cpu->readMiscRegNoEffect(
si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
@@ -135,7 +135,7 @@ class AlphaDynInst : public BaseDynInst<Impl>
/** Reads a misc. register, including any side-effects the read
* might have as defined by the architecture.
*/
- TheISA::MiscReg readMiscRegOperandWithEffect(const StaticInst *si, int idx)
+ TheISA::MiscReg readMiscRegOperand(const StaticInst *si, int idx)
{
return this->cpu->readMiscReg(
si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
@@ -143,7 +143,7 @@ class AlphaDynInst : public BaseDynInst<Impl>
}
/** Sets a misc. register. */
- void setMiscRegOperand(const StaticInst * si, int idx, const MiscReg &val)
+ void setMiscRegOperandNoEffect(const StaticInst * si, int idx, const MiscReg &val)
{
this->instResult.integer = val;
return this->cpu->setMiscRegNoEffect(
@@ -154,7 +154,7 @@ class AlphaDynInst : public BaseDynInst<Impl>
/** Sets a misc. register, including any side-effects the write
* might have as defined by the architecture.
*/
- void setMiscRegOperandWithEffect(const StaticInst *si, int idx,
+ void setMiscRegOperand(const StaticInst *si, int idx,
const MiscReg &val)
{
return this->cpu->setMiscReg(
diff --git a/src/cpu/o3/sparc/dyn_inst.hh b/src/cpu/o3/sparc/dyn_inst.hh
index bd61b0384..72242b161 100644
--- a/src/cpu/o3/sparc/dyn_inst.hh
+++ b/src/cpu/o3/sparc/dyn_inst.hh
@@ -107,7 +107,7 @@ class SparcDynInst : public BaseDynInst<Impl>
}
/** Reads a miscellaneous register. */
- TheISA::MiscReg readMiscRegOperand(const StaticInst *si, int idx)
+ TheISA::MiscReg readMiscRegOperandNoEffect(const StaticInst *si, int idx)
{
return this->cpu->readMiscRegNoEffect(
si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
@@ -117,7 +117,7 @@ class SparcDynInst : public BaseDynInst<Impl>
/** Reads a misc. register, including any side-effects the read
* might have as defined by the architecture.
*/
- TheISA::MiscReg readMiscRegOperandWithEffect(const StaticInst *si, int idx)
+ TheISA::MiscReg readMiscRegOperand(const StaticInst *si, int idx)
{
return this->cpu->readMiscReg(
si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
@@ -125,7 +125,7 @@ class SparcDynInst : public BaseDynInst<Impl>
}
/** Sets a misc. register. */
- void setMiscRegOperand(const StaticInst * si,
+ void setMiscRegOperandNoEffect(const StaticInst * si,
int idx, const TheISA::MiscReg &val)
{
this->instResult.integer = val;
@@ -137,7 +137,7 @@ class SparcDynInst : public BaseDynInst<Impl>
/** Sets a misc. register, including any side-effects the write
* might have as defined by the architecture.
*/
- void setMiscRegOperandWithEffect(
+ void setMiscRegOperand(
const StaticInst *si, int idx, const TheISA::MiscReg &val)
{
return this->cpu->setMiscReg(
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index 980ea2f96..eae24014b 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -304,25 +304,25 @@ class BaseSimpleCPU : public BaseCPU
return thread->setMiscReg(misc_reg, val);
}
- MiscReg readMiscRegOperand(const StaticInst *si, int idx)
+ MiscReg readMiscRegOperandNoEffect(const StaticInst *si, int idx)
{
int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
return thread->readMiscRegNoEffect(reg_idx);
}
- MiscReg readMiscRegOperandWithEffect(const StaticInst *si, int idx)
+ MiscReg readMiscRegOperand(const StaticInst *si, int idx)
{
int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
return thread->readMiscReg(reg_idx);
}
- void setMiscRegOperand(const StaticInst *si, int idx, const MiscReg &val)
+ void setMiscRegOperandNoEffect(const StaticInst *si, int idx, const MiscReg &val)
{
int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
return thread->setMiscRegNoEffect(reg_idx, val);
}
- void setMiscRegOperandWithEffect(
+ void setMiscRegOperand(
const StaticInst *si, int idx, const MiscReg &val)
{
int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-06 05:11:17 +0000