diff options
| -rw-r--r-- | src/arch/sparc/intregfile.cc | 7 | ||||
| -rw-r--r-- | src/arch/sparc/isa/decoder.isa | 4 | ||||
| -rw-r--r-- | src/arch/sparc/miscregfile.cc | 5 |
3 files changed, 10 insertions, 6 deletions
diff --git a/src/arch/sparc/intregfile.cc b/src/arch/sparc/intregfile.cc index 0a8ac055f..60856d3fa 100644 --- a/src/arch/sparc/intregfile.cc +++ b/src/arch/sparc/intregfile.cc @@ -111,6 +111,8 @@ void IntRegFile::setReg(int intReg, const IntReg &val) void IntRegFile::setCWP(int cwp) { int index = ((NWindows - cwp) % NWindows) * 2; + if (index < 0) + panic("Index less than 0. cwp=%d nwin=%d\n", cwp, NWindows); offset[Outputs] = FrameOffset + (index * RegsPerFrame); offset[Locals] = FrameOffset + ((index+1) * RegsPerFrame); offset[Inputs] = FrameOffset + @@ -128,6 +130,11 @@ void IntRegFile::setGlobals(int gl) regView[Globals] = regGlobals[gl]; offset[Globals] = RegGlobalOffset + gl * RegsPerFrame; + + if (regView[Globals] == regView[Inputs] || + regView[Globals] == regView[Locals] || + regView[Globals] == regView[Outputs] ) + panic("Two register arrays set to the same thing!\n"); } void IntRegFile::serialize(std::ostream &os) diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa index e2bebd987..2e1344a8f 100644 --- a/src/arch/sparc/isa/decoder.isa +++ b/src/arch/sparc/isa/decoder.isa @@ -1,4 +1,4 @@ -// Copyright (c) 2006 The Regents of The University of Michigan +// Copyright (c) 2006-2007 The Regents of The University of Michigan // All rights reserved. // // Redistribution and use in source and binary forms, with or without @@ -184,7 +184,7 @@ decode OP default Unknown::unknown() }}); 0x0B: smul({{ Rd.sdw = Rs1.sdw<31:0> * Rs2_or_imm13<31:0>; - Y = Rd.sdw; + Y = Rd.sdw<63:32>; }}); 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 - Ccr<0:0>}}); 0x0D: udivx({{ diff --git a/src/arch/sparc/miscregfile.cc b/src/arch/sparc/miscregfile.cc index 2dde5afd5..50f510289 100644 --- a/src/arch/sparc/miscregfile.cc +++ b/src/arch/sparc/miscregfile.cc @@ -327,10 +327,7 @@ MiscReg MiscRegFile::readRegWithEffect(int miscReg, ThreadContext * tc) mbits(tick,63,63); case MISCREG_FPRS: // in legion if fp is enabled du and dl are set - if (fprs & 0x4) - return 0x7; - else - return 0; + return fprs | 0x3; case MISCREG_PCR: case MISCREG_PIC: panic("Performance Instrumentation not impl\n"); |