diff options
| -rw-r--r-- | src/arch/SConscript | 1 | ||||
| -rw-r--r-- | src/arch/alpha/pseudo_inst.hh | 45 | ||||
| -rw-r--r-- | src/arch/arm/pseudo_inst.hh | 45 | ||||
| -rw-r--r-- | src/arch/generic/SConscript | 1 | ||||
| -rw-r--r-- | src/arch/generic/pseudo_inst.cc | 48 | ||||
| -rw-r--r-- | src/arch/generic/pseudo_inst.hh | 55 | ||||
| -rw-r--r-- | src/arch/mips/pseudo_inst.hh | 45 | ||||
| -rw-r--r-- | src/arch/power/pseudo_inst.hh | 45 | ||||
| -rw-r--r-- | src/arch/sparc/pseudo_inst.hh | 45 | ||||
| -rw-r--r-- | src/arch/x86/SConscript | 1 | ||||
| -rw-r--r-- | src/arch/x86/pseudo_inst.cc | 69 | ||||
| -rw-r--r-- | src/arch/x86/pseudo_inst.hh | 41 | ||||
| -rw-r--r-- | src/arch/x86/tlb.cc | 20 | ||||
| -rw-r--r-- | src/arch/x86/utility.cc | 4 | ||||
| -rw-r--r-- | src/cpu/kvm/base.cc | 13 | ||||
| -rw-r--r-- | src/sim/pseudo_inst.cc | 11 | ||||
| -rw-r--r-- | src/sim/system.cc | 10 | ||||
| -rw-r--r-- | util/m5/m5ops.h | 7 |
18 files changed, 489 insertions, 17 deletions
diff --git a/src/arch/SConscript b/src/arch/SConscript index 31ea0b78f..e0d6845f5 100644 --- a/src/arch/SConscript +++ b/src/arch/SConscript @@ -55,6 +55,7 @@ isa_switch_hdrs = Split(''' mmapped_ipr.hh mt.hh process.hh + pseudo_inst.hh registers.hh remote_gdb.hh stacktrace.hh diff --git a/src/arch/alpha/pseudo_inst.hh b/src/arch/alpha/pseudo_inst.hh new file mode 100644 index 000000000..8147f7abe --- /dev/null +++ b/src/arch/alpha/pseudo_inst.hh @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2014 Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Alexandru Dutu + */ + +#ifndef __ARCH_ALPHA_PSEUDO_INST_HH__ +#define __ARCH_ALPHA_PSEUDO_INST_HH__ + +#include "arch/generic/pseudo_inst.hh" +#include "base/misc.hh" + +class ThreadContext; + +namespace AlphaISA { + using GenericISA::m5Syscall; + using GenericISA::m5PageFault; +} + +#endif // __ARCH_ALPHA_PSEUDO_INST_HH__ + diff --git a/src/arch/arm/pseudo_inst.hh b/src/arch/arm/pseudo_inst.hh new file mode 100644 index 000000000..8da25ef87 --- /dev/null +++ b/src/arch/arm/pseudo_inst.hh @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2014 Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Alexandru Dutu + */ + +#ifndef __ARCH_ARM_PSEUDO_INST_HH__ +#define __ARCH_ARM_PSEUDO_INST_HH__ + +#include "arch/generic/pseudo_inst.hh" +#include "base/misc.hh" + +class ThreadContext; + +namespace ArmISA { + using GenericISA::m5Syscall; + using GenericISA::m5PageFault; +} + +#endif // __ARCH_ARM_PSEUDO_INST_HH__ + diff --git a/src/arch/generic/SConscript b/src/arch/generic/SConscript index bac70fa32..9d59fa269 100644 --- a/src/arch/generic/SConscript +++ b/src/arch/generic/SConscript @@ -33,3 +33,4 @@ if env['TARGET_ISA'] == 'null': Source('decode_cache.cc') Source('mmapped_ipr.cc') +Source('pseudo_inst.cc') diff --git a/src/arch/generic/pseudo_inst.cc b/src/arch/generic/pseudo_inst.cc new file mode 100644 index 000000000..e914b05a0 --- /dev/null +++ b/src/arch/generic/pseudo_inst.cc @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2014 Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Alexandru Dutu + */ + +#include "arch/generic/pseudo_inst.hh" +#include "base/misc.hh" + +class ThreadContext; + +using namespace GenericISA; + +void +GenericISA::m5Syscall(ThreadContext *tc) +{ + panic("m5Syscall not implemented for current ISA"); +} + +void +GenericISA::m5PageFault(ThreadContext *tc) +{ + panic("m5PageFault not implemented for current ISA"); +} diff --git a/src/arch/generic/pseudo_inst.hh b/src/arch/generic/pseudo_inst.hh new file mode 100644 index 000000000..001334726 --- /dev/null +++ b/src/arch/generic/pseudo_inst.hh @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2014 Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Alexandru Dutu + */ + +#ifndef __ARCH_GENERIC_PSEUDO_INST_HH__ +#define __ARCH_GENERIC_PSEUDO_INST_HH__ + +class ThreadContext; + +namespace GenericISA { + +/* + * This function is executed when the simulation is executing the syscall + * handler in System Emulation mode. + */ +void +m5Syscall(ThreadContext *tc); + +/* + * This function is executed when the simulation is executing the pagefault + * handler in System Emulation mode. + */ +void +m5PageFault(ThreadContext *tc); + +} // namespace GenericISA + +#endif // __ARCH_GENERIC_PSEUDO_INST_HH__ + diff --git a/src/arch/mips/pseudo_inst.hh b/src/arch/mips/pseudo_inst.hh new file mode 100644 index 000000000..1aae21abb --- /dev/null +++ b/src/arch/mips/pseudo_inst.hh @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2014 Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Alexandru Dutu + */ + +#ifndef __ARCH_MIPS_PSEUDO_INST_HH__ +#define __ARCH_MIPS_PSEUDO_INST_HH__ + +#include "arch/generic/pseudo_inst.hh" +#include "base/misc.hh" + +class ThreadContext; + +namespace MipsISA { + using GenericISA::m5Syscall; + using GenericISA::m5PageFault; +} + +#endif // __ARCH_MIPS_PSEUDO_INST_HH__ + diff --git a/src/arch/power/pseudo_inst.hh b/src/arch/power/pseudo_inst.hh new file mode 100644 index 000000000..295b33320 --- /dev/null +++ b/src/arch/power/pseudo_inst.hh @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2014 Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Alexandru Dutu + */ + +#ifndef __ARCH_POWER_PSEUDO_INST_HH__ +#define __ARCH_POWER_PSEUDO_INST_HH__ + +#include "arch/generic/pseudo_inst.hh" +#include "base/misc.hh" + +class ThreadContext; + +namespace PowerISA { + using GenericISA::m5Syscall; + using GenericISA::m5PageFault; +} + +#endif // __ARCH_POWER_PSEUDO_INST_HH__ + diff --git a/src/arch/sparc/pseudo_inst.hh b/src/arch/sparc/pseudo_inst.hh new file mode 100644 index 000000000..5d54391b2 --- /dev/null +++ b/src/arch/sparc/pseudo_inst.hh @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2014 Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Alexandru Dutu + */ + +#ifndef __ARCH_SPARC_PSEUDO_INST_HH__ +#define __ARCH_SPARC_PSEUDO_INST_HH__ + +#include "arch/generic/pseudo_inst.hh" +#include "base/misc.hh" + +class ThreadContext; + +namespace SparcISA { + using GenericISA::m5Syscall; + using GenericISA::m5PageFault; +} + +#endif // __ARCH_SPARC_PSEUDO_INST_HH__ + diff --git a/src/arch/x86/SConscript b/src/arch/x86/SConscript index 1c8277482..bdc012259 100644 --- a/src/arch/x86/SConscript +++ b/src/arch/x86/SConscript @@ -64,6 +64,7 @@ if env['TARGET_ISA'] == 'x86': Source('pagetable.cc') Source('pagetable_walker.cc') Source('process.cc') + Source('pseudo_inst.cc') Source('remote_gdb.cc') Source('stacktrace.cc') Source('system.cc') diff --git a/src/arch/x86/pseudo_inst.cc b/src/arch/x86/pseudo_inst.cc new file mode 100644 index 000000000..bd3b5ac7c --- /dev/null +++ b/src/arch/x86/pseudo_inst.cc @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2014 Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Alexandru Dutu + */ + +#include "arch/x86/pseudo_inst.hh" +#include "debug/PseudoInst.hh" +#include "sim/process.hh" + +using namespace X86ISA; + +namespace X86ISA { + +/* + * This function is executed when the simulation is executing the syscall + * handler in System Emulation mode. + */ +void +m5Syscall(ThreadContext *tc) +{ + DPRINTF(PseudoInst, "PseudoInst::m5Syscall()\n"); + + tc->syscall(tc->readIntReg(INTREG_RAX)); + MiscReg rflags = tc->readMiscReg(MISCREG_RFLAGS); + rflags &= ~(1 << 16); + tc->setMiscReg(MISCREG_RFLAGS, rflags); +} + +/* + * This function is executed when the simulation is executing the pagefault + * handler in System Emulation mode. + */ +void +m5PageFault(ThreadContext *tc) +{ + DPRINTF(PseudoInst, "PseudoInst::m5PageFault()\n"); + + Process *p = tc->getProcessPtr(); + if (!p->fixupStackFault(tc->readMiscReg(MISCREG_CR2))) { + panic("Page fault at %#x ", tc->readMiscReg(MISCREG_CR2)); + } +} + +} // namespace X86ISA diff --git a/src/arch/x86/pseudo_inst.hh b/src/arch/x86/pseudo_inst.hh new file mode 100644 index 000000000..5074d1fc3 --- /dev/null +++ b/src/arch/x86/pseudo_inst.hh @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2014 Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Alexandru Dutu + */ + +#ifndef __ARCH_X86_PSEUDO_INST_HH__ +#define __ARCH_X86_PSEUDO_INST_HH__ + +class ThreadContext; + +namespace X86ISA { + void m5Syscall(ThreadContext *tc); + void m5PageFault(ThreadContext *tc); +} + +#endif // __ARCH_X86_PSEUDO_INST_HH__ diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc index fa226ac55..dd0aed770 100644 --- a/src/arch/x86/tlb.cc +++ b/src/arch/x86/tlb.cc @@ -232,15 +232,22 @@ TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const { Addr paddr = req->getPaddr(); - // Check for an access to the local APIC - if (FullSystem) { + AddrRange m5opRange(0xFFFF0000, 0xFFFFFFFF); + + if (m5opRange.contains(paddr)) { + if (m5opRange.contains(paddr)) { + req->setFlags(Request::MMAPPED_IPR | Request::GENERIC_IPR); + req->setPaddr(GenericISA::iprAddressPseudoInst( + (paddr >> 8) & 0xFF, + paddr & 0xFF)); + } + } else if (FullSystem) { + // Check for an access to the local APIC LocalApicBase localApicBase = tc->readMiscRegNoEffect(MISCREG_APIC_BASE); AddrRange apicRange(localApicBase.base * PageBytes, (localApicBase.base + 1) * PageBytes - 1); - AddrRange m5opRange(0xFFFF0000, 0xFFFFFFFF); - if (apicRange.contains(paddr)) { // The Intel developer's manuals say the below restrictions apply, // but the linux kernel, because of a compiler optimization, breaks @@ -257,11 +264,6 @@ TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const req->setFlags(Request::UNCACHEABLE); req->setPaddr(x86LocalAPICAddress(tc->contextId(), paddr - apicRange.start())); - } else if (m5opRange.contains(paddr)) { - req->setFlags(Request::MMAPPED_IPR | Request::GENERIC_IPR); - req->setPaddr(GenericISA::iprAddressPseudoInst( - (paddr >> 8) & 0xFF, - paddr & 0xFF)); } } diff --git a/src/arch/x86/utility.cc b/src/arch/x86/utility.cc index d58498be2..f7d0f816e 100644 --- a/src/arch/x86/utility.cc +++ b/src/arch/x86/utility.cc @@ -52,9 +52,7 @@ namespace X86ISA { uint64_t getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp) { - if (!FullSystem) { - panic("getArgument() only implemented for full system mode.\n"); - } else if (fp) { + if (fp) { panic("getArgument(): Floating point arguments not implemented\n"); } else if (size != 8) { panic("getArgument(): Can only handle 64-bit arguments.\n"); diff --git a/src/cpu/kvm/base.cc b/src/cpu/kvm/base.cc index ef9e8bb31..95d91467e 100644 --- a/src/cpu/kvm/base.cc +++ b/src/cpu/kvm/base.cc @@ -85,8 +85,14 @@ BaseKvmCPU::BaseKvmCPU(BaseKvmCPUParams *params) panic("KVM: Failed to determine host page size (%i)\n", errno); - thread = new SimpleThread(this, 0, params->system, - params->itb, params->dtb, params->isa[0]); + if (FullSystem) + thread = new SimpleThread(this, 0, params->system, params->itb, params->dtb, + params->isa[0]); + else + thread = new SimpleThread(this, /* thread_num */ 0, params->system, + params->workload[0], params->itb, + params->dtb, params->isa[0]); + thread->setStatus(ThreadContext::Halted); tc = thread->getTC(); threadContexts.push_back(tc); @@ -458,7 +464,7 @@ BaseKvmCPU::suspendContext(ThreadID thread_num) if (_status == Idle) return; - assert(_status == Running); + assert(_status == Running || _status == RunningServiceCompletion); // The tick event may no be scheduled if the quest has requested // the monitor to wait for interrupts. The normal CPU models can @@ -1011,6 +1017,7 @@ BaseKvmCPU::doMMIOAccess(Addr paddr, void *data, int size, bool write) const Cycles ipr_delay(write ? TheISA::handleIprWrite(tc, &pkt) : TheISA::handleIprRead(tc, &pkt)); + threadContextDirty = true; return clockPeriod() * ipr_delay; } else { // Temporarily lock and migrate to the event queue of the diff --git a/src/sim/pseudo_inst.cc b/src/sim/pseudo_inst.cc index e85e3d19a..80737003c 100644 --- a/src/sim/pseudo_inst.cc +++ b/src/sim/pseudo_inst.cc @@ -52,6 +52,7 @@ #include "arch/kernel_stats.hh" #include "arch/utility.hh" #include "arch/vtophys.hh" +#include "arch/pseudo_inst.hh" #include "base/debug.hh" #include "base/output.hh" #include "config/the_isa.hh" @@ -64,6 +65,7 @@ #include "debug/WorkItems.hh" #include "params/BaseCPU.hh" #include "sim/full_system.hh" +#include "sim/process.hh" #include "sim/pseudo_inst.hh" #include "sim/serialize.hh" #include "sim/sim_events.hh" @@ -198,6 +200,15 @@ pseudoInst(ThreadContext *tc, uint8_t func, uint8_t subfunc) warn("Unimplemented m5 op (0x%x)\n", func); break; + /* SE mode functions */ + case 0x60: // syscall_func + m5Syscall(tc); + break; + + case 0x61: // pagefault_func + m5PageFault(tc); + break; + default: warn("Unhandled m5 op: 0x%x\n", func); break; diff --git a/src/sim/system.cc b/src/sim/system.cc index 1f63dbf33..c311d65b9 100644 --- a/src/sim/system.cc +++ b/src/sim/system.cc @@ -324,6 +324,16 @@ System::allocPhysPages(int npages) { Addr return_addr = pagePtr << PageShift; pagePtr += npages; + + Addr next_return_addr = pagePtr << PageShift; + + AddrRange m5opRange(0xffff0000, 0xffffffff); + if (m5opRange.contains(next_return_addr)) { + warn("Reached m5ops MMIO region\n"); + return_addr = 0xffffffff; + pagePtr = 0xffffffff >> PageShift; + } + if ((pagePtr << PageShift) > physmem.totalSize()) fatal("Out of memory, please increase size of physical memory."); return return_addr; diff --git a/util/m5/m5ops.h b/util/m5/m5ops.h index 8ff1ac42f..cd3b17b2d 100644 --- a/util/m5/m5ops.h +++ b/util/m5/m5ops.h @@ -59,8 +59,11 @@ #define reserved4_func 0x58 // Reserved for user #define reserved5_func 0x59 // Reserved for user -#define work_begin_func 0x5a -#define work_end_func 0x5b +#define work_begin_func 0x5a +#define work_end_func 0x5b + +#define syscall_func 0x60 // Reserved for user +#define pagefault_func 0x61 // Reserved for user // These operations are for critical path annotation #define annotate_func 0x55 |