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-rw-r--r--src/arch/x86/floatregfile.hh4
-rw-r--r--src/arch/x86/isa/operands.isa2
-rw-r--r--src/arch/x86/miscregs.hh81
-rw-r--r--src/arch/x86/x86_traits.hh6
4 files changed, 81 insertions, 12 deletions
diff --git a/src/arch/x86/floatregfile.hh b/src/arch/x86/floatregfile.hh
index 18371280d..282cac796 100644
--- a/src/arch/x86/floatregfile.hh
+++ b/src/arch/x86/floatregfile.hh
@@ -100,7 +100,8 @@ namespace X86ISA
{
std::string getFloatRegName(RegIndex);
- const int NumFloatArchRegs = NumMMXRegs + NumXMMRegs;
+ //Each 128 bit xmm register is broken into two effective 64 bit registers.
+ const int NumFloatArchRegs = NumMMXRegs + 2 * NumXMMRegs;
const int NumFloatRegs = NumFloatArchRegs;
class FloatRegFile
@@ -115,6 +116,7 @@ namespace X86ISA
{
uint64_t q[NumFloatRegs];
double d[NumFloatRegs];
+ float f[NumFloatRegs][2];
};
public:
diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa
index 098a75370..3a557169f 100644
--- a/src/arch/x86/isa/operands.isa
+++ b/src/arch/x86/isa/operands.isa
@@ -107,6 +107,6 @@ def operands {{
'uIP': ('UPC', 'uqw', None, (None, None, 'IsControl'), 11),
'nuIP': ('NUPC', 'uqw', None, (None, None, 'IsControl'), 12),
'ccFlagBits': ('IntReg', 'uqw', 'NUM_INTREGS + NumMicroIntRegs', None, 20),
- 'SegBase': ('ControlReg', 'uqw', 'MISCREG_SEG_BASE_BASE + segment', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 50),
+ 'SegBase': ('ControlReg', 'uqw', 'MISCREG_SEG_BASE(segment)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 50),
'Mem': ('Mem', 'uqw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100)
}};
diff --git a/src/arch/x86/miscregs.hh b/src/arch/x86/miscregs.hh
index 8792bf6dd..01499e7ad 100644
--- a/src/arch/x86/miscregs.hh
+++ b/src/arch/x86/miscregs.hh
@@ -58,6 +58,7 @@
#ifndef __ARCH_X86_MISCREGS_HH__
#define __ARCH_X86_MISCREGS_HH__
+#include "arch/x86/x86_traits.hh"
#include "base/bitunion.hh"
namespace X86ISA
@@ -97,7 +98,7 @@ namespace X86ISA
MISCREG_CR15,
// Debug registers
- MISCREG_DR_BASE,
+ MISCREG_DR_BASE = MISCREG_CR_BASE + NumCRegs,
MISCREG_DR0 = MISCREG_DR_BASE,
MISCREG_DR1,
MISCREG_DR2,
@@ -108,7 +109,7 @@ namespace X86ISA
MISCREG_DR7,
// Flags register
- MISCREG_RFLAGS,
+ MISCREG_RFLAGS = MISCREG_DR_BASE + NumDRegs,
// Segment selectors
MISCREG_SEG_SEL_BASE,
@@ -120,7 +121,7 @@ namespace X86ISA
MISCREG_GS,
// Hidden segment base field
- MISCREG_SEG_BASE_BASE,
+ MISCREG_SEG_BASE_BASE = MISCREG_SEG_SEL_BASE + NumSegments,
MISCREG_ES_BASE = MISCREG_SEG_BASE_BASE,
MISCREG_CS_BASE,
MISCREG_SS_BASE,
@@ -129,7 +130,7 @@ namespace X86ISA
MISCREG_GS_BASE,
// Hidden segment limit field
- MISCREG_SEG_LIMIT_BASE,
+ MISCREG_SEG_LIMIT_BASE = MISCREG_SEG_BASE_BASE + NumSegments,
MISCREG_ES_LIMIT = MISCREG_SEG_LIMIT_BASE,
MISCREG_CS_LIMIT,
MISCREG_SS_LIMIT,
@@ -138,7 +139,7 @@ namespace X86ISA
MISCREG_GS_LIMIT,
// Hidden segment limit attributes
- MISCREG_SEG_ATTR_BASE,
+ MISCREG_SEG_ATTR_BASE = MISCREG_SEG_LIMIT_BASE + NumSegments,
MISCREG_ES_ATTR = MISCREG_SEG_ATTR_BASE,
MISCREG_CS_ATTR,
MISCREG_SS_ATTR,
@@ -147,34 +148,94 @@ namespace X86ISA
MISCREG_GS_ATTR,
// System segment selectors
- MISCREG_SYSSEG_SEL_BASE,
+ MISCREG_SYSSEG_SEL_BASE = MISCREG_SEG_ATTR_BASE + NumSegments,
MISCREG_LDTR = MISCREG_SYSSEG_SEL_BASE,
MISCREG_TR,
// Hidden system segment base field
- MISCREG_SYSSEG_BASE_BASE,
+ MISCREG_SYSSEG_BASE_BASE = MISCREG_SYSSEG_SEL_BASE + NumSysSegments,
MISCREG_LDTR_BASE = MISCREG_SYSSEG_BASE_BASE,
MISCREG_TR_BASE,
MISCREG_GDTR_BASE,
MISCREG_IDTR_BASE,
// Hidden system segment limit field
- MISCREG_SYSSEG_LIMIT_BASE,
+ MISCREG_SYSSEG_LIMIT_BASE = MISCREG_SYSSEG_BASE_BASE + NumSysSegments,
MISCREG_LDTR_LIMIT = MISCREG_SYSSEG_LIMIT_BASE,
MISCREG_TR_LIMIT,
MISCREG_GDTR_LIMIT,
MISCREG_IDTR_LIMIT,
// Hidden system segment attribute field
- MISCREG_SYSSEG_ATTR_BASE,
+ MISCREG_SYSSEG_ATTR_BASE = MISCREG_SYSSEG_LIMIT_BASE + NumSysSegments,
MISCREG_LDTR_ATTR = MISCREG_SYSSEG_ATTR_BASE,
MISCREG_TR_ATTR,
//XXX Add "Model-Specific Registers"
- NUM_MISCREGS
+ NUM_MISCREGS = MISCREG_SYSSEG_ATTR_BASE + NumSysSegments
};
+ static inline MiscRegIndex
+ MISCREG_CR(int index)
+ {
+ return (MiscRegIndex)(MISCREG_CR_BASE + index);
+ }
+
+ static inline MiscRegIndex
+ MISCREG_DR(int index)
+ {
+ return (MiscRegIndex)(MISCREG_DR_BASE + index);
+ }
+
+ static inline MiscRegIndex
+ MISCREG_SEG_SEL(int index)
+ {
+ return (MiscRegIndex)(MISCREG_SEG_SEL_BASE + index);
+ }
+
+ static inline MiscRegIndex
+ MISCREG_SEG_BASE(int index)
+ {
+ return (MiscRegIndex)(MISCREG_SEG_BASE_BASE + index);
+ }
+
+ static inline MiscRegIndex
+ MISCREG_SEG_LIMIT(int index)
+ {
+ return (MiscRegIndex)(MISCREG_SEG_LIMIT_BASE + index);
+ }
+
+ static inline MiscRegIndex
+ MISCREG_SEG_ATTR(int index)
+ {
+ return (MiscRegIndex)(MISCREG_SEG_ATTR_BASE + index);
+ }
+
+ static inline MiscRegIndex
+ MISCREG_SYSSEG_SEL(int index)
+ {
+ return (MiscRegIndex)(MISCREG_SYSSEG_SEL_BASE + index);
+ }
+
+ static inline MiscRegIndex
+ MISCREG_SYSSEG_BASE(int index)
+ {
+ return (MiscRegIndex)(MISCREG_SYSSEG_BASE_BASE + index);
+ }
+
+ static inline MiscRegIndex
+ MISCREG_SYSSEG_LIMIT(int index)
+ {
+ return (MiscRegIndex)(MISCREG_SYSSEG_LIMIT_BASE + index);
+ }
+
+ static inline MiscRegIndex
+ MISCREG_SYSSEG_ATTR(int index)
+ {
+ return (MiscRegIndex)(MISCREG_SYSSEG_ATTR_BASE + index);
+ }
+
/**
* A type to describe the condition code bits of the RFLAGS register,
* plus two flags, EZF and ECF, which are only visible to microcode.
diff --git a/src/arch/x86/x86_traits.hh b/src/arch/x86/x86_traits.hh
index 5794e7079..381a60a63 100644
--- a/src/arch/x86/x86_traits.hh
+++ b/src/arch/x86/x86_traits.hh
@@ -65,6 +65,12 @@ namespace X86ISA
const int NumMMXRegs = 8;
const int NumXMMRegs = 16;
+
+ const int NumCRegs = 16;
+ const int NumDRegs = 8;
+
+ const int NumSegments = 6;
+ const int NumSysSegments = 4;
}
#endif //__ARCH_X86_X86TRAITS_HH__