diff options
| -rw-r--r-- | src/arch/arm/tlb.cc | 6 | ||||
| -rw-r--r-- | src/arch/arm/tlb.hh | 1 |
2 files changed, 5 insertions, 2 deletions
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc index aee6a251a..688c0d46b 100644 --- a/src/arch/arm/tlb.cc +++ b/src/arch/arm/tlb.cc @@ -78,7 +78,7 @@ TLB::TLB(const ArmTLBParams *p) stage2Mmu(NULL), rangeMRU(1), aarch64(false), aarch64EL(EL0), isPriv(false), isSecure(false), isHyp(false), asid(0), vmid(0), dacr(0), - miscRegValid(false), curTranType(NormalTran) + miscRegValid(false), miscRegContext(0), curTranType(NormalTran) { tableWalker->setTlb(this); @@ -1204,7 +1204,8 @@ TLB::updateMiscReg(ThreadContext *tc, ArmTranslationType tranType) // check if the regs have changed, or the translation mode is different. // NOTE: the tran type doesn't affect stage 2 TLB's as they only handle // one type of translation anyway - if (miscRegValid && ((tranType == curTranType) || isStage2)) { + if (miscRegValid && miscRegContext == tc->contextId() && + ((tranType == curTranType) || isStage2)) { return; } @@ -1300,6 +1301,7 @@ TLB::updateMiscReg(ThreadContext *tc, ArmTranslationType tranType) } } miscRegValid = true; + miscRegContext = tc->contextId(); curTranType = tranType; } diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh index 63707dba2..35049db48 100644 --- a/src/arch/arm/tlb.hh +++ b/src/arch/arm/tlb.hh @@ -327,6 +327,7 @@ protected: HCR hcr; uint32_t dacr; bool miscRegValid; + ContextID miscRegContext; ArmTranslationType curTranType; // Cached copies of system-level properties |