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-rw-r--r--src/base/traceflags.py152
-rw-r--r--src/mem/bus.cc8
-rw-r--r--src/mem/port.cc8
-rw-r--r--src/mem/port.hh4
4 files changed, 91 insertions, 81 deletions
diff --git a/src/base/traceflags.py b/src/base/traceflags.py
index 7dbaac60e..3b7dd0f81 100644
--- a/src/base/traceflags.py
+++ b/src/base/traceflags.py
@@ -45,105 +45,107 @@ ccfilename = sys.argv[1] + '.cc'
# To define a new flag, simply add it to this list.
#
baseFlags = [
- 'TCPIP',
+ 'AlphaConsole',
+ 'BADADDR',
+ 'BPredRAS',
'Bus',
- 'ScsiDisk',
- 'ScsiCtrl',
- 'ScsiNone',
- 'DMA',
- 'DMAReadVerbose',
- 'DMAWriteVerbose',
- 'TLB',
- 'SimpleDisk',
- 'SimpleDiskData',
+ 'BusAddrRanges',
+ 'BusBridge',
+ 'Cache',
+ 'Chains',
'Clock',
- 'Regs',
- 'MC146818',
- 'IPI',
- 'Timer',
- 'Mbox',
- 'PCIA',
- 'PCIDEV',
- 'PciConfigAll',
- 'ISP',
- 'BADADDR',
+ 'Commit',
+ 'CommitRate',
+ 'Config',
'Console',
'ConsolePoll',
'ConsoleVerbose',
- 'AlphaConsole',
- 'Flow',
- 'Interrupt',
- 'Fault',
+ 'Context',
'Cycle',
- 'Loader',
- 'MMU',
+ 'DMA',
+ 'DMAReadVerbose',
+ 'DMAWriteVerbose',
+ 'DebugPrintf',
+ 'Decode',
+ 'DiskImage',
+ 'DiskImageRead',
+ 'DiskImageWrite',
+ 'DynInst',
'Ethernet',
- 'EthernetPIO',
+ 'EthernetCksum',
'EthernetDMA',
'EthernetData',
'EthernetDesc',
'EthernetIntr',
+ 'EthernetPIO',
'EthernetSM',
- 'EthernetCksum',
- 'GDBMisc',
+ 'Event',
+ 'Fault',
+ 'Fetch',
+ 'Flow',
+ 'FreeList',
+ 'FullCPU',
'GDBAcc',
+ 'GDBExtra',
+ 'GDBMisc',
'GDBRead',
- 'GDBWrite',
- 'GDBSend',
'GDBRecv',
- 'GDBExtra',
- 'VtoPhys',
- 'Printf',
- 'DebugPrintf',
- 'Serialize',
- 'Event',
- 'PCEvent',
- 'Syscall',
- 'SyscallVerbose',
- 'DiskImage',
- 'DiskImageRead',
- 'DiskImageWrite',
- 'InstExec',
- 'BPredRAS',
- 'Cache',
+ 'GDBSend',
+ 'GDBWrite',
+ 'HWPrefetch',
+ 'IEW',
'IIC',
'IICMore',
- 'MSHR',
- 'Chains',
- 'Pipeline',
- 'Stats',
- 'StatEvents',
- 'Context',
- 'Config',
- 'Sampler',
- 'WriteBarrier',
+ 'IPI',
+ 'IQ',
+ 'ISP',
'IdeCtrl',
'IdeDisk',
- 'Tsunami',
- 'Uart',
- 'Split',
- 'SQL',
- 'Thread',
- 'Fetch',
- 'Decode',
- 'Rename',
- 'IEW',
- 'Commit',
- 'IQ',
- 'ROB',
- 'FreeList',
- 'RenameMap',
+ 'InstExec',
+ 'Interrupt',
'LDSTQ',
- 'StoreSet',
+ 'Loader',
+ 'MC146818',
+ 'MMU',
+ 'MSHR',
+ 'Mbox',
'MemDepUnit',
- 'DynInst',
- 'FullCPU',
- 'CommitRate',
'OoOCPU',
- 'HWPrefetch',
- 'Stack',
+ 'PCEvent',
+ 'PCIA',
+ 'PCIDEV',
+ 'PciConfigAll',
+ 'Pipeline',
+ 'Printf',
+ 'ROB',
+ 'Regs',
+ 'Rename',
+ 'RenameMap',
+ 'SQL',
+ 'Sampler',
+ 'ScsiCtrl',
+ 'ScsiDisk',
+ 'ScsiNone',
+ 'Serialize',
'SimpleCPU',
+ 'SimpleDisk',
+ 'SimpleDiskData',
'Sparc',
+ 'Split',
+ 'Stack',
+ 'StatEvents',
+ 'Stats',
+ 'StoreSet',
+ 'Syscall',
+ 'SyscallVerbose',
+ 'TCPIP',
+ 'TLB',
+ 'Thread',
+ 'Timer',
+ 'Tsunami',
+ 'Uart',
+ 'VtoPhys',
+ 'WriteBarrier',
]
#
diff --git a/src/mem/bus.cc b/src/mem/bus.cc
index a2ce00139..cfc99a64f 100644
--- a/src/mem/bus.cc
+++ b/src/mem/bus.cc
@@ -130,7 +130,7 @@ Bus::recvStatusChange(Port::Status status, int id)
assert(status == Port::RangeChange &&
"The other statuses need to be implemented.");
- DPRINTF(Bus, "received RangeChange from device id %d\n", id);
+ DPRINTF(BusAddrRanges, "received RangeChange from device id %d\n", id);
assert(id < interfaces.size() && id >= 0);
int x;
@@ -157,7 +157,7 @@ Bus::recvStatusChange(Port::Status status, int id)
dm.portId = id;
dm.range = *iter;
- DPRINTF(Bus, "Adding range %llx - %llx for id %d\n",
+ DPRINTF(BusAddrRanges, "Adding range %llx - %llx for id %d\n",
dm.range.start, dm.range.end, id);
portList.push_back(dm);
}
@@ -178,11 +178,11 @@ Bus::addressRanges(AddrRangeList &resp, AddrRangeList &snoop, int id)
resp.clear();
snoop.clear();
- DPRINTF(Bus, "received address range request, returning:\n");
+ DPRINTF(BusAddrRanges, "received address range request, returning:\n");
for (portIter = portList.begin(); portIter != portList.end(); portIter++) {
if (portIter->portId != id) {
resp.push_back(portIter->range);
- DPRINTF(Bus, " -- %#llX : %#llX\n",
+ DPRINTF(BusAddrRanges, " -- %#llX : %#llX\n",
portIter->range.start, portIter->range.end);
}
}
diff --git a/src/mem/port.cc b/src/mem/port.cc
index ee224d92b..651cb739a 100644
--- a/src/mem/port.cc
+++ b/src/mem/port.cc
@@ -31,10 +31,18 @@
*/
#include "base/chunk_generator.hh"
+#include "base/trace.hh"
#include "mem/packet_impl.hh"
#include "mem/port.hh"
void
+Port::setPeer(Port *port)
+{
+ DPRINTF(Config, "setting peer to %s\n", port->name());
+ peer = port;
+}
+
+void
Port::blobHelper(Addr addr, uint8_t *p, int size, Packet::Command cmd)
{
Request req(false);
diff --git a/src/mem/port.hh b/src/mem/port.hh
index 85209964e..f9103865e 100644
--- a/src/mem/port.hh
+++ b/src/mem/port.hh
@@ -112,9 +112,9 @@ class Port
/** Function to set the pointer for the peer port.
@todo should be called by the configuration stuff (python).
*/
- void setPeer(Port *port) { peer = port; }
+ void setPeer(Port *port);
- /** Function to set the pointer for the peer port.
+ /** Function to set the pointer for the peer port.
@todo should be called by the configuration stuff (python).
*/
Port *getPeer() { return peer; }