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-rw-r--r--configs/common/Caches.py36
-rw-r--r--tests/configs/o3-timing-mp.py25
-rw-r--r--tests/configs/pc-o3-timing.py53
-rw-r--r--tests/configs/pc-simple-atomic.py55
-rw-r--r--tests/configs/pc-simple-timing.py54
-rw-r--r--tests/configs/realview-o3-checker.py42
-rw-r--r--tests/configs/realview-o3-dual.py41
-rw-r--r--tests/configs/realview-o3.py42
-rw-r--r--tests/configs/realview-simple-atomic-dual.py41
-rw-r--r--tests/configs/realview-simple-atomic.py41
-rw-r--r--tests/configs/realview-simple-timing-dual.py41
-rw-r--r--tests/configs/realview-simple-timing.py42
-rw-r--r--tests/configs/tsunami-inorder.py43
-rw-r--r--tests/configs/tsunami-o3-dual.py43
-rw-r--r--tests/configs/tsunami-o3.py43
-rw-r--r--tests/configs/tsunami-simple-atomic-dual.py42
-rw-r--r--tests/configs/tsunami-simple-atomic.py42
-rw-r--r--tests/configs/tsunami-simple-timing-dual.py42
-rw-r--r--tests/configs/tsunami-simple-timing.py43
19 files changed, 57 insertions, 754 deletions
diff --git a/configs/common/Caches.py b/configs/common/Caches.py
index 0b5f9e182..867d0cb2e 100644
--- a/configs/common/Caches.py
+++ b/configs/common/Caches.py
@@ -40,22 +40,40 @@
from m5.objects import *
-class L1Cache(BaseCache):
+# Base implementations of L1, L2, IO and TLB-walker caches. There are
+# used in the regressions and also as base components in the
+# system-configuration scripts. The values are meant to serve as a
+# starting point, and specific parameters can be overridden in the
+# specific instantiations.
+
+class L1(BaseCache):
assoc = 2
- block_size = 64
hit_latency = 2
response_latency = 2
- mshrs = 10
+ block_size = 64
+ mshrs = 4
tgts_per_mshr = 20
is_top_level = True
-class L2Cache(BaseCache):
+class L2(BaseCache):
assoc = 8
block_size = 64
hit_latency = 20
response_latency = 20
+ mshrs = 92
+ tgts_per_mshr = 16
+ write_buffers = 8
+
+class IOCache(BaseCache):
+ assoc = 8
+ block_size = 64
+ hit_latency = 50
+ response_latency = 50
mshrs = 20
+ size = '1kB'
tgts_per_mshr = 12
+ forward_snoops = False
+ is_top_level = True
class PageTableWalkerCache(BaseCache):
assoc = 2
@@ -67,13 +85,3 @@ class PageTableWalkerCache(BaseCache):
tgts_per_mshr = 12
is_top_level = True
-class IOCache(BaseCache):
- assoc = 8
- block_size = 64
- hit_latency = 50
- response_latency = 50
- mshrs = 20
- size = '1kB'
- tgts_per_mshr = 12
- forward_snoops = False
- is_top_level = True
diff --git a/tests/configs/o3-timing-mp.py b/tests/configs/o3-timing-mp.py
index 0b10f5766..b02b43d03 100644
--- a/tests/configs/o3-timing-mp.py
+++ b/tests/configs/o3-timing-mp.py
@@ -29,30 +29,7 @@
import m5
from m5.objects import *
m5.util.addToPath('../configs/common')
-
-# --------------------
-# Base L1 Cache
-# ====================
-
-class L1(BaseCache):
- hit_latency = 2
- response_latency = 2
- block_size = 64
- mshrs = 4
- tgts_per_mshr = 20
- is_top_level = True
-
-# ----------------------
-# Base L2 Cache
-# ----------------------
-
-class L2(BaseCache):
- block_size = 64
- hit_latency = 20
- response_latency = 20
- mshrs = 92
- tgts_per_mshr = 16
- write_buffers = 8
+from Caches import *
nb_cores = 4
cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(nb_cores) ]
diff --git a/tests/configs/pc-o3-timing.py b/tests/configs/pc-o3-timing.py
index 729f3bd8f..c4317ec23 100644
--- a/tests/configs/pc-o3-timing.py
+++ b/tests/configs/pc-o3-timing.py
@@ -31,59 +31,10 @@ from m5.objects import *
m5.util.addToPath('../configs/common')
from Benchmarks import SysConfig
import FSConfig
+from Caches import *
mem_size = '128MB'
-# --------------------
-# Base L1 Cache
-# ====================
-
-class L1(BaseCache):
- hit_latency = 2
- response_latency = 2
- block_size = 64
- mshrs = 4
- tgts_per_mshr = 20
- is_top_level = True
-
-# ----------------------
-# Base L2 Cache
-# ----------------------
-
-class L2(BaseCache):
- block_size = 64
- hit_latency = 20
- response_latency = 20
- mshrs = 92
- tgts_per_mshr = 16
- write_buffers = 8
-
-# ---------------------
-# Page table walker cache
-# ---------------------
-class PageTableWalkerCache(BaseCache):
- assoc = 2
- block_size = 64
- hit_latency = 2
- response_latency = 2
- mshrs = 10
- size = '1kB'
- tgts_per_mshr = 12
-
-# ---------------------
-# I/O Cache
-# ---------------------
-class IOCache(BaseCache):
- assoc = 8
- block_size = 64
- hit_latency = 50
- response_latency = 50
- mshrs = 20
- size = '1kB'
- tgts_per_mshr = 12
- addr_ranges = [AddrRange(0, size=mem_size)]
- forward_snoops = False
-
#cpu
cpu = DerivO3CPU(cpu_id=0)
#the system
@@ -94,7 +45,7 @@ system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9')
system.cpu = cpu
#create the iocache
-system.iocache = IOCache(clock = '1GHz')
+system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange(mem_size)])
system.iocache.cpu_side = system.iobus.master
system.iocache.mem_side = system.membus.slave
diff --git a/tests/configs/pc-simple-atomic.py b/tests/configs/pc-simple-atomic.py
index 7dfec362e..44ba51b3c 100644
--- a/tests/configs/pc-simple-atomic.py
+++ b/tests/configs/pc-simple-atomic.py
@@ -31,61 +31,10 @@ from m5.objects import *
m5.util.addToPath('../configs/common')
from Benchmarks import SysConfig
import FSConfig
+from Caches import *
mem_size = '128MB'
-# --------------------
-# Base L1 Cache
-# ====================
-
-class L1(BaseCache):
- hit_latency = 2
- response_latency = 2
- block_size = 64
- mshrs = 4
- tgts_per_mshr = 8
- is_top_level = True
-
-# ----------------------
-# Base L2 Cache
-# ----------------------
-
-class L2(BaseCache):
- block_size = 64
- hit_latency = 20
- response_latency = 20
- mshrs = 92
- tgts_per_mshr = 16
- write_buffers = 8
-
-# ---------------------
-# Page table walker cache
-# ---------------------
-class PageTableWalkerCache(BaseCache):
- assoc = 2
- block_size = 64
- hit_latency = 2
- response_latency = 2
- mshrs = 10
- size = '1kB'
- tgts_per_mshr = 12
- is_top_level = True
-
-# ---------------------
-# I/O Cache
-# ---------------------
-class IOCache(BaseCache):
- assoc = 8
- block_size = 64
- hit_latency = 50
- response_latency = 50
- mshrs = 20
- size = '1kB'
- tgts_per_mshr = 12
- addr_ranges = [AddrRange(0, size=mem_size)]
- forward_snoops = False
- is_top_level = True
-
#cpu
cpu = AtomicSimpleCPU(cpu_id=0)
#the system
@@ -96,7 +45,7 @@ system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9')
system.cpu = cpu
#create the iocache
-system.iocache = IOCache(clock = '1GHz')
+system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange(mem_size)])
system.iocache.cpu_side = system.iobus.master
system.iocache.mem_side = system.membus.slave
diff --git a/tests/configs/pc-simple-timing.py b/tests/configs/pc-simple-timing.py
index bfbf926dc..990179008 100644
--- a/tests/configs/pc-simple-timing.py
+++ b/tests/configs/pc-simple-timing.py
@@ -31,60 +31,10 @@ from m5.objects import *
m5.util.addToPath('../configs/common')
from Benchmarks import SysConfig
import FSConfig
-
+from Caches import *
mem_size = '128MB'
-# --------------------
-# Base L1 Cache
-# ====================
-
-class L1(BaseCache):
- hit_latency = 2
- response_latency = 2
- block_size = 64
- mshrs = 4
- tgts_per_mshr = 8
- is_top_level = True
-
-# ----------------------
-# Base L2 Cache
-# ----------------------
-
-class L2(BaseCache):
- block_size = 64
- hit_latency = 20
- response_latency = 20
- mshrs = 92
- tgts_per_mshr = 16
- write_buffers = 8
-
-# ---------------------
-# Page table walker cache
-# ---------------------
-class PageTableWalkerCache(BaseCache):
- assoc = 2
- block_size = 64
- hit_latency = 2
- response_latency = 2
- mshrs = 10
- size = '1kB'
- tgts_per_mshr = 12
-
-# ---------------------
-# I/O Cache
-# ---------------------
-class IOCache(BaseCache):
- assoc = 8
- block_size = 64
- hit_latency = 50
- response_latency = 50
- mshrs = 20
- size = '1kB'
- tgts_per_mshr = 12
- addr_ranges = [AddrRange(0, size=mem_size)]
- forward_snoops = False
-
#cpu
cpu = TimingSimpleCPU(cpu_id=0)
#the system
@@ -95,7 +45,7 @@ system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9')
system.cpu = cpu
#create the iocache
-system.iocache = IOCache(clock = '1GHz')
+system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange(mem_size)])
system.iocache.cpu_side = system.iobus.master
system.iocache.mem_side = system.membus.slave
diff --git a/tests/configs/realview-o3-checker.py b/tests/configs/realview-o3-checker.py
index a791b3983..248a1d41b 100644
--- a/tests/configs/realview-o3-checker.py
+++ b/tests/configs/realview-o3-checker.py
@@ -39,45 +39,7 @@ import m5
from m5.objects import *
m5.util.addToPath('../configs/common')
import FSConfig
-
-
-# --------------------
-# Base L1 Cache
-# ====================
-
-class L1(BaseCache):
- hit_latency = 2
- response_latency = 2
- block_size = 64
- mshrs = 4
- tgts_per_mshr = 20
- is_top_level = True
-
-# ----------------------
-# Base L2 Cache
-# ----------------------
-
-class L2(BaseCache):
- block_size = 64
- hit_latency = 20
- response_latency = 20
- mshrs = 92
- tgts_per_mshr = 16
- write_buffers = 8
-
-# ---------------------
-# I/O Cache
-# ---------------------
-class IOCache(BaseCache):
- assoc = 8
- block_size = 64
- hit_latency = 50
- response_latency = 50
- mshrs = 20
- size = '1kB'
- tgts_per_mshr = 12
- addr_ranges = [AddrRange(0, size='256MB')]
- forward_snoops = False
+from Caches import *
#cpu
cpu = DerivO3CPU(cpu_id=0)
@@ -89,7 +51,7 @@ system.cpu = cpu
cpu.addCheckerCpu()
#create the iocache
-system.iocache = IOCache(clock = '1GHz')
+system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('256MB')])
system.iocache.cpu_side = system.iobus.master
system.iocache.mem_side = system.membus.slave
diff --git a/tests/configs/realview-o3-dual.py b/tests/configs/realview-o3-dual.py
index 599ef6f8c..cc4fa236f 100644
--- a/tests/configs/realview-o3-dual.py
+++ b/tests/configs/realview-o3-dual.py
@@ -31,50 +31,13 @@ from m5.objects import *
m5.util.addToPath('../configs/common')
import FSConfig
from Benchmarks import *
-
-# --------------------
-# Base L1 Cache
-# ====================
-
-class L1(BaseCache):
- hit_latency = 2
- response_latency = 2
- block_size = 64
- mshrs = 4
- tgts_per_mshr = 20
- is_top_level = True
-
-# ----------------------
-# Base L2 Cache
-# ----------------------
-
-class L2(BaseCache):
- block_size = 64
- hit_latency = 20
- response_latency = 20
- mshrs = 92
- tgts_per_mshr = 16
- write_buffers = 8
-
-# ---------------------
-# I/O Cache
-# ---------------------
-class IOCache(BaseCache):
- assoc = 8
- block_size = 64
- hit_latency = 50
- response_latency = 50
- mshrs = 20
- size = '1kB'
- tgts_per_mshr = 12
- addr_ranges = [AddrRange(0, size='256MB')]
- forward_snoops = False
+from Caches import *
#cpu
cpus = [DerivO3CPU(cpu_id=i) for i in xrange(2) ]
#the system
system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False)
-system.iocache = IOCache(clock = '1GHz')
+system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('256MB')])
system.iocache.cpu_side = system.iobus.master
system.iocache.mem_side = system.membus.slave
diff --git a/tests/configs/realview-o3.py b/tests/configs/realview-o3.py
index 698c6dd14..6f98309fe 100644
--- a/tests/configs/realview-o3.py
+++ b/tests/configs/realview-o3.py
@@ -30,45 +30,7 @@ import m5
from m5.objects import *
m5.util.addToPath('../configs/common')
import FSConfig
-
-
-# --------------------
-# Base L1 Cache
-# ====================
-
-class L1(BaseCache):
- hit_latency = 2
- response_latency = 2
- block_size = 64
- mshrs = 4
- tgts_per_mshr = 20
- is_top_level = True
-
-# ----------------------
-# Base L2 Cache
-# ----------------------
-
-class L2(BaseCache):
- block_size = 64
- hit_latency = 20
- response_latency = 20
- mshrs = 92
- tgts_per_mshr = 16
- write_buffers = 8
-
-# ---------------------
-# I/O Cache
-# ---------------------
-class IOCache(BaseCache):
- assoc = 8
- block_size = 64
- hit_latency = 50
- response_latency = 50
- mshrs = 20
- size = '1kB'
- tgts_per_mshr = 12
- addr_ranges = [AddrRange(0, size='256MB')]
- forward_snoops = False
+from Caches import *
#cpu
cpu = DerivO3CPU(cpu_id=0)
@@ -78,7 +40,7 @@ system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False)
system.cpu = cpu
#create the iocache
-system.iocache = IOCache(clock = '1GHz')
+system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('256MB')])
system.iocache.cpu_side = system.iobus.master
system.iocache.mem_side = system.membus.slave
diff --git a/tests/configs/realview-simple-atomic-dual.py b/tests/configs/realview-simple-atomic-dual.py
index 9bf2fd70d..b26272a91 100644
--- a/tests/configs/realview-simple-atomic-dual.py
+++ b/tests/configs/realview-simple-atomic-dual.py
@@ -31,50 +31,13 @@ from m5.objects import *
m5.util.addToPath('../configs/common')
import FSConfig
from Benchmarks import *
-
-# --------------------
-# Base L1 Cache
-# ====================
-
-class L1(BaseCache):
- hit_latency = 2
- response_latency = 2
- block_size = 64
- mshrs = 4
- tgts_per_mshr = 8
- is_top_level = True
-
-# ----------------------
-# Base L2 Cache
-# ----------------------
-
-class L2(BaseCache):
- block_size = 64
- hit_latency = 20
- response_latency = 20
- mshrs = 92
- tgts_per_mshr = 16
- write_buffers = 8
-
-# ---------------------
-# I/O Cache
-# ---------------------
-class IOCache(BaseCache):
- assoc = 8
- block_size = 64
- hit_latency = 50
- response_latency = 50
- mshrs = 20
- size = '1kB'
- tgts_per_mshr = 12
- addr_ranges = [AddrRange(0, size='256MB')]
- forward_snoops = False
+from Caches import *
#cpu
cpus = [AtomicSimpleCPU(cpu_id=i) for i in xrange(2) ]
#the system
system = FSConfig.makeArmSystem('atomic', "RealView_PBX", None, False)
-system.iocache = IOCache(clock = '1GHz')
+system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('256MB')])
system.iocache.cpu_side = system.iobus.master
system.iocache.mem_side = system.membus.slave
diff --git a/tests/configs/realview-simple-atomic.py b/tests/configs/realview-simple-atomic.py
index 05ef0dd63..2d1efe3fe 100644
--- a/tests/configs/realview-simple-atomic.py
+++ b/tests/configs/realview-simple-atomic.py
@@ -30,44 +30,7 @@ import m5
from m5.objects import *
m5.util.addToPath('../configs/common')
import FSConfig
-
-# --------------------
-# Base L1 Cache
-# ====================
-
-class L1(BaseCache):
- hit_latency = 2
- response_latency = 2
- block_size = 64
- mshrs = 4
- tgts_per_mshr = 8
- is_top_level = True
-
-# ----------------------
-# Base L2 Cache
-# ----------------------
-
-class L2(BaseCache):
- block_size = 64
- hit_latency = 20
- response_latency = 20
- mshrs = 92
- tgts_per_mshr = 16
- write_buffers = 8
-
-# ---------------------
-# I/O Cache
-# ---------------------
-class IOCache(BaseCache):
- assoc = 8
- block_size = 64
- hit_latency = 50
- response_latency = 50
- mshrs = 20
- size = '1kB'
- tgts_per_mshr = 12
- addr_ranges = [AddrRange(0, size='256MB')]
- forward_snoops = False
+from Caches import *
#cpu
cpu = AtomicSimpleCPU(cpu_id=0)
@@ -77,7 +40,7 @@ system = FSConfig.makeArmSystem('atomic', "RealView_PBX", None, False)
system.cpu = cpu
#create the iocache
-system.iocache = IOCache(clock = '1GHz')
+system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('256MB')])
system.iocache.cpu_side = system.iobus.master
system.iocache.mem_side = system.membus.slave
diff --git a/tests/configs/realview-simple-timing-dual.py b/tests/configs/realview-simple-timing-dual.py
index ee5ffaf06..1c86f42bf 100644
--- a/tests/configs/realview-simple-timing-dual.py
+++ b/tests/configs/realview-simple-timing-dual.py
@@ -31,50 +31,13 @@ from m5.objects import *
m5.util.addToPath('../configs/common')
import FSConfig
from Benchmarks import *
-
-# --------------------
-# Base L1 Cache
-# ====================
-
-class L1(BaseCache):
- hit_latency = 2
- response_latency = 2
- block_size = 64
- mshrs = 4
- tgts_per_mshr = 8
- is_top_level = True
-
-# ----------------------
-# Base L2 Cache
-# ----------------------
-
-class L2(BaseCache):
- block_size = 64
- hit_latency = 20
- response_latency = 20
- mshrs = 92
- tgts_per_mshr = 16
- write_buffers = 8
-
-# ---------------------
-# I/O Cache
-# ---------------------
-class IOCache(BaseCache):
- assoc = 8
- block_size = 64
- hit_latency = 50
- response_latency = 50
- mshrs = 20
- size = '1kB'
- tgts_per_mshr = 12
- addr_ranges = [AddrRange(0, size='256MB')]
- forward_snoops = False
+from Caches import *
#cpu
cpus = [TimingSimpleCPU(cpu_id=i) for i in xrange(2) ]
#the system
system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False)
-system.iocache = IOCache(clock = '1GHz')
+system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('256MB')])
system.iocache.cpu_side = system.iobus.master
system.iocache.mem_side = system.membus.slave
diff --git a/tests/configs/realview-simple-timing.py b/tests/configs/realview-simple-timing.py
index 28cd3163f..4bb641e80 100644
--- a/tests/configs/realview-simple-timing.py
+++ b/tests/configs/realview-simple-timing.py
@@ -30,45 +30,7 @@ import m5
from m5.objects import *
m5.util.addToPath('../configs/common')
import FSConfig
-
-
-# --------------------
-# Base L1 Cache
-# ====================
-
-class L1(BaseCache):
- hit_latency = 2
- response_latency = 2
- block_size = 64
- mshrs = 4
- tgts_per_mshr = 8
- is_top_level = True
-
-# ----------------------
-# Base L2 Cache
-# ----------------------
-
-class L2(BaseCache):
- block_size = 64
- hit_latency = 20
- response_latency = 20
- mshrs = 92
- tgts_per_mshr = 16
- write_buffers = 8
-
-# ---------------------
-# I/O Cache
-# ---------------------
-class IOCache(BaseCache):
- assoc = 8
- block_size = 64
- hit_latency = 50
- response_latency = 50
- mshrs = 20
- size = '1kB'
- tgts_per_mshr = 12
- addr_ranges = [AddrRange(0, size='256MB')]
- forward_snoops = False
+from Caches import *
#cpu
cpu = TimingSimpleCPU(cpu_id=0)
@@ -78,7 +40,7 @@ system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False)
system.cpu = cpu
#create the iocache
-system.iocache = IOCache(clock = '1GHz')
+system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('256MB')])
system.iocache.cpu_side = system.iobus.master
system.iocache.mem_side = system.membus.slave
diff --git a/tests/configs/tsunami-inorder.py b/tests/configs/tsunami-inorder.py
index 163ac3ba6..0d7e817e0 100644
--- a/tests/configs/tsunami-inorder.py
+++ b/tests/configs/tsunami-inorder.py
@@ -30,46 +30,7 @@ import m5
from m5.objects import *
m5.util.addToPath('../configs/common')
import FSConfig
-
-
-# --------------------
-# Base L1 Cache
-# ====================
-
-class L1(BaseCache):
- hit_latency = 2
- response_latency = 2
- block_size = 64
- mshrs = 4
- tgts_per_mshr = 8
- is_top_level = True
-
-# ----------------------
-# Base L2 Cache
-# ----------------------
-
-class L2(BaseCache):
- block_size = 64
- hit_latency = 20
- response_latency = 20
- mshrs = 92
- tgts_per_mshr = 16
- write_buffers = 8
-
-# ---------------------
-# I/O Cache
-# ---------------------
-class IOCache(BaseCache):
- assoc = 8
- block_size = 64
- hit_latency = 50
- response_latency = 50
- mshrs = 20
- size = '1kB'
- tgts_per_mshr = 12
- addr_ranges = [AddrRange(0, size='8GB')]
- forward_snoops = False
- is_top_level = True
+from Caches import *
#cpu
cpu = InOrderCPU(cpu_id=0)
@@ -82,7 +43,7 @@ system = FSConfig.makeLinuxAlphaSystem('timing')
system.cpu = cpu
#create the iocache
-system.iocache = IOCache(clock = '1GHz')
+system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('8GB')])
system.iocache.cpu_side = system.iobus.master
system.iocache.mem_side = system.membus.slave
diff --git a/tests/configs/tsunami-o3-dual.py b/tests/configs/tsunami-o3-dual.py
index 5ba14753d..a1564f8f8 100644
--- a/tests/configs/tsunami-o3-dual.py
+++ b/tests/configs/tsunami-o3-dual.py
@@ -30,46 +30,7 @@ import m5
from m5.objects import *
m5.util.addToPath('../configs/common')
import FSConfig
-
-
-# --------------------
-# Base L1 Cache
-# ====================
-
-class L1(BaseCache):
- hit_latency = 2
- response_latency = 2
- block_size = 64
- mshrs = 4
- tgts_per_mshr = 20
- is_top_level = True
-
-# ----------------------
-# Base L2 Cache
-# ----------------------
-
-class L2(BaseCache):
- block_size = 64
- hit_latency = 20
- response_latency = 20
- mshrs = 92
- tgts_per_mshr = 16
- write_buffers = 8
-
-# ---------------------
-# I/O Cache
-# ---------------------
-class IOCache(BaseCache):
- assoc = 8
- block_size = 64
- hit_latency = 50
- response_latency = 50
- mshrs = 20
- size = '1kB'
- tgts_per_mshr = 12
- addr_ranges = [AddrRange(0, size='8GB')]
- forward_snoops = False
- is_top_level = True
+from Caches import *
#cpu
cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(2) ]
@@ -79,7 +40,7 @@ system = FSConfig.makeLinuxAlphaSystem('timing')
system.cpu = cpus
#create the l1/l2 bus
system.toL2Bus = CoherentBus(clock = '2GHz')
-system.iocache = IOCache(clock = '1GHz')
+system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('8GB')])
system.iocache.cpu_side = system.iobus.master
system.iocache.mem_side = system.membus.slave
diff --git a/tests/configs/tsunami-o3.py b/tests/configs/tsunami-o3.py
index 2920c878a..18cbf1db1 100644
--- a/tests/configs/tsunami-o3.py
+++ b/tests/configs/tsunami-o3.py
@@ -30,46 +30,7 @@ import m5
from m5.objects import *
m5.util.addToPath('../configs/common')
import FSConfig
-
-
-# --------------------
-# Base L1 Cache
-# ====================
-
-class L1(BaseCache):
- hit_latency = 2
- response_latency = 2
- block_size = 64
- mshrs = 4
- tgts_per_mshr = 20
- is_top_level = True
-
-# ----------------------
-# Base L2 Cache
-# ----------------------
-
-class L2(BaseCache):
- block_size = 64
- hit_latency = 20
- response_latency = 20
- mshrs = 92
- tgts_per_mshr = 16
- write_buffers = 8
-
-# ---------------------
-# I/O Cache
-# ---------------------
-class IOCache(BaseCache):
- assoc = 8
- block_size = 64
- hit_latency = 50
- response_latency = 50
- mshrs = 20
- size = '1kB'
- tgts_per_mshr = 12
- addr_ranges = [AddrRange(0, size='8GB')]
- forward_snoops = False
- is_top_level = True
+from Caches import *
#cpu
cpu = DerivO3CPU(cpu_id=0)
@@ -79,7 +40,7 @@ system = FSConfig.makeLinuxAlphaSystem('timing')
system.cpu = cpu
#create the iocache
-system.iocache = IOCache(clock = '1GHz')
+system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('8GB')])
system.iocache.cpu_side = system.iobus.master
system.iocache.mem_side = system.membus.slave
diff --git a/tests/configs/tsunami-simple-atomic-dual.py b/tests/configs/tsunami-simple-atomic-dual.py
index 851ec847b..1f63ff7a8 100644
--- a/tests/configs/tsunami-simple-atomic-dual.py
+++ b/tests/configs/tsunami-simple-atomic-dual.py
@@ -30,51 +30,13 @@ import m5
from m5.objects import *
m5.util.addToPath('../configs/common')
import FSConfig
-
-# --------------------
-# Base L1 Cache
-# ====================
-
-class L1(BaseCache):
- hit_latency = 2
- response_latency = 2
- block_size = 64
- mshrs = 4
- tgts_per_mshr = 8
- is_top_level = True
-
-# ----------------------
-# Base L2 Cache
-# ----------------------
-
-class L2(BaseCache):
- block_size = 64
- hit_latency = 20
- response_latency = 20
- mshrs = 92
- tgts_per_mshr = 16
- write_buffers = 8
-
-# ---------------------
-# I/O Cache
-# ---------------------
-class IOCache(BaseCache):
- assoc = 8
- block_size = 64
- hit_latency = 50
- response_latency = 50
- mshrs = 20
- size = '1kB'
- tgts_per_mshr = 12
- addr_ranges = [AddrRange(0, size='8GB')]
- forward_snoops = False
- is_top_level = True
+from Caches import *
#cpu
cpus = [ AtomicSimpleCPU(cpu_id=i) for i in xrange(2) ]
#the system
system = FSConfig.makeLinuxAlphaSystem('atomic')
-system.iocache = IOCache(clock = '1GHz')
+system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('8GB')])
system.iocache.cpu_side = system.iobus.master
system.iocache.mem_side = system.membus.slave
diff --git a/tests/configs/tsunami-simple-atomic.py b/tests/configs/tsunami-simple-atomic.py
index c583f9d2b..9c7e5c265 100644
--- a/tests/configs/tsunami-simple-atomic.py
+++ b/tests/configs/tsunami-simple-atomic.py
@@ -30,45 +30,7 @@ import m5
from m5.objects import *
m5.util.addToPath('../configs/common')
import FSConfig
-
-# --------------------
-# Base L1 Cache
-# ====================
-
-class L1(BaseCache):
- hit_latency = 2
- response_latency = 2
- block_size = 64
- mshrs = 4
- tgts_per_mshr = 8
- is_top_level = True
-
-# ----------------------
-# Base L2 Cache
-# ----------------------
-
-class L2(BaseCache):
- block_size = 64
- hit_latency = 20
- response_latency = 20
- mshrs = 92
- tgts_per_mshr = 16
- write_buffers = 8
-
-# ---------------------
-# I/O Cache
-# ---------------------
-class IOCache(BaseCache):
- assoc = 8
- block_size = 64
- hit_latency = 50
- response_latency = 50
- mshrs = 20
- size = '1kB'
- tgts_per_mshr = 12
- addr_ranges = [AddrRange(0, size='8GB')]
- forward_snoops = False
- is_top_level = True
+from Caches import *
#cpu
cpu = AtomicSimpleCPU(cpu_id=0)
@@ -78,7 +40,7 @@ system = FSConfig.makeLinuxAlphaSystem('atomic')
system.cpu = cpu
#create the iocache
-system.iocache = IOCache(clock = '1GHz')
+system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('8GB')])
system.iocache.cpu_side = system.iobus.master
system.iocache.mem_side = system.membus.slave
diff --git a/tests/configs/tsunami-simple-timing-dual.py b/tests/configs/tsunami-simple-timing-dual.py
index e69db3438..8bac5bd90 100644
--- a/tests/configs/tsunami-simple-timing-dual.py
+++ b/tests/configs/tsunami-simple-timing-dual.py
@@ -30,51 +30,13 @@ import m5
from m5.objects import *
m5.util.addToPath('../configs/common')
import FSConfig
-
-# --------------------
-# Base L1 Cache
-# ====================
-
-class L1(BaseCache):
- hit_latency = 2
- response_latency = 2
- block_size = 64
- mshrs = 4
- tgts_per_mshr = 8
- is_top_level = True
-
-# ----------------------
-# Base L2 Cache
-# ----------------------
-
-class L2(BaseCache):
- block_size = 64
- hit_latency = 20
- response_latency = 20
- mshrs = 92
- tgts_per_mshr = 16
- write_buffers = 8
-
-# ---------------------
-# I/O Cache
-# ---------------------
-class IOCache(BaseCache):
- assoc = 8
- block_size = 64
- hit_latency = 50
- response_latency = 50
- mshrs = 20
- size = '1kB'
- tgts_per_mshr = 12
- addr_ranges = [AddrRange(0, size='8GB')]
- forward_snoops = False
- is_top_level = True
+from Caches import *
#cpu
cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(2) ]
#the system
system = FSConfig.makeLinuxAlphaSystem('timing')
-system.iocache = IOCache(clock = '1GHz')
+system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('8GB')])
system.iocache.cpu_side = system.iobus.master
system.iocache.mem_side = system.membus.slave
diff --git a/tests/configs/tsunami-simple-timing.py b/tests/configs/tsunami-simple-timing.py
index e71d75846..60b4e47f4 100644
--- a/tests/configs/tsunami-simple-timing.py
+++ b/tests/configs/tsunami-simple-timing.py
@@ -30,46 +30,7 @@ import m5
from m5.objects import *
m5.util.addToPath('../configs/common')
import FSConfig
-
-
-# --------------------
-# Base L1 Cache
-# ====================
-
-class L1(BaseCache):
- hit_latency = 2
- response_latency = 2
- block_size = 64
- mshrs = 4
- tgts_per_mshr = 8
- is_top_level = True
-
-# ----------------------
-# Base L2 Cache
-# ----------------------
-
-class L2(BaseCache):
- block_size = 64
- hit_latency = 20
- response_latency = 20
- mshrs = 92
- tgts_per_mshr = 16
- write_buffers = 8
-
-# ---------------------
-# I/O Cache
-# ---------------------
-class IOCache(BaseCache):
- assoc = 8
- block_size = 64
- hit_latency = 50
- response_latency = 50
- mshrs = 20
- size = '1kB'
- tgts_per_mshr = 12
- addr_ranges = [AddrRange(0, size='8GB')]
- forward_snoops = False
- is_top_level = True
+from Caches import *
#cpu
cpu = TimingSimpleCPU(cpu_id=0)
@@ -79,7 +40,7 @@ system = FSConfig.makeLinuxAlphaSystem('timing')
system.cpu = cpu
#create the iocache
-system.iocache = IOCache(clock = '1GHz')
+system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('8GB')])
system.iocache.cpu_side = system.iobus.master
system.iocache.mem_side = system.membus.slave
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-08 21:55:41 +0000