diff options
| -rw-r--r-- | src/arch/x86/isa/decoder/two_byte_opcodes.isa | 2 | ||||
| -rw-r--r-- | src/arch/x86/isa/insts/system/msrs.py | 11 |
2 files changed, 12 insertions, 1 deletions
diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa b/src/arch/x86/isa/decoder/two_byte_opcodes.isa index aa60e4c48..761e8381e 100644 --- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa +++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa @@ -133,7 +133,7 @@ 0x7: decode MODRM_MOD { 0x3: decode MODRM_RM { 0x0: Inst::SWAPGS(); - 0x1: rdtscp(); + 0x1: Inst::RDTSCP(); default: Inst::UD2(); } default: Inst::INVLPG(M); diff --git a/src/arch/x86/isa/insts/system/msrs.py b/src/arch/x86/isa/insts/system/msrs.py index fe9c5b262..b79b6dbe9 100644 --- a/src/arch/x86/isa/insts/system/msrs.py +++ b/src/arch/x86/isa/insts/system/msrs.py @@ -66,4 +66,15 @@ def macroop RDTSC srli t1, t1, 32, dataSize=8 mov rdx, rdx, t1, dataSize=4 }; + +def macroop RDTSCP +{ + .serialize_before + mfence + rdtsc t1 + mov rax, rax, t1, dataSize=4 + srli t1, t1, 32, dataSize=8 + mov rdx, rdx, t1, dataSize=4 + rdval rcx, "InstRegIndex(MISCREG_TSC_AUX)", dataSize=4 +}; ''' |