diff options
| -rw-r--r-- | tests/configs/alpha_generic.py | 93 | ||||
| -rw-r--r-- | tests/configs/arm_generic.py | 95 | ||||
| -rw-r--r-- | tests/configs/base_config.py | 175 | ||||
| -rw-r--r-- | tests/configs/pc-o3-timing.py | 53 | ||||
| -rw-r--r-- | tests/configs/pc-simple-atomic.py | 53 | ||||
| -rw-r--r-- | tests/configs/pc-simple-timing.py | 52 | ||||
| -rw-r--r-- | tests/configs/realview-o3-checker.py | 42 | ||||
| -rw-r--r-- | tests/configs/realview-o3-dual.py | 52 | ||||
| -rw-r--r-- | tests/configs/realview-o3.py | 46 | ||||
| -rw-r--r-- | tests/configs/realview-simple-atomic-dual.py | 52 | ||||
| -rw-r--r-- | tests/configs/realview-simple-atomic.py | 45 | ||||
| -rw-r--r-- | tests/configs/realview-simple-timing-dual.py | 52 | ||||
| -rw-r--r-- | tests/configs/realview-simple-timing.py | 46 | ||||
| -rw-r--r-- | tests/configs/tsunami-inorder.py | 49 | ||||
| -rw-r--r-- | tests/configs/tsunami-o3-dual.py | 51 | ||||
| -rw-r--r-- | tests/configs/tsunami-o3.py | 46 | ||||
| -rw-r--r-- | tests/configs/tsunami-simple-atomic-dual.py | 49 | ||||
| -rw-r--r-- | tests/configs/tsunami-simple-atomic.py | 46 | ||||
| -rw-r--r-- | tests/configs/tsunami-simple-timing-dual.py | 51 | ||||
| -rw-r--r-- | tests/configs/tsunami-simple-timing.py | 46 | ||||
| -rw-r--r-- | tests/configs/x86_generic.py | 108 |
21 files changed, 702 insertions, 600 deletions
diff --git a/tests/configs/alpha_generic.py b/tests/configs/alpha_generic.py new file mode 100644 index 000000000..429f4faba --- /dev/null +++ b/tests/configs/alpha_generic.py @@ -0,0 +1,93 @@ +# Copyright (c) 2012 ARM Limited +# All rights reserved. +# +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Andreas Sandberg + +from abc import ABCMeta, abstractmethod +import m5 +from m5.objects import * +from m5.proxy import * +m5.util.addToPath('../configs/common') +import FSConfig +from Caches import * +from base_config import * + +class LinuxAlphaSystemBuilder(object): + """Mix-in that implements create_system. + + This mix-in is intended as a convenient way of adding an + Alpha-specific create_system method to a class deriving from one of + the generic base systems. + """ + def __init__(self): + """ + Arguments: + machine_type -- String describing the platform to simulate + """ + pass + + def create_system(self): + system = FSConfig.makeLinuxAlphaSystem(self.mem_mode) + self.init_system(system) + return system + +class LinuxAlphaFSSystem(LinuxAlphaSystemBuilder, + BaseFSSystem): + """Basic Alpha full system builder.""" + + def __init__(self, **kwargs): + """Initialize an Alpha system that supports full system simulation. + + Note: Keyword arguments that are not listed below will be + passed to the BaseFSSystem. + + Keyword Arguments: + - + """ + BaseSystem.__init__(self, **kwargs) + LinuxAlphaSystemBuilder.__init__(self) + +class LinuxAlphaFSSystemUniprocessor(LinuxAlphaSystemBuilder, + BaseFSSystemUniprocessor): + """Basic Alpha full system builder for uniprocessor systems. + + Note: This class is a specialization of the AlphaFSSystem and is + only really needed to provide backwards compatibility for existing + test cases. + """ + + def __init__(self, **kwargs): + BaseFSSystemUniprocessor.__init__(self, **kwargs) + LinuxAlphaSystemBuilder.__init__(self) diff --git a/tests/configs/arm_generic.py b/tests/configs/arm_generic.py new file mode 100644 index 000000000..07251f2d6 --- /dev/null +++ b/tests/configs/arm_generic.py @@ -0,0 +1,95 @@ +# Copyright (c) 2012 ARM Limited +# All rights reserved. +# +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Andreas Sandberg + +from abc import ABCMeta, abstractmethod +import m5 +from m5.objects import * +from m5.proxy import * +m5.util.addToPath('../configs/common') +import FSConfig +from Caches import * +from base_config import * + +class LinuxArmSystemBuilder(object): + """Mix-in that implements create_system. + + This mix-in is intended as a convenient way of adding an + ARM-specific create_system method to a class deriving from one of + the generic base systems. + """ + def __init__(self, machine_type): + """ + Arguments: + machine_type -- String describing the platform to simulate + """ + self.machine_type = machine_type + + def create_system(self): + system = FSConfig.makeArmSystem(self.mem_mode, + self.machine_type, + None, False) + self.init_system(system) + return system + +class LinuxArmFSSystem(LinuxArmSystemBuilder, + BaseFSSystem): + """Basic ARM full system builder.""" + + def __init__(self, machine_type='RealView_PBX', **kwargs): + """Initialize an ARM system that supports full system simulation. + + Note: Keyword arguments that are not listed below will be + passed to the BaseFSSystem. + + Keyword Arguments: + machine_type -- String describing the platform to simulate + """ + BaseSystem.__init__(self, **kwargs) + LinuxArmSystemBuilder.__init__(self, machine_type) + +class LinuxArmFSSystemUniprocessor(LinuxArmSystemBuilder, + BaseFSSystemUniprocessor): + """Basic ARM full system builder for uniprocessor systems. + + Note: This class is a specialization of the ArmFSSystem and is + only really needed to provide backwards compatibility for existing + test cases. + """ + + def __init__(self, machine_type='RealView_PBX', **kwargs): + BaseFSSystemUniprocessor.__init__(self, **kwargs) + LinuxArmSystemBuilder.__init__(self, machine_type) diff --git a/tests/configs/base_config.py b/tests/configs/base_config.py new file mode 100644 index 000000000..3efbe46fb --- /dev/null +++ b/tests/configs/base_config.py @@ -0,0 +1,175 @@ +# Copyright (c) 2012 ARM Limited +# All rights reserved. +# +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Andreas Sandberg + +from abc import ABCMeta, abstractmethod +import m5 +from m5.objects import * +from m5.proxy import * +m5.util.addToPath('../configs/common') +import FSConfig +from Caches import * + +class BaseSystem(object): + """Base system builder. + + This class provides some basic functionality for creating an ARM + system with the usual peripherals (caches, GIC, etc.). It allows + customization by defining separate methods for different parts of + the initialization process. + """ + + __metaclass__ = ABCMeta + + def __init__(self, mem_mode='timing', cpu_class=TimingSimpleCPU, + num_cpus=1, checker=False): + """Initialize a simple ARM system. + + Keyword Arguments: + mem_mode -- String describing the memory mode (timing or atomic) + cpu_class -- CPU class to use + num_cpus -- Number of CPUs to instantiate + checker -- Set to True to add checker CPUs + """ + self.mem_mode = mem_mode + self.cpu_class = cpu_class + self.num_cpus = num_cpus + self.checker = checker + + def create_cpus(self): + """Return a list of CPU objects to add to a system.""" + cpus = [ self.cpu_class(cpu_id=i, clock='2GHz') + for i in range(self.num_cpus) ] + if self.checker: + for c in cpus: + c.addCheckerCpu() + return cpus + + def create_caches_private(self, cpu): + """Add private caches to a CPU. + + Arguments: + cpu -- CPU instance to work on. + """ + cpu.addPrivateSplitL1Caches(L1Cache(size='32kB', assoc=1), + L1Cache(size='32kB', assoc=4)) + + def create_caches_shared(self, system): + """Add shared caches to a system. + + Arguments: + system -- System to work on. + + Returns: + A bus that CPUs should use to connect to the shared cache. + """ + system.toL2Bus = CoherentBus(clock='2GHz') + system.l2c = L2Cache(clock='2GHz', size='4MB', assoc=8) + system.l2c.cpu_side = system.toL2Bus.master + system.l2c.mem_side = system.membus.slave + return system.toL2Bus + + def init_cpu(self, system, cpu): + """Initialize a CPU. + + Arguments: + system -- System to work on. + cpu -- CPU to initialize. + """ + cpu.createInterruptController() + + def init_system(self, system): + """Initialize a system. + + Arguments: + system -- System to initialize. + """ + system.cpu = self.create_cpus() + + sha_bus = self.create_caches_shared(system) + for cpu in system.cpu: + self.create_caches_private(cpu) + self.init_cpu(system, cpu) + cpu.connectAllPorts(sha_bus if sha_bus != None else system.membus, + system.membus) + + @abstractmethod + def create_system(self): + """Create an return an initialized system.""" + pass + + @abstractmethod + def create_root(self): + """Create and return a simulation root using the system + defined by this class.""" + pass + +class BaseFSSystem(BaseSystem): + """Basic full system builder.""" + + def __init__(self, **kwargs): + BaseSystem.__init__(self, **kwargs) + + def init_system(self, system): + BaseSystem.init_system(self, system) + + #create the iocache + system.iocache = IOCache(clock='1GHz', addr_ranges=[system.physmem.range]) + system.iocache.cpu_side = system.iobus.master + system.iocache.mem_side = system.membus.slave + + def create_root(self): + system = self.create_system() + m5.ticks.setGlobalFrequency('1THz') + return Root(full_system=True, system=system) + +class BaseFSSystemUniprocessor(BaseFSSystem): + """Basic full system builder for uniprocessor systems. + + Note: This class is only really needed to provide backwards + compatibility in existing test cases. + """ + + def __init__(self, **kwargs): + BaseFSSystem.__init__(self, **kwargs) + + def create_caches_private(self, cpu): + cpu.addTwoLevelCacheHierarchy(L1Cache(size='32kB', assoc=1), + L1Cache(size='32kB', assoc=4), + L2Cache(size='4MB', assoc=8)) + + def create_caches_shared(self, system): + return None diff --git a/tests/configs/pc-o3-timing.py b/tests/configs/pc-o3-timing.py index 6bab4c448..6020478a0 100644 --- a/tests/configs/pc-o3-timing.py +++ b/tests/configs/pc-o3-timing.py @@ -1,6 +1,15 @@ -# Copyright (c) 2006-2007 The Regents of The University of Michigan +# Copyright (c) 2012 ARM Limited # All rights reserved. # +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are # met: redistributions of source code must retain the above copyright @@ -24,44 +33,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # -# Authors: Steve Reinhardt +# Authors: Andreas Sandberg -import m5 from m5.objects import * -m5.util.addToPath('../configs/common') -from Benchmarks import SysConfig -import FSConfig -from Caches import * - -mem_size = '128MB' - -#cpu -cpu = DerivO3CPU(cpu_id=0) -#the system -mdesc = SysConfig(disk = 'linux-x86.img') -system = FSConfig.makeLinuxX86System('timing', mdesc=mdesc) -system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9') - -system.cpu = cpu - -#create the iocache -system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange(mem_size)]) -system.iocache.cpu_side = system.iobus.master -system.iocache.mem_side = system.membus.slave - -#connect up the cpu and caches -cpu.addTwoLevelCacheHierarchy(L1Cache(size = '32kB', assoc = 1), - L1Cache(size = '32kB', assoc = 4), - L2Cache(size = '4MB', assoc = 8), - PageTableWalkerCache(), - PageTableWalkerCache()) -# create the interrupt controller -cpu.createInterruptController() -# connect cpu and caches to the rest of the system -cpu.connectAllPorts(system.membus) -# set the cpu clock along with the caches and l1-l2 bus -cpu.clock = '2GHz' - -root = Root(full_system=True, system=system) -m5.ticks.setGlobalFrequency('1THz') +from x86_generic import * +root = LinuxX86FSSystemUniprocessor(mem_mode='timing', + cpu_class=DerivO3CPU).create_root() diff --git a/tests/configs/pc-simple-atomic.py b/tests/configs/pc-simple-atomic.py index 74d47fe41..ce6aa0616 100644 --- a/tests/configs/pc-simple-atomic.py +++ b/tests/configs/pc-simple-atomic.py @@ -1,6 +1,15 @@ -# Copyright (c) 2006-2007 The Regents of The University of Michigan +# Copyright (c) 2012 ARM Limited # All rights reserved. # +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are # met: redistributions of source code must retain the above copyright @@ -24,44 +33,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # -# Authors: Steve Reinhardt +# Authors: Andreas Sandberg -import m5 from m5.objects import * -m5.util.addToPath('../configs/common') -from Benchmarks import SysConfig -import FSConfig -from Caches import * - -mem_size = '128MB' - -#cpu -cpu = AtomicSimpleCPU(cpu_id=0) -#the system -mdesc = SysConfig(disk = 'linux-x86.img') -system = FSConfig.makeLinuxX86System('atomic', mdesc=mdesc) -system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9') - -system.cpu = cpu - -#create the iocache -system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange(mem_size)]) -system.iocache.cpu_side = system.iobus.master -system.iocache.mem_side = system.membus.slave - -#connect up the cpu and caches -cpu.addTwoLevelCacheHierarchy(L1Cache(size = '32kB', assoc = 1), - L1Cache(size = '32kB', assoc = 4), - L2Cache(size = '4MB', assoc = 8), - PageTableWalkerCache(), - PageTableWalkerCache()) -# create the interrupt controller -cpu.createInterruptController() -# connect cpu and caches to the rest of the system -cpu.connectAllPorts(system.membus) -# set the cpu clock along with the caches and l1-l2 bus -cpu.clock = '2GHz' - -root = Root(full_system=True, system=system) -m5.ticks.setGlobalFrequency('1THz') +from x86_generic import * +root = LinuxX86FSSystemUniprocessor(mem_mode='atomic', + cpu_class=AtomicSimpleCPU).create_root() diff --git a/tests/configs/pc-simple-timing.py b/tests/configs/pc-simple-timing.py index 1b7e809f7..e8d73a249 100644 --- a/tests/configs/pc-simple-timing.py +++ b/tests/configs/pc-simple-timing.py @@ -1,6 +1,15 @@ -# Copyright (c) 2006-2007 The Regents of The University of Michigan +# Copyright (c) 2012 ARM Limited # All rights reserved. # +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are # met: redistributions of source code must retain the above copyright @@ -24,44 +33,11 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # -# Authors: Steve Reinhardt +# Authors: Andreas Sandberg -import m5 from m5.objects import * -m5.util.addToPath('../configs/common') -from Benchmarks import SysConfig -import FSConfig -from Caches import * - -mem_size = '128MB' - -#cpu -cpu = TimingSimpleCPU(cpu_id=0) -#the system -mdesc = SysConfig(disk = 'linux-x86.img') -system = FSConfig.makeLinuxX86System('timing', mdesc = mdesc) -system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9') - -system.cpu = cpu - -#create the iocache -system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange(mem_size)]) -system.iocache.cpu_side = system.iobus.master -system.iocache.mem_side = system.membus.slave - -#connect up the cpu and caches -cpu.addTwoLevelCacheHierarchy(L1Cache(size = '32kB', assoc = 1), - L1Cache(size = '32kB', assoc = 4), - L2Cache(size = '4MB', assoc = 8), - PageTableWalkerCache(), - PageTableWalkerCache()) -# create the interrupt controller -cpu.createInterruptController() -# connect cpu and caches to the rest of the system -cpu.connectAllPorts(system.membus) -# set the cpu clock along with the caches and l1-l2 bus -cpu.clock = '2GHz' +from x86_generic import * -root = Root(full_system=True, system=system) -m5.ticks.setGlobalFrequency('1THz') +root = LinuxX86FSSystemUniprocessor(mem_mode='timing', + cpu_class=TimingSimpleCPU).create_root() diff --git a/tests/configs/realview-o3-checker.py b/tests/configs/realview-o3-checker.py index 8c5d4086d..3f252bf2c 100644 --- a/tests/configs/realview-o3-checker.py +++ b/tests/configs/realview-o3-checker.py @@ -1,5 +1,5 @@ -# Copyright (c) 2011 ARM Limited -# All rights reserved +# Copyright (c) 2012 ARM Limited +# All rights reserved. # # The license below extends only to copyright in the software and shall # not be construed as granting a license to any other intellectual @@ -33,39 +33,11 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # -# Authors: Geoffrey Blake +# Authors: Andreas Sandberg -import m5 from m5.objects import * -m5.util.addToPath('../configs/common') -import FSConfig -from Caches import * - -#cpu -cpu = DerivO3CPU(cpu_id=0) -#the system -system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False) - -system.cpu = cpu -#connect up the checker -cpu.addCheckerCpu() - -#create the iocache -system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('256MB')]) -system.iocache.cpu_side = system.iobus.master -system.iocache.mem_side = system.membus.slave - -#connect up the cpu and caches -cpu.addTwoLevelCacheHierarchy(L1Cache(size = '32kB', assoc = 1), - L1Cache(size = '32kB', assoc = 4), - L2Cache(size = '4MB', assoc = 8)) -# create the interrupt controller -cpu.createInterruptController() -# connect cpu and caches to the rest of the system -cpu.connectAllPorts(system.membus) -# set the cpu clock along with the caches and l1-l2 bus -cpu.clock = '2GHz' - -root = Root(full_system=True, system=system) -m5.ticks.setGlobalFrequency('1THz') +from arm_generic import * +root = LinuxArmFSSystemUniprocessor(mem_mode='timing', + cpu_class=DerivO3CPU, + checker=True).create_root() diff --git a/tests/configs/realview-o3-dual.py b/tests/configs/realview-o3-dual.py index b5c235a67..56e6aee73 100644 --- a/tests/configs/realview-o3-dual.py +++ b/tests/configs/realview-o3-dual.py @@ -1,6 +1,15 @@ -# Copyright (c) 2006-2007 The Regents of The University of Michigan +# Copyright (c) 2012 ARM Limited # All rights reserved. # +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are # met: redistributions of source code must retain the above copyright @@ -24,43 +33,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # -# Authors: Steve Reinhardt +# Authors: Andreas Sandberg -import m5 from m5.objects import * -m5.util.addToPath('../configs/common') -import FSConfig -from Benchmarks import * -from Caches import * - -#cpu -cpus = [DerivO3CPU(cpu_id=i) for i in xrange(2) ] -#the system -system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False) -system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('256MB')]) -system.iocache.cpu_side = system.iobus.master -system.iocache.mem_side = system.membus.slave - -system.cpu = cpus -#create the l1/l2 bus -system.toL2Bus = CoherentBus(clock = '2GHz') - -#connect up the l2 cache -system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8) -system.l2c.cpu_side = system.toL2Bus.master -system.l2c.mem_side = system.membus.slave - -#connect up the cpu and l1s -for c in cpus: - c.addPrivateSplitL1Caches(L1Cache(size = '32kB', assoc = 1), - L1Cache(size = '32kB', assoc = 4)) - # create the interrupt controller - c.createInterruptController() - # connect cpu level-1 caches to shared level-2 cache - c.connectAllPorts(system.toL2Bus, system.membus) - c.clock = '2GHz' - - -root = Root(full_system=True, system=system) -m5.ticks.setGlobalFrequency('1THz') +from arm_generic import * +root = LinuxArmFSSystem(mem_mode='timing', cpu_class=DerivO3CPU, + num_cpus=2).create_root() diff --git a/tests/configs/realview-o3.py b/tests/configs/realview-o3.py index 6dbc0c828..99f8ea3dc 100644 --- a/tests/configs/realview-o3.py +++ b/tests/configs/realview-o3.py @@ -1,6 +1,15 @@ -# Copyright (c) 2006-2007 The Regents of The University of Michigan +# Copyright (c) 2012 ARM Limited # All rights reserved. # +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are # met: redistributions of source code must retain the above copyright @@ -24,37 +33,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # -# Authors: Steve Reinhardt +# Authors: Andreas Sandberg -import m5 from m5.objects import * -m5.util.addToPath('../configs/common') -import FSConfig -from Caches import * - -#cpu -cpu = DerivO3CPU(cpu_id=0) -#the system -system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False) - -system.cpu = cpu - -#create the iocache -system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('256MB')]) -system.iocache.cpu_side = system.iobus.master -system.iocache.mem_side = system.membus.slave - -#connect up the cpu and caches -cpu.addTwoLevelCacheHierarchy(L1Cache(size = '32kB', assoc = 1), - L1Cache(size = '32kB', assoc = 4), - L2Cache(size = '4MB', assoc = 8)) -# create the interrupt controller -cpu.createInterruptController() -# connect cpu and caches to the rest of the system -cpu.connectAllPorts(system.membus) -# set the cpu clock along with the caches and l1-l2 bus -cpu.clock = '2GHz' - -root = Root(full_system=True, system=system) -m5.ticks.setGlobalFrequency('1THz') +from arm_generic import * +root = LinuxArmFSSystemUniprocessor(mem_mode='timing', + cpu_class=DerivO3CPU).create_root() diff --git a/tests/configs/realview-simple-atomic-dual.py b/tests/configs/realview-simple-atomic-dual.py index 90a9d5537..64ddf0595 100644 --- a/tests/configs/realview-simple-atomic-dual.py +++ b/tests/configs/realview-simple-atomic-dual.py @@ -1,6 +1,15 @@ -# Copyright (c) 2006-2007 The Regents of The University of Michigan +# Copyright (c) 2012 ARM Limited # All rights reserved. # +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are # met: redistributions of source code must retain the above copyright @@ -24,43 +33,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # -# Authors: Steve Reinhardt +# Authors: Andreas Sandberg -import m5 from m5.objects import * -m5.util.addToPath('../configs/common') -import FSConfig -from Benchmarks import * -from Caches import * - -#cpu -cpus = [AtomicSimpleCPU(cpu_id=i) for i in xrange(2) ] -#the system -system = FSConfig.makeArmSystem('atomic', "RealView_PBX", None, False) -system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('256MB')]) -system.iocache.cpu_side = system.iobus.master -system.iocache.mem_side = system.membus.slave - -system.cpu = cpus -#create the l1/l2 bus -system.toL2Bus = CoherentBus(clock = '2GHz') - -#connect up the l2 cache -system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8) -system.l2c.cpu_side = system.toL2Bus.master -system.l2c.mem_side = system.membus.slave - -#connect up the cpu and l1s -for c in cpus: - c.addPrivateSplitL1Caches(L1Cache(size = '32kB', assoc = 1), - L1Cache(size = '32kB', assoc = 4)) - # create the interrupt controller - c.createInterruptController() - # connect cpu level-1 caches to shared level-2 cache - c.connectAllPorts(system.toL2Bus, system.membus) - c.clock = '2GHz' - - -root = Root(full_system=True, system=system) -m5.ticks.setGlobalFrequency('1THz') +from arm_generic import * +root = LinuxArmFSSystem(mem_mode='atomic', cpu_class=AtomicSimpleCPU, + num_cpus=2).create_root() diff --git a/tests/configs/realview-simple-atomic.py b/tests/configs/realview-simple-atomic.py index 5cad3a2cb..866a13395 100644 --- a/tests/configs/realview-simple-atomic.py +++ b/tests/configs/realview-simple-atomic.py @@ -1,6 +1,15 @@ -# Copyright (c) 2006-2007 The Regents of The University of Michigan +# Copyright (c) 2012 ARM Limited # All rights reserved. # +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are # met: redistributions of source code must retain the above copyright @@ -24,37 +33,11 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # -# Authors: Steve Reinhardt +# Authors: Andreas Sandberg -import m5 from m5.objects import * -m5.util.addToPath('../configs/common') -import FSConfig -from Caches import * - -#cpu -cpu = AtomicSimpleCPU(cpu_id=0) -#the system -system = FSConfig.makeArmSystem('atomic', "RealView_PBX", None, False) - -system.cpu = cpu - -#create the iocache -system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('256MB')]) -system.iocache.cpu_side = system.iobus.master -system.iocache.mem_side = system.membus.slave - -#connect up the cpu and caches -cpu.addTwoLevelCacheHierarchy(L1Cache(size = '32kB', assoc = 1), - L1Cache(size = '32kB', assoc = 4), - L2Cache(size = '4MB', assoc = 8)) -# create the interrupt controller -cpu.createInterruptController() -# connect cpu and caches to the rest of the system -cpu.connectAllPorts(system.membus) -# set the cpu clock along with the caches and l1-l2 bus -cpu.clock = '2GHz' +from arm_generic import * -root = Root(full_system=True, system=system) -m5.ticks.setGlobalFrequency('1THz') +root = LinuxArmFSSystemUniprocessor(mem_mode='atomic', + cpu_class=AtomicSimpleCPU).create_root() diff --git a/tests/configs/realview-simple-timing-dual.py b/tests/configs/realview-simple-timing-dual.py index 5b8e6e0e3..86efd4c1a 100644 --- a/tests/configs/realview-simple-timing-dual.py +++ b/tests/configs/realview-simple-timing-dual.py @@ -1,6 +1,15 @@ -# Copyright (c) 2006-2007 The Regents of The University of Michigan +# Copyright (c) 2012 ARM Limited # All rights reserved. # +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are # met: redistributions of source code must retain the above copyright @@ -24,43 +33,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # -# Authors: Steve Reinhardt +# Authors: Andreas Sandberg -import m5 from m5.objects import * -m5.util.addToPath('../configs/common') -import FSConfig -from Benchmarks import * -from Caches import * - -#cpu -cpus = [TimingSimpleCPU(cpu_id=i) for i in xrange(2) ] -#the system -system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False) -system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('256MB')]) -system.iocache.cpu_side = system.iobus.master -system.iocache.mem_side = system.membus.slave - -system.cpu = cpus -#create the l1/l2 bus -system.toL2Bus = CoherentBus(clock = '2GHz') - -#connect up the l2 cache -system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8) -system.l2c.cpu_side = system.toL2Bus.master -system.l2c.mem_side = system.membus.slave - -#connect up the cpu and l1s -for c in cpus: - c.addPrivateSplitL1Caches(L1Cache(size = '32kB', assoc = 1), - L1Cache(size = '32kB', assoc = 4)) - # create the interrupt controller - c.createInterruptController() - # connect cpu level-1 caches to shared level-2 cache - c.connectAllPorts(system.toL2Bus, system.membus) - c.clock = '2GHz' - - -root = Root(full_system=True, system=system) -m5.ticks.setGlobalFrequency('1THz') +from arm_generic import * +root = LinuxArmFSSystem(mem_mode='timing', cpu_class=TimingSimpleCPU, + num_cpus=2).create_root() diff --git a/tests/configs/realview-simple-timing.py b/tests/configs/realview-simple-timing.py index c2dc27b48..9ff8b33e0 100644 --- a/tests/configs/realview-simple-timing.py +++ b/tests/configs/realview-simple-timing.py @@ -1,6 +1,15 @@ -# Copyright (c) 2006-2007 The Regents of The University of Michigan +# Copyright (c) 2012 ARM Limited # All rights reserved. # +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are # met: redistributions of source code must retain the above copyright @@ -24,37 +33,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # -# Authors: Steve Reinhardt +# Authors: Andreas Sandberg -import m5 from m5.objects import * -m5.util.addToPath('../configs/common') -import FSConfig -from Caches import * - -#cpu -cpu = TimingSimpleCPU(cpu_id=0) -#the system -system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False) - -system.cpu = cpu - -#create the iocache -system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('256MB')]) -system.iocache.cpu_side = system.iobus.master -system.iocache.mem_side = system.membus.slave - -#connect up the cpu and caches -cpu.addTwoLevelCacheHierarchy(L1Cache(size = '32kB', assoc = 1), - L1Cache(size = '32kB', assoc = 4), - L2Cache(size = '4MB', assoc = 8)) -# create the interrupt controller -cpu.createInterruptController() -# connect cpu and caches to the rest of the system -cpu.connectAllPorts(system.membus) -# set the cpu clock along with the caches and l1-l2 bus -cpu.clock = '2GHz' - -root = Root(full_system=True, system=system) -m5.ticks.setGlobalFrequency('1THz') +from arm_generic import * +root = LinuxArmFSSystemUniprocessor(mem_mode='timing', + cpu_class=TimingSimpleCPU).create_root() diff --git a/tests/configs/tsunami-inorder.py b/tests/configs/tsunami-inorder.py index b0aa1c7cd..102c5a8d2 100644 --- a/tests/configs/tsunami-inorder.py +++ b/tests/configs/tsunami-inorder.py @@ -1,6 +1,15 @@ -# Copyright (c) 2006-2007 The Regents of The University of Michigan +# Copyright (c) 2012 ARM Limited # All rights reserved. # +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are # met: redistributions of source code must retain the above copyright @@ -24,40 +33,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # -# Authors: Steve Reinhardt +# Authors: Andreas Sandberg -import m5 from m5.objects import * -m5.util.addToPath('../configs/common') -import FSConfig -from Caches import * - -#cpu -cpu = InOrderCPU(cpu_id=0) -cpu.stageWidth = 4 -cpu.fetchBuffSize = 1 - -#the system -system = FSConfig.makeLinuxAlphaSystem('timing') - -system.cpu = cpu - -#create the iocache -system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('8GB')]) -system.iocache.cpu_side = system.iobus.master -system.iocache.mem_side = system.membus.slave - -#connect up the cpu and caches -cpu.addTwoLevelCacheHierarchy(L1Cache(size = '32kB', assoc = 1), - L1Cache(size = '32kB', assoc = 4), - L2Cache(size = '4MB', assoc = 8)) -# create the interrupt controller -cpu.createInterruptController() -# connect cpu and caches to the rest of the system -cpu.connectAllPorts(system.membus) -# set the cpu clock along with the caches and l1-l2 bus -cpu.clock = '2GHz' - -root = Root(full_system=True, system=system) -m5.ticks.setGlobalFrequency('1THz') +from alpha_generic import * +root = LinuxAlphaFSSystemUniprocessor(mem_mode='timing', + cpu_class=InOrderCPU).create_root() diff --git a/tests/configs/tsunami-o3-dual.py b/tests/configs/tsunami-o3-dual.py index 9aac5e744..d7964b4d8 100644 --- a/tests/configs/tsunami-o3-dual.py +++ b/tests/configs/tsunami-o3-dual.py @@ -1,6 +1,15 @@ -# Copyright (c) 2006-2007 The Regents of The University of Michigan +# Copyright (c) 2012 ARM Limited # All rights reserved. # +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are # met: redistributions of source code must retain the above copyright @@ -24,42 +33,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # -# Authors: Steve Reinhardt +# Authors: Andreas Sandberg -import m5 from m5.objects import * -m5.util.addToPath('../configs/common') -import FSConfig -from Caches import * - -#cpu -cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(2) ] -#the system -system = FSConfig.makeLinuxAlphaSystem('timing') - -system.cpu = cpus -#create the l1/l2 bus -system.toL2Bus = CoherentBus(clock = '2GHz') -system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('8GB')]) -system.iocache.cpu_side = system.iobus.master -system.iocache.mem_side = system.membus.slave - - -#connect up the l2 cache -system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8) -system.l2c.cpu_side = system.toL2Bus.master -system.l2c.mem_side = system.membus.slave - -#connect up the cpu and l1s -for c in cpus: - c.addPrivateSplitL1Caches(L1Cache(size = '32kB', assoc = 1), - L1Cache(size = '32kB', assoc = 4)) - # create the interrupt controller - c.createInterruptController() - # connect cpu level-1 caches to shared level-2 cache - c.connectAllPorts(system.toL2Bus, system.membus) - c.clock = '2GHz' - -root = Root(full_system=True, system=system) -m5.ticks.setGlobalFrequency('1THz') +from alpha_generic import * +root = LinuxAlphaFSSystem(mem_mode='timing', cpu_class=DerivO3CPU, + num_cpus=2).create_root() diff --git a/tests/configs/tsunami-o3.py b/tests/configs/tsunami-o3.py index d50b59257..2c782e2cc 100644 --- a/tests/configs/tsunami-o3.py +++ b/tests/configs/tsunami-o3.py @@ -1,6 +1,15 @@ -# Copyright (c) 2006-2007 The Regents of The University of Michigan +# Copyright (c) 2012 ARM Limited # All rights reserved. # +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are # met: redistributions of source code must retain the above copyright @@ -24,37 +33,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # -# Authors: Steve Reinhardt +# Authors: Andreas Sandberg -import m5 from m5.objects import * -m5.util.addToPath('../configs/common') -import FSConfig -from Caches import * - -#cpu -cpu = DerivO3CPU(cpu_id=0) -#the system -system = FSConfig.makeLinuxAlphaSystem('timing') - -system.cpu = cpu - -#create the iocache -system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('8GB')]) -system.iocache.cpu_side = system.iobus.master -system.iocache.mem_side = system.membus.slave - -#connect up the cpu and caches -cpu.addTwoLevelCacheHierarchy(L1Cache(size = '32kB', assoc = 1), - L1Cache(size = '32kB', assoc = 4), - L2Cache(size = '4MB', assoc = 8)) -# create the interrupt controller -cpu.createInterruptController() -# connect cpu and caches to the rest of the system -cpu.connectAllPorts(system.membus) -# set the cpu clock along with the caches and l1-l2 bus -cpu.clock = '2GHz' - -root = Root(full_system=True, system=system) -m5.ticks.setGlobalFrequency('1THz') +from alpha_generic import * +root = LinuxAlphaFSSystemUniprocessor(mem_mode='timing', + cpu_class=DerivO3CPU).create_root() diff --git a/tests/configs/tsunami-simple-atomic-dual.py b/tests/configs/tsunami-simple-atomic-dual.py index b91d56cec..36dc8133b 100644 --- a/tests/configs/tsunami-simple-atomic-dual.py +++ b/tests/configs/tsunami-simple-atomic-dual.py @@ -1,6 +1,15 @@ -# Copyright (c) 2006-2007 The Regents of The University of Michigan +# Copyright (c) 2012 ARM Limited # All rights reserved. # +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are # met: redistributions of source code must retain the above copyright @@ -24,40 +33,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # -# Authors: Steve Reinhardt +# Authors: Andreas Sandberg -import m5 from m5.objects import * -m5.util.addToPath('../configs/common') -import FSConfig -from Caches import * - -#cpu -cpus = [ AtomicSimpleCPU(cpu_id=i) for i in xrange(2) ] -#the system -system = FSConfig.makeLinuxAlphaSystem('atomic') -system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('8GB')]) -system.iocache.cpu_side = system.iobus.master -system.iocache.mem_side = system.membus.slave - -system.cpu = cpus -#create the l1/l2 bus -system.toL2Bus = CoherentBus(clock = '2GHz') - -#connect up the l2 cache -system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8) -system.l2c.cpu_side = system.toL2Bus.master -system.l2c.mem_side = system.membus.slave - -#connect up the cpu and l1s -for c in cpus: - c.addPrivateSplitL1Caches(L1Cache(size = '32kB', assoc = 1), - L1Cache(size = '32kB', assoc = 4)) - # create the interrupt controller - c.createInterruptController() - # connect cpu level-1 caches to shared level-2 cache - c.connectAllPorts(system.toL2Bus, system.membus) - c.clock = '2GHz' +from alpha_generic import * -root = Root(full_system=True, system=system) -m5.ticks.setGlobalFrequency('1THz') +root = LinuxAlphaFSSystem(mem_mode='atomic', cpu_class=AtomicSimpleCPU, + num_cpus=2).create_root() diff --git a/tests/configs/tsunami-simple-atomic.py b/tests/configs/tsunami-simple-atomic.py index bbab929cd..be8e93a18 100644 --- a/tests/configs/tsunami-simple-atomic.py +++ b/tests/configs/tsunami-simple-atomic.py @@ -1,6 +1,15 @@ -# Copyright (c) 2006-2007 The Regents of The University of Michigan +# Copyright (c) 2012 ARM Limited # All rights reserved. # +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are # met: redistributions of source code must retain the above copyright @@ -24,37 +33,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # -# Authors: Steve Reinhardt +# Authors: Andreas Sandberg -import m5 from m5.objects import * -m5.util.addToPath('../configs/common') -import FSConfig -from Caches import * - -#cpu -cpu = AtomicSimpleCPU(cpu_id=0) -#the system -system = FSConfig.makeLinuxAlphaSystem('atomic') - -system.cpu = cpu - -#create the iocache -system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('8GB')]) -system.iocache.cpu_side = system.iobus.master -system.iocache.mem_side = system.membus.slave - -#connect up the cpu and caches -cpu.addTwoLevelCacheHierarchy(L1Cache(size = '32kB', assoc = 1), - L1Cache(size = '32kB', assoc = 4), - L2Cache(size = '4MB', assoc = 8)) -# create the interrupt controller -cpu.createInterruptController() -# connect cpu and caches to the rest of the system -cpu.connectAllPorts(system.membus) -# set the cpu clock along with the caches and l1-l2 bus -cpu.clock = '2GHz' - -root = Root(full_system=True, system=system) -m5.ticks.setGlobalFrequency('1THz') +from alpha_generic import * +root = LinuxAlphaFSSystemUniprocessor(mem_mode='atomic', + cpu_class=AtomicSimpleCPU).create_root() diff --git a/tests/configs/tsunami-simple-timing-dual.py b/tests/configs/tsunami-simple-timing-dual.py index 4d74d9057..2ca280f06 100644 --- a/tests/configs/tsunami-simple-timing-dual.py +++ b/tests/configs/tsunami-simple-timing-dual.py @@ -1,6 +1,15 @@ -# Copyright (c) 2006-2007 The Regents of The University of Michigan +# Copyright (c) 2012 ARM Limited # All rights reserved. # +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are # met: redistributions of source code must retain the above copyright @@ -24,42 +33,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # -# Authors: Steve Reinhardt +# Authors: Andreas Sandberg -import m5 from m5.objects import * -m5.util.addToPath('../configs/common') -import FSConfig -from Caches import * - -#cpu -cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(2) ] -#the system -system = FSConfig.makeLinuxAlphaSystem('timing') -system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('8GB')]) -system.iocache.cpu_side = system.iobus.master -system.iocache.mem_side = system.membus.slave - -system.cpu = cpus -#create the l1/l2 bus -system.toL2Bus = CoherentBus(clock = '2GHz') - -#connect up the l2 cache -system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8) -system.l2c.cpu_side = system.toL2Bus.master -system.l2c.mem_side = system.membus.slave - -#connect up the cpu and l1s -for c in cpus: - c.addPrivateSplitL1Caches(L1Cache(size = '32kB', assoc = 1), - L1Cache(size = '32kB', assoc = 4)) - # create the interrupt controller - c.createInterruptController() - # connect cpu level-1 caches to shared level-2 cache - c.connectAllPorts(system.toL2Bus, system.membus) - c.clock = '2GHz' - -root = Root(full_system=True, system=system) -m5.ticks.setGlobalFrequency('1THz') - +from alpha_generic import * +root = LinuxAlphaFSSystem(mem_mode='timing', cpu_class=TimingSimpleCPU, + num_cpus=2).create_root() diff --git a/tests/configs/tsunami-simple-timing.py b/tests/configs/tsunami-simple-timing.py index 7bba6f938..27cb679b8 100644 --- a/tests/configs/tsunami-simple-timing.py +++ b/tests/configs/tsunami-simple-timing.py @@ -1,6 +1,15 @@ -# Copyright (c) 2006-2007 The Regents of The University of Michigan +# Copyright (c) 2012 ARM Limited # All rights reserved. # +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are # met: redistributions of source code must retain the above copyright @@ -24,37 +33,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # -# Authors: Steve Reinhardt +# Authors: Andreas Sandberg -import m5 from m5.objects import * -m5.util.addToPath('../configs/common') -import FSConfig -from Caches import * - -#cpu -cpu = TimingSimpleCPU(cpu_id=0) -#the system -system = FSConfig.makeLinuxAlphaSystem('timing') - -system.cpu = cpu - -#create the iocache -system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('8GB')]) -system.iocache.cpu_side = system.iobus.master -system.iocache.mem_side = system.membus.slave - -#connect up the cpu and caches -cpu.addTwoLevelCacheHierarchy(L1Cache(size = '32kB', assoc = 1), - L1Cache(size = '32kB', assoc = 4), - L2Cache(size = '4MB', assoc = 8)) -# create the interrupt controller -cpu.createInterruptController() -# connect cpu and caches to the rest of the system -cpu.connectAllPorts(system.membus) -# set the cpu clock along with the caches and l1-l2 bus -cpu.clock = '2GHz' - -root = Root(full_system=True, system=system) -m5.ticks.setGlobalFrequency('1THz') +from alpha_generic import * +root = LinuxAlphaFSSystemUniprocessor(mem_mode='timing', + cpu_class=TimingSimpleCPU).create_root() diff --git a/tests/configs/x86_generic.py b/tests/configs/x86_generic.py new file mode 100644 index 000000000..b9f8f7122 --- /dev/null +++ b/tests/configs/x86_generic.py @@ -0,0 +1,108 @@ +# Copyright (c) 2012 ARM Limited +# All rights reserved. +# +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Andreas Sandberg + +from abc import ABCMeta, abstractmethod +import m5 +from m5.objects import * +from m5.proxy import * +m5.util.addToPath('../configs/common') +from Benchmarks import SysConfig +import FSConfig +from Caches import * +from base_config import * + +class LinuxX86SystemBuilder(object): + """Mix-in that implements create_system. + + This mix-in is intended as a convenient way of adding an + X86-specific create_system method to a class deriving from one of + the generic base systems. + """ + def __init__(self): + pass + + def create_system(self): + mdesc = SysConfig(disk = 'linux-x86.img') + system = FSConfig.makeLinuxX86System(self.mem_mode, + numCPUs=self.num_cpus, + mdesc=mdesc) + system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9') + + self.init_system(system) + return system + +class LinuxX86FSSystem(LinuxX86SystemBuilder, + BaseFSSystem): + """Basic X86 full system builder.""" + + def __init__(self, **kwargs): + """Initialize an X86 system that supports full system simulation. + + Note: Keyword arguments that are not listed below will be + passed to the BaseFSSystem. + + Keyword Arguments: + machine_type -- String describing the platform to simulate + """ + BaseSystem.__init__(self, **kwargs) + LinuxX86SystemBuilder.__init__(self) + + def create_caches_private(self, cpu): + cpu.addPrivateSplitL1Caches(L1Cache(size='32kB', assoc=1), + L1Cache(size='32kB', assoc=4), + PageTableWalkerCache(), + PageTableWalkerCache()) + +class LinuxX86FSSystemUniprocessor(LinuxX86SystemBuilder, + BaseFSSystemUniprocessor): + """Basic X86 full system builder for uniprocessor systems. + + Note: This class is a specialization of the X86FSSystem and is + only really needed to provide backwards compatibility for existing + test cases. + """ + + def __init__(self, **kwargs): + BaseFSSystemUniprocessor.__init__(self, **kwargs) + LinuxX86SystemBuilder.__init__(self) + + def create_caches_private(self, cpu): + cpu.addTwoLevelCacheHierarchy(L1Cache(size='32kB', assoc=1), + L1Cache(size='32kB', assoc=4), + L2Cache(size='4MB', assoc=8), + PageTableWalkerCache(), + PageTableWalkerCache()) |