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-rw-r--r--tests/configs/memtest-ruby.py2
-rw-r--r--tests/configs/memtest.py6
2 files changed, 4 insertions, 4 deletions
diff --git a/tests/configs/memtest-ruby.py b/tests/configs/memtest-ruby.py
index 560a8fd65..397e9f0c7 100644
--- a/tests/configs/memtest-ruby.py
+++ b/tests/configs/memtest-ruby.py
@@ -69,7 +69,7 @@ options.l3_assoc=2
nb_cores = 8
# ruby does not support atomic, functional, or uncacheable accesses
-cpus = [ MemTest(atomic=False, percent_functional=50,
+cpus = [ MemTest(clock = '2GHz', atomic=False, percent_functional=50,
percent_uncacheable=0, suppress_func_warnings=True) \
for i in xrange(nb_cores) ]
diff --git a/tests/configs/memtest.py b/tests/configs/memtest.py
index f91a7eb78..5d60ee0ea 100644
--- a/tests/configs/memtest.py
+++ b/tests/configs/memtest.py
@@ -55,16 +55,16 @@ class L2(BaseCache):
#MAX CORES IS 8 with the fals sharing method
nb_cores = 8
-cpus = [ MemTest() for i in xrange(nb_cores) ]
+cpus = [ MemTest(clock = '2GHz') for i in xrange(nb_cores) ]
# system simulated
system = System(cpu = cpus, funcmem = SimpleMemory(in_addr_map = False),
funcbus = NoncoherentBus(),
physmem = SimpleMemory(),
- membus = CoherentBus(clock="500GHz", width=16))
+ membus = CoherentBus(clock="1GHz", width=16))
# l2cache & bus
-system.toL2Bus = CoherentBus(clock="500GHz", width=16)
+system.toL2Bus = CoherentBus(clock="2GHz", width=16)
system.l2c = L2(size='64kB', assoc=8)
system.l2c.cpu_side = system.toL2Bus.master