diff options
22 files changed, 2144 insertions, 2143 deletions
diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini index 98177ee67..083bb5627 100644 --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini @@ -11,7 +11,7 @@ children=bridge cpu diskmem intrctrl iobus iocache l2c membus physmem realview t boot_cpu_frequency=500 boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB slram=slram0,0x8000000,+0x8000000 mtdparts=slram0:- root=/dev/mtdblock0 init_param=0 -kernel=/dist/m5/system/binaries/vmlinux.arm +kernel=/chips/pd/randd/dist/binaries/vmlinux.arm load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing @@ -495,7 +495,7 @@ type=ExeTracer [system.diskmem] type=PhysicalMemory -file=/dist/m5/system/disks/ael-arm.ext2 +file=/chips/pd/randd/dist/disks/ael-arm.ext2 latency=30000 latency_var=0 null=false diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout index 64f7ad077..59ec5e402 100755 --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2011 12:05:49 -M5 started Apr 21 2011 15:19:16 -M5 executing on maize +M5 compiled May 1 2011 21:51:08 +M5 started May 1 2011 21:52:01 +M5 executing on u200439-lin.austin.arm.com command line: build/ARM_FS/m5.fast -d build/ARM_FS/tests/fast/long/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM_FS/tests/fast/long/10.linux-boot/arm/linux/realview-o3 Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux.arm +info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux.arm info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 82662490500 because m5_exit instruction encountered +Exiting @ tick 82642207500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index f3579a27d..2bcb37e3c 100644 --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,430 +1,430 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 112653 # Simulator instruction rate (inst/s) -host_mem_usage 348660 # Number of bytes of host memory used -host_seconds 461.40 # Real time elapsed on the host -host_tick_rate 179154205 # Simulator tick rate (ticks/s) +host_inst_rate 118050 # Simulator instruction rate (inst/s) +host_mem_usage 388868 # Number of bytes of host memory used +host_seconds 439.34 # Real time elapsed on the host +host_tick_rate 188104852 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 51978682 # Number of instructions simulated -sim_seconds 0.082662 # Number of seconds simulated -sim_ticks 82662490500 # Number of ticks simulated +sim_insts 51864248 # Number of instructions simulated +sim_seconds 0.082642 # Number of seconds simulated +sim_ticks 82642207500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 9175263 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 11695749 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 155381 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 665245 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 11246732 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 13229511 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 787550 # Number of times the RAS was used to get a target. -system.cpu.commit.branchMispredicts 641726 # The number of times a branch was mispredicted -system.cpu.commit.branches 8445621 # Number of branches committed -system.cpu.commit.bw_lim_events 801383 # number cycles where commit BW limit reached +system.cpu.BPredUnit.BTBHits 9217139 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 11723346 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 156768 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 663592 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 11213737 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 13194323 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 788661 # Number of times the RAS was used to get a target. +system.cpu.commit.branchMispredicts 639897 # The number of times a branch was mispredicted +system.cpu.commit.branches 8427507 # Number of branches committed +system.cpu.commit.bw_lim_events 797883 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.commitCommittedInsts 52101862 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 2963383 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 16147201 # The number of squashed insts skipped by commit -system.cpu.commit.committed_per_cycle::samples 93507712 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.557193 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.351787 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 51987478 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 2962739 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 16084299 # The number of squashed insts skipped by commit +system.cpu.commit.committed_per_cycle::samples 93469913 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.556195 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.349609 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 71892468 76.88% 76.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 10568988 11.30% 88.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3427833 3.67% 91.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 1711600 1.83% 93.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 3527395 3.77% 97.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 741726 0.79% 98.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 541099 0.58% 98.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 295220 0.32% 99.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 801383 0.86% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 71838189 76.86% 76.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 10610207 11.35% 88.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3480363 3.72% 91.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 1644006 1.76% 93.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 3523448 3.77% 97.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 741299 0.79% 98.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 540450 0.58% 98.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 294068 0.31% 99.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 797883 0.85% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 93507712 # Number of insts commited each cycle -system.cpu.commit.count 52101862 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 93469913 # Number of insts commited each cycle +system.cpu.commit.count 51987478 # Number of instructions committed system.cpu.commit.fp_insts 6017 # Number of committed floating point instructions. -system.cpu.commit.function_calls 529734 # Number of function calls committed. -system.cpu.commit.int_insts 42509491 # Number of committed integer instructions. -system.cpu.commit.loads 9207015 # Number of loads committed +system.cpu.commit.function_calls 529811 # Number of function calls committed. +system.cpu.commit.int_insts 42411675 # Number of committed integer instructions. +system.cpu.commit.loads 9176268 # Number of loads committed system.cpu.commit.membars 3 # Number of memory barriers committed -system.cpu.commit.refs 16293738 # Number of memory references committed +system.cpu.commit.refs 16251703 # Number of memory references committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.committedInsts 51978682 # Number of Instructions Simulated -system.cpu.committedInsts_total 51978682 # Number of Instructions Simulated -system.cpu.cpi 3.180631 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.180631 # CPI: Total CPI of All Threads -system.cpu.dcache.LoadLockedReq_accesses::0 111504 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 111504 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14941.207869 # average LoadLockedReq miss latency +system.cpu.committedInsts 51864248 # Number of Instructions Simulated +system.cpu.committedInsts_total 51864248 # Number of Instructions Simulated +system.cpu.cpi 3.186866 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.186866 # CPI: Total CPI of All Threads +system.cpu.dcache.LoadLockedReq_accesses::0 111590 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 111590 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14996.059342 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11805.277281 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_hits::0 104947 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 104947 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_miss_latency 97969500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_rate::0 0.058805 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_misses::0 6557 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 6557 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_mshr_hits 967 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 65991500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.050133 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11857.982282 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::0 105119 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 105119 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_miss_latency 97039500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_rate::0 0.057989 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_misses::0 6471 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 6471 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_mshr_hits 940 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_miss_latency 65586500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.049565 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_misses 5590 # number of LoadLockedReq MSHR misses -system.cpu.dcache.ReadReq_accesses::0 9423338 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9423338 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency::0 14823.280125 # average ReadReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_misses 5531 # number of LoadLockedReq MSHR misses +system.cpu.dcache.ReadReq_accesses::0 9392794 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9392794 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency::0 14764.348504 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13267.626376 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13258.945954 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_hits::0 8937009 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 8937009 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 7208991000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate::0 0.051609 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses::0 486329 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 486329 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 237469 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 3301781500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.026409 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_hits::0 8903858 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 8903858 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 7218821500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate::0 0.052054 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses::0 488936 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 488936 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 240332 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 3296227000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.026468 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 248860 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_uncacheable_latency 38194393000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.StoreCondReq_accesses::0 105004 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 105004 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_hits::0 105004 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 105004 # number of StoreCondReq hits -system.cpu.dcache.WriteReq_accesses::0 6672578 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6672578 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency::0 39930.375248 # average WriteReq miss latency +system.cpu.dcache.ReadReq_mshr_misses 248604 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable_latency 38194550500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.StoreCondReq_accesses::0 105035 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 105035 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits::0 105035 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 105035 # number of StoreCondReq hits +system.cpu.dcache.WriteReq_accesses::0 6661106 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6661106 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency::0 39940.947710 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 38504.296551 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 38496.257162 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_hits::0 4626571 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4626571 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 81697827271 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate::0 0.306629 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses::0 2046007 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2046007 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 1875409 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 6568755983 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.025567 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_hits::0 4616668 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4616668 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 81656791255 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate::0 0.306922 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses::0 2044438 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2044438 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 1873841 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 6567345983 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.025611 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 170598 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 940173192 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.avg_blocked_cycles::no_mshrs 7672.355023 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 21291.666667 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 32.542596 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 876 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 24 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 6720983 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 511000 # number of cycles access was blocked +system.cpu.dcache.WriteReq_mshr_misses 170597 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_uncacheable_latency 940602193 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.avg_blocked_cycles::no_mshrs 7422.728541 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 22666.666667 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 32.464127 # Average number of references to valid blocks. +system.cpu.dcache.blocked::no_mshrs 932 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 30 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 6917983 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 680000 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses::0 16095916 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::0 16053900 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 16095916 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency::0 35108.618395 # average overall miss latency +system.cpu.dcache.demand_accesses::total 16053900 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency::0 35081.915562 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 23531.646751 # average overall mshr miss latency -system.cpu.dcache.demand_hits::0 13563580 # number of demand (read+write) hits +system.cpu.dcache.demand_avg_mshr_miss_latency 23529.459574 # average overall mshr miss latency +system.cpu.dcache.demand_hits::0 13520526 # number of demand (read+write) hits system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13563580 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 88906818271 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate::0 0.157328 # miss rate for demand accesses +system.cpu.dcache.demand_hits::total 13520526 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 88875612755 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate::0 0.157804 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.demand_misses::0 2532336 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::0 2533374 # number of demand (read+write) misses system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2532336 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 2112878 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 9870537483 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate::0 0.026060 # mshr miss rate for demand accesses +system.cpu.dcache.demand_misses::total 2533374 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 2114173 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 9863572983 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::0 0.026112 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 419458 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 419201 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_blocks::0 511.750765 # Average occupied blocks per context +system.cpu.dcache.occ_blocks::0 511.750704 # Average occupied blocks per context system.cpu.dcache.occ_percent::0 0.999513 # Average percentage of cache occupancy -system.cpu.dcache.overall_accesses::0 16095916 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::0 16053900 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 16095916 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency::0 35108.618395 # average overall miss latency +system.cpu.dcache.overall_accesses::total 16053900 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency::0 35081.915562 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 23531.646751 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 23529.459574 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits::0 13563580 # number of overall hits +system.cpu.dcache.overall_hits::0 13520526 # number of overall hits system.cpu.dcache.overall_hits::1 0 # number of overall hits -system.cpu.dcache.overall_hits::total 13563580 # number of overall hits -system.cpu.dcache.overall_miss_latency 88906818271 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate::0 0.157328 # miss rate for overall accesses +system.cpu.dcache.overall_hits::total 13520526 # number of overall hits +system.cpu.dcache.overall_miss_latency 88875612755 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate::0 0.157804 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.overall_misses::0 2532336 # number of overall misses +system.cpu.dcache.overall_misses::0 2533374 # number of overall misses system.cpu.dcache.overall_misses::1 0 # number of overall misses -system.cpu.dcache.overall_misses::total 2532336 # number of overall misses -system.cpu.dcache.overall_mshr_hits 2112878 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 9870537483 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate::0 0.026060 # mshr miss rate for overall accesses +system.cpu.dcache.overall_misses::total 2533374 # number of overall misses +system.cpu.dcache.overall_mshr_hits 2114173 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 9863572983 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate::0 0.026112 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 419458 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 39134566192 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_misses 419201 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 39135152693 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 422792 # number of replacements -system.cpu.dcache.sampled_refs 423304 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 422493 # number of replacements +system.cpu.dcache.sampled_refs 423005 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 511.750765 # Cycle average of tags in use -system.cpu.dcache.total_refs 13775411 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 511.750704 # Cycle average of tags in use +system.cpu.dcache.total_refs 13732488 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 48224000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 391506 # number of writebacks -system.cpu.decode.BlockedCycles 53936622 # Number of cycles decode is blocked -system.cpu.decode.BranchMispred 70601 # Number of times decode detected a branch misprediction -system.cpu.decode.BranchResolved 1224137 # Number of times decode resolved a branch -system.cpu.decode.DecodedInsts 76419738 # Number of instructions handled by decode -system.cpu.decode.IdleCycles 23948605 # Number of cycles decode is idle -system.cpu.decode.RunCycles 14435253 # Number of cycles decode is running -system.cpu.decode.SquashCycles 2568567 # Number of cycles decode is squashing -system.cpu.decode.SquashedInsts 235986 # Number of squashed instructions handled by decode -system.cpu.decode.UnblockCycles 1187204 # Number of cycles decode is unblocking -system.cpu.dtb.accesses 35246983 # DTB accesses -system.cpu.dtb.align_faults 1461 # Number of TLB faults due to alignment restrictions +system.cpu.dcache.writebacks 390869 # number of writebacks +system.cpu.decode.BlockedCycles 53918623 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 70743 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 1221974 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 76222777 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 23898664 # Number of cycles decode is idle +system.cpu.decode.RunCycles 14467362 # Number of cycles decode is running +system.cpu.decode.SquashCycles 2560103 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 235239 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 1185236 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 35200912 # DTB accesses +system.cpu.dtb.align_faults 1566 # Number of TLB faults due to alignment restrictions system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.flush_entries 2766 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 2768 # Number of entries that have been flushed from TLB system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 33670 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.hits 35174002 # DTB hits +system.cpu.dtb.flush_tlb_mva_asid 33678 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 35128520 # DTB hits system.cpu.dtb.inst_accesses 0 # ITB inst accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.misses 72981 # DTB misses -system.cpu.dtb.perms_faults 1114 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.prefetch_faults 1061 # Number of TLB faults due to prefetch -system.cpu.dtb.read_accesses 27744902 # DTB read accesses -system.cpu.dtb.read_hits 27682402 # DTB read hits -system.cpu.dtb.read_misses 62500 # DTB read misses -system.cpu.dtb.write_accesses 7502081 # DTB write accesses -system.cpu.dtb.write_hits 7491600 # DTB write hits -system.cpu.dtb.write_misses 10481 # DTB write misses -system.cpu.fetch.Branches 13229511 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 6553650 # Number of cache lines fetched -system.cpu.fetch.Cycles 16012029 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 257276 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 64080399 # Number of instructions fetch has processed -system.cpu.fetch.ItlbSquashes 4041 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.MiscStallCycles 17184 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 1041966 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 7137 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.branchRate 0.080021 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 6552269 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 9962813 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.387603 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 96076251 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.821047 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.076929 # Number of instructions fetched each cycle (Total) +system.cpu.dtb.misses 72392 # DTB misses +system.cpu.dtb.perms_faults 1141 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 1038 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 27711875 # DTB read accesses +system.cpu.dtb.read_hits 27650210 # DTB read hits +system.cpu.dtb.read_misses 61665 # DTB read misses +system.cpu.dtb.write_accesses 7489037 # DTB write accesses +system.cpu.dtb.write_hits 7478310 # DTB write hits +system.cpu.dtb.write_misses 10727 # DTB write misses +system.cpu.fetch.Branches 13194323 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 6536368 # Number of cache lines fetched +system.cpu.fetch.Cycles 16040697 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 256520 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 63901338 # Number of instructions fetch has processed +system.cpu.fetch.ItlbSquashes 4100 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.MiscStallCycles 17647 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 1039734 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 7258 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.branchRate 0.079828 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 6534883 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 10005800 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.386614 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 96029988 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.819324 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.073932 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 80080684 83.35% 83.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1206606 1.26% 84.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1754286 1.83% 86.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1219002 1.27% 87.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4793265 4.99% 92.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 802218 0.83% 93.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 845287 0.88% 94.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 744134 0.77% 95.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4630769 4.82% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 80005841 83.31% 83.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1273067 1.33% 84.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1748855 1.82% 86.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1275883 1.33% 87.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4729341 4.92% 92.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 797324 0.83% 93.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 838519 0.87% 94.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 743131 0.77% 95.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4618027 4.81% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 96076251 # Number of instructions fetched each cycle (Total) -system.cpu.fp_regfile_reads 5420 # number of floating regfile reads +system.cpu.fetch.rateDist::total 96029988 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 5517 # number of floating regfile reads system.cpu.fp_regfile_writes 1898 # number of floating regfile writes -system.cpu.icache.ReadReq_accesses::0 6553557 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 6553557 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency::0 14743.844575 # average ReadReq miss latency +system.cpu.icache.ReadReq_accesses::0 6536276 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 6536276 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency::0 14765.188780 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 12014.286786 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 12018.413931 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu.icache.ReadReq_hits::0 6005950 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 6005950 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 8073832496 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate::0 0.083559 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses::0 547607 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 547607 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 44625 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 6042969996 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.076749 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_hits::0 5990561 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 5990561 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 8057584995 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate::0 0.083490 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses::0 545715 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 545715 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 43351 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 6037618496 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::0 0.076858 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 502982 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses 502364 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_uncacheable_latency 4957500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.avg_blocked_cycles::no_mshrs 7957.783133 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 7107.483871 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 11.941659 # Average number of references to valid blocks. -system.cpu.icache.blocked::no_mshrs 83 # number of cycles access was blocked +system.cpu.icache.avg_refs 11.925573 # Average number of references to valid blocks. +system.cpu.icache.blocked::no_mshrs 93 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_mshrs 660496 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 660996 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses::0 6553557 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::0 6536276 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 6553557 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency::0 14743.844575 # average overall miss latency +system.cpu.icache.demand_accesses::total 6536276 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency::0 14765.188780 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 12014.286786 # average overall mshr miss latency -system.cpu.icache.demand_hits::0 6005950 # number of demand (read+write) hits +system.cpu.icache.demand_avg_mshr_miss_latency 12018.413931 # average overall mshr miss latency +system.cpu.icache.demand_hits::0 5990561 # number of demand (read+write) hits system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 6005950 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 8073832496 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate::0 0.083559 # miss rate for demand accesses +system.cpu.icache.demand_hits::total 5990561 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 8057584995 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate::0 0.083490 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.demand_misses::0 547607 # number of demand (read+write) misses +system.cpu.icache.demand_misses::0 545715 # number of demand (read+write) misses system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 547607 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 44625 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 6042969996 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate::0 0.076749 # mshr miss rate for demand accesses +system.cpu.icache.demand_misses::total 545715 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 43351 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 6037618496 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::0 0.076858 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 502982 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 502364 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_blocks::0 496.652768 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.970025 # Average percentage of cache occupancy -system.cpu.icache.overall_accesses::0 6553557 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::0 496.613032 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.969947 # Average percentage of cache occupancy +system.cpu.icache.overall_accesses::0 6536276 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 6553557 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency::0 14743.844575 # average overall miss latency +system.cpu.icache.overall_accesses::total 6536276 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency::0 14765.188780 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 12014.286786 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 12018.413931 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu.icache.overall_hits::0 6005950 # number of overall hits +system.cpu.icache.overall_hits::0 5990561 # number of overall hits system.cpu.icache.overall_hits::1 0 # number of overall hits -system.cpu.icache.overall_hits::total 6005950 # number of overall hits -system.cpu.icache.overall_miss_latency 8073832496 # number of overall miss cycles -system.cpu.icache.overall_miss_rate::0 0.083559 # miss rate for overall accesses +system.cpu.icache.overall_hits::total 5990561 # number of overall hits +system.cpu.icache.overall_miss_latency 8057584995 # number of overall miss cycles +system.cpu.icache.overall_miss_rate::0 0.083490 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.overall_misses::0 547607 # number of overall misses +system.cpu.icache.overall_misses::0 545715 # number of overall misses system.cpu.icache.overall_misses::1 0 # number of overall misses -system.cpu.icache.overall_misses::total 547607 # number of overall misses -system.cpu.icache.overall_mshr_hits 44625 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 6042969996 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate::0 0.076749 # mshr miss rate for overall accesses +system.cpu.icache.overall_misses::total 545715 # number of overall misses +system.cpu.icache.overall_mshr_hits 43351 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 6037618496 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate::0 0.076858 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 502982 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 502364 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 4957500 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 502429 # number of replacements -system.cpu.icache.sampled_refs 502941 # Sample count of references to valid blocks. +system.cpu.icache.replacements 501817 # number of replacements +system.cpu.icache.sampled_refs 502329 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 496.652768 # Cycle average of tags in use -system.cpu.icache.total_refs 6005950 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 6210686000 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 41369 # number of writebacks -system.cpu.idleCycles 69248731 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.branchMispredicts 711242 # Number of branch mispredicts detected at execute -system.cpu.iew.exec_branches 10230019 # Number of branches executed -system.cpu.iew.exec_nop 166886 # number of nop insts executed -system.cpu.iew.exec_rate 0.475904 # Inst execution rate -system.cpu.iew.exec_refs 35985354 # number of memory reference insts executed -system.cpu.iew.exec_stores 7801149 # Number of stores executed +system.cpu.icache.tagsinuse 496.613032 # Cycle average of tags in use +system.cpu.icache.total_refs 5990561 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 6206760000 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 41345 # number of writebacks +system.cpu.idleCycles 69254428 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 709509 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 10208989 # Number of branches executed +system.cpu.iew.exec_nop 166594 # number of nop insts executed +system.cpu.iew.exec_rate 0.475153 # Inst execution rate +system.cpu.iew.exec_refs 35930461 # number of memory reference insts executed +system.cpu.iew.exec_stores 7787986 # Number of stores executed system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.iewBlockCycles 21406073 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 12848037 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 4002488 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 354669 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 8736360 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 70502341 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 28184205 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1059977 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 78678877 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 28556 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewBlockCycles 21409997 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 12801352 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 4001963 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 354229 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 8717928 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 70324411 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 28142475 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1056013 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 78535348 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 28684 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 45641 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 2568567 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 263948 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 45618 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 2560103 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 263512 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.cacheBlocked 8235 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread0.forwLoads 331109 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.ignoredResponses 7560 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.cacheBlocked 8416 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 328766 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 7567 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.memOrderViolation 280540 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.rescheduledLoads 17000484 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.squashedLoads 3641022 # Number of loads squashed -system.cpu.iew.lsq.thread0.squashedStores 1649637 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 280540 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 186102 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 525140 # Number of branches that were predicted taken incorrectly -system.cpu.iew.wb_consumers 62345618 # num instructions consuming a value -system.cpu.iew.wb_count 60884415 # cumulative count of insts written-back -system.cpu.iew.wb_fanout 0.509768 # average fanout of values written-back +system.cpu.iew.lsq.thread0.memOrderViolation 279979 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 17000828 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 3625084 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 1642493 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 279979 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 185766 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 523743 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 62153325 # num instructions consuming a value +system.cpu.iew.wb_count 60744260 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.509987 # average fanout of values written-back system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.wb_producers 31781773 # num instructions producing a value -system.cpu.iew.wb_rate 0.368271 # insts written-back per cycle -system.cpu.iew.wb_sent 78152559 # cumulative count of insts sent to commit -system.cpu.int_regfile_reads 182840055 # number of integer regfile reads -system.cpu.int_regfile_writes 43911822 # number of integer regfile writes -system.cpu.ipc 0.314403 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.314403 # IPC: Total IPC of All Threads -system.cpu.iq.FU_type_0::No_OpClass 2393207 3.00% 3.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 40767716 51.13% 54.13% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 71906 0.09% 54.22% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 54.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 54.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 54.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 54.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 54.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 54.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 10 0.00% 54.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 6 0.00% 54.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 895 0.00% 54.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 54.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.22% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 28538408 35.79% 90.01% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 7966700 9.99% 100.00% # Type of FU issued +system.cpu.iew.wb_producers 31697370 # num instructions producing a value +system.cpu.iew.wb_rate 0.367514 # insts written-back per cycle +system.cpu.iew.wb_sent 78012051 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 182457772 # number of integer regfile reads +system.cpu.int_regfile_writes 43778590 # number of integer regfile writes +system.cpu.ipc 0.313788 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.313788 # IPC: Total IPC of All Threads +system.cpu.iq.FU_type_0::No_OpClass 2393223 3.01% 3.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 40680159 51.11% 54.12% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 71135 0.09% 54.21% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 54.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 54.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 54.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 54.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 54.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 54.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 14 0.00% 54.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 5 0.00% 54.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 880 0.00% 54.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 54.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.21% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 28494301 35.80% 90.01% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 7951639 9.99% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 79738854 # Type of FU issued -system.cpu.iq.fp_alu_accesses 8555 # Number of floating point alu accesses -system.cpu.iq.fp_inst_queue_reads 16356 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_wakeup_accesses 6330 # Number of floating instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_writes 9324 # Number of floating instruction queue writes -system.cpu.iq.fu_busy_cnt 4821847 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.060470 # FU busy rate (busy events/executed inst) +system.cpu.iq.FU_type_0::total 79591361 # Type of FU issued +system.cpu.iq.fp_alu_accesses 8649 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 16528 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 6413 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 9518 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 4821398 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.060577 # FU busy rate (busy events/executed inst) system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 5252 0.11% 0.11% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 1 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 5422 0.11% 0.11% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 0.11% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.11% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.11% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.11% # attempts to use FU when none available @@ -452,53 +452,53 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.11% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.11% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.11% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 4503965 93.41% 93.52% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 312629 6.48% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 4503057 93.40% 93.51% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 312919 6.49% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.int_alu_accesses 82158939 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 260560114 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 60878085 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 88252468 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 66303042 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 79738854 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 4032413 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 17660461 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 127886 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 1069030 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 22275203 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.issued_per_cycle::samples 96076251 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.829954 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.379344 # Number of insts issued each cycle +system.cpu.iq.int_alu_accesses 82010887 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 260214449 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 60737847 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 88009636 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 66125775 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 79591361 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 4032042 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 17595997 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 124696 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 1069303 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 22170829 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 96029988 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.828818 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.378506 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 59918658 62.37% 62.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 16598524 17.28% 79.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7253913 7.55% 87.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 4126106 4.29% 91.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5947858 6.19% 97.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1304063 1.36% 99.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 619735 0.65% 99.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 235123 0.24% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 72271 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 59877651 62.35% 62.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 16701073 17.39% 79.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7167891 7.46% 87.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 4116385 4.29% 91.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5937883 6.18% 97.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1300941 1.35% 99.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 620651 0.65% 99.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 234896 0.24% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 72617 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 96076251 # Number of insts issued each cycle -system.cpu.iq.rate 0.482316 # Inst issue rate -system.cpu.itb.accesses 6566505 # DTB accesses +system.cpu.iq.issued_per_cycle::total 96029988 # Number of insts issued each cycle +system.cpu.iq.rate 0.481542 # Inst issue rate +system.cpu.itb.accesses 6549493 # DTB accesses system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.flush_entries 1618 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 1627 # Number of entries that have been flushed from TLB system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 33670 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.hits 6559368 # DTB hits -system.cpu.itb.inst_accesses 6566505 # ITB inst accesses -system.cpu.itb.inst_hits 6559368 # ITB inst hits -system.cpu.itb.inst_misses 7137 # ITB inst misses -system.cpu.itb.misses 7137 # DTB misses -system.cpu.itb.perms_faults 5235 # Number of TLB faults due to permissions restrictions +system.cpu.itb.flush_tlb_mva_asid 33678 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 6542235 # DTB hits +system.cpu.itb.inst_accesses 6549493 # ITB inst accesses +system.cpu.itb.inst_hits 6542235 # ITB inst hits +system.cpu.itb.inst_misses 7258 # ITB inst misses +system.cpu.itb.misses 7258 # DTB misses +system.cpu.itb.perms_faults 5302 # Number of TLB faults due to permissions restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_hits 0 # DTB read hits @@ -508,37 +508,37 @@ system.cpu.itb.write_hits 0 # DT system.cpu.itb.write_misses 0 # DTB write misses system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu.memDep0.conflictingLoads 3427 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 9862 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 12848037 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 8736360 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 84327441 # number of misc regfile reads -system.cpu.misc_regfile_writes 505947 # number of misc regfile writes -system.cpu.numCycles 165324982 # number of cpu cycles simulated +system.cpu.memDep0.conflictingLoads 527 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1505 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 12801352 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 8717928 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 84103631 # number of misc regfile reads +system.cpu.misc_regfile_writes 505277 # number of misc regfile writes +system.cpu.numCycles 165284416 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.BlockCycles 33112132 # Number of cycles rename is blocking -system.cpu.rename.CommittedMaps 36741742 # Number of HB maps that are committed -system.cpu.rename.IQFullEvents 775024 # Number of times rename has blocked due to IQ full -system.cpu.rename.IdleCycles 25585942 # Number of cycles rename is idle -system.cpu.rename.LSQFullEvents 2464411 # Number of times rename has blocked due to LSQ full -system.cpu.rename.ROBFullEvents 439406 # Number of times rename has blocked due to ROB full -system.cpu.rename.RenameLookups 190546426 # Number of register rename lookups that rename has made -system.cpu.rename.RenamedInsts 73652077 # Number of instructions processed by rename -system.cpu.rename.RenamedOperands 53332963 # Number of destination operands rename has renamed -system.cpu.rename.RunCycles 13017560 # Number of cycles rename is running -system.cpu.rename.SquashCycles 2568567 # Number of cycles rename is squashing -system.cpu.rename.UnblockCycles 5444932 # Number of cycles rename is unblocking -system.cpu.rename.UndoneMaps 16591220 # Number of HB maps that are undone due to squashing -system.cpu.rename.fp_rename_lookups 49319 # Number of floating rename lookups -system.cpu.rename.int_rename_lookups 190497107 # Number of integer rename lookups -system.cpu.rename.serializeStallCycles 16347118 # count of cycles rename stalled for serializing inst -system.cpu.rename.serializingInsts 812559 # count of serializing insts renamed -system.cpu.rename.skidInsts 14268469 # count of insts added to the skid buffer -system.cpu.rename.tempSerializingInsts 662925 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 160015001 # The number of ROB reads -system.cpu.rob.rob_writes 139111158 # The number of ROB writes -system.cpu.timesIdled 1092841 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.BlockCycles 33115437 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 36635967 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 774543 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 25534118 # Number of cycles rename is idle +system.cpu.rename.LSQFullEvents 2455786 # Number of times rename has blocked due to LSQ full +system.cpu.rename.ROBFullEvents 439444 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 190012528 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 73459196 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 53155574 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 13048942 # Number of cycles rename is running +system.cpu.rename.SquashCycles 2560103 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 5434449 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 16519606 # Number of HB maps that are undone due to squashing +system.cpu.rename.fp_rename_lookups 49943 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 189962585 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 16336939 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 811757 # count of serializing insts renamed +system.cpu.rename.skidInsts 14251840 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 662762 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 159803078 # The number of ROB reads +system.cpu.rob.rob_writes 138748293 # The number of ROB writes +system.cpu.timesIdled 1093520 # Number of times that the entire CPU went into an idle state and unscheduled itself system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.avg_refs no_value # Average number of references to valid blocks. @@ -606,141 +606,141 @@ system.iocache.tagsinuse 0 # Cy system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.iocache.writebacks 0 # number of writebacks -system.l2c.ReadExReq_accesses::0 168878 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 168878 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency::0 52453.870744 # average ReadExReq miss latency +system.l2c.ReadExReq_accesses::0 168895 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 168895 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency::0 52452.689806 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40012.272411 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_hits::0 60953 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 60953 # number of ReadExReq hits -system.l2c.ReadExReq_miss_latency 5661084000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_rate::0 0.639071 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses::0 107925 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 107925 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_miss_latency 4318324500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_rate::0 0.639071 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_avg_mshr_miss_latency 40011.850713 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_hits::0 60969 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 60969 # number of ReadExReq hits +system.l2c.ReadExReq_miss_latency 5661009000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_rate::0 0.639012 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses::0 107926 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 107926 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 4318319000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_rate::0 0.639012 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 107925 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses::0 754907 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 102462 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 857369 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency::0 52723.366686 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 5971800 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 6024523.366686 # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 40042.738791 # average ReadReq mshr miss latency +system.l2c.ReadExReq_mshr_misses 107926 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses::0 754009 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 102736 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 856745 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency::0 52493.894964 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 11763824.175824 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 11816318.070788 # average ReadReq miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40042.808219 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits::0 734519 # number of ReadReq hits -system.l2c.ReadReq_hits::1 102282 # number of ReadReq hits -system.l2c.ReadReq_hits::total 836801 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 1074924000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate::0 0.027007 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.001757 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.028764 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses::0 20388 # number of ReadReq misses -system.l2c.ReadReq_misses::1 180 # number of ReadReq misses -system.l2c.ReadReq_misses::total 20568 # number of ReadReq misses -system.l2c.ReadReq_mshr_hits 48 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_miss_latency 821677000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.027182 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 0.200269 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.227452 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 20520 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_uncacheable_latency 28942557500 # number of ReadReq MSHR uncacheable cycles -system.l2c.UpgradeReq_accesses::0 1743 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 1743 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency::0 399.055490 # average UpgradeReq miss latency +system.l2c.ReadReq_hits::0 733616 # number of ReadReq hits +system.l2c.ReadReq_hits::1 102645 # number of ReadReq hits +system.l2c.ReadReq_hits::total 836261 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 1070508000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate::0 0.027046 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.000886 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.027932 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses::0 20393 # number of ReadReq misses +system.l2c.ReadReq_misses::1 91 # number of ReadReq misses +system.l2c.ReadReq_misses::total 20484 # number of ReadReq misses +system.l2c.ReadReq_mshr_hits 44 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_miss_latency 818475000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.027108 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 0.198957 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.226065 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_misses 20440 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable_latency 28942346500 # number of ReadReq MSHR uncacheable cycles +system.l2c.UpgradeReq_accesses::0 1727 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 1727 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency::0 400.236827 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_hits::0 49 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 49 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::0 38 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 38 # number of UpgradeReq hits system.l2c.UpgradeReq_miss_latency 676000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_rate::0 0.971888 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses::0 1694 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 1694 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_miss_latency 67760000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_rate::0 0.971888 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::0 0.977997 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses::0 1689 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 1689 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 67560000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_rate::0 0.977997 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 1694 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 1689 # number of UpgradeReq MSHR misses system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_mshr_uncacheable_latency 745944450 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses::0 432875 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 432875 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits::0 432875 # number of Writeback hits -system.l2c.Writeback_hits::total 432875 # number of Writeback hits +system.l2c.WriteReq_mshr_uncacheable_latency 746141450 # number of WriteReq MSHR uncacheable cycles +system.l2c.Writeback_accesses::0 432214 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 432214 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits::0 432214 # number of Writeback hits +system.l2c.Writeback_hits::total 432214 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.l2c.avg_refs 8.172694 # Average number of references to valid blocks. +system.l2c.avg_refs 8.138796 # Average number of references to valid blocks. system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses::0 923785 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 102462 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1026247 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency::0 52496.691684 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 37422266.666667 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 37474763.358350 # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 40017.139632 # average overall mshr miss latency -system.l2c.demand_hits::0 795472 # number of demand (read+write) hits -system.l2c.demand_hits::1 102282 # number of demand (read+write) hits -system.l2c.demand_hits::total 897754 # number of demand (read+write) hits -system.l2c.demand_miss_latency 6736008000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate::0 0.138899 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.001757 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.140656 # miss rate for demand accesses -system.l2c.demand_misses::0 128313 # number of demand (read+write) misses -system.l2c.demand_misses::1 180 # number of demand (read+write) misses -system.l2c.demand_misses::total 128493 # number of demand (read+write) misses -system.l2c.demand_mshr_hits 48 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 5140001500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate::0 0.139042 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 1.253587 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 1.392629 # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 128445 # number of demand (read+write) MSHR misses +system.l2c.demand_accesses::0 922904 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 102736 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1025640 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency::0 52459.238305 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 73972714.285714 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 74025173.524019 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency 40016.780144 # average overall mshr miss latency +system.l2c.demand_hits::0 794585 # number of demand (read+write) hits +system.l2c.demand_hits::1 102645 # number of demand (read+write) hits +system.l2c.demand_hits::total 897230 # number of demand (read+write) hits +system.l2c.demand_miss_latency 6731517000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate::0 0.139038 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.000886 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.139924 # miss rate for demand accesses +system.l2c.demand_misses::0 128319 # number of demand (read+write) misses +system.l2c.demand_misses::1 91 # number of demand (read+write) misses +system.l2c.demand_misses::total 128410 # number of demand (read+write) misses +system.l2c.demand_mshr_hits 44 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_miss_latency 5136794000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate::0 0.139089 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 1.249474 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 1.388564 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 128366 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_blocks::0 6518.840874 # Average occupied blocks per context -system.l2c.occ_blocks::1 31565.358061 # Average occupied blocks per context -system.l2c.occ_percent::0 0.099470 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.481649 # Average percentage of cache occupancy -system.l2c.overall_accesses::0 923785 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 102462 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1026247 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency::0 52496.691684 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 37422266.666667 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 37474763.358350 # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 40017.139632 # average overall mshr miss latency +system.l2c.occ_blocks::0 6525.669057 # Average occupied blocks per context +system.l2c.occ_blocks::1 31523.989164 # Average occupied blocks per context +system.l2c.occ_percent::0 0.099574 # Average percentage of cache occupancy +system.l2c.occ_percent::1 0.481018 # Average percentage of cache occupancy +system.l2c.overall_accesses::0 922904 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 102736 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1025640 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency::0 52459.238305 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 73972714.285714 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 74025173.524019 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency 40016.780144 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits::0 795472 # number of overall hits -system.l2c.overall_hits::1 102282 # number of overall hits -system.l2c.overall_hits::total 897754 # number of overall hits -system.l2c.overall_miss_latency 6736008000 # number of overall miss cycles -system.l2c.overall_miss_rate::0 0.138899 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.001757 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.140656 # miss rate for overall accesses -system.l2c.overall_misses::0 128313 # number of overall misses -system.l2c.overall_misses::1 180 # number of overall misses -system.l2c.overall_misses::total 128493 # number of overall misses -system.l2c.overall_mshr_hits 48 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 5140001500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate::0 0.139042 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 1.253587 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 1.392629 # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 128445 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 29688501950 # number of overall MSHR uncacheable cycles +system.l2c.overall_hits::0 794585 # number of overall hits +system.l2c.overall_hits::1 102645 # number of overall hits +system.l2c.overall_hits::total 897230 # number of overall hits +system.l2c.overall_miss_latency 6731517000 # number of overall miss cycles +system.l2c.overall_miss_rate::0 0.139038 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.000886 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.139924 # miss rate for overall accesses +system.l2c.overall_misses::0 128319 # number of overall misses +system.l2c.overall_misses::1 91 # number of overall misses +system.l2c.overall_misses::total 128410 # number of overall misses +system.l2c.overall_mshr_hits 44 # number of overall MSHR hits +system.l2c.overall_mshr_miss_latency 5136794000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate::0 0.139089 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 1.249474 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 1.388564 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 128366 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 29688487950 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.replacements 94647 # number of replacements -system.l2c.sampled_refs 126947 # Sample count of references to valid blocks. +system.l2c.replacements 94658 # number of replacements +system.l2c.sampled_refs 126891 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 38084.198936 # Cycle average of tags in use -system.l2c.total_refs 1037499 # Total number of references to valid blocks. +system.l2c.tagsinuse 38049.658221 # Cycle average of tags in use +system.l2c.total_refs 1032740 # Total number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 87563 # number of writebacks +system.l2c.writebacks 87784 # number of writebacks ---------- End Simulation Statistics ---------- diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/status b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/status index 9541cca97..f27ebe211 100644 --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/status +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/status @@ -1 +1 @@ -build/ARM_FS/tests/fast/long/10.linux-boot/arm/linux/realview-o3 passed. +build/ARM_FS/tests/fast/long/10.linux-boot/arm/linux/realview-o3 FAILED! diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/system.terminal b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/system.terminal Binary files differindex 3d9759fde..6d04c79ea 100644 --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/system.terminal +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/system.terminal diff --git a/tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini b/tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini index 2426ff257..9419f3f42 100644 --- a/tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini @@ -498,7 +498,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/vortex +executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/vortex gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/50.vortex/ref/arm/linux/o3-timing/simout b/tests/long/50.vortex/ref/arm/linux/o3-timing/simout index f3dc52cc8..a49d7b0da 100755 --- a/tests/long/50.vortex/ref/arm/linux/o3-timing/simout +++ b/tests/long/50.vortex/ref/arm/linux/o3-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2011 12:05:01 -M5 started Apr 21 2011 14:53:22 -M5 executing on maize +M5 compiled May 1 2011 19:23:04 +M5 started May 1 2011 19:48:10 +M5 executing on u200439-lin.austin.arm.com command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/50.vortex/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 39891736000 because target called exit() +Exiting @ tick 39989822000 because target called exit() diff --git a/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt index d0dfce1d1..2d1b25b5c 100644 --- a/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,146 +1,146 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 153606 # Simulator instruction rate (inst/s) -host_mem_usage 226292 # Number of bytes of host memory used -host_seconds 655.14 # Real time elapsed on the host -host_tick_rate 60890397 # Simulator tick rate (ticks/s) +host_inst_rate 102961 # Simulator instruction rate (inst/s) +host_mem_usage 269452 # Number of bytes of host memory used +host_seconds 977.39 # Real time elapsed on the host +host_tick_rate 40914717 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 100633305 # Number of instructions simulated -sim_seconds 0.039892 # Number of seconds simulated -sim_ticks 39891736000 # Number of ticks simulated +sim_insts 100633290 # Number of instructions simulated +sim_seconds 0.039990 # Number of seconds simulated +sim_ticks 39989822000 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 9865367 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 15339513 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 176572 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 830445 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 11914381 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 18227498 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 1851553 # Number of times the RAS was used to get a target. -system.cpu.commit.branchMispredicts 800437 # The number of times a branch was mispredicted -system.cpu.commit.branches 13669912 # Number of branches committed -system.cpu.commit.bw_lim_events 2877364 # number cycles where commit BW limit reached +system.cpu.BPredUnit.BTBHits 9867090 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 15337107 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 176470 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 829676 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 11914855 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 18228284 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 1851579 # Number of times the RAS was used to get a target. +system.cpu.commit.branchMispredicts 800204 # The number of times a branch was mispredicted +system.cpu.commit.branches 13669909 # Number of branches committed +system.cpu.commit.bw_lim_events 2821197 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.commitCommittedInsts 100638857 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 700914 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 13588852 # The number of squashed insts skipped by commit -system.cpu.commit.committed_per_cycle::samples 76617428 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.313524 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.896154 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 100638842 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 700911 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 13587653 # The number of squashed insts skipped by commit +system.cpu.commit.committed_per_cycle::samples 76811336 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.310208 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.890150 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 34018334 44.40% 44.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 22269182 29.07% 73.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 6570057 8.58% 82.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 4759391 6.21% 88.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 3903161 5.09% 93.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1377879 1.80% 95.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 463983 0.61% 95.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 378077 0.49% 96.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2877364 3.76% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 34147257 44.46% 44.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 22326004 29.07% 73.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 6547391 8.52% 82.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4777302 6.22% 88.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 3867270 5.03% 93.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1481997 1.93% 95.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 462917 0.60% 95.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 380001 0.49% 96.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2821197 3.67% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 76617428 # Number of insts commited each cycle -system.cpu.commit.count 100638857 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 76811336 # Number of insts commited each cycle +system.cpu.commit.count 100638842 # Number of instructions committed system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. system.cpu.commit.function_calls 1679850 # Number of function calls committed. -system.cpu.commit.int_insts 91477923 # Number of committed integer instructions. -system.cpu.commit.loads 27308393 # Number of loads committed +system.cpu.commit.int_insts 91477911 # Number of committed integer instructions. +system.cpu.commit.loads 27308390 # Number of loads committed system.cpu.commit.membars 15920 # Number of memory barriers committed -system.cpu.commit.refs 47865415 # Number of memory references committed +system.cpu.commit.refs 47865409 # Number of memory references committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.committedInsts 100633305 # Number of Instructions Simulated -system.cpu.committedInsts_total 100633305 # Number of Instructions Simulated -system.cpu.cpi 0.792814 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.792814 # CPI: Total CPI of All Threads -system.cpu.dcache.LoadLockedReq_accesses 18795 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_avg_miss_latency 13515.151515 # average LoadLockedReq miss latency +system.cpu.committedInsts 100633290 # Number of Instructions Simulated +system.cpu.committedInsts_total 100633290 # Number of Instructions Simulated +system.cpu.cpi 0.794763 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.794763 # CPI: Total CPI of All Threads +system.cpu.dcache.LoadLockedReq_accesses 18794 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_avg_miss_latency 13530.303030 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 35500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_hits 18762 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_miss_latency 446000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_hits 18761 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_miss_latency 446500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_rate 0.001756 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_misses 33 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_mshr_hits 32 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_miss_latency 35500 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.000053 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_misses 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.ReadReq_accesses 26949457 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 22750.430442 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18884.806074 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 26845494 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 2365203000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.003858 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 103963 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 49303 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 1032243500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.002028 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 54660 # number of ReadReq MSHR misses -system.cpu.dcache.StoreCondReq_accesses 17203 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_hits 17203 # number of StoreCondReq hits +system.cpu.dcache.ReadReq_accesses 26968856 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 22747.311569 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18885.481864 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 26864892 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 2364901500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.003855 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 103964 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 49322 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 1031940500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.002026 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 54642 # number of ReadReq MSHR misses +system.cpu.dcache.StoreCondReq_accesses 17200 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits 17200 # number of StoreCondReq hits system.cpu.dcache.WriteReq_accesses 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 32591.489503 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34153.863424 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 18304057 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 50381358500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.077877 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 1545844 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 1438944 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 3651048000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_avg_miss_latency 32625.233627 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34171.269142 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 18304166 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 50429965500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.077871 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 1545735 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 1438836 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 3652874500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.005385 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 106900 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 106899 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 22000 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 279.703475 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 279.850161 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 22000 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 46799358 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 31971.352710 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 28987.939465 # average overall mshr miss latency -system.cpu.dcache.demand_hits 45149551 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 52746561500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.035253 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1649807 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 1488247 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 4683291500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.003452 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 161560 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 46818757 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 32002.727164 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 29000.779988 # average overall mshr miss latency +system.cpu.dcache.demand_hits 45169058 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 52794867000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.035236 # miss rate for demand accesses +system.cpu.dcache.demand_misses 1649699 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 1488158 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 4684815000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.003450 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 161541 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_blocks::0 4075.453819 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.994984 # Average percentage of cache occupancy -system.cpu.dcache.overall_accesses 46799358 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 31971.352710 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 28987.939465 # average overall mshr miss latency +system.cpu.dcache.occ_blocks::0 4075.504214 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.994996 # Average percentage of cache occupancy +system.cpu.dcache.overall_accesses 46818757 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 32002.727164 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 29000.779988 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 45149551 # number of overall hits -system.cpu.dcache.overall_miss_latency 52746561500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.035253 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1649807 # number of overall misses -system.cpu.dcache.overall_mshr_hits 1488247 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 4683291500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.003452 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 161560 # number of overall MSHR misses +system.cpu.dcache.overall_hits 45169058 # number of overall hits +system.cpu.dcache.overall_miss_latency 52794867000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.035236 # miss rate for overall accesses +system.cpu.dcache.overall_misses 1649699 # number of overall misses +system.cpu.dcache.overall_mshr_hits 1488158 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 4684815000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.003450 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 161541 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 157452 # number of replacements -system.cpu.dcache.sampled_refs 161548 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 157437 # number of replacements +system.cpu.dcache.sampled_refs 161533 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4075.453819 # Cycle average of tags in use -system.cpu.dcache.total_refs 45185537 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4075.504214 # Cycle average of tags in use +system.cpu.dcache.total_refs 45205036 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 327416000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 123381 # number of writebacks -system.cpu.decode.BlockedCycles 28767889 # Number of cycles decode is blocked -system.cpu.decode.BranchMispred 93628 # Number of times decode detected a branch misprediction -system.cpu.decode.BranchResolved 3727749 # Number of times decode resolved a branch -system.cpu.decode.DecodedInsts 120621461 # Number of instructions handled by decode -system.cpu.decode.IdleCycles 25476849 # Number of cycles decode is idle -system.cpu.decode.RunCycles 21756774 # Number of cycles decode is running -system.cpu.decode.SquashCycles 2130394 # Number of cycles decode is squashing -system.cpu.decode.SquashedInsts 323992 # Number of squashed instructions handled by decode -system.cpu.decode.UnblockCycles 615915 # Number of cycles decode is unblocking +system.cpu.dcache.writebacks 123374 # number of writebacks +system.cpu.decode.BlockedCycles 28971891 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 93075 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 3727390 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 120629333 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 25465357 # Number of cycles decode is idle +system.cpu.decode.RunCycles 21763410 # Number of cycles decode is running +system.cpu.decode.SquashCycles 2130818 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 323625 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 610677 # Number of cycles decode is unblocking system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -162,243 +162,243 @@ system.cpu.dtb.read_misses 0 # DT system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.fetch.Branches 18227498 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 11770565 # Number of cache lines fetched -system.cpu.fetch.Cycles 22825886 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 173702 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 89192210 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 72 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 899278 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.228462 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 11770565 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 11716920 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.117928 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 78747821 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.567287 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.842624 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.Branches 18228284 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 11769962 # Number of cache lines fetched +system.cpu.fetch.Cycles 22827336 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 173608 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 89202846 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 75 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 898458 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.227912 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 11769962 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 11718669 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.115319 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 78942153 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.563587 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.840250 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 55936810 71.03% 71.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2349634 2.98% 74.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2668515 3.39% 77.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2236984 2.84% 80.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1645406 2.09% 82.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1774436 2.25% 84.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 998371 1.27% 85.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1522539 1.93% 87.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9615126 12.21% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 56129596 71.10% 71.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2349851 2.98% 74.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2666538 3.38% 77.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2237184 2.83% 80.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1644999 2.08% 82.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1777059 2.25% 84.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 999675 1.27% 85.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1522909 1.93% 87.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9614342 12.18% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 78747821 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 78942153 # Number of instructions fetched each cycle (Total) system.cpu.fp_regfile_reads 90 # number of floating regfile reads system.cpu.fp_regfile_writes 71 # number of floating regfile writes -system.cpu.icache.ReadReq_accesses 11770565 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 12757.129371 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 9282.013745 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 11745142 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 324324500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.002160 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 25423 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 832 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 228254000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.002089 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 24591 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 11769962 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 12766.812347 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 9293.910530 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 11744564 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 324251500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.002158 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 25398 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 831 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 228323500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.002087 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 24567 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 477.833279 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 478.218331 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 11770565 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 12757.129371 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 9282.013745 # average overall mshr miss latency -system.cpu.icache.demand_hits 11745142 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 324324500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.002160 # miss rate for demand accesses -system.cpu.icache.demand_misses 25423 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 832 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 228254000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.002089 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 24591 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 11769962 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 12766.812347 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 9293.910530 # average overall mshr miss latency +system.cpu.icache.demand_hits 11744564 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 324251500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.002158 # miss rate for demand accesses +system.cpu.icache.demand_misses 25398 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 831 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 228323500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.002087 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 24567 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_blocks::0 1793.424749 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.875696 # Average percentage of cache occupancy -system.cpu.icache.overall_accesses 11770565 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 12757.129371 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 9282.013745 # average overall mshr miss latency +system.cpu.icache.occ_blocks::0 1794.323879 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.876135 # Average percentage of cache occupancy +system.cpu.icache.overall_accesses 11769962 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 12766.812347 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 9293.910530 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 11745142 # number of overall hits -system.cpu.icache.overall_miss_latency 324324500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.002160 # miss rate for overall accesses -system.cpu.icache.overall_misses 25423 # number of overall misses -system.cpu.icache.overall_mshr_hits 832 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 228254000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.002089 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 24591 # number of overall MSHR misses +system.cpu.icache.overall_hits 11744564 # number of overall hits +system.cpu.icache.overall_miss_latency 324251500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.002158 # miss rate for overall accesses +system.cpu.icache.overall_misses 25398 # number of overall misses +system.cpu.icache.overall_mshr_hits 831 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 228323500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.002087 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 24567 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 22549 # number of replacements -system.cpu.icache.sampled_refs 24580 # Sample count of references to valid blocks. +system.cpu.icache.replacements 22528 # number of replacements +system.cpu.icache.sampled_refs 24559 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1793.424749 # Cycle average of tags in use -system.cpu.icache.total_refs 11745142 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1794.323879 # Cycle average of tags in use +system.cpu.icache.total_refs 11744564 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 1035652 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.branchMispredicts 874742 # Number of branch mispredicts detected at execute -system.cpu.iew.exec_branches 14732348 # Number of branches executed -system.cpu.iew.exec_nop 77233 # number of nop insts executed -system.cpu.iew.exec_rate 1.323750 # Inst execution rate -system.cpu.iew.exec_refs 49299625 # number of memory reference insts executed -system.cpu.iew.exec_stores 21011299 # Number of stores executed +system.cpu.idleCycles 1037492 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 874393 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 14730992 # Number of branches executed +system.cpu.iew.exec_nop 77229 # number of nop insts executed +system.cpu.iew.exec_rate 1.320506 # Inst execution rate +system.cpu.iew.exec_refs 49310444 # number of memory reference insts executed +system.cpu.iew.exec_stores 21021544 # Number of stores executed system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.iewBlockCycles 976865 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 29744817 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 738677 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 687790 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 22207815 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 114301833 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 28288326 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 931089 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 105613393 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 6026 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewBlockCycles 976883 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 29736331 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 738487 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 690502 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 22216200 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 114300611 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 28288900 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 942660 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 105613612 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 6120 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 6915 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 2130394 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 55938 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 6972 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 2130818 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 56086 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.cacheBlocked 7 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread0.forwLoads 1108085 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.ignoredResponses 2818 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.forwLoads 1088745 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 2833 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.memOrderViolation 8523 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.memOrderViolation 8497 # Number of memory ordering violations system.cpu.iew.lsq.thread0.rescheduledLoads 41 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.squashedLoads 2436412 # Number of loads squashed -system.cpu.iew.lsq.thread0.squashedStores 1650781 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 8523 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 227397 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 647345 # Number of branches that were predicted taken incorrectly -system.cpu.iew.wb_consumers 107738460 # num instructions consuming a value -system.cpu.iew.wb_count 105037825 # cumulative count of insts written-back -system.cpu.iew.wb_fanout 0.490563 # average fanout of values written-back +system.cpu.iew.lsq.thread0.squashedLoads 2427929 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 1659169 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 8497 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 227081 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 647312 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 107769064 # num instructions consuming a value +system.cpu.iew.wb_count 105038909 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.490744 # average fanout of values written-back system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.wb_producers 52852456 # num instructions producing a value -system.cpu.iew.wb_rate 1.316536 # insts written-back per cycle -system.cpu.iew.wb_sent 105209239 # cumulative count of insts sent to commit -system.cpu.int_regfile_reads 252839831 # number of integer regfile reads -system.cpu.int_regfile_writes 78127703 # number of integer regfile writes -system.cpu.ipc 1.261330 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.261330 # IPC: Total IPC of All Threads +system.cpu.iew.wb_producers 52886985 # num instructions producing a value +system.cpu.iew.wb_rate 1.313321 # insts written-back per cycle +system.cpu.iew.wb_sent 105210613 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 252852862 # number of integer regfile reads +system.cpu.int_regfile_writes 78118633 # number of integer regfile writes +system.cpu.ipc 1.258236 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.258236 # IPC: Total IPC of All Threads system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 56712642 53.23% 53.23% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 95301 0.09% 53.32% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 53.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 11 0.00% 53.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 53.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 53.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 53.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 53.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 53.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 1 0.00% 53.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 53.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 53.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 53.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 53.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 53.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 53.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 53.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 53.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 53.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 53.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 53.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 53.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 53.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 53.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 53.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 8 0.00% 53.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 53.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 53.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 53.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 28583241 26.83% 80.15% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21153285 19.85% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 56704676 53.22% 53.22% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 95260 0.09% 53.31% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 53.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 10 0.00% 53.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 53.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 53.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 53.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 53.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 53.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 1 0.00% 53.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 53.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 53.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 53.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 53.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 53.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 53.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 53.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 53.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 53.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 53.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 53.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 53.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 53.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 53.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 53.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 8 0.00% 53.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 53.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 53.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 53.31% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 28589913 26.83% 80.14% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21166411 19.86% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 106544489 # Type of FU issued -system.cpu.iq.fp_alu_accesses 82 # Number of floating point alu accesses -system.cpu.iq.fp_inst_queue_reads 160 # Number of floating instruction queue reads +system.cpu.iq.FU_type_0::total 106556279 # Type of FU issued +system.cpu.iq.fp_alu_accesses 81 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 158 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_wakeup_accesses 68 # Number of floating instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_writes 144 # Number of floating instruction queue writes -system.cpu.iq.fu_busy_cnt 1792992 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.016829 # FU busy rate (busy events/executed inst) +system.cpu.iq.fp_inst_queue_writes 142 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 1839661 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.017265 # FU busy rate (busy events/executed inst) system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 49061 2.74% 2.74% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 2.74% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.74% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.74% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.74% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.74% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.74% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.74% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.74% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1439096 80.26% 83.00% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 304835 17.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 48521 2.64% 2.64% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 2.64% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.64% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1487460 80.86% 83.49% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 303680 16.51% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.int_alu_accesses 108337399 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 293735316 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 105037757 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 127630070 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 113468820 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 106544489 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 755780 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 13400232 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 105692 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 54866 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 21923544 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.issued_per_cycle::samples 78747821 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.352983 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.550711 # Number of insts issued each cycle +system.cpu.iq.int_alu_accesses 108395859 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 294001111 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 105038841 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 127626959 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 113467798 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 106556279 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 755584 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 13398397 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 106904 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 54673 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 21906182 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 78942153 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.349802 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.549470 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 30449549 38.67% 38.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 20272773 25.74% 64.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 12837785 16.30% 80.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6496976 8.25% 88.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4874072 6.19% 95.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2197331 2.79% 97.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 925872 1.18% 99.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 480661 0.61% 99.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 212802 0.27% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 30593123 38.75% 38.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 20374659 25.81% 64.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 12756017 16.16% 80.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6534002 8.28% 89.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4851612 6.15% 95.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2240036 2.84% 97.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 902250 1.14% 99.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 476180 0.60% 99.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 214274 0.27% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 78747821 # Number of insts issued each cycle -system.cpu.iq.rate 1.335421 # Inst issue rate +system.cpu.iq.issued_per_cycle::total 78942153 # Number of insts issued each cycle +system.cpu.iq.rate 1.332292 # Inst issue rate system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -420,115 +420,115 @@ system.cpu.itb.read_misses 0 # DT system.cpu.itb.write_accesses 0 # DTB write accesses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses 106889 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34386.744639 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31232.309942 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits 4289 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 3528080000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.959874 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 102600 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 3204435000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.959874 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 102600 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 79238 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34336.176999 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31108.810299 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 46944 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1108852500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.407557 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_accesses 106892 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34401.384977 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31241.713044 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_hits 4291 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 3529616500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.959857 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 102601 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 3205431000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.959857 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 102601 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 79200 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34336.641481 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31108.469055 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 46906 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1108867500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.407753 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 32294 # number of ReadReq misses system.cpu.l2cache.ReadReq_mshr_hits 59 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_miss_latency 1002792500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.406812 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1002781500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.407008 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 32235 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 12 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses 8 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_hits 4 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_miss_rate 0.666667 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 8 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 248000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.666667 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 8 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 123381 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 123381 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_miss_rate 0.500000 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 4 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 124000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.500000 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 4 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 123374 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 123374 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.515289 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.514918 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 186127 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34374.638605 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31202.784885 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 51233 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 4636932500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.724742 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 134894 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 186092 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34385.885318 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31209.858643 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 51197 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 4638484000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.724883 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 134895 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 59 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 4207227500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.724425 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 134835 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 4208212500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.724566 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 134836 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_blocks::0 2296.436358 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 16005.968558 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.070082 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.488463 # Average percentage of cache occupancy -system.cpu.l2cache.overall_accesses 186127 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34374.638605 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31202.784885 # average overall mshr miss latency +system.cpu.l2cache.occ_blocks::0 2298.143473 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 16005.861783 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.070134 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.488460 # Average percentage of cache occupancy +system.cpu.l2cache.overall_accesses 186092 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34385.885318 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31209.858643 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 51233 # number of overall hits -system.cpu.l2cache.overall_miss_latency 4636932500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.724742 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 134894 # number of overall misses +system.cpu.l2cache.overall_hits 51197 # number of overall hits +system.cpu.l2cache.overall_miss_latency 4638484000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.724883 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 134895 # number of overall misses system.cpu.l2cache.overall_mshr_hits 59 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 4207227500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.724425 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 134835 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 4208212500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.724566 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 134836 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 114581 # number of replacements -system.cpu.l2cache.sampled_refs 133428 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 114587 # number of replacements +system.cpu.l2cache.sampled_refs 133431 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 18302.404916 # Cycle average of tags in use -system.cpu.l2cache.total_refs 68754 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 18304.005255 # Cycle average of tags in use +system.cpu.l2cache.total_refs 68706 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 88457 # number of writebacks -system.cpu.memDep0.conflictingLoads 15454792 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 13946617 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 29744817 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 22207815 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 146355254 # number of misc regfile reads -system.cpu.misc_regfile_writes 34408 # number of misc regfile writes -system.cpu.numCycles 79783473 # number of cpu cycles simulated +system.cpu.l2cache.writebacks 88458 # number of writebacks +system.cpu.memDep0.conflictingLoads 15829057 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 13995589 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 29736331 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 22216200 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 146370110 # number of misc regfile reads +system.cpu.misc_regfile_writes 34402 # number of misc regfile writes +system.cpu.numCycles 79979645 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.BlockCycles 2921057 # Number of cycles rename is blocking -system.cpu.rename.CommittedMaps 75878617 # Number of HB maps that are committed -system.cpu.rename.IQFullEvents 205954 # Number of times rename has blocked due to IQ full -system.cpu.rename.IdleCycles 27124909 # Number of cycles rename is idle -system.cpu.rename.LSQFullEvents 2993782 # Number of times rename has blocked due to LSQ full +system.cpu.rename.BlockCycles 2934776 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 75878602 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 208173 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 27131253 # Number of cycles rename is idle +system.cpu.rename.LSQFullEvents 3054544 # Number of times rename has blocked due to LSQ full system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full -system.cpu.rename.RenameLookups 315599119 # Number of register rename lookups that rename has made -system.cpu.rename.RenamedInsts 118180992 # Number of instructions processed by rename -system.cpu.rename.RenamedOperands 90551096 # Number of destination operands rename has renamed -system.cpu.rename.RunCycles 20607135 # Number of cycles rename is running -system.cpu.rename.SquashCycles 2130394 # Number of cycles rename is squashing -system.cpu.rename.UnblockCycles 4279204 # Number of cycles rename is unblocking -system.cpu.rename.UndoneMaps 14672443 # Number of HB maps that are undone due to squashing -system.cpu.rename.fp_rename_lookups 83429 # Number of floating rename lookups -system.cpu.rename.int_rename_lookups 315515690 # Number of integer rename lookups -system.cpu.rename.serializeStallCycles 21685122 # count of cycles rename stalled for serializing inst -system.cpu.rename.serializingInsts 759000 # count of serializing insts renamed -system.cpu.rename.skidInsts 12013897 # count of insts added to the skid buffer -system.cpu.rename.tempSerializingInsts 759711 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 187942474 # The number of ROB reads -system.cpu.rob.rob_writes 230588533 # The number of ROB writes -system.cpu.timesIdled 60808 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RenameLookups 315617756 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 118187842 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 90561212 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 20595374 # Number of cycles rename is running +system.cpu.rename.SquashCycles 2130818 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 4332267 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 14682574 # Number of HB maps that are undone due to squashing +system.cpu.rename.fp_rename_lookups 83434 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 315534322 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 21817665 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 758712 # count of serializing insts renamed +system.cpu.rename.skidInsts 12129084 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 759493 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 188191335 # The number of ROB reads +system.cpu.rob.rob_writes 230586603 # The number of ROB writes +system.cpu.timesIdled 60768 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.num_syscalls 1946 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini b/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini index 15faea73a..98cead180 100644 --- a/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini @@ -498,7 +498,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/twolf +executable=/chips/pd/randd/dist/cpu2000/binaries/x86/linux/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/simout b/tests/long/70.twolf/ref/x86/linux/o3-timing/simout index 5be7bed53..1b4fcdc8a 100755 --- a/tests/long/70.twolf/ref/x86/linux/o3-timing/simout +++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2011 13:30:37 -M5 started Apr 21 2011 13:53:57 -M5 executing on maize +M5 compiled May 1 2011 16:48:51 +M5 started May 1 2011 16:48:54 +M5 executing on u200439-lin.austin.arm.com command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing/smred.sav Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing/smred.sv2 @@ -28,4 +28,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 106785381000 because target called exit() +122 123 124 Exiting @ tick 106659390000 because target called exit() diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt index e5f49060a..176877f02 100644 --- a/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,45 +1,45 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 120975 # Simulator instruction rate (inst/s) -host_mem_usage 223752 # Number of bytes of host memory used -host_seconds 1829.83 # Real time elapsed on the host -host_tick_rate 58358040 # Simulator tick rate (ticks/s) +host_inst_rate 88999 # Simulator instruction rate (inst/s) +host_mem_usage 265284 # Number of bytes of host memory used +host_seconds 2487.25 # Real time elapsed on the host +host_tick_rate 42882469 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 221363017 # Number of instructions simulated -sim_seconds 0.106785 # Number of seconds simulated -sim_ticks 106785381000 # Number of ticks simulated +sim_seconds 0.106659 # Number of seconds simulated +sim_ticks 106659390000 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 19602584 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 22433110 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 19559071 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 22388883 # Number of BTB lookups system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 3071588 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 25075434 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 25075434 # Number of BP lookups +system.cpu.BPredUnit.condIncorrect 3071862 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 25034838 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 25034838 # Number of BP lookups system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -system.cpu.commit.branchMispredicts 3071621 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 3071894 # The number of times a branch was mispredicted system.cpu.commit.branches 12326943 # Number of branches committed -system.cpu.commit.bw_lim_events 2318001 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 2350531 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.commitCommittedInsts 221363017 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 1246 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 174370767 # The number of squashed insts skipped by commit -system.cpu.commit.committed_per_cycle::samples 190318905 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.163116 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.516800 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 173965235 # The number of squashed insts skipped by commit +system.cpu.commit.committed_per_cycle::samples 190108496 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.164404 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.519902 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 74095187 38.93% 38.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 71171116 37.40% 76.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 18278998 9.60% 85.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 12739096 6.69% 92.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 5868968 3.08% 95.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2789277 1.47% 97.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1957482 1.03% 98.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1100780 0.58% 98.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2318001 1.22% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 74006380 38.93% 38.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 71095556 37.40% 76.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 18250817 9.60% 85.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 12666090 6.66% 92.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 5885570 3.10% 95.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2802504 1.47% 97.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1948827 1.03% 98.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1102221 0.58% 98.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2350531 1.24% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 190318905 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 190108496 # Number of insts commited each cycle system.cpu.commit.count 221363017 # Number of instructions committed system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. @@ -50,337 +50,337 @@ system.cpu.commit.refs 77165306 # Nu system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.committedInsts 221363017 # Number of Instructions Simulated system.cpu.committedInsts_total 221363017 # Number of Instructions Simulated -system.cpu.cpi 0.964799 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.964799 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 50490336 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 33183.118741 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34227.979275 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 50489637 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 23195000 # number of ReadReq miss cycles +system.cpu.cpi 0.963660 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.963660 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 50560876 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 33172.166428 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34228.682171 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 50560179 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 23121000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000014 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 699 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 313 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 13212000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_misses 697 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 310 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 13246500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000008 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 386 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses 387 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 20515730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 26460.898971 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35474.187380 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 26488.657179 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35473.248408 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 20508633 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 187793000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 187990000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.000346 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 7097 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 5528 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 55659000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000076 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 1569 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_hits 5527 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 55693000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.000077 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 1570 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 36353.441884 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 36352.334527 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 71006066 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 27063.622370 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 35228.132992 # average overall mshr miss latency -system.cpu.dcache.demand_hits 70998270 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 210988000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_accesses 71076606 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 27086.348473 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 35227.133367 # average overall mshr miss latency +system.cpu.dcache.demand_hits 71068812 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 211111000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000110 # miss rate for demand accesses -system.cpu.dcache.demand_misses 7796 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 5841 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 68871000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_misses 7794 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 5837 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 68939500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000028 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 1955 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 1957 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_blocks::0 1398.546932 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.341442 # Average percentage of cache occupancy -system.cpu.dcache.overall_accesses 71006066 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 27063.622370 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 35228.132992 # average overall mshr miss latency +system.cpu.dcache.occ_blocks::0 1400.398145 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.341894 # Average percentage of cache occupancy +system.cpu.dcache.overall_accesses 71076606 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 27086.348473 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 35227.133367 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 70998270 # number of overall hits -system.cpu.dcache.overall_miss_latency 210988000 # number of overall miss cycles +system.cpu.dcache.overall_hits 71068812 # number of overall hits +system.cpu.dcache.overall_miss_latency 211111000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000110 # miss rate for overall accesses -system.cpu.dcache.overall_misses 7796 # number of overall misses -system.cpu.dcache.overall_mshr_hits 5841 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 68871000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_misses 7794 # number of overall misses +system.cpu.dcache.overall_mshr_hits 5837 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 68939500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000028 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 1955 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 1957 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 48 # number of replacements -system.cpu.dcache.sampled_refs 1953 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 1955 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1398.546932 # Cycle average of tags in use -system.cpu.dcache.total_refs 70998272 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 1400.398145 # Cycle average of tags in use +system.cpu.dcache.total_refs 71068814 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 10 # number of writebacks -system.cpu.decode.BlockedCycles 57112679 # Number of cycles decode is blocked -system.cpu.decode.DecodedInsts 420105654 # Number of instructions handled by decode -system.cpu.decode.IdleCycles 67048451 # Number of cycles decode is idle -system.cpu.decode.RunCycles 60385094 # Number of cycles decode is running -system.cpu.decode.SquashCycles 23161998 # Number of cycles decode is squashing -system.cpu.decode.UnblockCycles 5772681 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 25075434 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 27531173 # Number of cache lines fetched -system.cpu.fetch.Cycles 69569563 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 448608 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 261554963 # Number of instructions fetch has processed +system.cpu.decode.BlockedCycles 57002752 # Number of cycles decode is blocked +system.cpu.decode.DecodedInsts 419872535 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 66995296 # Number of cycles decode is idle +system.cpu.decode.RunCycles 60323444 # Number of cycles decode is running +system.cpu.decode.SquashCycles 23120513 # Number of cycles decode is squashing +system.cpu.decode.UnblockCycles 5787004 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 25034838 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 27511716 # Number of cache lines fetched +system.cpu.fetch.Cycles 69512577 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 449654 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 261443886 # Number of instructions fetch has processed system.cpu.fetch.MiscStallCycles 62 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 3099299 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.117410 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 27531173 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 19602584 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.224676 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 213480903 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.014170 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.226415 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.SquashCycles 3099669 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.117359 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 27511716 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 19559071 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.225602 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 213229009 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.015146 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.226933 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 145760613 68.28% 68.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3769966 1.77% 70.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 3155448 1.48% 71.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 4279066 2.00% 73.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4652490 2.18% 75.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4411215 2.07% 77.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5002306 2.34% 80.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3209548 1.50% 81.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 39240251 18.38% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 145563800 68.27% 68.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3763912 1.77% 70.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 3143749 1.47% 71.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 4274487 2.00% 73.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4655568 2.18% 75.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4407393 2.07% 77.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4998818 2.34% 80.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3209647 1.51% 81.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 39211635 18.39% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 213480903 # Number of instructions fetched each cycle (Total) -system.cpu.fp_regfile_reads 3511578 # number of floating regfile reads -system.cpu.fp_regfile_writes 2187329 # number of floating regfile writes -system.cpu.icache.ReadReq_accesses 27531173 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 25557.221784 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 22462.481426 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 27524838 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 161905000 # number of ReadReq miss cycles +system.cpu.fetch.rateDist::total 213229009 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 3514377 # number of floating regfile reads +system.cpu.fp_regfile_writes 2187528 # number of floating regfile writes +system.cpu.icache.ReadReq_accesses 27511716 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 25569.940006 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 22464.790041 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 27505382 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 161960000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000230 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 6335 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 951 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 120938000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_misses 6334 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 952 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 120905500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000196 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 5384 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses 5382 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 5114.239688 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 5112.524535 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 27531173 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 25557.221784 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 22462.481426 # average overall mshr miss latency -system.cpu.icache.demand_hits 27524838 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 161905000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_accesses 27511716 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 25569.940006 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 22464.790041 # average overall mshr miss latency +system.cpu.icache.demand_hits 27505382 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 161960000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000230 # miss rate for demand accesses -system.cpu.icache.demand_misses 6335 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 951 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 120938000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_misses 6334 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 952 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 120905500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000196 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 5384 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 5382 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_blocks::0 1605.721886 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.784044 # Average percentage of cache occupancy -system.cpu.icache.overall_accesses 27531173 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 25557.221784 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 22462.481426 # average overall mshr miss latency +system.cpu.icache.occ_blocks::0 1605.599338 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.783984 # Average percentage of cache occupancy +system.cpu.icache.overall_accesses 27511716 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 25569.940006 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 22464.790041 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 27524838 # number of overall hits -system.cpu.icache.overall_miss_latency 161905000 # number of overall miss cycles +system.cpu.icache.overall_hits 27505382 # number of overall hits +system.cpu.icache.overall_miss_latency 161960000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000230 # miss rate for overall accesses -system.cpu.icache.overall_misses 6335 # number of overall misses -system.cpu.icache.overall_mshr_hits 951 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 120938000 # number of overall MSHR miss cycles +system.cpu.icache.overall_misses 6334 # number of overall misses +system.cpu.icache.overall_mshr_hits 952 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 120905500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000196 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 5384 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 5382 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 3426 # number of replacements -system.cpu.icache.sampled_refs 5382 # Sample count of references to valid blocks. +system.cpu.icache.replacements 3421 # number of replacements +system.cpu.icache.sampled_refs 5380 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1605.721886 # Cycle average of tags in use -system.cpu.icache.total_refs 27524838 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1605.599338 # Cycle average of tags in use +system.cpu.icache.total_refs 27505382 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 89860 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.branchMispredicts 3274274 # Number of branch mispredicts detected at execute -system.cpu.iew.exec_branches 15858881 # Number of branches executed +system.cpu.idleCycles 89772 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 3285583 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 15876599 # Number of branches executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_rate 1.303230 # Inst execution rate -system.cpu.iew.exec_refs 90240962 # number of memory reference insts executed -system.cpu.iew.exec_stores 23196856 # Number of stores executed +system.cpu.iew.exec_rate 1.304758 # Inst execution rate +system.cpu.iew.exec_refs 90277406 # number of memory reference insts executed +system.cpu.iew.exec_stores 23169669 # Number of stores executed system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.iewBlockCycles 536838 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 104995800 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 1427 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 231101 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 37116725 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 395719031 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 67044106 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3514925 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 278331746 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 453294 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewBlockCycles 535171 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 104943598 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 1424 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 227523 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 37082263 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 395310289 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 67107737 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3518032 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 278329468 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 451527 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 13026 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 23161998 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 523918 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 13065 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 23120513 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 520097 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread0.forwLoads 16343714 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.ignoredResponses 20445 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.forwLoads 16336525 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 15761 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.memOrderViolation 35659 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.rescheduledLoads 45746 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.squashedLoads 48346210 # Number of loads squashed -system.cpu.iew.lsq.thread0.squashedStores 16601009 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 35659 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 741660 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 2532614 # Number of branches that were predicted taken incorrectly -system.cpu.iew.wb_consumers 371845968 # num instructions consuming a value -system.cpu.iew.wb_count 275965139 # cumulative count of insts written-back -system.cpu.iew.wb_fanout 0.599241 # average fanout of values written-back +system.cpu.iew.lsq.thread0.memOrderViolation 34193 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 46033 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 48294008 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 16566547 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 34193 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 745041 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 2540542 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 371832293 # num instructions consuming a value +system.cpu.iew.wb_count 275994943 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.599268 # average fanout of values written-back system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.wb_producers 222825226 # num instructions producing a value -system.cpu.iew.wb_rate 1.292148 # insts written-back per cycle -system.cpu.iew.wb_sent 277010234 # cumulative count of insts sent to commit -system.cpu.int_regfile_reads 516469209 # number of integer regfile reads -system.cpu.int_regfile_writes 283974364 # number of integer regfile writes -system.cpu.ipc 1.036486 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.036486 # IPC: Total IPC of All Threads -system.cpu.iq.FU_type_0::No_OpClass 1200408 0.43% 0.43% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 187079024 66.38% 66.80% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.80% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.80% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1589764 0.56% 67.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 68461114 24.29% 91.66% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 23516361 8.34% 100.00% # Type of FU issued +system.cpu.iew.wb_producers 222827233 # num instructions producing a value +system.cpu.iew.wb_rate 1.293815 # insts written-back per cycle +system.cpu.iew.wb_sent 277038754 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 516581259 # number of integer regfile reads +system.cpu.int_regfile_writes 284038520 # number of integer regfile writes +system.cpu.ipc 1.037710 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.037710 # IPC: Total IPC of All Threads +system.cpu.iq.FU_type_0::No_OpClass 1197054 0.42% 0.42% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 187021337 66.36% 66.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1590291 0.56% 67.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.34% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 68531630 24.32% 91.66% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 23507188 8.34% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 281846671 # Type of FU issued -system.cpu.iq.fp_alu_accesses 2636909 # Number of floating point alu accesses -system.cpu.iq.fp_inst_queue_reads 5233833 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_wakeup_accesses 2531388 # Number of floating instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_writes 5663526 # Number of floating instruction queue writes -system.cpu.iq.fu_busy_cnt 2813875 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.009984 # FU busy rate (busy events/executed inst) +system.cpu.iq.FU_type_0::total 281847500 # Type of FU issued +system.cpu.iq.fp_alu_accesses 2638444 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 5236518 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 2534154 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 5693561 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 2791850 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.009906 # FU busy rate (busy events/executed inst) system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 68222 2.42% 2.42% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2379596 84.57% 86.99% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 366057 13.01% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 67290 2.41% 2.41% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 2.41% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.41% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2359047 84.50% 86.91% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 365513 13.09% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.int_alu_accesses 280823229 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 774810101 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 273433751 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 564126820 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 395717604 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 281846671 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 1427 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 174039946 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 55814 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 181 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 358439815 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.issued_per_cycle::samples 213480903 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.320243 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.372505 # Number of insts issued each cycle +system.cpu.iq.int_alu_accesses 280803852 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 774570053 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 273460789 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 563268520 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 395308865 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 281847500 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 1424 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 173620640 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 90712 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 178 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 357064626 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 213229009 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.321807 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.374231 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 72600816 34.01% 34.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 65586069 30.72% 64.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 36613512 17.15% 81.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 20576315 9.64% 91.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12054901 5.65% 97.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3944773 1.85% 99.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1483005 0.69% 99.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 508962 0.24% 99.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 112550 0.05% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 72462076 33.98% 33.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 65441995 30.69% 64.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 36667606 17.20% 81.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 20567003 9.65% 91.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 11965683 5.61% 97.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3990809 1.87% 99.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1502036 0.70% 99.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 514117 0.24% 99.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 117684 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 213480903 # Number of insts issued each cycle -system.cpu.iq.rate 1.319688 # Inst issue rate -system.cpu.l2cache.ReadExReq_accesses 1567 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34548.046124 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31351.697630 # average ReadExReq mshr miss latency +system.cpu.iq.issued_per_cycle::total 213229009 # Number of insts issued each cycle +system.cpu.iq.rate 1.321250 # Inst issue rate +system.cpu.l2cache.ReadExReq_accesses 1568 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34547.695262 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31351.472471 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_hits 6 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 53929500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.996171 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 1561 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 48940000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.996171 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 1561 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 5768 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34292.872747 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31042.872747 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 2106 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 125580500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.634882 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_latency 53963500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.996173 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 1562 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 48971000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.996173 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 1562 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 5767 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34290.551611 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31042.326597 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 2105 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 125572000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.634992 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 3662 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 113679000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.634882 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_latency 113677000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.634992 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 3662 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 2 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency @@ -393,81 +393,82 @@ system.cpu.l2cache.Writeback_accesses 10 # nu system.cpu.l2cache.Writeback_hits 10 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.574468 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.574195 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 7335 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34369.136512 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31135.171357 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 2112 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 179510000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.712065 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 5223 # number of demand (read+write) misses +system.cpu.l2cache.demand_avg_miss_latency 34367.438744 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31134.762634 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 2111 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 179535500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.712202 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 5224 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 162619000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.712065 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 5223 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 162648000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.712202 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 5224 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_blocks::0 2429.985932 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 1.014854 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.074157 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 2429.722700 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 1.014710 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.074149 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::1 0.000031 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 7335 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34369.136512 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31135.171357 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 34367.438744 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31134.762634 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 2112 # number of overall hits -system.cpu.l2cache.overall_miss_latency 179510000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.712065 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 5223 # number of overall misses +system.cpu.l2cache.overall_hits 2111 # number of overall hits +system.cpu.l2cache.overall_miss_latency 179535500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.712202 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 5224 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 162619000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.712065 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 5223 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 162648000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.712202 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 5224 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 3666 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 2431.000786 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2106 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 2430.737411 # Cycle average of tags in use +system.cpu.l2cache.total_refs 2105 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.memDep0.conflictingLoads 90499072 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 30541649 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 104995800 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 37116725 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 145140832 # number of misc regfile reads +system.cpu.memDep0.conflictingLoads 90595235 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 30370608 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 104943598 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 37082263 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 145181965 # number of misc regfile reads system.cpu.misc_regfile_writes 844 # number of misc regfile writes -system.cpu.numCycles 213570763 # number of cpu cycles simulated +system.cpu.numCycles 213318781 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.BlockCycles 18060003 # Number of cycles rename is blocking +system.cpu.rename.BlockCycles 18031749 # Number of cycles rename is blocking system.cpu.rename.CommittedMaps 234363409 # Number of HB maps that are committed -system.cpu.rename.IQFullEvents 21564374 # Number of times rename has blocked due to IQ full -system.cpu.rename.IdleCycles 74887260 # Number of cycles rename is idle -system.cpu.rename.LSQFullEvents 16382604 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenameLookups 1054491347 # Number of register rename lookups that rename has made -system.cpu.rename.RenamedInsts 409882715 # Number of instructions processed by rename -system.cpu.rename.RenamedOperands 430914543 # Number of destination operands rename has renamed -system.cpu.rename.RunCycles 57380379 # Number of cycles rename is running -system.cpu.rename.SquashCycles 23161998 # Number of cycles rename is squashing -system.cpu.rename.UnblockCycles 39968831 # Number of cycles rename is unblocking -system.cpu.rename.UndoneMaps 196551134 # Number of HB maps that are undone due to squashing -system.cpu.rename.fp_rename_lookups 11087102 # Number of floating rename lookups -system.cpu.rename.int_rename_lookups 1043404245 # Number of integer rename lookups -system.cpu.rename.serializeStallCycles 22432 # count of cycles rename stalled for serializing inst -system.cpu.rename.serializingInsts 1444 # count of serializing insts renamed -system.cpu.rename.skidInsts 83221554 # count of insts added to the skid buffer -system.cpu.rename.tempSerializingInsts 1312 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 583734688 # The number of ROB reads -system.cpu.rob.rob_writes 814640460 # The number of ROB writes -system.cpu.timesIdled 1934 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.IQFullEvents 21548402 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 74813235 # Number of cycles rename is idle +system.cpu.rename.LSQFullEvents 16345466 # Number of times rename has blocked due to LSQ full +system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 1053910938 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 409668647 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 430592677 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 57355298 # Number of cycles rename is running +system.cpu.rename.SquashCycles 23120513 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 39885814 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 196229268 # Number of HB maps that are undone due to squashing +system.cpu.rename.fp_rename_lookups 11151271 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 1042759667 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 22400 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 1440 # count of serializing insts renamed +system.cpu.rename.skidInsts 83004304 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 1309 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 583086217 # The number of ROB reads +system.cpu.rob.rob_writes 813789002 # The number of ROB writes +system.cpu.timesIdled 1930 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.num_syscalls 400 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini index fa239be0f..22389fff7 100644 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini @@ -11,7 +11,7 @@ children=bridge cpu diskmem intrctrl iobus iocache l2c membus physmem realview t boot_cpu_frequency=500 boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB slram=slram0,0x8000000,+0x8000000 mtdparts=slram0:- root=/dev/mtdblock0 init_param=0 -kernel=/dist/m5/system/binaries/vmlinux.arm +kernel=/chips/pd/randd/dist/binaries/vmlinux.arm load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=atomic @@ -169,7 +169,7 @@ type=ExeTracer [system.diskmem] type=PhysicalMemory -file=/dist/m5/system/disks/ael-arm.ext2 +file=/chips/pd/randd/dist/disks/ael-arm.ext2 latency=30000 latency_var=0 null=false diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout index b43a524ba..6553d17c6 100755 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 19 2011 13:41:05 -M5 started Apr 19 2011 13:41:08 -M5 executing on maize +M5 compiled May 1 2011 21:51:08 +M5 started May 1 2011 21:51:14 +M5 executing on u200439-lin.austin.arm.com command line: build/ARM_FS/m5.fast -d build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-atomic -re tests/run.py build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-atomic Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux.arm +info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux.arm info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 26405524500 because m5_exit instruction encountered +Exiting @ tick 26341084000 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index 1d1cbe8c6..9bbce3daa 100644 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -1,63 +1,63 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 3981428 # Simulator instruction rate (inst/s) -host_mem_usage 333640 # Number of bytes of host memory used -host_seconds 13.09 # Real time elapsed on the host -host_tick_rate 2017840381 # Simulator tick rate (ticks/s) +host_inst_rate 1460315 # Simulator instruction rate (inst/s) +host_mem_usage 380976 # Number of bytes of host memory used +host_seconds 35.59 # Real time elapsed on the host +host_tick_rate 740141754 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 52100192 # Number of instructions simulated -sim_seconds 0.026406 # Number of seconds simulated -sim_ticks 26405524500 # Number of ticks simulated -system.cpu.dcache.LoadLockedReq_accesses::0 100461 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 100461 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_hits::0 95296 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 95296 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_miss_rate::0 0.051413 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_misses::0 5165 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 5165 # number of LoadLockedReq misses -system.cpu.dcache.ReadReq_accesses::0 7831528 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 7831528 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_hits::0 7594963 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7594963 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_rate::0 0.030207 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses::0 236565 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 236565 # number of ReadReq misses -system.cpu.dcache.StoreCondReq_accesses::0 100460 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 100460 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_hits::0 100460 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 100460 # number of StoreCondReq hits -system.cpu.dcache.WriteReq_accesses::0 6676897 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6676897 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_hits::0 6504656 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6504656 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_rate::0 0.025797 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses::0 172241 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 172241 # number of WriteReq misses +sim_insts 51971087 # Number of instructions simulated +sim_seconds 0.026341 # Number of seconds simulated +sim_ticks 26341084000 # Number of ticks simulated +system.cpu.dcache.LoadLockedReq_accesses::0 100443 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 100443 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_hits::0 95328 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 95328 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_miss_rate::0 0.050924 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_misses::0 5115 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 5115 # number of LoadLockedReq misses +system.cpu.dcache.ReadReq_accesses::0 7807332 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 7807332 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_hits::0 7570991 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7570991 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_rate::0 0.030272 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses::0 236341 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 236341 # number of ReadReq misses +system.cpu.dcache.StoreCondReq_accesses::0 100442 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 100442 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits::0 100442 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 100442 # number of StoreCondReq hits +system.cpu.dcache.WriteReq_accesses::0 6662917 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6662917 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_hits::0 6490820 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6490820 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_rate::0 0.025829 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses::0 172097 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 172097 # number of WriteReq misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 34.690601 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 34.634545 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses::0 14508425 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::0 14470249 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 14508425 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 14470249 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency::0 0 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total no_value # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu.dcache.demand_hits::0 14099619 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::0 14061811 # number of demand (read+write) hits system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 14099619 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 14061811 # number of demand (read+write) hits system.cpu.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate::0 0.028177 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::0 0.028226 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.demand_misses::0 408806 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::0 408438 # number of demand (read+write) misses system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 408806 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 408438 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses @@ -67,26 +67,26 @@ system.cpu.dcache.demand_mshr_misses 0 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_blocks::0 511.737186 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999487 # Average percentage of cache occupancy -system.cpu.dcache.overall_accesses::0 14508425 # number of overall (read+write) accesses +system.cpu.dcache.occ_blocks::0 511.736543 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999485 # Average percentage of cache occupancy +system.cpu.dcache.overall_accesses::0 14470249 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 14508425 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 14470249 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency::0 0 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::1 no_value # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total no_value # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits::0 14099619 # number of overall hits +system.cpu.dcache.overall_hits::0 14061811 # number of overall hits system.cpu.dcache.overall_hits::1 0 # number of overall hits -system.cpu.dcache.overall_hits::total 14099619 # number of overall hits +system.cpu.dcache.overall_hits::total 14061811 # number of overall hits system.cpu.dcache.overall_miss_latency 0 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate::0 0.028177 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::0 0.028226 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.overall_misses::0 408806 # number of overall misses +system.cpu.dcache.overall_misses::0 408438 # number of overall misses system.cpu.dcache.overall_misses::1 0 # number of overall misses -system.cpu.dcache.overall_misses::total 408806 # number of overall misses +system.cpu.dcache.overall_misses::total 408438 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses @@ -95,66 +95,66 @@ system.cpu.dcache.overall_mshr_miss_rate::total no_value system.cpu.dcache.overall_mshr_misses 0 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 411623 # number of replacements -system.cpu.dcache.sampled_refs 412135 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 411199 # number of replacements +system.cpu.dcache.sampled_refs 411711 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 511.737186 # Cycle average of tags in use -system.cpu.dcache.total_refs 14297211 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 511.736543 # Cycle average of tags in use +system.cpu.dcache.total_refs 14259423 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 21760500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 381909 # number of writebacks -system.cpu.dtb.accesses 15532989 # DTB accesses +system.cpu.dcache.writebacks 380342 # number of writebacks +system.cpu.dtb.accesses 15494791 # DTB accesses system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.flush_entries 2238 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 2239 # Number of entries that have been flushed from TLB system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 33670 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.hits 15527459 # DTB hits +system.cpu.dtb.flush_tlb_mva_asid 33678 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 15489154 # DTB hits system.cpu.dtb.inst_accesses 0 # ITB inst accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.misses 5530 # DTB misses -system.cpu.dtb.perms_faults 255 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.prefetch_faults 767 # Number of TLB faults due to prefetch -system.cpu.dtb.read_accesses 8743878 # DTB read accesses -system.cpu.dtb.read_hits 8739345 # DTB read hits -system.cpu.dtb.read_misses 4533 # DTB read misses -system.cpu.dtb.write_accesses 6789111 # DTB write accesses -system.cpu.dtb.write_hits 6788114 # DTB write hits -system.cpu.dtb.write_misses 997 # DTB write misses -system.cpu.icache.ReadReq_accesses::0 41566870 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 41566870 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_hits::0 41133444 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 41133444 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_rate::0 0.010427 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses::0 433426 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 433426 # number of ReadReq misses +system.cpu.dtb.misses 5637 # DTB misses +system.cpu.dtb.perms_faults 263 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 787 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 8719654 # DTB read accesses +system.cpu.dtb.read_hits 8715002 # DTB read hits +system.cpu.dtb.read_misses 4652 # DTB read misses +system.cpu.dtb.write_accesses 6775137 # DTB write accesses +system.cpu.dtb.write_hits 6774152 # DTB write hits +system.cpu.dtb.write_misses 985 # DTB write misses +system.cpu.icache.ReadReq_accesses::0 41451981 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 41451981 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_hits::0 41019813 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 41019813 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_rate::0 0.010426 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses::0 432168 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 432168 # number of ReadReq misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 94.903257 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 94.916579 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses::0 41566870 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::0 41451981 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 41566870 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 41451981 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency::0 0 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::1 no_value # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total no_value # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu.icache.demand_hits::0 41133444 # number of demand (read+write) hits +system.cpu.icache.demand_hits::0 41019813 # number of demand (read+write) hits system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 41133444 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 41019813 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate::0 0.010427 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::0 0.010426 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.demand_misses::0 433426 # number of demand (read+write) misses +system.cpu.icache.demand_misses::0 432168 # number of demand (read+write) misses system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 433426 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 432168 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses @@ -164,26 +164,26 @@ system.cpu.icache.demand_mshr_misses 0 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_blocks::0 476.427204 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.930522 # Average percentage of cache occupancy -system.cpu.icache.overall_accesses::0 41566870 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::0 476.338478 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.930349 # Average percentage of cache occupancy +system.cpu.icache.overall_accesses::0 41451981 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 41566870 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 41451981 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency::0 0 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::1 no_value # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total no_value # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits::0 41133444 # number of overall hits +system.cpu.icache.overall_hits::0 41019813 # number of overall hits system.cpu.icache.overall_hits::1 0 # number of overall hits -system.cpu.icache.overall_hits::total 41133444 # number of overall hits +system.cpu.icache.overall_hits::total 41019813 # number of overall hits system.cpu.icache.overall_miss_latency 0 # number of overall miss cycles -system.cpu.icache.overall_miss_rate::0 0.010427 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::0 0.010426 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.overall_misses::0 433426 # number of overall misses +system.cpu.icache.overall_misses::0 432168 # number of overall misses system.cpu.icache.overall_misses::1 0 # number of overall misses -system.cpu.icache.overall_misses::total 433426 # number of overall misses +system.cpu.icache.overall_misses::total 432168 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses @@ -192,27 +192,27 @@ system.cpu.icache.overall_mshr_miss_rate::total no_value system.cpu.icache.overall_mshr_misses 0 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 432913 # number of replacements -system.cpu.icache.sampled_refs 433425 # Sample count of references to valid blocks. +system.cpu.icache.replacements 431655 # number of replacements +system.cpu.icache.sampled_refs 432167 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 476.427204 # Cycle average of tags in use -system.cpu.icache.total_refs 41133444 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 4575402000 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 33681 # number of writebacks +system.cpu.icache.tagsinuse 476.338478 # Cycle average of tags in use +system.cpu.icache.total_refs 41019813 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 4572561500 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 33762 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.itb.accesses 41567997 # DTB accesses +system.cpu.itb.accesses 41453108 # DTB accesses system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.flush_entries 1478 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 1476 # Number of entries that have been flushed from TLB system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 33670 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.hits 41565169 # DTB hits -system.cpu.itb.inst_accesses 41567997 # ITB inst accesses -system.cpu.itb.inst_hits 41565169 # ITB inst hits -system.cpu.itb.inst_misses 2828 # ITB inst misses -system.cpu.itb.misses 2828 # DTB misses +system.cpu.itb.flush_tlb_mva_asid 33678 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 41450178 # DTB hits +system.cpu.itb.inst_accesses 41453108 # ITB inst accesses +system.cpu.itb.inst_hits 41450178 # ITB inst hits +system.cpu.itb.inst_misses 2930 # ITB inst misses +system.cpu.itb.misses 2930 # DTB misses system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.read_accesses 0 # DTB read accesses @@ -224,25 +224,25 @@ system.cpu.itb.write_misses 0 # DT system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 52811050 # number of cpu cycles simulated +system.cpu.numCycles 52682169 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.num_busy_cycles 52811050 # Number of busy cycles -system.cpu.num_conditional_control_insts 7028967 # number of instructions that are conditional controls +system.cpu.num_busy_cycles 52682169 # Number of busy cycles +system.cpu.num_conditional_control_insts 7011337 # number of instructions that are conditional controls system.cpu.num_fp_alu_accesses 6058 # Number of float alu accesses system.cpu.num_fp_insts 6058 # number of float instructions system.cpu.num_fp_register_reads 4226 # number of times the floating registers were read system.cpu.num_fp_register_writes 1834 # number of times the floating registers were written -system.cpu.num_func_calls 1109362 # number of times a function call or return occured +system.cpu.num_func_calls 1107940 # number of times a function call or return occured system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_insts 52100192 # Number of instructions executed -system.cpu.num_int_alu_accesses 42511691 # Number of integer alu accesses -system.cpu.num_int_insts 42511691 # number of integer instructions -system.cpu.num_int_register_reads 131109932 # number of times the integer registers were read -system.cpu.num_int_register_writes 34554918 # number of times the integer registers were written -system.cpu.num_load_insts 9209160 # Number of load instructions -system.cpu.num_mem_refs 16296226 # number of memory refs -system.cpu.num_store_insts 7087066 # Number of store instructions +system.cpu.num_insts 51971087 # Number of instructions executed +system.cpu.num_int_alu_accesses 42400620 # Number of integer alu accesses +system.cpu.num_int_insts 42400620 # number of integer instructions +system.cpu.num_int_register_reads 130759048 # number of times the integer registers were read +system.cpu.num_int_register_writes 34454879 # number of times the integer registers were written +system.cpu.num_load_insts 9174729 # Number of load instructions +system.cpu.num_mem_refs 16247961 # number of memory refs +system.cpu.num_store_insts 7073232 # Number of store instructions system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.avg_refs no_value # Average number of references to valid blocks. @@ -310,61 +310,61 @@ system.iocache.tagsinuse 0 # Cy system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.iocache.writebacks 0 # number of writebacks -system.l2c.ReadExReq_accesses::0 170405 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 170405 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_hits::0 60553 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 60553 # number of ReadExReq hits -system.l2c.ReadExReq_miss_rate::0 0.644652 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses::0 109852 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 109852 # number of ReadExReq misses -system.l2c.ReadReq_accesses::0 673057 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 6142 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 679199 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_hits::0 651904 # number of ReadReq hits -system.l2c.ReadReq_hits::1 6117 # number of ReadReq hits -system.l2c.ReadReq_hits::total 658021 # number of ReadReq hits -system.l2c.ReadReq_miss_rate::0 0.031428 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.004070 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.035499 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses::0 21153 # number of ReadReq misses -system.l2c.ReadReq_misses::1 25 # number of ReadReq misses -system.l2c.ReadReq_misses::total 21178 # number of ReadReq misses -system.l2c.UpgradeReq_accesses::0 1836 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 1836 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_hits::0 17 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 17 # number of UpgradeReq hits -system.l2c.UpgradeReq_miss_rate::0 0.990741 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses::0 1819 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 1819 # number of UpgradeReq misses -system.l2c.Writeback_accesses::0 415590 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 415590 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits::0 415590 # number of Writeback hits -system.l2c.Writeback_hits::total 415590 # number of Writeback hits +system.l2c.ReadExReq_accesses::0 170255 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 170255 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_hits::0 60589 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 60589 # number of ReadExReq hits +system.l2c.ReadExReq_miss_rate::0 0.644128 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses::0 109666 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 109666 # number of ReadExReq misses +system.l2c.ReadReq_accesses::0 671527 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 7078 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 678605 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_hits::0 650296 # number of ReadReq hits +system.l2c.ReadReq_hits::1 7047 # number of ReadReq hits +system.l2c.ReadReq_hits::total 657343 # number of ReadReq hits +system.l2c.ReadReq_miss_rate::0 0.031616 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.004380 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.035996 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses::0 21231 # number of ReadReq misses +system.l2c.ReadReq_misses::1 31 # number of ReadReq misses +system.l2c.ReadReq_misses::total 21262 # number of ReadReq misses +system.l2c.UpgradeReq_accesses::0 1842 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 1842 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_hits::0 19 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 19 # number of UpgradeReq hits +system.l2c.UpgradeReq_miss_rate::0 0.989685 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses::0 1823 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 1823 # number of UpgradeReq misses +system.l2c.Writeback_accesses::0 414104 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 414104 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits::0 414104 # number of Writeback hits +system.l2c.Writeback_hits::total 414104 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.l2c.avg_refs 6.746349 # Average number of references to valid blocks. +system.l2c.avg_refs 6.723520 # Average number of references to valid blocks. system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses::0 843462 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 6142 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 849604 # number of demand (read+write) accesses +system.l2c.demand_accesses::0 841782 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 7078 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 848860 # number of demand (read+write) accesses system.l2c.demand_avg_miss_latency::0 0 # average overall miss latency system.l2c.demand_avg_miss_latency::1 0 # average overall miss latency system.l2c.demand_avg_miss_latency::total 0 # average overall miss latency system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.l2c.demand_hits::0 712457 # number of demand (read+write) hits -system.l2c.demand_hits::1 6117 # number of demand (read+write) hits -system.l2c.demand_hits::total 718574 # number of demand (read+write) hits +system.l2c.demand_hits::0 710885 # number of demand (read+write) hits +system.l2c.demand_hits::1 7047 # number of demand (read+write) hits +system.l2c.demand_hits::total 717932 # number of demand (read+write) hits system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate::0 0.155318 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.004070 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.159389 # miss rate for demand accesses -system.l2c.demand_misses::0 131005 # number of demand (read+write) misses -system.l2c.demand_misses::1 25 # number of demand (read+write) misses -system.l2c.demand_misses::total 131030 # number of demand (read+write) misses +system.l2c.demand_miss_rate::0 0.155500 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.004380 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.159880 # miss rate for demand accesses +system.l2c.demand_misses::0 130897 # number of demand (read+write) misses +system.l2c.demand_misses::1 31 # number of demand (read+write) misses +system.l2c.demand_misses::total 130928 # number of demand (read+write) misses system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses @@ -374,28 +374,28 @@ system.l2c.demand_mshr_misses 0 # nu system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_blocks::0 5042.918302 # Average occupied blocks per context -system.l2c.occ_blocks::1 31264.310783 # Average occupied blocks per context -system.l2c.occ_percent::0 0.076949 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.477056 # Average percentage of cache occupancy -system.l2c.overall_accesses::0 843462 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 6142 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 849604 # number of overall (read+write) accesses +system.l2c.occ_blocks::0 5062.788087 # Average occupied blocks per context +system.l2c.occ_blocks::1 31189.705520 # Average occupied blocks per context +system.l2c.occ_percent::0 0.077252 # Average percentage of cache occupancy +system.l2c.occ_percent::1 0.475917 # Average percentage of cache occupancy +system.l2c.overall_accesses::0 841782 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 7078 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 848860 # number of overall (read+write) accesses system.l2c.overall_avg_miss_latency::0 0 # average overall miss latency system.l2c.overall_avg_miss_latency::1 0 # average overall miss latency system.l2c.overall_avg_miss_latency::total 0 # average overall miss latency system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.l2c.overall_hits::0 712457 # number of overall hits -system.l2c.overall_hits::1 6117 # number of overall hits -system.l2c.overall_hits::total 718574 # number of overall hits +system.l2c.overall_hits::0 710885 # number of overall hits +system.l2c.overall_hits::1 7047 # number of overall hits +system.l2c.overall_hits::total 717932 # number of overall hits system.l2c.overall_miss_latency 0 # number of overall miss cycles -system.l2c.overall_miss_rate::0 0.155318 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.004070 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.159389 # miss rate for overall accesses -system.l2c.overall_misses::0 131005 # number of overall misses -system.l2c.overall_misses::1 25 # number of overall misses -system.l2c.overall_misses::total 131030 # number of overall misses +system.l2c.overall_miss_rate::0 0.155500 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.004380 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.159880 # miss rate for overall accesses +system.l2c.overall_misses::0 130897 # number of overall misses +system.l2c.overall_misses::1 31 # number of overall misses +system.l2c.overall_misses::total 130928 # number of overall misses system.l2c.overall_mshr_hits 0 # number of overall MSHR hits system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses @@ -404,12 +404,12 @@ system.l2c.overall_mshr_miss_rate::total 0 # ms system.l2c.overall_mshr_misses 0 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.replacements 97025 # number of replacements -system.l2c.sampled_refs 129753 # Sample count of references to valid blocks. +system.l2c.replacements 97110 # number of replacements +system.l2c.sampled_refs 129684 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 36307.229085 # Cycle average of tags in use -system.l2c.total_refs 875359 # Total number of references to valid blocks. +system.l2c.tagsinuse 36252.493607 # Cycle average of tags in use +system.l2c.total_refs 871933 # Total number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 90930 # number of writebacks +system.l2c.writebacks 91106 # number of writebacks ---------- End Simulation Statistics ---------- diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/system.terminal b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/system.terminal Binary files differindex 3959577f4..628fa9f5d 100644 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/system.terminal +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/system.terminal diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini index 6cf3e5508..5e47cea73 100644 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini @@ -11,7 +11,7 @@ children=bridge cpu diskmem intrctrl iobus iocache l2c membus physmem realview t boot_cpu_frequency=500 boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB slram=slram0,0x8000000,+0x8000000 mtdparts=slram0:- root=/dev/mtdblock0 init_param=0 -kernel=/dist/m5/system/binaries/vmlinux.arm +kernel=/chips/pd/randd/dist/binaries/vmlinux.arm load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing @@ -166,7 +166,7 @@ type=ExeTracer [system.diskmem] type=PhysicalMemory -file=/dist/m5/system/disks/ael-arm.ext2 +file=/chips/pd/randd/dist/disks/ael-arm.ext2 latency=30000 latency_var=0 null=false diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout index 397e3f68f..c0358507b 100755 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 19 2011 13:41:05 -M5 started Apr 19 2011 13:41:07 -M5 executing on maize +M5 compiled May 1 2011 21:51:08 +M5 started May 1 2011 21:51:14 +M5 executing on u200439-lin.austin.arm.com command line: build/ARM_FS/m5.fast -d build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-timing Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux.arm +info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux.arm info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 114405702000 because m5_exit instruction encountered +Exiting @ tick 114293937000 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index 1213d5a93..1c9e3b842 100644 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,264 +1,264 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1969505 # Simulator instruction rate (inst/s) -host_mem_usage 333648 # Number of bytes of host memory used -host_seconds 26.01 # Real time elapsed on the host -host_tick_rate 4398008175 # Simulator tick rate (ticks/s) +host_inst_rate 703032 # Simulator instruction rate (inst/s) +host_mem_usage 381000 # Number of bytes of host memory used +host_seconds 72.76 # Real time elapsed on the host +host_tick_rate 1570917363 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 51232482 # Number of instructions simulated -sim_seconds 0.114406 # Number of seconds simulated -sim_ticks 114405702000 # Number of ticks simulated -system.cpu.dcache.LoadLockedReq_accesses::0 100305 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 100305 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14522.379495 # average LoadLockedReq miss latency +sim_insts 51149744 # Number of instructions simulated +sim_seconds 0.114294 # Number of seconds simulated +sim_ticks 114293937000 # Number of ticks simulated +system.cpu.dcache.LoadLockedReq_accesses::0 100301 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 100301 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14594.610314 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11522.379495 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_hits::0 95077 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 95077 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_miss_latency 75923000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_rate::0 0.052121 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_misses::0 5228 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 5228 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 60239000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.052121 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11594.610314 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::0 95143 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 95143 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_miss_latency 75279000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_rate::0 0.051425 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_misses::0 5158 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 5158 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_mshr_miss_latency 59805000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.051425 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_misses 5228 # number of LoadLockedReq MSHR misses -system.cpu.dcache.ReadReq_accesses::0 7829265 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 7829265 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency::0 15673.279330 # average ReadReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_misses 5158 # number of LoadLockedReq MSHR misses +system.cpu.dcache.ReadReq_accesses::0 7812826 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 7812826 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency::0 15651.475503 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12672.933246 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12651.150503 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_hits::0 7590884 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7590884 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 3736212000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate::0 0.030447 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses::0 238381 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 238381 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3020986500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.030447 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_hits::0 7574365 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7574365 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 3732266500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate::0 0.030522 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses::0 238461 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 238461 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 3016806000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.030522 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 238381 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_uncacheable_latency 38191861000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.StoreCondReq_accesses::0 100304 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 100304 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_hits::0 100304 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 100304 # number of StoreCondReq hits -system.cpu.dcache.WriteReq_accesses::0 6674712 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6674712 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency::0 40727.602969 # average WriteReq miss latency +system.cpu.dcache.ReadReq_mshr_misses 238461 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable_latency 38192110000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.StoreCondReq_accesses::0 100300 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 100300 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits::0 100300 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 100300 # number of StoreCondReq hits +system.cpu.dcache.WriteReq_accesses::0 6665523 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6665523 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency::0 40729.480776 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 37727.353242 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 37729.274596 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_hits::0 6502524 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6502524 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 7012804500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate::0 0.025797 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses::0 172188 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 172188 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 6496197500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.025797 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_hits::0 6493343 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6493343 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 7012802000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate::0 0.025831 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses::0 172180 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 172180 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 6496226500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.025831 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 172188 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 927430500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_misses 172180 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_uncacheable_latency 927806000 # number of WriteReq MSHR uncacheable cycles system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 34.521241 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 34.459827 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses::0 14503977 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::0 14478349 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 14503977 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency::0 26180.779601 # average overall miss latency +system.cpu.dcache.demand_accesses::total 14478349 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency::0 26166.574940 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 23180.473928 # average overall mshr miss latency -system.cpu.dcache.demand_hits::0 14093408 # number of demand (read+write) hits +system.cpu.dcache.demand_avg_mshr_miss_latency 23166.299761 # average overall mshr miss latency +system.cpu.dcache.demand_hits::0 14067708 # number of demand (read+write) hits system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 14093408 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 10749016500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate::0 0.028307 # miss rate for demand accesses +system.cpu.dcache.demand_hits::total 14067708 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 10745068500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate::0 0.028362 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.demand_misses::0 410569 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::0 410641 # number of demand (read+write) misses system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 410569 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 410641 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 9517184000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate::0 0.028307 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_latency 9513032500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::0 0.028362 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 410569 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 410641 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_blocks::0 509.191392 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.994514 # Average percentage of cache occupancy -system.cpu.dcache.overall_accesses::0 14503977 # number of overall (read+write) accesses +system.cpu.dcache.occ_blocks::0 509.188646 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.994509 # Average percentage of cache occupancy +system.cpu.dcache.overall_accesses::0 14478349 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 14503977 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency::0 26180.779601 # average overall miss latency +system.cpu.dcache.overall_accesses::total 14478349 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency::0 26166.574940 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 23180.473928 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 23166.299761 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits::0 14093408 # number of overall hits +system.cpu.dcache.overall_hits::0 14067708 # number of overall hits system.cpu.dcache.overall_hits::1 0 # number of overall hits -system.cpu.dcache.overall_hits::total 14093408 # number of overall hits -system.cpu.dcache.overall_miss_latency 10749016500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate::0 0.028307 # miss rate for overall accesses +system.cpu.dcache.overall_hits::total 14067708 # number of overall hits +system.cpu.dcache.overall_miss_latency 10745068500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate::0 0.028362 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.overall_misses::0 410569 # number of overall misses +system.cpu.dcache.overall_misses::0 410641 # number of overall misses system.cpu.dcache.overall_misses::1 0 # number of overall misses -system.cpu.dcache.overall_misses::total 410569 # number of overall misses +system.cpu.dcache.overall_misses::total 410641 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 9517184000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate::0 0.028307 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_latency 9513032500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate::0 0.028362 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 410569 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 39119291500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_misses 410641 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 39119916000 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 413454 # number of replacements -system.cpu.dcache.sampled_refs 413966 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 413448 # number of replacements +system.cpu.dcache.sampled_refs 413960 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 509.191392 # Cycle average of tags in use -system.cpu.dcache.total_refs 14290620 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 509.188646 # Cycle average of tags in use +system.cpu.dcache.total_refs 14264990 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 658097000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 381963 # number of writebacks -system.cpu.dtb.accesses 15532506 # DTB accesses +system.cpu.dcache.writebacks 382785 # number of writebacks +system.cpu.dtb.accesses 15507021 # DTB accesses system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.flush_entries 2224 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 2208 # Number of entries that have been flushed from TLB system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 33670 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.hits 15526972 # DTB hits +system.cpu.dtb.flush_tlb_mva_asid 33678 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 15501368 # DTB hits system.cpu.dtb.inst_accesses 0 # ITB inst accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.misses 5534 # DTB misses -system.cpu.dtb.perms_faults 255 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.prefetch_faults 762 # Number of TLB faults due to prefetch -system.cpu.dtb.read_accesses 8744906 # DTB read accesses -system.cpu.dtb.read_hits 8740351 # DTB read hits -system.cpu.dtb.read_misses 4555 # DTB read misses -system.cpu.dtb.write_accesses 6787600 # DTB write accesses -system.cpu.dtb.write_hits 6786621 # DTB write hits -system.cpu.dtb.write_misses 979 # DTB write misses -system.cpu.icache.ReadReq_accesses::0 41556337 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 41556337 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency::0 14789.924361 # average ReadReq miss latency +system.cpu.dtb.misses 5653 # DTB misses +system.cpu.dtb.perms_faults 263 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 801 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 8728602 # DTB read accesses +system.cpu.dtb.read_hits 8723916 # DTB read hits +system.cpu.dtb.read_misses 4686 # DTB read misses +system.cpu.dtb.write_accesses 6778419 # DTB write accesses +system.cpu.dtb.write_hits 6777452 # DTB write hits +system.cpu.dtb.write_misses 967 # DTB write misses +system.cpu.icache.ReadReq_accesses::0 41474839 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 41474839 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency::0 14791.660330 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11788.627271 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11790.344583 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu.icache.ReadReq_hits::0 41121903 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 41121903 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 6425246000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate::0 0.010454 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses::0 434434 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 434434 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 5121380500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.010454 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_hits::0 41040865 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 41040865 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 6419196000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate::0 0.010464 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses::0 433974 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 433974 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 5116703000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::0 0.010464 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 434434 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses 433974 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_uncacheable_latency 349111000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 94.656272 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 94.569871 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses::0 41556337 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::0 41474839 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 41556337 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency::0 14789.924361 # average overall miss latency +system.cpu.icache.demand_accesses::total 41474839 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency::0 14791.660330 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11788.627271 # average overall mshr miss latency -system.cpu.icache.demand_hits::0 41121903 # number of demand (read+write) hits +system.cpu.icache.demand_avg_mshr_miss_latency 11790.344583 # average overall mshr miss latency +system.cpu.icache.demand_hits::0 41040865 # number of demand (read+write) hits system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 41121903 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 6425246000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate::0 0.010454 # miss rate for demand accesses +system.cpu.icache.demand_hits::total 41040865 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 6419196000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate::0 0.010464 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.demand_misses::0 434434 # number of demand (read+write) misses +system.cpu.icache.demand_misses::0 433974 # number of demand (read+write) misses system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 434434 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 433974 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 5121380500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate::0 0.010454 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_latency 5116703000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::0 0.010464 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 434434 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 433974 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_blocks::0 484.333151 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.945963 # Average percentage of cache occupancy -system.cpu.icache.overall_accesses::0 41556337 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::0 484.306355 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.945911 # Average percentage of cache occupancy +system.cpu.icache.overall_accesses::0 41474839 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 41556337 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency::0 14789.924361 # average overall miss latency +system.cpu.icache.overall_accesses::total 41474839 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency::0 14791.660330 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11788.627271 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11790.344583 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu.icache.overall_hits::0 41121903 # number of overall hits +system.cpu.icache.overall_hits::0 41040865 # number of overall hits system.cpu.icache.overall_hits::1 0 # number of overall hits -system.cpu.icache.overall_hits::total 41121903 # number of overall hits -system.cpu.icache.overall_miss_latency 6425246000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate::0 0.010454 # miss rate for overall accesses +system.cpu.icache.overall_hits::total 41040865 # number of overall hits +system.cpu.icache.overall_miss_latency 6419196000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate::0 0.010464 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.overall_misses::0 434434 # number of overall misses +system.cpu.icache.overall_misses::0 433974 # number of overall misses system.cpu.icache.overall_misses::1 0 # number of overall misses -system.cpu.icache.overall_misses::total 434434 # number of overall misses +system.cpu.icache.overall_misses::total 433974 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 5121380500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate::0 0.010454 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_latency 5116703000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate::0 0.010464 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 434434 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 433974 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 349111000 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 433922 # number of replacements -system.cpu.icache.sampled_refs 434434 # Sample count of references to valid blocks. +system.cpu.icache.replacements 433462 # number of replacements +system.cpu.icache.sampled_refs 433974 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 484.333151 # Cycle average of tags in use -system.cpu.icache.total_refs 41121903 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 14253166000 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 34027 # number of writebacks +system.cpu.icache.tagsinuse 484.306355 # Cycle average of tags in use +system.cpu.icache.total_refs 41040865 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 14247556000 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 34334 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.itb.accesses 41559156 # DTB accesses +system.cpu.itb.accesses 41477769 # DTB accesses system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.flush_entries 1478 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 1476 # Number of entries that have been flushed from TLB system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 33670 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.hits 41556337 # DTB hits -system.cpu.itb.inst_accesses 41559156 # ITB inst accesses -system.cpu.itb.inst_hits 41556337 # ITB inst hits -system.cpu.itb.inst_misses 2819 # ITB inst misses -system.cpu.itb.misses 2819 # DTB misses +system.cpu.itb.flush_tlb_mva_asid 33678 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 41474839 # DTB hits +system.cpu.itb.inst_accesses 41477769 # ITB inst accesses +system.cpu.itb.inst_hits 41474839 # ITB inst hits +system.cpu.itb.inst_misses 2930 # ITB inst misses +system.cpu.itb.misses 2930 # DTB misses system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.read_accesses 0 # DTB read accesses @@ -270,25 +270,25 @@ system.cpu.itb.write_misses 0 # DT system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 228811404 # number of cpu cycles simulated +system.cpu.numCycles 228587874 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.num_busy_cycles 228811404 # Number of busy cycles -system.cpu.num_conditional_control_insts 7027409 # number of instructions that are conditional controls -system.cpu.num_fp_alu_accesses 6059 # Number of float alu accesses -system.cpu.num_fp_insts 6059 # number of float instructions -system.cpu.num_fp_register_reads 4227 # number of times the floating registers were read +system.cpu.num_busy_cycles 228587874 # Number of busy cycles +system.cpu.num_conditional_control_insts 7014796 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 6058 # Number of float alu accesses +system.cpu.num_fp_insts 6058 # number of float instructions +system.cpu.num_fp_register_reads 4226 # number of times the floating registers were read system.cpu.num_fp_register_writes 1834 # number of times the floating registers were written -system.cpu.num_func_calls 1109850 # number of times a function call or return occured +system.cpu.num_func_calls 1108768 # number of times a function call or return occured system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_insts 51232482 # Number of instructions executed -system.cpu.num_int_alu_accesses 42503602 # Number of integer alu accesses -system.cpu.num_int_insts 42503602 # number of integer instructions -system.cpu.num_int_register_reads 139360817 # number of times the integer registers were read -system.cpu.num_int_register_writes 34549221 # number of times the integer registers were written -system.cpu.num_load_insts 9206942 # Number of load instructions -system.cpu.num_mem_refs 16291727 # number of memory refs -system.cpu.num_store_insts 7084785 # Number of store instructions +system.cpu.num_insts 51149744 # Number of instructions executed +system.cpu.num_int_alu_accesses 42422684 # Number of integer alu accesses +system.cpu.num_int_insts 42422684 # number of integer instructions +system.cpu.num_int_register_reads 139100376 # number of times the integer registers were read +system.cpu.num_int_register_writes 34478872 # number of times the integer registers were written +system.cpu.num_load_insts 9179491 # Number of load instructions +system.cpu.num_mem_refs 16255504 # number of memory refs +system.cpu.num_store_insts 7076013 # Number of store instructions system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.avg_refs no_value # Average number of references to valid blocks. @@ -356,140 +356,140 @@ system.iocache.tagsinuse 0 # Cy system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.iocache.writebacks 0 # number of writebacks -system.l2c.ReadExReq_accesses::0 170357 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 170357 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::0 170341 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 170341 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_avg_miss_latency::0 52000 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_hits::0 62554 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 62554 # number of ReadExReq hits -system.l2c.ReadExReq_miss_latency 5605756000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_rate::0 0.632806 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses::0 107803 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 107803 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_miss_latency 4312120000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_rate::0 0.632806 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_hits::0 62544 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 62544 # number of ReadExReq hits +system.l2c.ReadExReq_miss_latency 5605444000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_rate::0 0.632831 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses::0 107797 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 107797 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 4311880000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_rate::0 0.632831 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 107803 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses::0 675906 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 5729 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 681635 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency::0 52083.462261 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 32503672.413793 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 32555755.876054 # average ReadReq miss latency +system.l2c.ReadExReq_mshr_misses 107797 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses::0 675421 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 6188 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 681609 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency::0 52063.722222 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 42597590.909091 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 42649654.631313 # average ReadReq miss latency system.l2c.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits::0 657808 # number of ReadReq hits -system.l2c.ReadReq_hits::1 5700 # number of ReadReq hits -system.l2c.ReadReq_hits::total 663508 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 942606500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate::0 0.026776 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.005062 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.031838 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses::0 18098 # number of ReadReq misses -system.l2c.ReadReq_misses::1 29 # number of ReadReq misses -system.l2c.ReadReq_misses::total 18127 # number of ReadReq misses -system.l2c.ReadReq_mshr_miss_latency 725080000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.026819 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 3.164078 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 3.190896 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 18127 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_uncacheable_latency 29200537000 # number of ReadReq MSHR uncacheable cycles -system.l2c.UpgradeReq_accesses::0 1831 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 1831 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency::0 487.589630 # average UpgradeReq miss latency +system.l2c.ReadReq_hits::0 657421 # number of ReadReq hits +system.l2c.ReadReq_hits::1 6166 # number of ReadReq hits +system.l2c.ReadReq_hits::total 663587 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 937147000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate::0 0.026650 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.003555 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.030205 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses::0 18000 # number of ReadReq misses +system.l2c.ReadReq_misses::1 22 # number of ReadReq misses +system.l2c.ReadReq_misses::total 18022 # number of ReadReq misses +system.l2c.ReadReq_mshr_miss_latency 720880000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.026683 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 2.912411 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 2.939094 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_misses 18022 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable_latency 29200759000 # number of ReadReq MSHR uncacheable cycles +system.l2c.UpgradeReq_accesses::0 1839 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 1839 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency::0 313.940724 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_hits::0 18 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 18 # number of UpgradeReq hits -system.l2c.UpgradeReq_miss_latency 884000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_rate::0 0.990169 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses::0 1813 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 1813 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_miss_latency 72520000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_rate::0 0.990169 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_hits::0 17 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 17 # number of UpgradeReq hits +system.l2c.UpgradeReq_miss_latency 572000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_rate::0 0.990756 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses::0 1822 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 1822 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 72880000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_rate::0 0.990756 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 1813 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 1822 # number of UpgradeReq MSHR misses system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_mshr_uncacheable_latency 740916000 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses::0 415990 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 415990 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits::0 415990 # number of Writeback hits -system.l2c.Writeback_hits::total 415990 # number of Writeback hits +system.l2c.WriteReq_mshr_uncacheable_latency 741108000 # number of WriteReq MSHR uncacheable cycles +system.l2c.Writeback_accesses::0 417119 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 417119 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits::0 417119 # number of Writeback hits +system.l2c.Writeback_hits::total 417119 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.l2c.avg_refs 7.063302 # Average number of references to valid blocks. +system.l2c.avg_refs 7.066815 # Average number of references to valid blocks. system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses::0 846263 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 5729 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 851992 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency::0 52011.997522 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 225805603.448276 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 225857615.445798 # average overall miss latency +system.l2c.demand_accesses::0 845762 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 6188 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 851950 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency::0 52009.117864 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 297390500 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 297442509.117864 # average overall miss latency system.l2c.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.l2c.demand_hits::0 720362 # number of demand (read+write) hits -system.l2c.demand_hits::1 5700 # number of demand (read+write) hits -system.l2c.demand_hits::total 726062 # number of demand (read+write) hits -system.l2c.demand_miss_latency 6548362500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate::0 0.148773 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.005062 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.153835 # miss rate for demand accesses -system.l2c.demand_misses::0 125901 # number of demand (read+write) misses -system.l2c.demand_misses::1 29 # number of demand (read+write) misses -system.l2c.demand_misses::total 125930 # number of demand (read+write) misses +system.l2c.demand_hits::0 719965 # number of demand (read+write) hits +system.l2c.demand_hits::1 6166 # number of demand (read+write) hits +system.l2c.demand_hits::total 726131 # number of demand (read+write) hits +system.l2c.demand_miss_latency 6542591000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate::0 0.148738 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.003555 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.152293 # miss rate for demand accesses +system.l2c.demand_misses::0 125797 # number of demand (read+write) misses +system.l2c.demand_misses::1 22 # number of demand (read+write) misses +system.l2c.demand_misses::total 125819 # number of demand (read+write) misses system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 5037200000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate::0 0.148807 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 21.981149 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 22.129956 # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 125930 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_miss_latency 5032760000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate::0 0.148764 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 20.332741 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 20.481505 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 125819 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_blocks::0 5334.310202 # Average occupied blocks per context -system.l2c.occ_blocks::1 31332.032709 # Average occupied blocks per context -system.l2c.occ_percent::0 0.081395 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.478089 # Average percentage of cache occupancy -system.l2c.overall_accesses::0 846263 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 5729 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 851992 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency::0 52011.997522 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 225805603.448276 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 225857615.445798 # average overall miss latency +system.l2c.occ_blocks::0 5338.149518 # Average occupied blocks per context +system.l2c.occ_blocks::1 31318.985652 # Average occupied blocks per context +system.l2c.occ_percent::0 0.081454 # Average percentage of cache occupancy +system.l2c.occ_percent::1 0.477890 # Average percentage of cache occupancy +system.l2c.overall_accesses::0 845762 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 6188 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 851950 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency::0 52009.117864 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 297390500 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 297442509.117864 # average overall miss latency system.l2c.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits::0 720362 # number of overall hits -system.l2c.overall_hits::1 5700 # number of overall hits -system.l2c.overall_hits::total 726062 # number of overall hits -system.l2c.overall_miss_latency 6548362500 # number of overall miss cycles -system.l2c.overall_miss_rate::0 0.148773 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.005062 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.153835 # miss rate for overall accesses -system.l2c.overall_misses::0 125901 # number of overall misses -system.l2c.overall_misses::1 29 # number of overall misses -system.l2c.overall_misses::total 125930 # number of overall misses +system.l2c.overall_hits::0 719965 # number of overall hits +system.l2c.overall_hits::1 6166 # number of overall hits +system.l2c.overall_hits::total 726131 # number of overall hits +system.l2c.overall_miss_latency 6542591000 # number of overall miss cycles +system.l2c.overall_miss_rate::0 0.148738 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.003555 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.152293 # miss rate for overall accesses +system.l2c.overall_misses::0 125797 # number of overall misses +system.l2c.overall_misses::1 22 # number of overall misses +system.l2c.overall_misses::total 125819 # number of overall misses system.l2c.overall_mshr_hits 0 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 5037200000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate::0 0.148807 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 21.981149 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 22.129956 # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 125930 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 29941453000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_miss_latency 5032760000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate::0 0.148764 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 20.332741 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 20.481505 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 125819 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 29941867000 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.replacements 93179 # number of replacements -system.l2c.sampled_refs 124640 # Sample count of references to valid blocks. +system.l2c.replacements 93108 # number of replacements +system.l2c.sampled_refs 124568 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 36666.342911 # Cycle average of tags in use -system.l2c.total_refs 880370 # Total number of references to valid blocks. +system.l2c.tagsinuse 36657.135171 # Cycle average of tags in use +system.l2c.total_refs 880299 # Total number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 87304 # number of writebacks +system.l2c.writebacks 87346 # number of writebacks ---------- End Simulation Statistics ---------- diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal Binary files differindex 6933aa33c..d2aa844f8 100644 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini index 55707ec59..2570db111 100644 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini @@ -127,7 +127,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic +executable=/chips/pd/randd/dist/test-progs/m5threads/bin/sparc/linux/test_atomic gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout index 64cea276f..6949b715b 100755 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 19 2011 12:19:46 -M5 started Apr 19 2011 12:20:58 -M5 executing on maize +M5 compiled May 1 2011 16:25:10 +M5 started May 1 2011 16:26:16 +M5 executing on u200439-lin.austin.arm.com command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp -re tests/run.py build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -83,4 +83,4 @@ Iteration 9 completed [Iteration 10, Thread 3] Critical section done, previously next=1, now next=3 Iteration 10 completed PASSED :-) -Exiting @ tick 262295000 because target called exit() +Exiting @ tick 262298000 because target called exit() diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt index 42ad4fedc..8f7096e73 100644 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1033305 # Simulator instruction rate (inst/s) -host_mem_usage 211712 # Number of bytes of host memory used -host_seconds 0.63 # Real time elapsed on the host -host_tick_rate 416577686 # Simulator tick rate (ticks/s) +host_inst_rate 618975 # Simulator instruction rate (inst/s) +host_mem_usage 255292 # Number of bytes of host memory used +host_seconds 1.07 # Real time elapsed on the host +host_tick_rate 245078766 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 650423 # Number of instructions simulated +sim_insts 662307 # Number of instructions simulated sim_seconds 0.000262 # Number of seconds simulated -sim_ticks 262295000 # Number of ticks simulated +sim_ticks 262298000 # Number of ticks simulated system.cpu0.dcache.ReadReq_accesses 48920 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_avg_miss_latency 29314.814815 # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 26314.814815 # average ReadReq mshr miss latency @@ -29,13 +29,13 @@ system.cpu0.dcache.SwapReq_mshr_miss_latency 309000 system.cpu0.dcache.SwapReq_mshr_miss_rate 0.619048 # mshr miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_mshr_misses 26 # number of SwapReq MSHR misses system.cpu0.dcache.WriteReq_accesses 24924 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_avg_miss_latency 39191.256831 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 36191.256831 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency 39207.650273 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 36207.650273 # average WriteReq mshr miss latency system.cpu0.dcache.WriteReq_hits 24741 # number of WriteReq hits -system.cpu0.dcache.WriteReq_miss_latency 7172000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency 7175000 # number of WriteReq miss cycles system.cpu0.dcache.WriteReq_miss_rate 0.007342 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_misses 183 # number of WriteReq misses -system.cpu0.dcache.WriteReq_mshr_miss_latency 6623000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency 6626000 # number of WriteReq MSHR miss cycles system.cpu0.dcache.WriteReq_mshr_miss_rate 0.007342 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_misses 183 # number of WriteReq MSHR misses system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked @@ -47,31 +47,31 @@ system.cpu0.dcache.blocked_cycles::no_mshrs 0 # system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.demand_accesses 73844 # number of demand (read+write) accesses -system.cpu0.dcache.demand_avg_miss_latency 34553.623188 # average overall miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency 31553.623188 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_miss_latency 34562.318841 # average overall miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency 31562.318841 # average overall mshr miss latency system.cpu0.dcache.demand_hits 73499 # number of demand (read+write) hits -system.cpu0.dcache.demand_miss_latency 11921000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency 11924000 # number of demand (read+write) miss cycles system.cpu0.dcache.demand_miss_rate 0.004672 # miss rate for demand accesses system.cpu0.dcache.demand_misses 345 # number of demand (read+write) misses system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_miss_latency 10886000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency 10889000 # number of demand (read+write) MSHR miss cycles system.cpu0.dcache.demand_mshr_miss_rate 0.004672 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_misses 345 # number of demand (read+write) MSHR misses system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.occ_blocks::0 141.233241 # Average occupied blocks per context +system.cpu0.dcache.occ_blocks::0 141.233342 # Average occupied blocks per context system.cpu0.dcache.occ_percent::0 0.275846 # Average percentage of cache occupancy system.cpu0.dcache.overall_accesses 73844 # number of overall (read+write) accesses -system.cpu0.dcache.overall_avg_miss_latency 34553.623188 # average overall miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency 31553.623188 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_miss_latency 34562.318841 # average overall miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency 31562.318841 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu0.dcache.overall_hits 73499 # number of overall hits -system.cpu0.dcache.overall_miss_latency 11921000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency 11924000 # number of overall miss cycles system.cpu0.dcache.overall_miss_rate 0.004672 # miss rate for overall accesses system.cpu0.dcache.overall_misses 345 # number of overall misses system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_miss_latency 10886000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency 10889000 # number of overall MSHR miss cycles system.cpu0.dcache.overall_mshr_miss_rate 0.004672 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_misses 345 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -79,7 +79,7 @@ system.cpu0.dcache.overall_mshr_uncacheable_misses 0 system.cpu0.dcache.replacements 9 # number of replacements system.cpu0.dcache.sampled_refs 170 # Sample count of references to valid blocks. system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.dcache.tagsinuse 141.233241 # Cycle average of tags in use +system.cpu0.dcache.tagsinuse 141.233342 # Cycle average of tags in use system.cpu0.dcache.total_refs 56009 # Total number of references to valid blocks. system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu0.dcache.writebacks 6 # number of writebacks @@ -115,7 +115,7 @@ system.cpu0.icache.demand_mshr_misses 467 # nu system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.occ_blocks::0 212.478999 # Average occupied blocks per context +system.cpu0.icache.occ_blocks::0 212.479188 # Average occupied blocks per context system.cpu0.icache.occ_percent::0 0.414998 # Average percentage of cache occupancy system.cpu0.icache.overall_accesses 158416 # number of overall (read+write) accesses system.cpu0.icache.overall_avg_miss_latency 39665.952891 # average overall miss latency @@ -134,16 +134,16 @@ system.cpu0.icache.overall_mshr_uncacheable_misses 0 system.cpu0.icache.replacements 215 # number of replacements system.cpu0.icache.sampled_refs 467 # Sample count of references to valid blocks. system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.icache.tagsinuse 212.478999 # Cycle average of tags in use +system.cpu0.icache.tagsinuse 212.479188 # Cycle average of tags in use system.cpu0.icache.total_refs 157949 # Total number of references to valid blocks. system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu0.icache.writebacks 0 # number of writebacks system.cpu0.idle_fraction 0 # Percentage of idle cycles system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu0.numCycles 524590 # number of cpu cycles simulated +system.cpu0.numCycles 524596 # number of cpu cycles simulated system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu0.num_busy_cycles 524590 # Number of busy cycles +system.cpu0.num_busy_cycles 524596 # Number of busy cycles system.cpu0.num_conditional_control_insts 0 # number of instructions that are conditional controls system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu0.num_fp_insts 0 # number of float instructions @@ -160,16 +160,16 @@ system.cpu0.num_load_insts 48930 # Nu system.cpu0.num_mem_refs 73905 # number of memory refs system.cpu0.num_store_insts 24975 # Number of store instructions system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu1.dcache.ReadReq_accesses 38632 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_avg_miss_latency 20316.666667 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 17316.666667 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_hits 38452 # number of ReadReq hits -system.cpu1.dcache.ReadReq_miss_latency 3657000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_rate 0.004659 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_misses 180 # number of ReadReq misses -system.cpu1.dcache.ReadReq_mshr_miss_latency 3117000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate 0.004659 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_misses 180 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_accesses 39609 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_avg_miss_latency 20513.812155 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 17513.812155 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_hits 39428 # number of ReadReq hits +system.cpu1.dcache.ReadReq_miss_latency 3713000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_rate 0.004570 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_misses 181 # number of ReadReq misses +system.cpu1.dcache.ReadReq_mshr_miss_latency 3170000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate 0.004570 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_misses 181 # number of ReadReq MSHR misses system.cpu1.dcache.SwapReq_accesses 83 # number of SwapReq accesses(hits+misses) system.cpu1.dcache.SwapReq_avg_miss_latency 6384.615385 # average SwapReq miss latency system.cpu1.dcache.SwapReq_avg_mshr_miss_latency 3384.615385 # average SwapReq mshr miss latency @@ -180,149 +180,149 @@ system.cpu1.dcache.SwapReq_misses 65 # nu system.cpu1.dcache.SwapReq_mshr_miss_latency 220000 # number of SwapReq MSHR miss cycles system.cpu1.dcache.SwapReq_mshr_miss_rate 0.783133 # mshr miss rate for SwapReq accesses system.cpu1.dcache.SwapReq_mshr_misses 65 # number of SwapReq MSHR misses -system.cpu1.dcache.WriteReq_accesses 8194 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_avg_miss_latency 18489.583333 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 15489.583333 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_hits 8098 # number of WriteReq hits -system.cpu1.dcache.WriteReq_miss_latency 1775000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_rate 0.011716 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_misses 96 # number of WriteReq misses -system.cpu1.dcache.WriteReq_mshr_miss_latency 1487000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_rate 0.011716 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_misses 96 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_accesses 8197 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_avg_miss_latency 19275.510204 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 16275.510204 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_hits 8099 # number of WriteReq hits +system.cpu1.dcache.WriteReq_miss_latency 1889000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_rate 0.011956 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_misses 98 # number of WriteReq misses +system.cpu1.dcache.WriteReq_mshr_miss_latency 1595000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_rate 0.011956 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_misses 98 # number of WriteReq MSHR misses system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu1.dcache.avg_refs 640.392857 # Average number of references to valid blocks. +system.cpu1.dcache.avg_refs 609.935484 # Average number of references to valid blocks. system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.demand_accesses 46826 # number of demand (read+write) accesses -system.cpu1.dcache.demand_avg_miss_latency 19681.159420 # average overall miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency 16681.159420 # average overall mshr miss latency -system.cpu1.dcache.demand_hits 46550 # number of demand (read+write) hits -system.cpu1.dcache.demand_miss_latency 5432000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_rate 0.005894 # miss rate for demand accesses -system.cpu1.dcache.demand_misses 276 # number of demand (read+write) misses +system.cpu1.dcache.demand_accesses 47806 # number of demand (read+write) accesses +system.cpu1.dcache.demand_avg_miss_latency 20078.853047 # average overall miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency 17078.853047 # average overall mshr miss latency +system.cpu1.dcache.demand_hits 47527 # number of demand (read+write) hits +system.cpu1.dcache.demand_miss_latency 5602000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_rate 0.005836 # miss rate for demand accesses +system.cpu1.dcache.demand_misses 279 # number of demand (read+write) misses system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_miss_latency 4604000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_rate 0.005894 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_misses 276 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_miss_latency 4765000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_rate 0.005836 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_misses 279 # number of demand (read+write) MSHR misses system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.occ_blocks::0 26.636390 # Average occupied blocks per context -system.cpu1.dcache.occ_blocks::1 -3.989577 # Average occupied blocks per context -system.cpu1.dcache.occ_percent::0 0.052024 # Average percentage of cache occupancy +system.cpu1.dcache.occ_blocks::0 26.693562 # Average occupied blocks per context +system.cpu1.dcache.occ_blocks::1 -3.989645 # Average occupied blocks per context +system.cpu1.dcache.occ_percent::0 0.052136 # Average percentage of cache occupancy system.cpu1.dcache.occ_percent::1 -0.007792 # Average percentage of cache occupancy -system.cpu1.dcache.overall_accesses 46826 # number of overall (read+write) accesses -system.cpu1.dcache.overall_avg_miss_latency 19681.159420 # average overall miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency 16681.159420 # average overall mshr miss latency +system.cpu1.dcache.overall_accesses 47806 # number of overall (read+write) accesses +system.cpu1.dcache.overall_avg_miss_latency 20078.853047 # average overall miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency 17078.853047 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu1.dcache.overall_hits 46550 # number of overall hits -system.cpu1.dcache.overall_miss_latency 5432000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_rate 0.005894 # miss rate for overall accesses -system.cpu1.dcache.overall_misses 276 # number of overall misses +system.cpu1.dcache.overall_hits 47527 # number of overall hits +system.cpu1.dcache.overall_miss_latency 5602000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_rate 0.005836 # miss rate for overall accesses +system.cpu1.dcache.overall_misses 279 # number of overall misses system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_miss_latency 4604000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_rate 0.005894 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_misses 276 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_miss_latency 4765000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_rate 0.005836 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_misses 279 # number of overall MSHR misses system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu1.dcache.replacements 2 # number of replacements -system.cpu1.dcache.sampled_refs 28 # Sample count of references to valid blocks. +system.cpu1.dcache.sampled_refs 31 # Sample count of references to valid blocks. system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.dcache.tagsinuse 22.646814 # Cycle average of tags in use -system.cpu1.dcache.total_refs 17931 # Total number of references to valid blocks. +system.cpu1.dcache.tagsinuse 22.703917 # Cycle average of tags in use +system.cpu1.dcache.total_refs 18908 # Total number of references to valid blocks. system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu1.dcache.writebacks 1 # number of writebacks -system.cpu1.icache.ReadReq_accesses 168396 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_avg_miss_latency 21104.748603 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency 18103.351955 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_hits 168038 # number of ReadReq hits -system.cpu1.icache.ReadReq_miss_latency 7555500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_rate 0.002126 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_misses 358 # number of ReadReq misses -system.cpu1.icache.ReadReq_mshr_miss_latency 6481000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate 0.002126 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_misses 358 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_accesses 172358 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_avg_miss_latency 21640.710383 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency 18639.344262 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_hits 171992 # number of ReadReq hits +system.cpu1.icache.ReadReq_miss_latency 7920500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_rate 0.002123 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_misses 366 # number of ReadReq misses +system.cpu1.icache.ReadReq_mshr_miss_latency 6822000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate 0.002123 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_misses 366 # number of ReadReq MSHR misses system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu1.icache.avg_refs 469.379888 # Average number of references to valid blocks. +system.cpu1.icache.avg_refs 469.923497 # Average number of references to valid blocks. system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.demand_accesses 168396 # number of demand (read+write) accesses -system.cpu1.icache.demand_avg_miss_latency 21104.748603 # average overall miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency 18103.351955 # average overall mshr miss latency -system.cpu1.icache.demand_hits 168038 # number of demand (read+write) hits -system.cpu1.icache.demand_miss_latency 7555500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_rate 0.002126 # miss rate for demand accesses -system.cpu1.icache.demand_misses 358 # number of demand (read+write) misses +system.cpu1.icache.demand_accesses 172358 # number of demand (read+write) accesses +system.cpu1.icache.demand_avg_miss_latency 21640.710383 # average overall miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency 18639.344262 # average overall mshr miss latency +system.cpu1.icache.demand_hits 171992 # number of demand (read+write) hits +system.cpu1.icache.demand_miss_latency 7920500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_rate 0.002123 # miss rate for demand accesses +system.cpu1.icache.demand_misses 366 # number of demand (read+write) misses system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_miss_latency 6481000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_rate 0.002126 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_misses 358 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_miss_latency 6822000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_rate 0.002123 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_misses 366 # number of demand (read+write) MSHR misses system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.occ_blocks::0 69.958167 # Average occupied blocks per context -system.cpu1.icache.occ_percent::0 0.136637 # Average percentage of cache occupancy -system.cpu1.icache.overall_accesses 168396 # number of overall (read+write) accesses -system.cpu1.icache.overall_avg_miss_latency 21104.748603 # average overall miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency 18103.351955 # average overall mshr miss latency +system.cpu1.icache.occ_blocks::0 70.076133 # Average occupied blocks per context +system.cpu1.icache.occ_percent::0 0.136867 # Average percentage of cache occupancy +system.cpu1.icache.overall_accesses 172358 # number of overall (read+write) accesses +system.cpu1.icache.overall_avg_miss_latency 21640.710383 # average overall miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency 18639.344262 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu1.icache.overall_hits 168038 # number of overall hits -system.cpu1.icache.overall_miss_latency 7555500 # number of overall miss cycles -system.cpu1.icache.overall_miss_rate 0.002126 # miss rate for overall accesses -system.cpu1.icache.overall_misses 358 # number of overall misses +system.cpu1.icache.overall_hits 171992 # number of overall hits +system.cpu1.icache.overall_miss_latency 7920500 # number of overall miss cycles +system.cpu1.icache.overall_miss_rate 0.002123 # miss rate for overall accesses +system.cpu1.icache.overall_misses 366 # number of overall misses system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_miss_latency 6481000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_rate 0.002126 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_misses 358 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_miss_latency 6822000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_rate 0.002123 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_misses 366 # number of overall MSHR misses system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.icache.replacements 278 # number of replacements -system.cpu1.icache.sampled_refs 358 # Sample count of references to valid blocks. +system.cpu1.icache.replacements 280 # number of replacements +system.cpu1.icache.sampled_refs 366 # Sample count of references to valid blocks. system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.icache.tagsinuse 69.958167 # Cycle average of tags in use -system.cpu1.icache.total_refs 168038 # Total number of references to valid blocks. +system.cpu1.icache.tagsinuse 70.076133 # Cycle average of tags in use +system.cpu1.icache.total_refs 171992 # Total number of references to valid blocks. system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu1.icache.writebacks 0 # number of writebacks -system.cpu1.idle_fraction 0.130715 # Percentage of idle cycles -system.cpu1.not_idle_fraction 0.869285 # Percentage of non-idle cycles -system.cpu1.numCycles 513666 # number of cpu cycles simulated +system.cpu1.idle_fraction 0.130725 # Percentage of idle cycles +system.cpu1.not_idle_fraction 0.869275 # Percentage of non-idle cycles +system.cpu1.numCycles 524596 # number of cpu cycles simulated system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu1.num_busy_cycles 446521.933500 # Number of busy cycles +system.cpu1.num_busy_cycles 456017.998261 # Number of busy cycles system.cpu1.num_conditional_control_insts 0 # number of instructions that are conditional controls system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu1.num_fp_insts 0 # number of float instructions system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written system.cpu1.num_func_calls 0 # number of times a function call or return occured -system.cpu1.num_idle_cycles 67144.066500 # Number of idle cycles -system.cpu1.num_insts 168364 # Number of instructions executed -system.cpu1.num_int_alu_accesses 105930 # Number of integer alu accesses -system.cpu1.num_int_insts 105930 # number of integer instructions -system.cpu1.num_int_register_reads 244134 # number of times the integer registers were read -system.cpu1.num_int_register_writes 89763 # number of times the integer registers were written -system.cpu1.num_load_insts 38640 # Number of load instructions -system.cpu1.num_mem_refs 46919 # number of memory refs -system.cpu1.num_store_insts 8279 # Number of store instructions -system.cpu2.dcache.ReadReq_accesses 40867 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_avg_miss_latency 15941.935484 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency 12941.935484 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_hits 40712 # number of ReadReq hits -system.cpu2.dcache.ReadReq_miss_latency 2471000 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_rate 0.003793 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_misses 155 # number of ReadReq misses -system.cpu2.dcache.ReadReq_mshr_miss_latency 2006000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate 0.003793 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_misses 155 # number of ReadReq MSHR misses +system.cpu1.num_idle_cycles 68578.001739 # Number of idle cycles +system.cpu1.num_insts 172325 # Number of instructions executed +system.cpu1.num_int_alu_accesses 107932 # Number of integer alu accesses +system.cpu1.num_int_insts 107932 # number of integer instructions +system.cpu1.num_int_register_reads 249091 # number of times the integer registers were read +system.cpu1.num_int_register_writes 92744 # number of times the integer registers were written +system.cpu1.num_load_insts 39616 # Number of load instructions +system.cpu1.num_mem_refs 47898 # number of memory refs +system.cpu1.num_store_insts 8282 # Number of store instructions +system.cpu2.dcache.ReadReq_accesses 41844 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_avg_miss_latency 16198.717949 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency 13198.717949 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_hits 41688 # number of ReadReq hits +system.cpu2.dcache.ReadReq_miss_latency 2527000 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_rate 0.003728 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_misses 156 # number of ReadReq misses +system.cpu2.dcache.ReadReq_mshr_miss_latency 2059000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate 0.003728 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_misses 156 # number of ReadReq MSHR misses system.cpu2.dcache.SwapReq_accesses 62 # number of SwapReq accesses(hits+misses) system.cpu2.dcache.SwapReq_avg_miss_latency 5980.392157 # average SwapReq miss latency system.cpu2.dcache.SwapReq_avg_mshr_miss_latency 2980.392157 # average SwapReq mshr miss latency @@ -333,149 +333,149 @@ system.cpu2.dcache.SwapReq_misses 51 # nu system.cpu2.dcache.SwapReq_mshr_miss_latency 152000 # number of SwapReq MSHR miss cycles system.cpu2.dcache.SwapReq_mshr_miss_rate 0.822581 # mshr miss rate for SwapReq accesses system.cpu2.dcache.SwapReq_mshr_misses 51 # number of SwapReq MSHR misses -system.cpu2.dcache.WriteReq_accesses 16022 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_avg_miss_latency 18411.214953 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency 15411.214953 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_hits 15915 # number of WriteReq hits -system.cpu2.dcache.WriteReq_miss_latency 1970000 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_rate 0.006678 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_misses 107 # number of WriteReq misses -system.cpu2.dcache.WriteReq_mshr_miss_latency 1649000 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_rate 0.006678 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_misses 107 # number of WriteReq MSHR misses +system.cpu2.dcache.WriteReq_accesses 16025 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_avg_miss_latency 19119.266055 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency 16119.266055 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_hits 15916 # number of WriteReq hits +system.cpu2.dcache.WriteReq_miss_latency 2084000 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_rate 0.006802 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_misses 109 # number of WriteReq misses +system.cpu2.dcache.WriteReq_mshr_miss_latency 1757000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_rate 0.006802 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_misses 109 # number of WriteReq MSHR misses system.cpu2.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu2.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu2.dcache.avg_refs 1200.035714 # Average number of references to valid blocks. +system.cpu2.dcache.avg_refs 1115.419355 # Average number of references to valid blocks. system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.demand_accesses 56889 # number of demand (read+write) accesses -system.cpu2.dcache.demand_avg_miss_latency 16950.381679 # average overall miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency 13950.381679 # average overall mshr miss latency -system.cpu2.dcache.demand_hits 56627 # number of demand (read+write) hits -system.cpu2.dcache.demand_miss_latency 4441000 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_rate 0.004605 # miss rate for demand accesses -system.cpu2.dcache.demand_misses 262 # number of demand (read+write) misses +system.cpu2.dcache.demand_accesses 57869 # number of demand (read+write) accesses +system.cpu2.dcache.demand_avg_miss_latency 17400 # average overall miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency 14400 # average overall mshr miss latency +system.cpu2.dcache.demand_hits 57604 # number of demand (read+write) hits +system.cpu2.dcache.demand_miss_latency 4611000 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_rate 0.004579 # miss rate for demand accesses +system.cpu2.dcache.demand_misses 265 # number of demand (read+write) misses system.cpu2.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu2.dcache.demand_mshr_miss_latency 3655000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_rate 0.004605 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_misses 262 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_miss_latency 3816000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_rate 0.004579 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_misses 265 # number of demand (read+write) MSHR misses system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.dcache.occ_blocks::0 24.886220 # Average occupied blocks per context -system.cpu2.dcache.occ_blocks::1 -1.638018 # Average occupied blocks per context -system.cpu2.dcache.occ_percent::0 0.048606 # Average percentage of cache occupancy +system.cpu2.dcache.occ_blocks::0 24.943438 # Average occupied blocks per context +system.cpu2.dcache.occ_blocks::1 -1.638045 # Average occupied blocks per context +system.cpu2.dcache.occ_percent::0 0.048718 # Average percentage of cache occupancy system.cpu2.dcache.occ_percent::1 -0.003199 # Average percentage of cache occupancy -system.cpu2.dcache.overall_accesses 56889 # number of overall (read+write) accesses -system.cpu2.dcache.overall_avg_miss_latency 16950.381679 # average overall miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency 13950.381679 # average overall mshr miss latency +system.cpu2.dcache.overall_accesses 57869 # number of overall (read+write) accesses +system.cpu2.dcache.overall_avg_miss_latency 17400 # average overall miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency 14400 # average overall mshr miss latency system.cpu2.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu2.dcache.overall_hits 56627 # number of overall hits -system.cpu2.dcache.overall_miss_latency 4441000 # number of overall miss cycles -system.cpu2.dcache.overall_miss_rate 0.004605 # miss rate for overall accesses -system.cpu2.dcache.overall_misses 262 # number of overall misses +system.cpu2.dcache.overall_hits 57604 # number of overall hits +system.cpu2.dcache.overall_miss_latency 4611000 # number of overall miss cycles +system.cpu2.dcache.overall_miss_rate 0.004579 # miss rate for overall accesses +system.cpu2.dcache.overall_misses 265 # number of overall misses system.cpu2.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu2.dcache.overall_mshr_miss_latency 3655000 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_rate 0.004605 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_misses 262 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_miss_latency 3816000 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_rate 0.004579 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_misses 265 # number of overall MSHR misses system.cpu2.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu2.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu2.dcache.replacements 2 # number of replacements -system.cpu2.dcache.sampled_refs 28 # Sample count of references to valid blocks. +system.cpu2.dcache.sampled_refs 31 # Sample count of references to valid blocks. system.cpu2.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu2.dcache.tagsinuse 23.248201 # Cycle average of tags in use -system.cpu2.dcache.total_refs 33601 # Total number of references to valid blocks. +system.cpu2.dcache.tagsinuse 23.305393 # Cycle average of tags in use +system.cpu2.dcache.total_refs 34578 # Total number of references to valid blocks. system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu2.dcache.writebacks 1 # number of writebacks -system.cpu2.icache.ReadReq_accesses 161568 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_avg_miss_latency 14758.379888 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency 11758.379888 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_hits 161210 # number of ReadReq hits -system.cpu2.icache.ReadReq_miss_latency 5283500 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_rate 0.002216 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_misses 358 # number of ReadReq misses -system.cpu2.icache.ReadReq_mshr_miss_latency 4209500 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate 0.002216 # mshr miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_mshr_misses 358 # number of ReadReq MSHR misses +system.cpu2.icache.ReadReq_accesses 165532 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_avg_miss_latency 15433.060109 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency 12433.060109 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_hits 165166 # number of ReadReq hits +system.cpu2.icache.ReadReq_miss_latency 5648500 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_rate 0.002211 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_misses 366 # number of ReadReq misses +system.cpu2.icache.ReadReq_mshr_miss_latency 4550500 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate 0.002211 # mshr miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_mshr_misses 366 # number of ReadReq MSHR misses system.cpu2.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu2.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu2.icache.avg_refs 450.307263 # Average number of references to valid blocks. +system.cpu2.icache.avg_refs 451.273224 # Average number of references to valid blocks. system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.cache_copies 0 # number of cache copies performed -system.cpu2.icache.demand_accesses 161568 # number of demand (read+write) accesses -system.cpu2.icache.demand_avg_miss_latency 14758.379888 # average overall miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency 11758.379888 # average overall mshr miss latency -system.cpu2.icache.demand_hits 161210 # number of demand (read+write) hits -system.cpu2.icache.demand_miss_latency 5283500 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_rate 0.002216 # miss rate for demand accesses -system.cpu2.icache.demand_misses 358 # number of demand (read+write) misses +system.cpu2.icache.demand_accesses 165532 # number of demand (read+write) accesses +system.cpu2.icache.demand_avg_miss_latency 15433.060109 # average overall miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency 12433.060109 # average overall mshr miss latency +system.cpu2.icache.demand_hits 165166 # number of demand (read+write) hits +system.cpu2.icache.demand_miss_latency 5648500 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_rate 0.002211 # miss rate for demand accesses +system.cpu2.icache.demand_misses 366 # number of demand (read+write) misses system.cpu2.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu2.icache.demand_mshr_miss_latency 4209500 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_rate 0.002216 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_misses 358 # number of demand (read+write) MSHR misses +system.cpu2.icache.demand_mshr_miss_latency 4550500 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_rate 0.002211 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_misses 366 # number of demand (read+write) MSHR misses system.cpu2.icache.fast_writes 0 # number of fast writes performed system.cpu2.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.icache.occ_blocks::0 65.482956 # Average occupied blocks per context -system.cpu2.icache.occ_percent::0 0.127896 # Average percentage of cache occupancy -system.cpu2.icache.overall_accesses 161568 # number of overall (read+write) accesses -system.cpu2.icache.overall_avg_miss_latency 14758.379888 # average overall miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency 11758.379888 # average overall mshr miss latency +system.cpu2.icache.occ_blocks::0 65.601019 # Average occupied blocks per context +system.cpu2.icache.occ_percent::0 0.128127 # Average percentage of cache occupancy +system.cpu2.icache.overall_accesses 165532 # number of overall (read+write) accesses +system.cpu2.icache.overall_avg_miss_latency 15433.060109 # average overall miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency 12433.060109 # average overall mshr miss latency system.cpu2.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu2.icache.overall_hits 161210 # number of overall hits -system.cpu2.icache.overall_miss_latency 5283500 # number of overall miss cycles -system.cpu2.icache.overall_miss_rate 0.002216 # miss rate for overall accesses -system.cpu2.icache.overall_misses 358 # number of overall misses +system.cpu2.icache.overall_hits 165166 # number of overall hits +system.cpu2.icache.overall_miss_latency 5648500 # number of overall miss cycles +system.cpu2.icache.overall_miss_rate 0.002211 # miss rate for overall accesses +system.cpu2.icache.overall_misses 366 # number of overall misses system.cpu2.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu2.icache.overall_mshr_miss_latency 4209500 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_rate 0.002216 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_misses 358 # number of overall MSHR misses +system.cpu2.icache.overall_mshr_miss_latency 4550500 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_rate 0.002211 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_misses 366 # number of overall MSHR misses system.cpu2.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu2.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu2.icache.replacements 278 # number of replacements -system.cpu2.icache.sampled_refs 358 # Sample count of references to valid blocks. +system.cpu2.icache.replacements 280 # number of replacements +system.cpu2.icache.sampled_refs 366 # Sample count of references to valid blocks. system.cpu2.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu2.icache.tagsinuse 65.482956 # Cycle average of tags in use -system.cpu2.icache.total_refs 161210 # Total number of references to valid blocks. +system.cpu2.icache.tagsinuse 65.601019 # Cycle average of tags in use +system.cpu2.icache.total_refs 165166 # Total number of references to valid blocks. system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu2.icache.writebacks 0 # number of writebacks -system.cpu2.idle_fraction 0.131215 # Percentage of idle cycles -system.cpu2.not_idle_fraction 0.868785 # Percentage of non-idle cycles -system.cpu2.numCycles 513662 # number of cpu cycles simulated +system.cpu2.idle_fraction 0.131225 # Percentage of idle cycles +system.cpu2.not_idle_fraction 0.868775 # Percentage of non-idle cycles +system.cpu2.numCycles 524596 # number of cpu cycles simulated system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu2.num_busy_cycles 446261.914218 # Number of busy cycles +system.cpu2.num_busy_cycles 455755.998262 # Number of busy cycles system.cpu2.num_conditional_control_insts 0 # number of instructions that are conditional controls system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu2.num_fp_insts 0 # number of float instructions system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written system.cpu2.num_func_calls 0 # number of times a function call or return occured -system.cpu2.num_idle_cycles 67400.085782 # Number of idle cycles -system.cpu2.num_insts 161536 # Number of instructions executed -system.cpu2.num_int_alu_accesses 110351 # Number of integer alu accesses -system.cpu2.num_int_insts 110351 # number of integer instructions -system.cpu2.num_int_register_reads 284309 # number of times the integer registers were read -system.cpu2.num_int_register_writes 107647 # number of times the integer registers were written -system.cpu2.num_load_insts 40875 # Number of load instructions -system.cpu2.num_mem_refs 56961 # number of memory refs -system.cpu2.num_store_insts 16086 # Number of store instructions -system.cpu3.dcache.ReadReq_accesses 40736 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_avg_miss_latency 16115.384615 # average ReadReq miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency 13115.384615 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_hits 40580 # number of ReadReq hits -system.cpu3.dcache.ReadReq_miss_latency 2514000 # number of ReadReq miss cycles -system.cpu3.dcache.ReadReq_miss_rate 0.003830 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_misses 156 # number of ReadReq misses -system.cpu3.dcache.ReadReq_mshr_miss_latency 2046000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate 0.003830 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_mshr_misses 156 # number of ReadReq MSHR misses +system.cpu2.num_idle_cycles 68840.001738 # Number of idle cycles +system.cpu2.num_insts 165499 # Number of instructions executed +system.cpu2.num_int_alu_accesses 112355 # Number of integer alu accesses +system.cpu2.num_int_insts 112355 # number of integer instructions +system.cpu2.num_int_register_reads 289268 # number of times the integer registers were read +system.cpu2.num_int_register_writes 110631 # number of times the integer registers were written +system.cpu2.num_load_insts 41852 # Number of load instructions +system.cpu2.num_mem_refs 57941 # number of memory refs +system.cpu2.num_store_insts 16089 # Number of store instructions +system.cpu3.dcache.ReadReq_accesses 41712 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_avg_miss_latency 16363.057325 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency 13363.057325 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_hits 41555 # number of ReadReq hits +system.cpu3.dcache.ReadReq_miss_latency 2569000 # number of ReadReq miss cycles +system.cpu3.dcache.ReadReq_miss_rate 0.003764 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_misses 157 # number of ReadReq misses +system.cpu3.dcache.ReadReq_mshr_miss_latency 2098000 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate 0.003764 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_mshr_misses 157 # number of ReadReq MSHR misses system.cpu3.dcache.SwapReq_accesses 65 # number of SwapReq accesses(hits+misses) system.cpu3.dcache.SwapReq_avg_miss_latency 6037.037037 # average SwapReq miss latency system.cpu3.dcache.SwapReq_avg_mshr_miss_latency 3037.037037 # average SwapReq mshr miss latency @@ -486,203 +486,203 @@ system.cpu3.dcache.SwapReq_misses 54 # nu system.cpu3.dcache.SwapReq_mshr_miss_latency 164000 # number of SwapReq MSHR miss cycles system.cpu3.dcache.SwapReq_mshr_miss_rate 0.830769 # mshr miss rate for SwapReq accesses system.cpu3.dcache.SwapReq_mshr_misses 54 # number of SwapReq MSHR misses -system.cpu3.dcache.WriteReq_accesses 15453 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_avg_miss_latency 18537.735849 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency 15537.735849 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_hits 15347 # number of WriteReq hits -system.cpu3.dcache.WriteReq_miss_latency 1965000 # number of WriteReq miss cycles -system.cpu3.dcache.WriteReq_miss_rate 0.006860 # miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_misses 106 # number of WriteReq misses -system.cpu3.dcache.WriteReq_mshr_miss_latency 1647000 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_rate 0.006860 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_mshr_misses 106 # number of WriteReq MSHR misses +system.cpu3.dcache.WriteReq_accesses 15456 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_avg_miss_latency 19259.259259 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency 16259.259259 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_hits 15348 # number of WriteReq hits +system.cpu3.dcache.WriteReq_miss_latency 2080000 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_rate 0.006988 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_misses 108 # number of WriteReq misses +system.cpu3.dcache.WriteReq_mshr_miss_latency 1756000 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_rate 0.006988 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_mshr_misses 108 # number of WriteReq MSHR misses system.cpu3.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu3.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu3.dcache.avg_refs 1120.620690 # Average number of references to valid blocks. +system.cpu3.dcache.avg_refs 1046.062500 # Average number of references to valid blocks. system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.demand_accesses 56189 # number of demand (read+write) accesses -system.cpu3.dcache.demand_avg_miss_latency 17095.419847 # average overall miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency 14095.419847 # average overall mshr miss latency -system.cpu3.dcache.demand_hits 55927 # number of demand (read+write) hits -system.cpu3.dcache.demand_miss_latency 4479000 # number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_rate 0.004663 # miss rate for demand accesses -system.cpu3.dcache.demand_misses 262 # number of demand (read+write) misses +system.cpu3.dcache.demand_accesses 57168 # number of demand (read+write) accesses +system.cpu3.dcache.demand_avg_miss_latency 17543.396226 # average overall miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency 14543.396226 # average overall mshr miss latency +system.cpu3.dcache.demand_hits 56903 # number of demand (read+write) hits +system.cpu3.dcache.demand_miss_latency 4649000 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_rate 0.004635 # miss rate for demand accesses +system.cpu3.dcache.demand_misses 265 # number of demand (read+write) misses system.cpu3.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu3.dcache.demand_mshr_miss_latency 3693000 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_rate 0.004663 # mshr miss rate for demand accesses -system.cpu3.dcache.demand_mshr_misses 262 # number of demand (read+write) MSHR misses +system.cpu3.dcache.demand_mshr_miss_latency 3854000 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_rate 0.004635 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_misses 265 # number of demand (read+write) MSHR misses system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.dcache.occ_blocks::0 25.627740 # Average occupied blocks per context -system.cpu3.dcache.occ_blocks::1 -3.601472 # Average occupied blocks per context -system.cpu3.dcache.occ_percent::0 0.050054 # Average percentage of cache occupancy +system.cpu3.dcache.occ_blocks::0 25.684916 # Average occupied blocks per context +system.cpu3.dcache.occ_blocks::1 -3.601499 # Average occupied blocks per context +system.cpu3.dcache.occ_percent::0 0.050166 # Average percentage of cache occupancy system.cpu3.dcache.occ_percent::1 -0.007034 # Average percentage of cache occupancy -system.cpu3.dcache.overall_accesses 56189 # number of overall (read+write) accesses -system.cpu3.dcache.overall_avg_miss_latency 17095.419847 # average overall miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency 14095.419847 # average overall mshr miss latency +system.cpu3.dcache.overall_accesses 57168 # number of overall (read+write) accesses +system.cpu3.dcache.overall_avg_miss_latency 17543.396226 # average overall miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency 14543.396226 # average overall mshr miss latency system.cpu3.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu3.dcache.overall_hits 55927 # number of overall hits -system.cpu3.dcache.overall_miss_latency 4479000 # number of overall miss cycles -system.cpu3.dcache.overall_miss_rate 0.004663 # miss rate for overall accesses -system.cpu3.dcache.overall_misses 262 # number of overall misses +system.cpu3.dcache.overall_hits 56903 # number of overall hits +system.cpu3.dcache.overall_miss_latency 4649000 # number of overall miss cycles +system.cpu3.dcache.overall_miss_rate 0.004635 # miss rate for overall accesses +system.cpu3.dcache.overall_misses 265 # number of overall misses system.cpu3.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu3.dcache.overall_mshr_miss_latency 3693000 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_rate 0.004663 # mshr miss rate for overall accesses -system.cpu3.dcache.overall_mshr_misses 262 # number of overall MSHR misses +system.cpu3.dcache.overall_mshr_miss_latency 3854000 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_rate 0.004635 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_misses 265 # number of overall MSHR misses system.cpu3.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu3.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu3.dcache.replacements 2 # number of replacements -system.cpu3.dcache.sampled_refs 29 # Sample count of references to valid blocks. +system.cpu3.dcache.sampled_refs 32 # Sample count of references to valid blocks. system.cpu3.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu3.dcache.tagsinuse 22.026268 # Cycle average of tags in use -system.cpu3.dcache.total_refs 32498 # Total number of references to valid blocks. +system.cpu3.dcache.tagsinuse 22.083417 # Cycle average of tags in use +system.cpu3.dcache.total_refs 33474 # Total number of references to valid blocks. system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu3.dcache.writebacks 1 # number of writebacks -system.cpu3.icache.ReadReq_accesses 162202 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_avg_miss_latency 14391.364903 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_mshr_miss_latency 11391.364903 # average ReadReq mshr miss latency -system.cpu3.icache.ReadReq_hits 161843 # number of ReadReq hits -system.cpu3.icache.ReadReq_miss_latency 5166500 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_rate 0.002213 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_misses 359 # number of ReadReq misses -system.cpu3.icache.ReadReq_mshr_miss_latency 4089500 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_rate 0.002213 # mshr miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_mshr_misses 359 # number of ReadReq MSHR misses +system.cpu3.icache.ReadReq_accesses 166163 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_avg_miss_latency 15072.207084 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency 12072.207084 # average ReadReq mshr miss latency +system.cpu3.icache.ReadReq_hits 165796 # number of ReadReq hits +system.cpu3.icache.ReadReq_miss_latency 5531500 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_rate 0.002209 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_misses 367 # number of ReadReq misses +system.cpu3.icache.ReadReq_mshr_miss_latency 4430500 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_rate 0.002209 # mshr miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_mshr_misses 367 # number of ReadReq MSHR misses system.cpu3.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu3.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu3.icache.avg_refs 450.816156 # Average number of references to valid blocks. +system.cpu3.icache.avg_refs 451.760218 # Average number of references to valid blocks. system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.cache_copies 0 # number of cache copies performed -system.cpu3.icache.demand_accesses 162202 # number of demand (read+write) accesses -system.cpu3.icache.demand_avg_miss_latency 14391.364903 # average overall miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency 11391.364903 # average overall mshr miss latency -system.cpu3.icache.demand_hits 161843 # number of demand (read+write) hits -system.cpu3.icache.demand_miss_latency 5166500 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_rate 0.002213 # miss rate for demand accesses -system.cpu3.icache.demand_misses 359 # number of demand (read+write) misses +system.cpu3.icache.demand_accesses 166163 # number of demand (read+write) accesses +system.cpu3.icache.demand_avg_miss_latency 15072.207084 # average overall miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency 12072.207084 # average overall mshr miss latency +system.cpu3.icache.demand_hits 165796 # number of demand (read+write) hits +system.cpu3.icache.demand_miss_latency 5531500 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_rate 0.002209 # miss rate for demand accesses +system.cpu3.icache.demand_misses 367 # number of demand (read+write) misses system.cpu3.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu3.icache.demand_mshr_miss_latency 4089500 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_rate 0.002213 # mshr miss rate for demand accesses -system.cpu3.icache.demand_mshr_misses 359 # number of demand (read+write) MSHR misses +system.cpu3.icache.demand_mshr_miss_latency 4430500 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_rate 0.002209 # mshr miss rate for demand accesses +system.cpu3.icache.demand_mshr_misses 367 # number of demand (read+write) MSHR misses system.cpu3.icache.fast_writes 0 # number of fast writes performed system.cpu3.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.icache.occ_blocks::0 67.619703 # Average occupied blocks per context -system.cpu3.icache.occ_percent::0 0.132070 # Average percentage of cache occupancy -system.cpu3.icache.overall_accesses 162202 # number of overall (read+write) accesses -system.cpu3.icache.overall_avg_miss_latency 14391.364903 # average overall miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency 11391.364903 # average overall mshr miss latency +system.cpu3.icache.occ_blocks::0 67.737646 # Average occupied blocks per context +system.cpu3.icache.occ_percent::0 0.132300 # Average percentage of cache occupancy +system.cpu3.icache.overall_accesses 166163 # number of overall (read+write) accesses +system.cpu3.icache.overall_avg_miss_latency 15072.207084 # average overall miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency 12072.207084 # average overall mshr miss latency system.cpu3.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu3.icache.overall_hits 161843 # number of overall hits -system.cpu3.icache.overall_miss_latency 5166500 # number of overall miss cycles -system.cpu3.icache.overall_miss_rate 0.002213 # miss rate for overall accesses -system.cpu3.icache.overall_misses 359 # number of overall misses +system.cpu3.icache.overall_hits 165796 # number of overall hits +system.cpu3.icache.overall_miss_latency 5531500 # number of overall miss cycles +system.cpu3.icache.overall_miss_rate 0.002209 # miss rate for overall accesses +system.cpu3.icache.overall_misses 367 # number of overall misses system.cpu3.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu3.icache.overall_mshr_miss_latency 4089500 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_rate 0.002213 # mshr miss rate for overall accesses -system.cpu3.icache.overall_mshr_misses 359 # number of overall MSHR misses +system.cpu3.icache.overall_mshr_miss_latency 4430500 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_rate 0.002209 # mshr miss rate for overall accesses +system.cpu3.icache.overall_mshr_misses 367 # number of overall MSHR misses system.cpu3.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu3.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu3.icache.replacements 279 # number of replacements -system.cpu3.icache.sampled_refs 359 # Sample count of references to valid blocks. +system.cpu3.icache.replacements 281 # number of replacements +system.cpu3.icache.sampled_refs 367 # Sample count of references to valid blocks. system.cpu3.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu3.icache.tagsinuse 67.619703 # Cycle average of tags in use -system.cpu3.icache.total_refs 161843 # Total number of references to valid blocks. +system.cpu3.icache.tagsinuse 67.737646 # Cycle average of tags in use +system.cpu3.icache.total_refs 165796 # Total number of references to valid blocks. system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu3.icache.writebacks 0 # number of writebacks -system.cpu3.idle_fraction 0.131691 # Percentage of idle cycles -system.cpu3.not_idle_fraction 0.868309 # Percentage of non-idle cycles -system.cpu3.numCycles 513670 # number of cpu cycles simulated +system.cpu3.idle_fraction 0.131701 # Percentage of idle cycles +system.cpu3.not_idle_fraction 0.868299 # Percentage of non-idle cycles +system.cpu3.numCycles 524596 # number of cpu cycles simulated system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu3.num_busy_cycles 446024.068564 # Number of busy cycles +system.cpu3.num_busy_cycles 455505.998263 # Number of busy cycles system.cpu3.num_conditional_control_insts 0 # number of instructions that are conditional controls system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu3.num_fp_insts 0 # number of float instructions system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written system.cpu3.num_func_calls 0 # number of times a function call or return occured -system.cpu3.num_idle_cycles 67645.931436 # Number of idle cycles -system.cpu3.num_insts 162170 # Number of instructions executed -system.cpu3.num_int_alu_accesses 110096 # Number of integer alu accesses -system.cpu3.num_int_insts 110096 # number of integer instructions -system.cpu3.num_int_register_reads 281520 # number of times the integer registers were read -system.cpu3.num_int_register_writes 106379 # number of times the integer registers were written -system.cpu3.num_load_insts 40744 # Number of load instructions -system.cpu3.num_mem_refs 56264 # number of memory refs -system.cpu3.num_store_insts 15520 # Number of store instructions +system.cpu3.num_idle_cycles 69090.001737 # Number of idle cycles +system.cpu3.num_insts 166130 # Number of instructions executed +system.cpu3.num_int_alu_accesses 112098 # Number of integer alu accesses +system.cpu3.num_int_insts 112098 # number of integer instructions +system.cpu3.num_int_register_reads 286475 # number of times the integer registers were read +system.cpu3.num_int_register_writes 109360 # number of times the integer registers were written +system.cpu3.num_load_insts 41720 # Number of load instructions +system.cpu3.num_mem_refs 57243 # number of memory refs +system.cpu3.num_store_insts 15523 # Number of store instructions system.l2c.ReadExReq_accesses::0 99 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::1 13 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::2 12 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::3 12 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 136 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency::0 71434.343434 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::1 544000 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::2 589333.333333 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::3 589333.333333 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 1794101.010101 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_miss_latency 7072000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_accesses::1 15 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::2 14 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::3 14 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 142 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency::0 74595.959596 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::1 492333.333333 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::2 527500 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::3 527500 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 1621929.292929 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40007.042254 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_miss_latency 7385000 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::1 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::2 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::3 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::total 4 # miss rate for ReadExReq accesses system.l2c.ReadExReq_misses::0 99 # number of ReadExReq misses -system.l2c.ReadExReq_misses::1 13 # number of ReadExReq misses -system.l2c.ReadExReq_misses::2 12 # number of ReadExReq misses -system.l2c.ReadExReq_misses::3 12 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 136 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_miss_latency 5440000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_rate::0 1.373737 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::1 10.461538 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::2 11.333333 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::3 11.333333 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 34.501943 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 136 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_misses::1 15 # number of ReadExReq misses +system.l2c.ReadExReq_misses::2 14 # number of ReadExReq misses +system.l2c.ReadExReq_misses::3 14 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 142 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 5681000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_rate::0 1.434343 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::1 9.466667 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::2 10.142857 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::3 10.142857 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 31.186724 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_misses 142 # number of ReadExReq MSHR misses system.l2c.ReadReq_accesses::0 538 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 370 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::2 370 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::3 371 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1649 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency::0 63484.330484 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 332582.089552 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::2 3183285.714286 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::3 5570750 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 9150102.134322 # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 40007.092199 # average ReadReq mshr miss latency +system.l2c.ReadReq_accesses::1 379 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::2 379 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::3 380 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1676 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency::0 66467.236467 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 315270.270270 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::2 1666428.571429 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::3 2120909.090909 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 4169075.169075 # average ReadReq miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40006.976744 # average ReadReq mshr miss latency system.l2c.ReadReq_hits::0 187 # number of ReadReq hits -system.l2c.ReadReq_hits::1 303 # number of ReadReq hits -system.l2c.ReadReq_hits::2 363 # number of ReadReq hits -system.l2c.ReadReq_hits::3 367 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1220 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 22283000 # number of ReadReq miss cycles +system.l2c.ReadReq_hits::1 305 # number of ReadReq hits +system.l2c.ReadReq_hits::2 365 # number of ReadReq hits +system.l2c.ReadReq_hits::3 369 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1226 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 23330000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_rate::0 0.652416 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.181081 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::2 0.018919 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::3 0.010782 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.863198 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.195251 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::2 0.036939 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::3 0.028947 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.913554 # miss rate for ReadReq accesses system.l2c.ReadReq_misses::0 351 # number of ReadReq misses -system.l2c.ReadReq_misses::1 67 # number of ReadReq misses -system.l2c.ReadReq_misses::2 7 # number of ReadReq misses -system.l2c.ReadReq_misses::3 4 # number of ReadReq misses -system.l2c.ReadReq_misses::total 429 # number of ReadReq misses -system.l2c.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_miss_latency 16923000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.786245 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 1.143243 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::2 1.143243 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::3 1.140162 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 4.212894 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 423 # number of ReadReq MSHR misses +system.l2c.ReadReq_misses::1 74 # number of ReadReq misses +system.l2c.ReadReq_misses::2 14 # number of ReadReq misses +system.l2c.ReadReq_misses::3 11 # number of ReadReq misses +system.l2c.ReadReq_misses::total 450 # number of ReadReq misses +system.l2c.ReadReq_mshr_hits 20 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_miss_latency 17203000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.799257 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 1.134565 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::2 1.134565 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::3 1.131579 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 4.199965 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_misses 430 # number of ReadReq MSHR misses system.l2c.UpgradeReq_accesses::0 30 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::1 12 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::2 16 # number of UpgradeReq accesses(hits+misses) @@ -720,103 +720,103 @@ system.l2c.Writeback_hits::0 9 # nu system.l2c.Writeback_hits::total 9 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.l2c.avg_refs 2.850117 # Average number of references to valid blocks. +system.l2c.avg_refs 2.817972 # Average number of references to valid blocks. system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed system.l2c.demand_accesses::0 637 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 383 # number of demand (read+write) accesses -system.l2c.demand_accesses::2 382 # number of demand (read+write) accesses -system.l2c.demand_accesses::3 383 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1785 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency::0 65233.333333 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 366937.500000 # average overall miss latency -system.l2c.demand_avg_miss_latency::2 1545000 # average overall miss latency -system.l2c.demand_avg_miss_latency::3 1834687.500000 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 3811858.333333 # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 40005.366726 # average overall mshr miss latency +system.l2c.demand_accesses::1 394 # number of demand (read+write) accesses +system.l2c.demand_accesses::2 393 # number of demand (read+write) accesses +system.l2c.demand_accesses::3 394 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1818 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency::0 68255.555556 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 345112.359551 # average overall miss latency +system.l2c.demand_avg_miss_latency::2 1096964.285714 # average overall miss latency +system.l2c.demand_avg_miss_latency::3 1228600 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 2738932.200820 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency 40006.993007 # average overall mshr miss latency system.l2c.demand_hits::0 187 # number of demand (read+write) hits -system.l2c.demand_hits::1 303 # number of demand (read+write) hits -system.l2c.demand_hits::2 363 # number of demand (read+write) hits -system.l2c.demand_hits::3 367 # number of demand (read+write) hits -system.l2c.demand_hits::total 1220 # number of demand (read+write) hits -system.l2c.demand_miss_latency 29355000 # number of demand (read+write) miss cycles +system.l2c.demand_hits::1 305 # number of demand (read+write) hits +system.l2c.demand_hits::2 365 # number of demand (read+write) hits +system.l2c.demand_hits::3 369 # number of demand (read+write) hits +system.l2c.demand_hits::total 1226 # number of demand (read+write) hits +system.l2c.demand_miss_latency 30715000 # number of demand (read+write) miss cycles system.l2c.demand_miss_rate::0 0.706436 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.208877 # miss rate for demand accesses -system.l2c.demand_miss_rate::2 0.049738 # miss rate for demand accesses -system.l2c.demand_miss_rate::3 0.041775 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 1.006827 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.225888 # miss rate for demand accesses +system.l2c.demand_miss_rate::2 0.071247 # miss rate for demand accesses +system.l2c.demand_miss_rate::3 0.063452 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 1.067023 # miss rate for demand accesses system.l2c.demand_misses::0 450 # number of demand (read+write) misses -system.l2c.demand_misses::1 80 # number of demand (read+write) misses -system.l2c.demand_misses::2 19 # number of demand (read+write) misses -system.l2c.demand_misses::3 16 # number of demand (read+write) misses -system.l2c.demand_misses::total 565 # number of demand (read+write) misses -system.l2c.demand_mshr_hits 6 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 22363000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate::0 0.877551 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 1.459530 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::2 1.463351 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::3 1.459530 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 5.259962 # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 559 # number of demand (read+write) MSHR misses +system.l2c.demand_misses::1 89 # number of demand (read+write) misses +system.l2c.demand_misses::2 28 # number of demand (read+write) misses +system.l2c.demand_misses::3 25 # number of demand (read+write) misses +system.l2c.demand_misses::total 592 # number of demand (read+write) misses +system.l2c.demand_mshr_hits 20 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_miss_latency 22884000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate::0 0.897959 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 1.451777 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::2 1.455471 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::3 1.451777 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 5.256983 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 572 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_blocks::0 286.079338 # Average occupied blocks per context -system.l2c.occ_blocks::1 57.730266 # Average occupied blocks per context -system.l2c.occ_blocks::2 2.608262 # Average occupied blocks per context -system.l2c.occ_blocks::3 1.731871 # Average occupied blocks per context -system.l2c.occ_blocks::4 5.597892 # Average occupied blocks per context +system.l2c.occ_blocks::0 286.079543 # Average occupied blocks per context +system.l2c.occ_blocks::1 57.730360 # Average occupied blocks per context +system.l2c.occ_blocks::2 2.746586 # Average occupied blocks per context +system.l2c.occ_blocks::3 1.731874 # Average occupied blocks per context +system.l2c.occ_blocks::4 5.597896 # Average occupied blocks per context system.l2c.occ_percent::0 0.004365 # Average percentage of cache occupancy system.l2c.occ_percent::1 0.000881 # Average percentage of cache occupancy -system.l2c.occ_percent::2 0.000040 # Average percentage of cache occupancy +system.l2c.occ_percent::2 0.000042 # Average percentage of cache occupancy system.l2c.occ_percent::3 0.000026 # Average percentage of cache occupancy system.l2c.occ_percent::4 0.000085 # Average percentage of cache occupancy system.l2c.overall_accesses::0 637 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 383 # number of overall (read+write) accesses -system.l2c.overall_accesses::2 382 # number of overall (read+write) accesses -system.l2c.overall_accesses::3 383 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1785 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency::0 65233.333333 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 366937.500000 # average overall miss latency -system.l2c.overall_avg_miss_latency::2 1545000 # average overall miss latency -system.l2c.overall_avg_miss_latency::3 1834687.500000 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 3811858.333333 # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 40005.366726 # average overall mshr miss latency +system.l2c.overall_accesses::1 394 # number of overall (read+write) accesses +system.l2c.overall_accesses::2 393 # number of overall (read+write) accesses +system.l2c.overall_accesses::3 394 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1818 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency::0 68255.555556 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 345112.359551 # average overall miss latency +system.l2c.overall_avg_miss_latency::2 1096964.285714 # average overall miss latency +system.l2c.overall_avg_miss_latency::3 1228600 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 2738932.200820 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency 40006.993007 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.l2c.overall_hits::0 187 # number of overall hits -system.l2c.overall_hits::1 303 # number of overall hits -system.l2c.overall_hits::2 363 # number of overall hits -system.l2c.overall_hits::3 367 # number of overall hits -system.l2c.overall_hits::total 1220 # number of overall hits -system.l2c.overall_miss_latency 29355000 # number of overall miss cycles +system.l2c.overall_hits::1 305 # number of overall hits +system.l2c.overall_hits::2 365 # number of overall hits +system.l2c.overall_hits::3 369 # number of overall hits +system.l2c.overall_hits::total 1226 # number of overall hits +system.l2c.overall_miss_latency 30715000 # number of overall miss cycles system.l2c.overall_miss_rate::0 0.706436 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.208877 # miss rate for overall accesses -system.l2c.overall_miss_rate::2 0.049738 # miss rate for overall accesses -system.l2c.overall_miss_rate::3 0.041775 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 1.006827 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.225888 # miss rate for overall accesses +system.l2c.overall_miss_rate::2 0.071247 # miss rate for overall accesses +system.l2c.overall_miss_rate::3 0.063452 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 1.067023 # miss rate for overall accesses system.l2c.overall_misses::0 450 # number of overall misses -system.l2c.overall_misses::1 80 # number of overall misses -system.l2c.overall_misses::2 19 # number of overall misses -system.l2c.overall_misses::3 16 # number of overall misses -system.l2c.overall_misses::total 565 # number of overall misses -system.l2c.overall_mshr_hits 6 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 22363000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate::0 0.877551 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 1.459530 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::2 1.463351 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::3 1.459530 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 5.259962 # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 559 # number of overall MSHR misses +system.l2c.overall_misses::1 89 # number of overall misses +system.l2c.overall_misses::2 28 # number of overall misses +system.l2c.overall_misses::3 25 # number of overall misses +system.l2c.overall_misses::total 592 # number of overall misses +system.l2c.overall_mshr_hits 20 # number of overall MSHR hits +system.l2c.overall_mshr_miss_latency 22884000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate::0 0.897959 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 1.451777 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::2 1.455471 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::3 1.451777 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 5.256983 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 572 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.l2c.replacements 0 # number of replacements -system.l2c.sampled_refs 427 # Sample count of references to valid blocks. +system.l2c.sampled_refs 434 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 353.747628 # Cycle average of tags in use -system.l2c.total_refs 1217 # Total number of references to valid blocks. +system.l2c.tagsinuse 353.886259 # Cycle average of tags in use +system.l2c.total_refs 1223 # Total number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.l2c.writebacks 0 # number of writebacks |