diff options
| -rw-r--r-- | src/sim/serialize.hh | 2 | ||||
| -rwxr-xr-x | util/cpt_upgrader.py | 13 |
2 files changed, 14 insertions, 1 deletions
diff --git a/src/sim/serialize.hh b/src/sim/serialize.hh index e9de6f713..888dba614 100644 --- a/src/sim/serialize.hh +++ b/src/sim/serialize.hh @@ -59,7 +59,7 @@ class EventQueue; * SimObject shouldn't cause the version number to increase, only changes to * existing objects such as serializing/unserializing more state, changing sizes * of serialized arrays, etc. */ -static const uint64_t gem5CheckpointVersion = 0x000000000000000d; +static const uint64_t gem5CheckpointVersion = 0x000000000000000e; template <class T> void paramOut(std::ostream &os, const std::string &name, const T ¶m); diff --git a/util/cpt_upgrader.py b/util/cpt_upgrader.py index 66c671025..5d836a23d 100755 --- a/util/cpt_upgrader.py +++ b/util/cpt_upgrader.py @@ -602,6 +602,18 @@ def from_C(cpt): cpt.set(sec, 'intRegs', ' '.join(intRegs)) cpt.set(sec, 'ccRegs', ' '.join(ccRegs)) +# Checkpoint version E adds the ARM CONTEXTIDR_EL2 miscreg. +def from_D(cpt): + if cpt.get('root','isa') == 'arm': + for sec in cpt.sections(): + import re + # Search for all ISA sections + if re.search('.*sys.*\.cpu.*\.isa$', sec): + miscRegs = cpt.get(sec, 'miscRegs').split() + # CONTEXTIDR_EL2 defaults to 0b11111100000000000001 + miscRegs[599:599] = [0xFC001] + cpt.set(sec, 'miscRegs', ' '.join(str(x) for x in miscRegs)) + migrations = [] migrations.append(from_0) migrations.append(from_1) @@ -616,6 +628,7 @@ migrations.append(from_9) migrations.append(from_A) migrations.append(from_B) migrations.append(from_C) +migrations.append(from_D) verbose_print = False |