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-rw-r--r--arch/alpha/alpha_memory.cc13
-rw-r--r--base/range.hh51
-rw-r--r--base/remote_gdb.cc2
-rw-r--r--cpu/memtest/memtest.cc51
-rw-r--r--cpu/memtest/memtest.hh2
-rw-r--r--dev/alpha_access.h2
-rw-r--r--dev/alpha_console.cc28
-rw-r--r--dev/alpha_console.hh19
8 files changed, 110 insertions, 58 deletions
diff --git a/arch/alpha/alpha_memory.cc b/arch/alpha/alpha_memory.cc
index 0f9ad2cfc..00e97250f 100644
--- a/arch/alpha/alpha_memory.cc
+++ b/arch/alpha/alpha_memory.cc
@@ -90,8 +90,17 @@ AlphaTlb::checkCacheability(MemReqPtr &req)
if (req->paddr & PA_UNCACHED_BIT) {
if (PA_IPR_SPACE(req->paddr)) {
// IPR memory space not implemented
- if (!req->xc->misspeculating())
- panic("IPR memory space not implemented! PA=%x\n", req->paddr);
+ if (!req->xc->misspeculating()) {
+ switch (req->paddr) {
+ case 0xFFFFF00188:
+ req->data = 0;
+ break;
+
+ default:
+ panic("IPR memory space not implemented! PA=%x\n",
+ req->paddr);
+ }
+ }
} else {
// mark request as uncacheable
req->flags |= UNCACHEABLE;
diff --git a/base/range.hh b/base/range.hh
index 34bd34136..d72aa9755 100644
--- a/base/range.hh
+++ b/base/range.hh
@@ -62,6 +62,10 @@ struct Range
invalidate();
}
+ Range(T first, T second)
+ : start(first), end(second)
+ {}
+
template <class U>
Range(const Range<U> &r)
: start(r.start), end(r.end)
@@ -100,11 +104,18 @@ struct Range
}
void invalidate() { start = 0; end = 0; }
- bool size() const { return end - start; }
+ T size() const { return end - start; }
bool valid() const { return start < end; }
};
-template<class T>
+template <class T>
+inline Range<T>
+make_range(T start, T end)
+{
+ return Range<T>(start, end);
+}
+
+template <class T>
inline std::ostream &
operator<<(std::ostream &o, const Range<T> &r)
{
@@ -124,7 +135,7 @@ operator<<(std::ostream &o, const Range<T> &r)
* @param range2 is a range.
* @return if range1 and range2 are identical.
*/
-template<class T, class U>
+template <class T, class U>
inline bool
operator==(const Range<T> &range1, const Range<U> &range2)
{
@@ -137,7 +148,7 @@ operator==(const Range<T> &range1, const Range<U> &range2)
* @param range2 is a range.
* @return if range1 and range2 are not identical.
*/
-template<class T, class U>
+template <class T, class U>
inline bool
operator!=(const Range<T> &range1, const Range<U> &range2)
{
@@ -150,7 +161,7 @@ operator!=(const Range<T> &range1, const Range<U> &range2)
* @param range2 is a range.
* @return if range1 is less than range2 and does not overlap range1.
*/
-template<class T, class U>
+template <class T, class U>
inline bool
operator<(const Range<T> &range1, const Range<U> &range2)
{
@@ -164,7 +175,7 @@ operator<(const Range<T> &range1, const Range<U> &range2)
* @return if range1 is less than range2. range1 may overlap range2,
* but not extend beyond the end of range2.
*/
-template<class T, class U>
+template <class T, class U>
inline bool
operator<=(const Range<T> &range1, const Range<U> &range2)
{
@@ -177,7 +188,7 @@ operator<=(const Range<T> &range1, const Range<U> &range2)
* @param range2 is a range.
* @return if range1 is greater than range2 and does not overlap range2.
*/
-template<class T, class U>
+template <class T, class U>
inline bool
operator>(const Range<T> &range1, const Range<U> &range2)
{
@@ -191,7 +202,7 @@ operator>(const Range<T> &range1, const Range<U> &range2)
* @return if range1 is greater than range2. range1 may overlap range2,
* but not extend beyond the beginning of range2.
*/
-template<class T, class U>
+template <class T, class U>
inline bool
operator>=(const Range<T> &range1, const Range<U> &range2)
{
@@ -209,7 +220,7 @@ operator>=(const Range<T> &range1, const Range<U> &range2)
* @param range range compared against.
* @return indicates that position pos is within the range.
*/
-template<class T, class U>
+template <class T, class U>
inline bool
operator==(const T &pos, const Range<U> &range)
{
@@ -222,7 +233,7 @@ operator==(const T &pos, const Range<U> &range)
* @param range range compared against.
* @return indicates that position pos is not within the range.
*/
-template<class T, class U>
+template <class T, class U>
inline bool
operator!=(const T &pos, const Range<U> &range)
{
@@ -235,7 +246,7 @@ operator!=(const T &pos, const Range<U> &range)
* @param range range compared against.
* @return indicates that position pos is below the range.
*/
-template<class T, class U>
+template <class T, class U>
inline bool
operator<(const T &pos, const Range<U> &range)
{
@@ -248,7 +259,7 @@ operator<(const T &pos, const Range<U> &range)
* @param range range compared against.
* @return indicates that position pos is below or in the range.
*/
-template<class T, class U>
+template <class T, class U>
inline bool
operator<=(const T &pos, const Range<U> &range)
{
@@ -261,7 +272,7 @@ operator<=(const T &pos, const Range<U> &range)
* @param range range compared against.
* @return indicates that position pos is above the range.
*/
-template<class T, class U>
+template <class T, class U>
inline bool
operator>(const T &pos, const Range<U> &range)
{
@@ -274,7 +285,7 @@ operator>(const T &pos, const Range<U> &range)
* @param range range compared against.
* @return indicates that position pos is above or in the range.
*/
-template<class T, class U>
+template <class T, class U>
inline bool
operator>=(const T &pos, const Range<U> &range)
{
@@ -292,7 +303,7 @@ operator>=(const T &pos, const Range<U> &range)
* @param pos position compared to the range.
* @return indicates that position pos is within the range.
*/
-template<class T, class U>
+template <class T, class U>
inline bool
operator==(const Range<T> &range, const U &pos)
{
@@ -305,7 +316,7 @@ operator==(const Range<T> &range, const U &pos)
* @param pos position compared to the range.
* @return indicates that position pos is not within the range.
*/
-template<class T, class U>
+template <class T, class U>
inline bool
operator!=(const Range<T> &range, const U &pos)
{
@@ -318,7 +329,7 @@ operator!=(const Range<T> &range, const U &pos)
* @param pos position compared to the range.
* @return indicates that position pos is above the range.
*/
-template<class T, class U>
+template <class T, class U>
inline bool
operator<(const Range<T> &range, const U &pos)
{
@@ -331,7 +342,7 @@ operator<(const Range<T> &range, const U &pos)
* @param pos position compared to the range.
* @return indicates that position pos is above or in the range.
*/
-template<class T, class U>
+template <class T, class U>
inline bool
operator<=(const Range<T> &range, const U &pos)
{
@@ -344,7 +355,7 @@ operator<=(const Range<T> &range, const U &pos)
* @param pos position compared to the range.
* 'range > pos' indicates that position pos is below the range.
*/
-template<class T, class U>
+template <class T, class U>
inline bool
operator>(const Range<T> &range, const U &pos)
{
@@ -357,7 +368,7 @@ operator>(const Range<T> &range, const U &pos)
* @param pos position compared to the range.
* 'range >= pos' indicates that position pos is below or in the range.
*/
-template<class T, class U>
+template <class T, class U>
inline bool
operator>=(const Range<T> &range, const U &pos)
{
diff --git a/base/remote_gdb.cc b/base/remote_gdb.cc
index e701b5a01..e20800d12 100644
--- a/base/remote_gdb.cc
+++ b/base/remote_gdb.cc
@@ -338,7 +338,7 @@ RemoteGDB::acc(Addr va, size_t len)
}
if (va < ALPHA_K1SEG_BASE) {
- if (va < (ALPHA_K0SEG_BASE + pmem->getSize())) {
+ if (va < (ALPHA_K0SEG_BASE + pmem->size())) {
DPRINTF(GDBAcc, "acc: Mapping is valid K0SEG <= "
"%#x < K0SEG + size\n", va);
return true;
diff --git a/cpu/memtest/memtest.cc b/cpu/memtest/memtest.cc
index 4ec5eed59..05de370fd 100644
--- a/cpu/memtest/memtest.cc
+++ b/cpu/memtest/memtest.cc
@@ -50,6 +50,7 @@ MemTest::MemTest(const string &name,
FunctionalMemory *check_mem,
unsigned _memorySize,
unsigned _percentReads,
+ unsigned _percentCopies,
unsigned _percentUncacheable,
unsigned _progressInterval,
Addr _traceAddr,
@@ -62,6 +63,7 @@ MemTest::MemTest(const string &name,
checkMem(check_mem),
size(_memorySize),
percentReads(_percentReads),
+ percentCopies(_percentCopies),
percentUncacheable(_percentUncacheable),
progressInterval(_progressInterval),
nextProgressMessage(_progressInterval)
@@ -149,15 +151,18 @@ MemTest::completeRequest(MemReqPtr &req, uint8_t *data)
numWrites++;
break;
+ case Copy:
+ break;
default:
panic("invalid command");
}
if (blockAddr(req->paddr) == traceBlockAddr) {
- cerr << name() << ": completed "
- << (req->cmd.isWrite() ? "write" : "read") << " access of "
- << req->size << " bytes at address 0x"
+ cerr << hex << traceBlockAddr << ": " << name() << ": completed "
+ << (req->cmd.isWrite() ? "write" : "read")
+ << " access of "
+ << dec << req->size << " bytes at address 0x"
<< hex << req->paddr << ", value = 0x";
printData(cerr, req->data, req->size);
cerr << " @ cycle " << dec << curTick;
@@ -209,6 +214,7 @@ MemTest::tick()
//make new request
unsigned cmd = rand() % 100;
unsigned offset1 = random() % size;
+ unsigned offset2 = random() % size;
unsigned base = random() % 2;
uint64_t data = random();
unsigned access_size = random() % 4;
@@ -237,9 +243,10 @@ MemTest::tick()
uint8_t *result = new uint8_t[8];
checkMem->access(Read, req->paddr, result, req->size);
if (blockAddr(req->paddr) == traceBlockAddr) {
- cerr << name() << ": initiating read "
+ cerr << hex << traceBlockAddr << ": " << name()
+ << ": initiating read "
<< ((probe)?"probe of ":"access of ")
- << req->size << " bytes from addr 0x"
+ << dec << req->size << " bytes from addr 0x"
<< hex << req->paddr << " at cycle "
<< dec << curTick << endl;
}
@@ -250,15 +257,16 @@ MemTest::tick()
req->completionEvent = new MemCompleteEvent(req, result, this);
cacheInterface->access(req);
}
- } else {
+ } else if (cmd < (100 - percentCopies)){
// write
req->cmd = Write;
memcpy(req->data, &data, req->size);
checkMem->access(Write, req->paddr, req->data, req->size);
if (blockAddr(req->paddr) == traceBlockAddr) {
- cerr << name() << ": initiating write "
+ cerr << hex << traceBlockAddr << ": "
+ << name() << ": initiating write "
<< ((probe)?"probe of ":"access of ")
- << req->size << " bytes (value = 0x";
+ << dec << req->size << " bytes (value = 0x";
printData(cerr, req->data, req->size);
cerr << ") to addr 0x"
<< hex << req->paddr << " at cycle "
@@ -271,6 +279,29 @@ MemTest::tick()
req->completionEvent = new MemCompleteEvent(req, NULL, this);
cacheInterface->access(req);
}
+ } else {
+ // copy
+ Addr source = blockAddr(((base) ? baseAddr1 : baseAddr2) + offset1);
+ Addr dest = blockAddr(((base) ? baseAddr2 : baseAddr1) + offset2);
+ req->cmd = Copy;
+ req->flags &= ~UNCACHEABLE;
+ req->paddr = source;
+ req->dest = dest;
+ delete [] req->data;
+ req->data = new uint8_t[blockSize];
+ req->size = blockSize;
+ if (source == traceBlockAddr || dest == traceBlockAddr) {
+ cerr << hex << traceBlockAddr << ": " << name()
+ << ": initiating copy of "
+ << dec << req->size << " bytes from addr 0x"
+ << hex << source << " to addr 0x"
+ << hex << dest << " at cycle "
+ << dec << curTick << endl;
+ }
+ cacheInterface->access(req);
+ uint8_t result[blockSize];
+ checkMem->access(Read, source, &result, blockSize);
+ checkMem->access(Write, dest, &result, blockSize);
}
}
@@ -297,6 +328,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(MemTest)
SimObjectParam<FunctionalMemory *> check_mem;
Param<unsigned> memory_size;
Param<unsigned> percent_reads;
+ Param<unsigned> percent_copies;
Param<unsigned> percent_uncacheable;
Param<unsigned> progress_interval;
Param<Addr> trace_addr;
@@ -313,6 +345,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(MemTest)
INIT_PARAM(check_mem, "check memory"),
INIT_PARAM_DFLT(memory_size, "memory size", 65536),
INIT_PARAM_DFLT(percent_reads, "target read percentage", 65),
+ INIT_PARAM_DFLT(percent_copies, "target copy percentage", 0),
INIT_PARAM_DFLT(percent_uncacheable, "target uncacheable percentage", 10),
INIT_PARAM_DFLT(progress_interval,
"progress report interval (in accesses)", 1000000),
@@ -330,7 +363,7 @@ END_INIT_SIM_OBJECT_PARAMS(MemTest)
CREATE_SIM_OBJECT(MemTest)
{
return new MemTest(getInstanceName(), cache->getInterface(), main_mem,
- check_mem, memory_size, percent_reads,
+ check_mem, memory_size, percent_reads, percent_copies,
percent_uncacheable, progress_interval,
trace_addr, max_loads_any_thread,
max_loads_all_threads);
diff --git a/cpu/memtest/memtest.hh b/cpu/memtest/memtest.hh
index 09f22a177..d3ac020fd 100644
--- a/cpu/memtest/memtest.hh
+++ b/cpu/memtest/memtest.hh
@@ -48,6 +48,7 @@ class MemTest : public BaseCPU
FunctionalMemory *check_mem,
unsigned _memorySize,
unsigned _percentReads,
+ unsigned _percentCopies,
unsigned _percentUncacheable,
unsigned _progressInterval,
Addr _traceAddr,
@@ -81,6 +82,7 @@ class MemTest : public BaseCPU
unsigned size; // size of testing memory region
unsigned percentReads; // target percentage of read accesses
+ unsigned percentCopies; // target percentage of copy accesses
unsigned percentUncacheable;
unsigned blockSize;
diff --git a/dev/alpha_access.h b/dev/alpha_access.h
index 7502635e9..40567e96f 100644
--- a/dev/alpha_access.h
+++ b/dev/alpha_access.h
@@ -36,7 +36,7 @@
#define ALPHA_ACCESS_VERSION (1301) /* CH++*/
#ifndef CONSOLE
-#include <ostream>
+#include <iosfwd>
#include <string>
class Checkpoint;
#endif
diff --git a/dev/alpha_console.cc b/dev/alpha_console.cc
index e708be514..2dc939b97 100644
--- a/dev/alpha_console.cc
+++ b/dev/alpha_console.cc
@@ -49,12 +49,13 @@
using namespace std;
-AlphaConsole::AlphaConsole(const string &name, SimConsole *cons,
- SimpleDisk *d, int size, System *system,
- BaseCPU *cpu, TlaserClock *clock, int num_cpus,
- Addr addr, Addr mask, MemoryController *mmu)
- : MmapDevice(name, addr, mask, mmu), disk(d), console(cons)
+AlphaConsole::AlphaConsole(const string &name, SimConsole *cons, SimpleDisk *d,
+ System *system, BaseCPU *cpu, TlaserClock *clock,
+ int num_cpus, MemoryController *mmu, Addr a)
+ : FunctionalMemory(name), disk(d), console(cons), addr(a)
{
+ mmu->add_child(this, Range<Addr>(addr, addr + size));
+
consoleData = new uint8_t[size];
memset(consoleData, 0, size);
@@ -65,7 +66,7 @@ AlphaConsole::AlphaConsole(const string &name, SimConsole *cons,
alphaAccess->version = ALPHA_ACCESS_VERSION;
alphaAccess->numCPUs = num_cpus;
- alphaAccess->mem_size = system->physmem->getSize();
+ alphaAccess->mem_size = system->physmem->size();
alphaAccess->cpuClock = cpu->getFreq() / 1000000;
alphaAccess->intrClockFrequency = clock->frequency();
@@ -78,7 +79,8 @@ AlphaConsole::read(MemReqPtr &req, uint8_t *data)
memset(data, 0, req->size);
uint64_t val;
- Addr daddr = req->paddr & addr_mask;
+ Addr daddr = req->paddr - addr;
+
switch (daddr) {
case offsetof(AlphaAccess, inputChar):
val = console->console_in();
@@ -125,7 +127,7 @@ AlphaConsole::write(MemReqPtr &req, const uint8_t *data)
return Machine_Check_Fault;
}
- Addr daddr = req->paddr & addr_mask;
+ Addr daddr = req->paddr - addr;
ExecContext *other_xc;
switch (daddr) {
@@ -243,11 +245,9 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaConsole)
SimObjectParam<SimConsole *> sim_console;
SimObjectParam<SimpleDisk *> disk;
- Param<int> size;
Param<int> num_cpus;
SimObjectParam<MemoryController *> mmu;
Param<Addr> addr;
- Param<Addr> mask;
SimObjectParam<System *> system;
SimObjectParam<BaseCPU *> cpu;
SimObjectParam<TlaserClock *> clock;
@@ -258,11 +258,9 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaConsole)
INIT_PARAM(sim_console, "The Simulator Console"),
INIT_PARAM(disk, "Simple Disk"),
- INIT_PARAM_DFLT(size, "AlphaConsole size", sizeof(AlphaAccess)),
INIT_PARAM_DFLT(num_cpus, "Number of CPU's", 1),
INIT_PARAM(mmu, "Memory Controller"),
INIT_PARAM(addr, "Device Address"),
- INIT_PARAM(mask, "Address Mask"),
INIT_PARAM(system, "system object"),
INIT_PARAM(cpu, "Processor"),
INIT_PARAM(clock, "Turbolaser Clock")
@@ -271,10 +269,8 @@ END_INIT_SIM_OBJECT_PARAMS(AlphaConsole)
CREATE_SIM_OBJECT(AlphaConsole)
{
- return new AlphaConsole(getInstanceName(), sim_console,
- disk, size, system,
- cpu, clock, num_cpus,
- addr, mask, mmu);
+ return new AlphaConsole(getInstanceName(), sim_console, disk,
+ system, cpu, clock, num_cpus, mmu, addr);
}
REGISTER_SIM_OBJECT("AlphaConsole", AlphaConsole)
diff --git a/dev/alpha_console.hh b/dev/alpha_console.hh
index c39b8e8d4..54a2af6d5 100644
--- a/dev/alpha_console.hh
+++ b/dev/alpha_console.hh
@@ -33,9 +33,10 @@
#ifndef __ALPHA_CONSOLE_HH__
#define __ALPHA_CONSOLE_HH__
-#include "sim/host.hh"
+#include "base/range.hh"
#include "dev/alpha_access.h"
-#include "mem/functional_mem/mmap_device.hh"
+#include "mem/functional_mem/functional_memory.hh"
+#include "sim/host.hh"
class BaseCPU;
class SimConsole;
@@ -68,7 +69,7 @@ class SimpleDisk;
* primarily used doing boot before the kernel has loaded its device
* drivers.
*/
-class AlphaConsole : public MmapDevice
+class AlphaConsole : public FunctionalMemory
{
protected:
union {
@@ -82,15 +83,15 @@ class AlphaConsole : public MmapDevice
/** the system console (the terminal) is accessable from the console */
SimConsole *console;
+ Addr addr;
+ static const Addr size = 0x80; // equal to sizeof(alpha_access);
+
public:
/** Standard Constructor */
- AlphaConsole(const std::string &name, SimConsole *cons,
- SimpleDisk *d, int size,
- System *system, BaseCPU *cpu,
- TlaserClock *clock, int num_cpus,
- Addr addr, Addr mask, MemoryController *mmu);
+ AlphaConsole(const std::string &name, SimConsole *cons, SimpleDisk *d,
+ System *system, BaseCPU *cpu, TlaserClock *clock,
+ int num_cpus, MemoryController *mmu, Addr addr);
- public:
/**
* memory mapped reads and writes
*/
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-07 16:02:00 +0000