diff options
31 files changed, 1854 insertions, 692 deletions
diff --git a/arch/alpha/isa_traits.hh b/arch/alpha/isa_traits.hh index 842eea05a..65c72115b 100644 --- a/arch/alpha/isa_traits.hh +++ b/arch/alpha/isa_traits.hh @@ -98,12 +98,12 @@ extern const int reg_redir[NumIntRegs]; // return value itself in the standard return value reg (v0). if (return_value.successful()) { // no error - regs->intRegFile[SyscallSuccessReg] = 0; - regs->intRegFile[ReturnValueReg] = return_value.value(); + regs->setIntReg(SyscallSuccessReg, 0); + regs->setIntReg(ReturnValueReg, return_value.value()); } else { // got an error, return details - regs->intRegFile[SyscallSuccessReg] = (IntReg) -1; - regs->intRegFile[ReturnValueReg] = -return_value.value(); + regs->setIntReg(SyscallSuccessReg, (IntReg)-1); + regs->setIntReg(ReturnValueReg, -return_value.value()); } } #endif diff --git a/arch/alpha/regfile.hh b/arch/alpha/regfile.hh index 8a11a8eb6..af01b7829 100644 --- a/arch/alpha/regfile.hh +++ b/arch/alpha/regfile.hh @@ -38,61 +38,38 @@ class ExecContext; namespace AlphaISA { - - typedef IntReg IntRegFile[NumIntRegs]; - - class FloatRegFile + class IntRegFile { protected: - - union { - uint64_t q[NumFloatRegs]; // integer qword view - double d[NumFloatRegs]; // double-precision floating point view - }; + IntReg regs[NumIntRegs]; public: - FloatReg readReg(int floatReg) + IntReg readReg(int intReg) { - return d[floatReg]; + return regs[intReg]; } - FloatReg readReg(int floatReg, int width) + Fault setReg(int intReg, const IntReg &val) { - return readReg(floatReg); - } - - FloatRegBits readRegBits(int floatReg) - { - return q[floatReg]; + regs[intReg] = val; + return NoFault; } - FloatRegBits readRegBits(int floatReg, int width) - { - return readRegBits(floatReg); - } + void serialize(std::ostream &os); - Fault setReg(int floatReg, const FloatReg &val) - { - d[floatReg] = val; - return NoFault; - } + void unserialize(Checkpoint *cp, const std::string §ion); - Fault setReg(int floatReg, const FloatReg &val, int width) - { - return setReg(floatReg, val); - } + }; - Fault setRegBits(int floatReg, const FloatRegBits &val) - { - q[floatReg] = val; - return NoFault; - } + class FloatRegFile + { + public: - Fault setRegBits(int floatReg, const FloatRegBits &val, int width) - { - return setRegBits(floatReg, val); - } + union { + uint64_t q[NumFloatRegs]; // integer qword view + double d[NumFloatRegs]; // double-precision floating point view + }; void serialize(std::ostream &os); @@ -110,17 +87,18 @@ namespace AlphaISA public: MiscReg readReg(int misc_reg); + MiscReg readRegWithEffect(int misc_reg, Fault &fault, + ExecContext *xc); + //These functions should be removed once the simplescalar cpu model //has been replaced. int getInstAsid(); int getDataAsid(); - MiscReg readRegWithEffect(int misc_reg, Fault &fault, ExecContext *xc); - Fault setReg(int misc_reg, const MiscReg &val); Fault setRegWithEffect(int misc_reg, const MiscReg &val, - ExecContext *xc); + ExecContext *xc); #if FULL_SYSTEM protected: @@ -136,24 +114,156 @@ namespace AlphaISA friend class RegFile; }; - struct RegFile { - IntRegFile intRegFile; // (signed) integer register file - FloatRegFile floatRegFile; // floating point register file - MiscRegFile miscRegs; // control register file + class RegFile { + + protected: Addr pc; // program counter Addr npc; // next-cycle program counter Addr nnpc; + public: + Addr readPC() + { + return pc; + } + + void setPC(Addr val) + { + pc = val; + } + + Addr readNextPC() + { + return npc; + } + + void setNextPC(Addr val) + { + npc = val; + } + + Addr readNextNPC() + { + return nnpc; + } + + void setNextNPC(Addr val) + { + nnpc = val; + } + + protected: + IntRegFile intRegFile; // (signed) integer register file + FloatRegFile floatRegFile; // floating point register file + MiscRegFile miscRegFile; // control register file + + public: + #if FULL_SYSTEM int intrflag; // interrupt flag inline int instAsid() - { return miscRegs.getInstAsid(); } + { return miscRegFile.getInstAsid(); } inline int dataAsid() - { return miscRegs.getDataAsid(); } + { return miscRegFile.getDataAsid(); } #endif // FULL_SYSTEM + void clear() + { + bzero(&intRegFile, sizeof(intRegFile)); + bzero(&floatRegFile, sizeof(floatRegFile)); + bzero(&miscRegFile, sizeof(miscRegFile)); + } + + MiscReg readMiscReg(int miscReg) + { + return miscRegFile.readReg(miscReg); + } + + MiscReg readMiscRegWithEffect(int miscReg, + Fault &fault, ExecContext *xc) + { + fault = NoFault; + return miscRegFile.readRegWithEffect(miscReg, fault, xc); + } + + Fault setMiscReg(int miscReg, const MiscReg &val) + { + return miscRegFile.setReg(miscReg, val); + } + + Fault setMiscRegWithEffect(int miscReg, const MiscReg &val, + ExecContext * xc) + { + return miscRegFile.setRegWithEffect(miscReg, val, xc); + } + + FloatReg readFloatReg(int floatReg) + { + return floatRegFile.d[floatReg]; + } + + FloatReg readFloatReg(int floatReg, int width) + { + return readFloatReg(floatReg); + } + + FloatRegBits readFloatRegBits(int floatReg) + { + return floatRegFile.q[floatReg]; + } + + FloatRegBits readFloatRegBits(int floatReg, int width) + { + return readFloatRegBits(floatReg); + } + + Fault setFloatReg(int floatReg, const FloatReg &val) + { + floatRegFile.d[floatReg] = val; + return NoFault; + } + + Fault setFloatReg(int floatReg, const FloatReg &val, int width) + { + return setFloatReg(floatReg, val); + } + + Fault setFloatRegBits(int floatReg, const FloatRegBits &val) + { + floatRegFile.q[floatReg] = val; + return NoFault; + } + + Fault setFloatRegBits(int floatReg, const FloatRegBits &val, int width) + { + return setFloatRegBits(floatReg, val); + } + + IntReg readIntReg(int intReg) + { + return intRegFile.readReg(intReg); + } + + Fault setIntReg(int intReg, const IntReg &val) + { + return intRegFile.setReg(intReg, val); + } + void serialize(std::ostream &os); void unserialize(Checkpoint *cp, const std::string §ion); + + enum ContextParam + { + CONTEXT_PALMODE + }; + + typedef bool ContextVal; + + void changeContext(ContextParam param, ContextVal val) + { + //This would be an alternative place to call/implement + //the swapPALShadow function + } }; void copyRegs(ExecContext *src, ExecContext *dest); diff --git a/arch/isa_parser.py b/arch/isa_parser.py index 6fce783b1..8279a6a5d 100755 --- a/arch/isa_parser.py +++ b/arch/isa_parser.py @@ -1618,13 +1618,27 @@ opClassRE = re.compile(r'.*Op|No_OpClass') class InstObjParams: def __init__(self, mnem, class_name, base_class = '', - code_block = None, opt_args = []): + code = None, opt_args = [], *extras): self.mnemonic = mnem self.class_name = class_name self.base_class = base_class - if code_block: - for code_attr in code_block.__dict__.keys(): - setattr(self, code_attr, getattr(code_block, code_attr)) + if code: + #If the user already made a CodeBlock, pick the parts from it + if isinstance(code, CodeBlock): + origCode = code.orig_code + codeBlock = code + else: + origCode = code + codeBlock = CodeBlock(code) + compositeCode = '\n'.join([origCode] + + [pair[1] for pair in extras]) + compositeBlock = CodeBlock(compositeCode) + for code_attr in compositeBlock.__dict__.keys(): + setattr(self, code_attr, getattr(compositeBlock, code_attr)) + for (key, snippet) in extras: + setattr(self, key, CodeBlock(snippet).code) + self.code = codeBlock.code + self.orig_code = origCode else: self.constructor = '' self.flags = [] diff --git a/arch/mips/isa_traits.cc b/arch/mips/isa_traits.cc index 849d3311d..c6cfb2a0f 100644 --- a/arch/mips/isa_traits.cc +++ b/arch/mips/isa_traits.cc @@ -275,9 +275,21 @@ RoundPage(Addr addr) { return (addr + MipsISA::PageBytes - 1) & ~(MipsISA::PageBytes - 1); } void +IntRegFile::serialize(std::ostream &os) +{ + SERIALIZE_ARRAY(regs, NumIntRegs); +} + +void +IntRegFile::unserialize(Checkpoint *cp, const std::string §ion) +{ + UNSERIALIZE_ARRAY(regs, NumIntRegs); +} + +void RegFile::serialize(std::ostream &os) { - SERIALIZE_ARRAY(intRegFile, NumIntRegs); + intRegFile.serialize(os); //SERIALIZE_ARRAY(floatRegFile.q, NumFloatRegs); //SERIALIZE_SCALAR(miscRegs.fpcr); //SERIALIZE_SCALAR(miscRegs.uniq); @@ -298,7 +310,7 @@ RegFile::serialize(std::ostream &os) void RegFile::unserialize(Checkpoint *cp, const std::string §ion) { - UNSERIALIZE_ARRAY(intRegFile, NumIntRegs); + intRegFile.unserialize(cp, section); //UNSERIALIZE_ARRAY(floatRegFile.q, NumFloatRegs); //UNSERIALIZE_SCALAR(miscRegs.fpcr); //UNSERIALIZE_SCALAR(miscRegs.uniq); diff --git a/arch/mips/isa_traits.hh b/arch/mips/isa_traits.hh index 486a5d130..35c207828 100644 --- a/arch/mips/isa_traits.hh +++ b/arch/mips/isa_traits.hh @@ -43,7 +43,6 @@ class Checkpoint; class ExecContext; namespace LittleEndianGuest {}; -using namespace LittleEndianGuest; #define TARGET_MIPS @@ -92,6 +91,8 @@ class SyscallReturn { namespace MipsISA { + using namespace LittleEndianGuest; + typedef uint32_t MachInst; typedef uint32_t MachInst; typedef uint64_t ExtMachInst; @@ -163,7 +164,29 @@ namespace MipsISA }; typedef uint64_t IntReg; - typedef IntReg IntRegFile[NumIntRegs]; + + class IntRegFile + { + protected: + IntReg regs[NumIntRegs]; + + public: + IntReg readReg(int intReg) + { + return regs[intReg]; + } + + Fault setReg(int intReg, const IntReg &val) + { + regs[intReg] = val; + return NoFault; + } + + void serialize(std::ostream &os); + + void unserialize(Checkpoint *cp, const std::string §ion); + + }; /* floating point register file entry type typedef union { @@ -483,17 +506,130 @@ extern const Addr PageOffset; MiscReg ctrlreg; } AnyReg; - struct RegFile { + class RegFile { + protected: IntRegFile intRegFile; // (signed) integer register file FloatRegFile floatRegFile; // floating point register file - MiscRegFile miscRegs; // control register file + MiscRegFile miscRegFile; // control register file + + public: + + void clear() + { + bzero(&intRegFile, sizeof(intRegFile)); + bzero(&floatRegFile, sizeof(floatRegFile)); + bzero(&miscRegFile, sizeof(miscRegFile)); + } + + MiscReg readMiscReg(int miscReg) + { + return miscRegFile.readReg(miscReg); + } + + MiscReg readMiscRegWithEffect(int miscReg, + Fault &fault, ExecContext *xc) + { + fault = NoFault; + return miscRegFile.readRegWithEffect(miscReg, fault, xc); + } + + Fault setMiscReg(int miscReg, const MiscReg &val) + { + return miscRegFile.setReg(miscReg, val); + } + + Fault setMiscRegWithEffect(int miscReg, const MiscReg &val, + ExecContext * xc) + { + return miscRegFile.setRegWithEffect(miscReg, val, xc); + } + + FloatReg readFloatReg(int floatReg) + { + return floatRegFile.readReg(floatReg); + } + + FloatReg readFloatReg(int floatReg, int width) + { + return readFloatReg(floatReg); + } + + FloatRegBits readFloatRegBits(int floatReg) + { + return floatRegFile.readRegBits(floatReg); + } + + FloatRegBits readFloatRegBits(int floatReg, int width) + { + return readFloatRegBits(floatReg); + } + + Fault setFloatReg(int floatReg, const FloatReg &val) + { + return floatRegFile.setReg(floatReg, val); + } + + Fault setFloatReg(int floatReg, const FloatReg &val, int width) + { + return setFloatReg(floatReg, val); + } + + Fault setFloatRegBits(int floatReg, const FloatRegBits &val) + { + return floatRegFile.setRegBits(floatReg, val); + } + + Fault setFloatRegBits(int floatReg, const FloatRegBits &val, int width) + { + return setFloatRegBits(floatReg, val); + } + IntReg readIntReg(int intReg) + { + return intRegFile.readReg(intReg); + } + + Fault setIntReg(int intReg, const IntReg &val) + { + return intRegFile.setReg(intReg, val); + } + protected: Addr pc; // program counter Addr npc; // next-cycle program counter Addr nnpc; // next-next-cycle program counter // used to implement branch delay slot // not real register + public: + Addr readPC() + { + return pc; + } + + void setPC(Addr val) + { + pc = val; + } + + Addr readNextPC() + { + return npc; + } + + void setNextPC(Addr val) + { + npc = val; + } + + Addr readNextNPC() + { + return nnpc; + } + + void setNextNPC(Addr val) + { + nnpc = val; + } MiscReg hi; // MIPS HI Register MiscReg lo; // MIPS LO Register @@ -514,6 +650,13 @@ extern const Addr PageOffset; void createCP0Regs(); void coldReset(); + + typedef int ContextParam; + typedef int ContextVal; + + void changeContext(ContextParam param, ContextVal val) + { + } }; StaticInstPtr decodeInst(ExtMachInst); @@ -594,12 +737,12 @@ extern const Addr PageOffset; // return value itself in the standard return value reg (v0). if (return_value.successful()) { // no error - regs->intRegFile[ReturnValueReg1] = 0; - regs->intRegFile[ReturnValueReg2] = return_value.value(); + regs->setIntReg(ReturnValueReg1, 0); + regs->setIntReg(ReturnValueReg2, return_value.value()); } else { // got an error, return details - regs->intRegFile[ReturnValueReg1] = (IntReg) -1; - regs->intRegFile[ReturnValueReg2] = -return_value.value(); + regs->setIntReg(ReturnValueReg1, (IntReg) -1); + regs->setIntReg(ReturnValueReg2, -return_value.value()); } //regs->intRegFile[ReturnValueReg1] = (IntReg)return_value; diff --git a/arch/sparc/faults.cc b/arch/sparc/faults.cc index 79ea7f54a..e83bba800 100644 --- a/arch/sparc/faults.cc +++ b/arch/sparc/faults.cc @@ -179,13 +179,13 @@ TrapType AsyncDataError::_trapType = 0x040; FaultPriority AsyncDataError::_priority = 2; FaultStat AsyncDataError::_count; -//The enumerated faults - FaultName CleanWindow::_name = "clean_win"; -TrapType CleanWindow::_baseTrapType = 0x024; +TrapType CleanWindow::_trapType = 0x024; FaultPriority CleanWindow::_priority = 10; FaultStat CleanWindow::_count; +//The enumerated faults + FaultName InterruptLevelN::_name = "interrupt_n"; TrapType InterruptLevelN::_baseTrapType = 0x041; FaultStat InterruptLevelN::_count; diff --git a/arch/sparc/faults.hh b/arch/sparc/faults.hh index 62bffa72e..87de8daaa 100644 --- a/arch/sparc/faults.hh +++ b/arch/sparc/faults.hh @@ -468,31 +468,30 @@ class AsyncDataError : public SparcFault FaultStat & countStat() {return _count;} }; -class EnumeratedFault : public SparcFault -{ - protected: - uint32_t _n; - virtual TrapType baseTrapType() = 0; - public: - EnumeratedFault(uint32_t n) : SparcFault() {_n = n;} - TrapType trapType() {return baseTrapType() + _n;} -}; - -class CleanWindow : public EnumeratedFault +class CleanWindow : public SparcFault { private: static FaultName _name; - static TrapType _baseTrapType; + static TrapType _trapType; static FaultPriority _priority; static FaultStat _count; - TrapType baseTrapType() {return _baseTrapType;} public: - CleanWindow(uint32_t n) : EnumeratedFault(n) {;} FaultName name() {return _name;} + TrapType trapType() {return _trapType;} FaultPriority priority() {return _priority;} FaultStat & countStat() {return _count;} }; +class EnumeratedFault : public SparcFault +{ + protected: + uint32_t _n; + virtual TrapType baseTrapType() = 0; + public: + EnumeratedFault(uint32_t n) : SparcFault() {_n = n;} + TrapType trapType() {return baseTrapType() + _n;} +}; + class InterruptLevelN : public EnumeratedFault { private: diff --git a/arch/sparc/isa/base.isa b/arch/sparc/isa/base.isa index 4721f728b..434426ffa 100644 --- a/arch/sparc/isa/base.isa +++ b/arch/sparc/isa/base.isa @@ -57,6 +57,12 @@ output header {{ }; bool passesCondition(uint32_t codes, uint32_t condition); + + inline int64_t sign_ext(uint64_t data, int origWidth) + { + int shiftAmount = 64 - origWidth; + return (((int64_t)data) << shiftAmount) >> shiftAmount; + } }}; def template ROrImmDecode {{ @@ -68,28 +74,46 @@ def template ROrImmDecode {{ let {{ def splitOutImm(code): - matcher = re.compile(r'Rs(?P<rNum>\d)_or_imm(?P<iNum>d{0,2})') + matcher = re.compile(r'Rs(?P<rNum>\d)_or_imm(?P<iNum>\d+)') rOrImmMatch = matcher.search(code) if (rOrImmMatch == None): - return (False, CodeBlock(code), None, '', '') - rString = matcher.sub(r'(?P=rNum)', rOrImmMatch.string) - iString = matcher.sub(r'(?P=iNum)', rOrImmMatch.string) + return (False, code, '', '', '') + rString = rOrImmMatch.group("rNum") + iString = rOrImmMatch.group("iNum") orig_code = code - code = matcher.sub(r'Rs(?P<rNum>)', orig_code) + code = matcher.sub('Rs' + rOrImmMatch.group("rNum"), orig_code) imm_code = matcher.sub('imm', orig_code) - return (True, CodeBlock(code), CodeBlock(imm_code), rString, iString) + return (True, code, imm_code, rString, iString) }}; output decoder {{ + inline void printMnemonic(std::ostream &os, const char * mnemonic) + { + ccprintf(os, "\t%s ", mnemonic); + } + void SparcStaticInst::printReg(std::ostream &os, int reg) const { - if (reg < FP_Base_DepTag) { - ccprintf(os, "r%d", reg); - } + const int MaxGlobal = 8; + const int MaxOutput = 16; + const int MaxLocal = 24; + const int MaxInput = 32; + if (reg == FramePointerReg) + ccprintf(os, "%%fp"); + else if (reg == StackPointerReg) + ccprintf(os, "%%sp"); + else if(reg < MaxGlobal) + ccprintf(os, "%%g%d", reg); + else if(reg < MaxOutput) + ccprintf(os, "%%o%d", reg - MaxGlobal); + else if(reg < MaxLocal) + ccprintf(os, "%%l%d", reg - MaxOutput); + else if(reg < MaxInput) + ccprintf(os, "%%i%d", reg - MaxLocal); else { - ccprintf(os, "f%d", reg - FP_Base_DepTag); + ccprintf(os, "%%f%d", reg - FP_Base_DepTag); } } @@ -98,7 +122,7 @@ output decoder {{ { std::stringstream ss; - ccprintf(ss, "%-10s ", mnemonic); + printMnemonic(ss, mnemonic); // just print the first two source regs... if there's // a third one, it's a read-modify-write dest (Rc), diff --git a/arch/sparc/isa/decoder.isa b/arch/sparc/isa/decoder.isa index 6c1356932..b4084518c 100644 --- a/arch/sparc/isa/decoder.isa +++ b/arch/sparc/isa/decoder.isa @@ -7,61 +7,64 @@ decode OP default Unknown::unknown() { 0x0: decode OP2 { - format Branch + //Throw an illegal instruction acception + 0x0: Trap::illtrap({{fault = new IllegalInstruction;}}); + 0x1: decode BPCC { - //Throw an illegal instruction acception - 0x0: Trap::illtrap({{fault = new IllegalInstruction;}}); - 0x1: decode BPCC + format Branch19 { 0x0: bpcci({{ if(passesCondition(CcrIcc, COND2)) - ;//branchHere + NNPC = xc->readPC() + disp; }}); 0x2: bpccx({{ if(passesCondition(CcrXcc, COND2)) - ;//branchHere + NNPC = xc->readPC() + disp; }}); } - 0x2: bicc({{ - if(passesCondition(CcrIcc, COND2)) - ;//branchHere - }}); - 0x3: decode RCOND2 + } + 0x2: Branch22::bicc({{ + if(passesCondition(CcrIcc, COND2)) + NNPC = xc->readPC() + disp; + }}); + 0x3: decode RCOND2 + { + format BranchSplit { 0x1: bpreq({{ if(Rs1 == 0) - ;//branchHere + NNPC = xc->readPC() + disp; }}); 0x2: bprle({{ if(Rs1 <= 0) - ;//branchHere + NNPC = xc->readPC() + disp; }}); 0x3: bprl({{ if(Rs1 < 0) - ;//branchHere + NNPC = xc->readPC() + disp; }}); 0x5: bprne({{ if(Rs1 != 0) - ;//branchHere + NNPC = xc->readPC() + disp; }}); 0x6: bprg({{ if(Rs1 > 0) - ;//branchHere + NNPC = xc->readPC() + disp; }}); 0x7: bprge({{ if(Rs1 >= 0) - ;//branchHere + NNPC = xc->readPC() + disp; }}); } - //SETHI (or NOP if rd == 0 and imm == 0) - 0x4: IntOp::sethi({{Rd = (IMM22 << 10) & 0xFFFFFC00;}}); - 0x5: Trap::fbpfcc({{fault = new FpDisabled;}}); - 0x6: Trap::fbfcc({{fault = new FpDisabled;}}); } + //SETHI (or NOP if rd == 0 and imm == 0) + 0x4: SetHi::sethi({{Rd = imm;}}); + 0x5: Trap::fbpfcc({{fault = new FpDisabled;}}); + 0x6: Trap::fbfcc({{fault = new FpDisabled;}}); } - 0x1: Branch::call({{ - //branch here - Rd = xc->readPC(); + 0x1: Branch30::call({{ + R15 = xc->readPC(); + NNPC = R15 + disp; }}); 0x2: decode OP3 { format IntOp { @@ -69,74 +72,73 @@ decode OP default Unknown::unknown() 0x01: and({{Rd = Rs1.udw & Rs2_or_imm13;}}); 0x02: or({{Rd = Rs1.udw | Rs2_or_imm13;}}); 0x03: xor({{Rd = Rs1.udw ^ Rs2_or_imm13;}}); - 0x04: sub({{Rd = Rs1.sdw + (~Rs2_or_imm)+1;}}); - 0x05: andn({{Rd = Rs1.udw & ~Rs2_or_imm;}}); - 0x06: orn({{Rd = Rs1.udw | ~Rs2_or_imm;}}); - 0x07: xnor({{Rd = ~(Rs1.udw ^ Rs2_or_imm);}}); - 0x08: addc({{Rd = Rs1.sdw + Rs2_or_imm + CcrIccC;}}); - 0x09: mulx({{Rd = Rs1 * Rs2_or_imm;}}); + 0x04: sub({{Rd = Rs1.sdw - Rs2_or_imm13;}}); + 0x05: andn({{Rd = Rs1.udw & ~Rs2_or_imm13;}}); + 0x06: orn({{Rd = Rs1.udw | ~Rs2_or_imm13;}}); + 0x07: xnor({{Rd = ~(Rs1.udw ^ Rs2_or_imm13);}}); + 0x08: addc({{Rd = Rs1.sdw + Rs2_or_imm13 + CcrIccC;}}); + 0x09: mulx({{Rd = Rs1 * Rs2_or_imm13;}}); 0x0A: umul({{ - Rd = Rs1.udw<31:0> * Rs2_or_imm<31:0>; + Rd = Rs1.udw<31:0> * Rs2_or_imm13<31:0>; YValue = Rd<63:32>; }}); 0x0B: smul({{ - Rd.sdw = Rs1.sdw<31:0> * Rs2_or_imm<31:0>; + Rd.sdw = Rs1.sdw<31:0> * Rs2_or_imm13<31:0>; YValue = Rd.sdw; }}); - 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm) + 1 + CcrIccC;}}); + 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 + CcrIccC;}}); 0x0D: udivx({{ - if(val2 == 0) fault = new DivisionByZero; - else Rd.udw = Rs1.udw / Rs2_or_imm; + if(Rs2_or_imm13 == 0) fault = new DivisionByZero; + else Rd.udw = Rs1.udw / Rs2_or_imm13; }}); 0x0E: udiv({{ - uint32_t resTemp, val2 = (I ? SIMM13 : Rs2.udw<31:0>); - if(Rs2_or_imm.udw == 0) fault = new DivisionByZero; + if(Rs2_or_imm13 == 0) fault = new DivisionByZero; else { - Rd.udw = ((YValue << 32) | Rs1.udw<31:0>) / Rs2_or_imm.udw; + Rd.udw = ((YValue << 32) | Rs1.udw<31:0>) / Rs2_or_imm13; if(Rd.udw >> 32 != 0) Rd.udw = 0xFFFFFFFF; } }}); 0x0F: sdiv({{ - if(val2 == 0) + if(Rs2_or_imm13 == 0) fault = new DivisionByZero; else { - Rd.udw = ((YValue << 32) | Rs1.sdw<31:0>) / Rs2_or_imm; + Rd.udw = ((YValue << 32) | Rs1.sdw<31:0>) / Rs2_or_imm13; if(Rd.udw<63:31> != 0) Rd.udw = 0x7FFFFFFF; else if(Rd.udw<63:> && Rd.udw<62:31> != 0xFFFFFFFF) Rd.udw = 0xFFFFFFFF80000000; } - }});//SDIV + }}); } format IntOpCc { 0x10: addcc({{ - int64_t resTemp, val2 = (I ? SIMM13 : Rs2); + int64_t resTemp, val2 = Rs2_or_imm13; Rd = resTemp = Rs1 + val2;}}, {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}}, {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}}, {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} - );//ADDcc + ); 0x11: IntOpCcRes::andcc({{Rd = Rs1 & Rs2_or_imm13;}}); 0x12: IntOpCcRes::orcc({{Rd = Rs1 | Rs2_or_imm13;}}); 0x13: IntOpCcRes::xorcc({{Rd = Rs1 ^ Rs2_or_imm13;}}); 0x14: subcc({{ - int64_t resTemp, val2 = (int64_t)(I ? SIMM13 : Rs2); + int64_t resTemp, val2 = Rs2_or_imm13; Rd = resTemp = Rs1 - val2;}}, - {{((Rs1 & 0xFFFFFFFF + (~val2) & 0xFFFFFFFF + 1) >> 31)}}, + {{((Rs1 & 0xFFFFFFFF - val2 & 0xFFFFFFFF) >> 31)}}, {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}}, - {{((Rs1 >> 1) + (~val2) >> 1) + + {{(((Rs1 >> 1) + (~val2) >> 1) + ((Rs1 | ~val2) & 0x1))<63:>}}, {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}} - );//SUBcc + ); 0x15: IntOpCcRes::andncc({{Rd = Rs1 & ~Rs2_or_imm13;}}); 0x16: IntOpCcRes::orncc({{Rd = Rs1 | ~Rs2_or_imm13;}}); 0x17: IntOpCcRes::xnorcc({{Rd = ~(Rs1 ^ Rs2_or_imm13);}}); 0x18: addccc({{ - int64_t resTemp, val2 = (I ? SIMM13 : Rs2); + int64_t resTemp, val2 = Rs2_or_imm13; int64_t carryin = CcrIccC; Rd = resTemp = Rs1 + val2 + carryin;}}, {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31 @@ -145,83 +147,84 @@ decode OP default Unknown::unknown() {{((Rs1 >> 1) + (val2 >> 1) + ((Rs1 & val2) | (carryin & (Rs1 | val2)) & 0x1))<63:>}}, {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} - );//ADDCcc + ); 0x1A: umulcc({{ - uint64_t resTemp, val2 = (I ? SIMM13 : Rs2); + uint64_t resTemp, val2 = Rs2_or_imm13; Rd = resTemp = Rs1.udw<31:0> * val2<31:0>; YValue = resTemp<63:32>;}}, - {{0}},{{0}},{{0}},{{0}});//UMULcc + {{0}},{{0}},{{0}},{{0}}); 0x1B: smulcc({{ - int64_t resTemp, val2 = (I ? SIMM13 : Rs2); + int64_t resTemp, val2 = Rs2_or_imm13; Rd = resTemp = Rs1.sdw<31:0> * val2<31:0>; - YValue = resTemp<63:32>;}} - ,{{0}},{{0}},{{0}},{{0}});//SMULcc + YValue = resTemp<63:32>;}}, + {{0}},{{0}},{{0}},{{0}}); 0x1C: subccc({{ - int64_t resTemp, val2 = (int64_t)(I ? SIMM13 : Rs2); + int64_t resTemp, val2 = Rs2_or_imm13; int64_t carryin = CcrIccC; Rd = resTemp = Rs1 + ~(val2 + carryin) + 1;}}, {{((Rs1 & 0xFFFFFFFF + (~(val2 + carryin)) & 0xFFFFFFFF + 1) >> 31)}}, {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}}, - {{((Rs1 >> 1) + (~(val2 + carryin)) >> 1) + ((Rs1 | ~(val2+carryin)) & 0x1))<63:>}}, + {{(((Rs1 >> 1) + (~(val2 + carryin)) >> 1) + ((Rs1 | ~(val2+carryin)) & 0x1))<63:>}}, {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}} - );//SUBCcc + ); 0x1D: udivxcc({{ - uint64_t val2 = (I ? SIMM13 : Rs2.udw); - if(val2 == 0) fault = new DivisionByZero; - else Rd.udw = Rs1.udw / val2;}} - ,{{0}},{{0}},{{0}},{{0}});//UDIVXcc + if(Rs2_or_imm13 == 0) fault = new DivisionByZero; + else Rd = Rs1.udw / Rs2_or_imm13;}} + ,{{0}},{{0}},{{0}},{{0}}); 0x1E: udivcc({{ - uint32_t resTemp, val2 = (I ? SIMM13 : Rs2.udw<31:0>); + uint32_t resTemp, val2 = Rs2_or_imm13; + int32_t overflow; if(val2 == 0) fault = new DivisionByZero; else { resTemp = (uint64_t)((YValue << 32) | Rs1.udw<31:0>) / val2; - int32_t overflow = (resTemp<63:32> != 0); - if(overflow) rd.udw = resTemp = 0xFFFFFFFF; - else rd.udw = resTemp; + overflow = (resTemp<63:32> != 0); + if(overflow) Rd = resTemp = 0xFFFFFFFF; + else Rd = resTemp; } }}, {{0}}, {{overflow}}, {{0}}, {{0}} - );//UDIVcc + ); 0x1F: sdivcc({{ - int32_t resTemp, val2 = (I ? SIMM13 : Rs2.sdw<31:0>); + int32_t resTemp, val2 = Rs2_or_imm13; + int32_t overflow, underflow; if(val2 == 0) fault = new DivisionByZero; else { - Rd.sdw = resTemp = (int64_t)((YValue << 32) | Rs1.sdw<31:0>) / val2; - int32_t overflow = (resTemp<63:31> != 0); - int32_t underflow = (resTemp<63:> && resTemp<62:31> != 0xFFFFFFFF); - if(overflow) rd.udw = resTemp = 0x7FFFFFFF; - else if(underflow) rd.udw = resTemp = 0xFFFFFFFF80000000; - else rd.udw = resTemp; + Rd = resTemp = (int64_t)((YValue << 32) | Rs1.sdw<31:0>) / val2; + overflow = (resTemp<63:31> != 0); + underflow = (resTemp<63:> && resTemp<62:31> != 0xFFFFFFFF); + if(overflow) Rd = resTemp = 0x7FFFFFFF; + else if(underflow) Rd = resTemp = 0xFFFFFFFF80000000; + else Rd = resTemp; } }}, {{0}}, {{overflow || underflow}}, {{0}}, {{0}} - );//SDIVcc + ); 0x20: taddcc({{ - int64_t resTemp, val2 = (I ? SIMM13 : Rs2); + int64_t resTemp, val2 = Rs2_or_imm13; Rd = resTemp = Rs1 + val2; int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}}, {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}}, {{overflow}}, {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} - );//TADDcc + ); 0x21: tsubcc({{ - int64_t resTemp, val2 = (I ? SIMM13 : Rs2); + int64_t resTemp, val2 = Rs2_or_imm13; Rd = resTemp = Rs1 + val2; int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}}, - {{(Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}}, + {{(Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31}}, {{overflow}}, {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} - );//TSUBcc + ); 0x22: taddcctv({{ - int64_t resTemp, val2 = (I ? SIMM13 : Rs2); + int64_t resTemp, val2 = Rs2_or_imm13; Rd = resTemp = Rs1 + val2; int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>); if(overflow) fault = new TagOverflow;}}, @@ -229,9 +232,9 @@ decode OP default Unknown::unknown() {{overflow}}, {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} - );//TADDccTV + ); 0x23: tsubcctv({{ - int64_t resTemp, val2 = (I ? SIMM13 : Rs2); + int64_t resTemp, val2 = Rs2_or_imm13; Rd = resTemp = Rs1 + val2; int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>); if(overflow) fault = new TagOverflow;}}, @@ -239,12 +242,12 @@ decode OP default Unknown::unknown() {{overflow}}, {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} - );//TSUBccTV + ); 0x24: mulscc({{ - int64_t resTemp, multiplicand = (I ? SIMM13 : Rs2); + int64_t resTemp, multiplicand = Rs2_or_imm13; int32_t multiplier = Rs1<31:0>; int32_t savedLSB = Rs1<0:>; - multiplier = multipler<31:1> | + multiplier = multiplier<31:1> | ((CcrIccN ^ CcrIccV) << 32); if(!YValue<0:>) @@ -255,286 +258,387 @@ decode OP default Unknown::unknown() {{multiplicand<31:> == multiplier<31:> && multiplier<31:> != resTemp<31:>}}, {{((multiplicand >> 1) + (multiplier >> 1) + (multiplicand & multiplier & 0x1))<63:>}}, {{multiplicand<63:> == multiplier<63:> && multiplier<63:> != resTemp<63:>}} - );//MULScc + ); + } + format IntOp + { + 0x25: decode X { + 0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}}); + 0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}}); } - format IntOp - { - 0x25: decode X { - 0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}}); - 0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}}); - } - 0x26: decode X { - 0x0: srl({{Rd = Rs1.uw >> (I ? SHCNT32 : Rs2<4:0>);}}); - 0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}}); - } - 0x27: decode X { - 0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}}); //SRA - 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}});//SRAX - } - 0x28: decode RS1 { - 0x0: rdy({{Rd = YValue;}}); //RDY - 0x2: rdccr({{Rd = Ccr;}}); //RDCCR - 0x3: rdasi({{Rd = Asi;}}); //RDASI - 0x4: PrivTick::rdtick({{Rd = Tick;}}); - 0x5: rdpc({{Rd = xc->regs.pc;}}); //RDPC - 0x6: rdfprs({{Rd = Fprs;}}); //RDFPRS - 0xF: decode I { - 0x0: Noop::membar({{/*Membar isn't needed yet*/}}); - 0x1: Noop::stbar({{/*Stbar isn't needed yet*/}}); - } - } - 0x2A: decode RS1 { - format Priv - { - 0x0: rdprtpc({{ - Rd = xc->readMiscReg(MISCREG_TPC_BASE + Tl); - }}); - 0x1: rdprtnpc({{ - Rd = xc->readMiscReg(MISCREG_TNPC_BASE + Tl); - }}); - 0x2: rdprtstate({{ - Rd = xc->readMiscReg(MISCREG_TSTATE_BASE + Tl); - }}); - 0x3: rdprtt({{ - Rd = xc->readMiscReg(MISCREG_TT_BASE + Tl); - }}); - 0x4: rdprtick({{Rd = Tick;}}); - 0x5: rdprtba({{Rd = Tba;}}); - 0x6: rdprpstate({{Rd = Pstate;}}); - 0x7: rdprtl({{Rd = Tl;}}); - 0x8: rdprpil({{Rd = Pil;}}); - 0x9: rdprcwp({{Rd = Cwp;}}); - 0xA: rdprcansave({{Rd = Cansave;}}); - 0xB: rdprcanrestore({{Rd = Canrestore;}}); - 0xC: rdprcleanwin({{Rd = Cleanwin;}}); - 0xD: rdprotherwin({{Rd = Otherwin;}}); - 0xE: rdprwstate({{Rd = Wstate;}}); - } - //The floating point queue isn't implemented right now. - 0xF: Trap::rdprfq({{fault = new IllegalInstruction;}}); - 0x1F: Priv::rdprver({{Rd = Ver;}}); + 0x26: decode X { + 0x0: srl({{Rd = Rs1.uw >> (I ? SHCNT32 : Rs2<4:0>);}}); + 0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}}); + } + 0x27: decode X { + 0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}}); + 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}}); + } + 0x28: decode RS1 { + 0x0: rdy({{Rd = YValue;}}); + 0x2: rdccr({{Rd = Ccr;}}); + 0x3: rdasi({{Rd = Asi;}}); + 0x4: PrivTick::rdtick({{Rd = Tick;}}); + 0x5: rdpc({{Rd = xc->readPC();}}); + 0x6: rdfprs({{Rd = Fprs;}}); + 0xF: decode I { + 0x0: Nop::membar({{/*Membar isn't needed yet*/}}); + 0x1: Nop::stbar({{/*Stbar isn't needed yet*/}}); } - 0x2B: BasicOperate::flushw({{/*window toilet*/}}); - 0x2C: decode MOVCC3 + } + 0x2A: decode RS1 { + format Priv { - 0x0: Trap::movccfcc({{fault = new FpDisabled;}}); - 0x1: decode CC - { - 0x0: movcci({{ - if(passesCondition(CcrIcc, COND4)) - Rd = (I ? SIMM11 : RS2); - }}); - 0x2: movccx({{ - if(passesCondition(CcrXcc, COND4)) - Rd = (I ? SIMM11 : RS2); - }}); - } - } - 0x2D: sdivx({{ - if(Rs2_or_imm13 == 0) fault = new DivisionByZero; - else Rd.sdw = Rs1.sdw / Rs2_or_imm13; - }});//SDIVX - 0x2E: decode RS1 { - 0x0: IntOp::popc({{ - int64_t count = 0, val2 = Rs2_or_imm; - uint8_t oneBits[] = {0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4}; - for(unsigned int x = 0; x < 16; x++) - { - count += oneBits[Rs2_or_imm13 & 0xF]; - val2 >> 4; - } - }});//POPC + 0x0: rdprtpc({{ + Rd = xc->readMiscReg(MISCREG_TPC_BASE + Tl); + }}); + 0x1: rdprtnpc({{ + Rd = xc->readMiscReg(MISCREG_TNPC_BASE + Tl); + }}); + 0x2: rdprtstate({{ + Rd = xc->readMiscReg(MISCREG_TSTATE_BASE + Tl); + }}); + 0x3: rdprtt({{ + Rd = xc->readMiscReg(MISCREG_TT_BASE + Tl); + }}); + 0x4: rdprtick({{Rd = Tick;}}); + 0x5: rdprtba({{Rd = Tba;}}); + 0x6: rdprpstate({{Rd = Pstate;}}); + 0x7: rdprtl({{Rd = Tl;}}); + 0x8: rdprpil({{Rd = Pil;}}); + 0x9: rdprcwp({{Rd = Cwp;}}); + 0xA: rdprcansave({{Rd = Cansave;}}); + 0xB: rdprcanrestore({{Rd = Canrestore;}}); + 0xC: rdprcleanwin({{Rd = Cleanwin;}}); + 0xD: rdprotherwin({{Rd = Otherwin;}}); + 0xE: rdprwstate({{Rd = Wstate;}}); } - 0x2F: decode RCOND3 + //The floating point queue isn't implemented right now. + 0xF: Trap::rdprfq({{fault = new IllegalInstruction;}}); + 0x1F: Priv::rdprver({{Rd = Ver;}}); + } + 0x2B: BasicOperate::flushw({{ + if(NWindows - 2 - Cansave == 0) { - 0x1: movreq({{if(Rs1 == 0) Rd = Rs2_or_imm10;}}); - 0x2: movrle({{if(Rs1 <= 0) Rd = Rs2_or_imm10;}}); - 0x3: movrl({{if(Rs1 < 0) Rd = Rs2_or_imm10;}}); - 0x5: movrne({{if(Rs1 != 0) Rd = Rs2_or_imm10;}}); - 0x6: movrg({{if(Rs1 > 0) Rd = Rs2_or_imm10;}}); - 0x7: movrge({{if(Rs1 >= 0) Rd = Rs2_or_imm10;}}); + if(Otherwin) + fault = new SpillNOther(WstateOther); + else + fault = new SpillNNormal(WstateNormal); } - 0x30: decode RD { - 0x0: wry({{Y = Rs1 ^ Rs2_or_imm13;}}); - 0x2: wrccr({{Ccr = Rs1 ^ Rs2_or_imm13;}}); - 0x3: wrasi({{Asi = Rs1 ^ Rs2_or_imm13;}}); - 0x6: wrfprs({{Asi = Rs1 ^ Rs2_or_imm13;}}); - 0xF: Trap::sir({{fault = new SoftwareInitiatedReset;}}); - } - 0x31: decode FCN { - 0x0: BasicOperate::saved({{/*Boogy Boogy*/}}); - 0x1: BasicOperate::restored({{/*Boogy Boogy*/}}); + }}); + 0x2C: decode MOVCC3 + { + 0x0: Trap::movccfcc({{fault = new FpDisabled;}}); + 0x1: decode CC + { + 0x0: movcci({{ + if(passesCondition(CcrIcc, COND4)) + Rd = (I ? SIMM11 : RS2); + }}); + 0x2: movccx({{ + if(passesCondition(CcrXcc, COND4)) + Rd = (I ? SIMM11 : RS2); + }}); } - 0x32: decode RD { - format Priv + } + 0x2D: sdivx({{ + if(Rs2_or_imm13 == 0) fault = new DivisionByZero; + else Rd.sdw = Rs1.sdw / Rs2_or_imm13; + }}); + 0x2E: decode RS1 { + 0x0: IntOp::popc({{ + int64_t count = 0; + uint64_t temp = Rs2_or_imm13; + //Count the 1s in the front 4bits until none are left + uint8_t oneBits[] = {0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4}; + while(temp) { - 0x0: wrprtpc({{ - xc->setMiscReg(MISCREG_TPC_BASE + Tl, - Rs1 ^ Rs2_or_imm13); - }}); - 0x1: wrprtnpc({{ - xc->setMiscReg(MISCREG_TNPC_BASE + Tl, - Rs1 ^ Rs2_or_imm13); - }}); - 0x2: wrprtstate({{ - xc->setMiscReg(MISCREG_TSTATE_BASE + Tl, - Rs1 ^ Rs2_or_imm13); - }}); - 0x3: wrprtt({{ - xc->setMiscReg(MISCREG_TT_BASE + Tl, - Rs1 ^ Rs2_or_imm13); - }}); - 0x4: wrprtick({{Tick = Rs1 ^ Rs2_or_imm13;}}); - 0x5: wrprtba({{Tba = Rs1 ^ Rs2_or_imm13;}}); - 0x6: wrprpstate({{Pstate = Rs1 ^ Rs2_or_imm13;}}); - 0x7: wrprtl({{Tl = Rs1 ^ Rs2_or_imm13;}}); - 0x8: wrprpil({{Pil = Rs1 ^ Rs2_or_imm13;}}); - 0x9: wrprcwp({{Cwp = Rs1 ^ Rs2_or_imm13;}}); - 0xA: wrprcansave({{Cansave = Rs1 ^ Rs2_or_imm13;}}); - 0xB: wrprcanrestore({{Canrestore = Rs1 ^ Rs2_or_imm13;}}); - 0xC: wrprcleanwin({{Cleanwin = Rs1 ^ Rs2_or_imm13;}}); - 0xD: wrprotherwin({{Otherwin = Rs1 ^ Rs2_or_imm13;}}); - 0xE: wrprwstate({{Wstate = Rs1 ^ Rs2_or_imm13;}}); + count += oneBits[temp & 0xF]; + temp = temp >> 4; } + }}); + } + 0x2F: decode RCOND3 + { + 0x1: movreq({{if(Rs1 == 0) Rd = Rs2_or_imm10;}}); + 0x2: movrle({{if(Rs1 <= 0) Rd = Rs2_or_imm10;}}); + 0x3: movrl({{if(Rs1 < 0) Rd = Rs2_or_imm10;}}); + 0x5: movrne({{if(Rs1 != 0) Rd = Rs2_or_imm10;}}); + 0x6: movrg({{if(Rs1 > 0) Rd = Rs2_or_imm10;}}); + 0x7: movrge({{if(Rs1 >= 0) Rd = Rs2_or_imm10;}}); + } + 0x30: decode RD { + 0x0: wry({{Y = Rs1 ^ Rs2_or_imm13;}}); + 0x2: wrccr({{Ccr = Rs1 ^ Rs2_or_imm13;}}); + 0x3: wrasi({{Asi = Rs1 ^ Rs2_or_imm13;}}); + 0x6: wrfprs({{Asi = Rs1 ^ Rs2_or_imm13;}}); + 0xF: Trap::sir({{fault = new SoftwareInitiatedReset;}}); + } + 0x31: decode FCN { + 0x0: BasicOperate::saved({{/*Boogy Boogy*/}}); + 0x1: BasicOperate::restored({{/*Boogy Boogy*/}}); + } + 0x32: decode RD { + format Priv + { + 0x0: wrprtpc({{ + xc->setMiscReg(MISCREG_TPC_BASE + Tl, + Rs1 ^ Rs2_or_imm13); + }}); + 0x1: wrprtnpc({{ + xc->setMiscReg(MISCREG_TNPC_BASE + Tl, + Rs1 ^ Rs2_or_imm13); + }}); + 0x2: wrprtstate({{ + xc->setMiscReg(MISCREG_TSTATE_BASE + Tl, + Rs1 ^ Rs2_or_imm13); + }}); + 0x3: wrprtt({{ + xc->setMiscReg(MISCREG_TT_BASE + Tl, + Rs1 ^ Rs2_or_imm13); + }}); + 0x4: wrprtick({{Tick = Rs1 ^ Rs2_or_imm13;}}); + 0x5: wrprtba({{Tba = Rs1 ^ Rs2_or_imm13;}}); + 0x6: wrprpstate({{Pstate = Rs1 ^ Rs2_or_imm13;}}); + 0x7: wrprtl({{Tl = Rs1 ^ Rs2_or_imm13;}}); + 0x8: wrprpil({{Pil = Rs1 ^ Rs2_or_imm13;}}); + 0x9: wrprcwp({{Cwp = Rs1 ^ Rs2_or_imm13;}}); + 0xA: wrprcansave({{Cansave = Rs1 ^ Rs2_or_imm13;}}); + 0xB: wrprcanrestore({{Canrestore = Rs1 ^ Rs2_or_imm13;}}); + 0xC: wrprcleanwin({{Cleanwin = Rs1 ^ Rs2_or_imm13;}}); + 0xD: wrprotherwin({{Otherwin = Rs1 ^ Rs2_or_imm13;}}); + 0xE: wrprwstate({{Wstate = Rs1 ^ Rs2_or_imm13;}}); } - - 0x34: Trap::fpop1({{fault = new FpDisabled;}}); - 0x35: Trap::fpop2({{fault = new FpDisabled;}}); - - 0x38: Branch::jmpl({{/*Stuff*/}}); - 0x39: Branch::return({{/*Other Stuff*/}}); - 0x3A: decode CC + } + 0x34: Trap::fpop1({{fault = new FpDisabled;}}); + 0x35: Trap::fpop2({{fault = new FpDisabled;}}); + 0x38: Branch::jmpl({{ + Addr target = Rs1 + Rs2_or_imm13; + if(target & 0x3) + fault = new MemAddressNotAligned; + else { - 0x0: Trap::tcci({{ + Rd = xc->readPC(); + NNPC = target; + } + }}); + 0x39: Branch::return({{ + Addr target = Rs1 + Rs2_or_imm13; + if(target & 0x3) + fault = new MemAddressNotAligned; + else + NNPC = target; + //This needs to change the register window + //like restore does + }}); + 0x3A: decode CC + { + 0x0: Trap::tcci({{ #if FULL_SYSTEM - fault = new TrapInstruction; + fault = new TrapInstruction; #else - if(passesCondition(CcrIcc, machInst<25:28>)) - // At least glibc only uses trap 0, - // solaris/sunos may use others - assert((I ? Rs1 + Rs2 : Rs1 + SW_TRAP) == 0); - xc->syscall(); + if(passesCondition(CcrIcc, machInst<25:28>)) + { + // At least glibc only uses trap 0, + // solaris/sunos may use others + assert((I ? Rs1 + Rs2 : Rs1 + SW_TRAP) == 0); + xc->syscall(); + } #endif - }}); - 0x2: Trap::tccx({{ + }}); + 0x2: Trap::tccx({{ #if FULL_SYSTEM - fault = new TrapInstruction; + fault = new TrapInstruction; #else - if(passesCondition(CcrXcc, machInst<25:28>)) - // At least glibc only uses trap 0, - // solaris/sunos may use others - assert((I ? Rs1 + Rs2 : Rs1 + SW_TRAP) == 0); - xc->syscall(); + if(passesCondition(CcrXcc, machInst<25:28>)) + { + // At least glibc only uses trap 0, + // solaris/sunos may use others + assert((I ? Rs1 + Rs2 : Rs1 + SW_TRAP) == 0); + xc->syscall(); + } #endif - }}); + }}); + } + 0x3B: Nop::flush({{/*Instruction memory flush*/}}); + 0x3C: save({{ + //CWP should be set directly so that it always happens + //Also, this will allow writing to the new window and + //reading from the old one + if(Cansave == 0) + { + if(Otherwin) + fault = new SpillNOther(WstateOther); + else + fault = new SpillNNormal(WstateNormal); + Cwp = (Cwp + 2) % NWindows; + } + else if(Cleanwin - Canrestore == 0) + { + Cwp = (Cwp + 1) % NWindows; + fault = new CleanWindow; } - 0x3B: BasicOperate::flush({{/*Lala*/}}); - 0x3C: BasicOperate::save({{/*leprechauns*/}}); - 0x3D: BasicOperate::restore({{/*Eat my short int*/}}); - 0x3E: decode FCN { - 0x1: BasicOperate::done({{/*Done thing*/}}); - 0x2: BasicOperate::retry({{/*Retry thing*/}}); + else + { + Cwp = (Cwp + 1) % NWindows; + Rd = Rs1 + Rs2_or_imm13; + Cansave--; + Canrestore++; + } + //This is here to make sure the CWP is written + //no matter what. This ensures that the results + //are written in the new window as well. + xc->setMiscRegWithEffect(MISCREG_CWP, Cwp); + }}); + 0x3D: restore({{ + //CWP should be set directly so that it always happens + //Also, this will allow writing to the new window and + //reading from the old one + Cwp = (Cwp - 1 + NWindows) % NWindows; + if(Canrestore == 0) + { + if(Otherwin) + fault = new FillNOther(WstateOther); + else + fault = new FillNNormal(WstateNormal); } + else + { + Rd = Rs1 + Rs2_or_imm13; + Cansave++; + Canrestore--; + } + //This is here to make sure the CWP is written + //no matter what. This ensures that the results + //are written in the new window as well. + xc->setMiscRegWithEffect(MISCREG_CWP, Cwp); + }}); + 0x3E: decode FCN { + 0x0: Priv::done({{ + if(Tl == 0) + return new IllegalInstruction; + Cwp = xc->readMiscReg(MISCREG_TSTATE_CWP_BASE + Tl); + Asi = xc->readMiscReg(MISCREG_TSTATE_ASI_BASE + Tl); + Ccr = xc->readMiscReg(MISCREG_TSTATE_CCR_BASE + Tl); + Pstate = xc->readMiscReg(MISCREG_TSTATE_PSTATE_BASE + Tl); + NPC = xc->readMiscReg(MISCREG_TNPC_BASE + Tl); + NNPC = NPC + 4; + Tl = Tl - 1; + }}); + 0x1: BasicOperate::retry({{ + if(Tl == 0) + return new IllegalInstruction; + Cwp = xc->readMiscReg(MISCREG_TSTATE_CWP_BASE + Tl); + Asi = xc->readMiscReg(MISCREG_TSTATE_ASI_BASE + Tl); + Ccr = xc->readMiscReg(MISCREG_TSTATE_CCR_BASE + Tl); + Pstate = xc->readMiscReg(MISCREG_TSTATE_PSTATE_BASE + Tl); + NPC = xc->readMiscReg(MISCREG_TPC_BASE + Tl); + NNPC = xc->readMiscReg(MISCREG_TNPC_BASE + Tl); + Tl = Tl - 1; + }}); } + } } 0x3: decode OP3 { - format Mem { - 0x00: lduw({{Rd.uw = Mem.uw;}}); //LDUW - 0x01: ldub({{Rd.ub = Mem.ub;}}); //LDUB - 0x02: lduh({{Rd.uhw = Mem.uhw;}}); //LDUH - 0x03: ldd({{ - uint64_t val = Mem.udw; - RdLow = val<31:0>; - RdHigh = val<63:32>; - }});//LDD - 0x04: stw({{Mem.sw = Rd.sw;}}); //STW - 0x05: stb({{Mem.sb = Rd.sb;}}); //STB - 0x06: sth({{Mem.shw = Rd.shw;}}); //STH - 0x07: std({{ - Mem.udw = RdLow<31:0> | RdHigh<31:0> << 32; - }});//STD - 0x08: ldsw({{Rd.sw = Mem.sw;}}); //LDSW - 0x09: ldsb({{Rd.sb = Mem.sb;}}); //LDSB - 0x0A: ldsh({{Rd.shw = Mem.shw;}}); //LDSH - 0x0B: ldx({{Rd.udw = Mem.udw;}}); //LDX - - 0x0D: ldstub({{ - Rd.ub = Mem.ub; - Mem.ub = 0xFF; - }}); //LDSTUB - 0x0E: stx({{Rd.udw = Mem.udw;}}); //STX - 0x0F: swap({{ - uint32_t temp = Rd.uw; - Rd.uw = Mem.uw; - Mem.uw = temp; - }}); //SWAP - 0x10: lduwa({{Rd.uw = Mem.uw;}}); //LDUWA - 0x11: lduba({{Rd.ub = Mem.ub;}}); //LDUBA - 0x12: lduha({{Rd.uhw = Mem.uhw;}}); //LDUHA - 0x13: ldda({{ - uint64_t val = Mem.udw; - RdLow = val<31:0>; - RdHigh = val<63:32>; - }}); //LDDA - 0x14: stwa({{Mem.uw = Rd.uw;}}); //STWA - 0x15: stba({{Mem.ub = Rd.ub;}}); //STBA - 0x16: stha({{Mem.uhw = Rd.uhw;}}); //STHA - 0x17: stda({{ - Mem.udw = RdLow<31:0> | RdHigh<31:0> << 32; - }}); //STDA - 0x18: ldswa({{Rd.sw = Mem.sw;}}); //LDSWA - 0x19: ldsba({{Rd.sb = Mem.sb;}}); //LDSBA - 0x1A: ldsha({{Rd.shw = Mem.shw;}}); //LDSHA - 0x1B: ldxa({{Rd.sdw = Mem.sdw;}}); //LDXA - - 0x1D: ldstuba({{ - Rd.ub = Mem.ub; - Mem.ub = 0xFF; - }}); //LDSTUBA - 0x1E: stxa({{Mem.sdw = Rd.sdw}}); //STXA - 0x1F: swapa({{ - uint32_t temp = Rd.uw; - Rd.uw = Mem.uw; - Mem.uw = temp; - }}); //SWAPA - 0x20: Trap::ldf({{fault = new FpDisabled;}}); - 0x21: decode X { - 0x0: Trap::ldfsr({{fault = new FpDisabled;}}); - 0x1: Trap::ldxfsr({{fault = new FpDisabled;}}); - } - 0x22: Trap::ldqf({{fault = new FpDisabled;}}); - 0x23: Trap::lddf({{fault = new FpDisabled;}}); - 0x24: Trap::stf({{fault = new FpDisabled;}}); - 0x25: decode X { - 0x0: Trap::stfsr({{fault = new FpDisabled;}}); - 0x1: Trap::stxfsr({{fault = new FpDisabled;}}); - } - 0x26: Trap::stqf({{fault = new FpDisabled;}}); - 0x27: Trap::stdf({{fault = new FpDisabled;}}); - - 0x2D: Noop::prefetch({{ }}); //PREFETCH - - 0x30: Trap::ldfa({{return new FpDisabled;}}); - - 0x32: Trap::ldqfa({{fault = new FpDisabled;}}); - 0x33: Trap::lddfa({{fault = new FpDisabled;}}); - 0x34: Trap::stfa({{fault = new FpDisabled;}}); - 0x35: Trap::stqfa({{fault = new FpDisabled;}}); - 0x36: Trap::stdfa({{fault = new FpDisabled;}}); - - 0x3C: Cas::casa( - {{uint64_t val = Mem.uw; - if(Rs2.uw == val) - Mem.uw = Rd.uw; - Rd.uw = val; - }}); //CASA - 0x3D: Noop::prefetcha({{ }}); //PREFETCHA - 0x3E: Cas::casxa({{ - uint64_t val = Mem.udw; - if(Rs2 == val) - Mem.udw = Rd; - Rd = val; - }}); //CASXA + format Load { + 0x00: lduw({{Rd = Mem;}}, {{32}}); + 0x01: ldub({{Rd = Mem;}}, {{8}}); + 0x02: lduh({{Rd = Mem;}}, {{16}}); + 0x03: ldd({{ + uint64_t val = Mem; + RdLow = val<31:0>; + RdHigh = val<63:32>; + }}, {{64}}); + } + format Store { + 0x04: stw({{Mem = Rd.sw;}}, {{32}}); + 0x05: stb({{Mem = Rd.sb;}}, {{8}}); + 0x06: sth({{Mem = Rd.shw;}}, {{16}}); + 0x07: std({{Mem = RdLow<31:0> | RdHigh<31:0> << 32;}}, {{64}}); + } + format Load { + 0x08: ldsw({{Rd = (int32_t)Mem;}}, {{32}}); + 0x09: ldsb({{Rd = (int8_t)Mem;}}, {{8}}); + 0x0A: ldsh({{Rd = (int16_t)Mem;}}, {{16}}); + 0x0B: ldx({{Rd = (int64_t)Mem;}}, {{64}}); + 0x0D: ldstub({{ + Rd = Mem; + Mem = 0xFF; + }}, {{8}}); + } + 0x0E: Store::stx({{Mem = Rd}}, {{64}}); + 0x0F: LoadStore::swap({{ + uint32_t temp = Rd; + Rd = Mem; + Mem = temp; + }}, {{32}}); + format Load { + 0x10: lduwa({{Rd = Mem;}}, {{32}}); + 0x11: lduba({{Rd = Mem;}}, {{8}}); + 0x12: lduha({{Rd = Mem;}}, {{16}}); + 0x13: ldda({{ + uint64_t val = Mem; + RdLow = val<31:0>; + RdHigh = val<63:32>; + }}, {{64}}); + } + format Store { + 0x14: stwa({{Mem = Rd;}}, {{32}}); + 0x15: stba({{Mem = Rd;}}, {{8}}); + 0x16: stha({{Mem = Rd;}}, {{16}}); + 0x17: stda({{Mem = RdLow<31:0> | RdHigh<31:0> << 32;}}, {{64}}); + } + format Load { + 0x18: ldswa({{Rd = (int32_t)Mem;}}, {{32}}); + 0x19: ldsba({{Rd = (int8_t)Mem;}}, {{8}}); + 0x1A: ldsha({{Rd = (int16_t)Mem;}}, {{16}}); + 0x1B: ldxa({{Rd = (int64_t)Mem;}}, {{64}}); + } + 0x1D: LoadStore::ldstuba({{ + Rd = Mem; + Mem = 0xFF; + }}, {{8}}); + 0x1E: Store::stxa({{Mem = Rd}}, {{64}}); + 0x1F: LoadStore::swapa({{ + uint32_t temp = Rd; + Rd = Mem; + Mem = temp; + }}, {{32}}); + format Trap { + 0x20: ldf({{fault = new FpDisabled;}}); + 0x21: decode X { + 0x0: ldfsr({{fault = new FpDisabled;}}); + 0x1: ldxfsr({{fault = new FpDisabled;}}); + } + 0x22: ldqf({{fault = new FpDisabled;}}); + 0x23: lddf({{fault = new FpDisabled;}}); + 0x24: stf({{fault = new FpDisabled;}}); + 0x25: decode X { + 0x0: stfsr({{fault = new FpDisabled;}}); + 0x1: stxfsr({{fault = new FpDisabled;}}); } + 0x26: stqf({{fault = new FpDisabled;}}); + 0x27: stdf({{fault = new FpDisabled;}}); + 0x2D: Nop::prefetch({{ }}); + 0x30: ldfa({{return new FpDisabled;}}); + 0x32: ldqfa({{fault = new FpDisabled;}}); + 0x33: lddfa({{fault = new FpDisabled;}}); + 0x34: stfa({{fault = new FpDisabled;}}); + 0x35: stqfa({{fault = new FpDisabled;}}); + 0x36: stdfa({{fault = new FpDisabled;}}); + 0x3C: Cas::casa({{ + uint64_t val = Mem.uw; + if(Rs2.uw == val) + Mem.uw = Rd.uw; + Rd.uw = val; + }}); + 0x3D: Nop::prefetcha({{ }}); + 0x3E: Cas::casxa({{ + uint64_t val = Mem.udw; + if(Rs2 == val) + Mem.udw = Rd; + Rd = val; + }}); + } } } diff --git a/arch/sparc/isa/formats.isa b/arch/sparc/isa/formats.isa index 8683f5e01..17d68061b 100644 --- a/arch/sparc/isa/formats.isa +++ b/arch/sparc/isa/formats.isa @@ -2,6 +2,9 @@ //Templates from this format are used later ##include "formats/basic.isa" +//Include the noop format +##include "formats/nop.isa" + //Include the integerOp and integerOpCc format ##include "formats/integerop.isa" @@ -23,6 +26,3 @@ //Include the branch format ##include "formats/branch.isa" -//Include the noop format -##include "formats/noop.isa" - diff --git a/arch/sparc/isa/formats/branch.isa b/arch/sparc/isa/formats/branch.isa index b9dc960de..e4ce4592c 100644 --- a/arch/sparc/isa/formats/branch.isa +++ b/arch/sparc/isa/formats/branch.isa @@ -5,7 +5,7 @@ output header {{ /** - * Base class for integer operations. + * Base class for branch operations. */ class Branch : public SparcStaticInst { @@ -19,12 +19,187 @@ output header {{ std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; }; + + /** + * Base class for branch operations with an immediate displacement. + */ + class BranchDisp : public Branch + { + protected: + // Constructor + BranchDisp(const char *mnem, MachInst _machInst, + OpClass __opClass) : + Branch(mnem, _machInst, __opClass) + { + } + + std::string generateDisassembly(Addr pc, + const SymbolTable *symtab) const; + + int32_t disp; + }; + + /** + * Base class for branches with 19 bit displacements. + */ + class Branch19 : public BranchDisp + { + protected: + // Constructor + Branch19(const char *mnem, MachInst _machInst, + OpClass __opClass) : + BranchDisp(mnem, _machInst, __opClass) + { + disp = sign_ext(DISP19 << 2, 21); + } + }; + + /** + * Base class for branches with 22 bit displacements. + */ + class Branch22 : public BranchDisp + { + protected: + // Constructor + Branch22(const char *mnem, MachInst _machInst, + OpClass __opClass) : + BranchDisp(mnem, _machInst, __opClass) + { + disp = sign_ext(DISP22 << 2, 24); + } + }; + + /** + * Base class for branches with 30 bit displacements. + */ + class Branch30 : public BranchDisp + { + protected: + // Constructor + Branch30(const char *mnem, MachInst _machInst, + OpClass __opClass) : + BranchDisp(mnem, _machInst, __opClass) + { + disp = sign_ext(DISP30 << 2, 32); + } + }; + + /** + * Base class for 16bit split displacements. + */ + class BranchSplit : public BranchDisp + { + protected: + // Constructor + BranchSplit(const char *mnem, MachInst _machInst, + OpClass __opClass) : + BranchDisp(mnem, _machInst, __opClass) + { + disp = sign_ext((D16HI << 16) | (D16LO << 2), 18); + } + }; + + /** + * Base class for branches that use an immediate and a register to + * compute their displacements. + */ + class BranchImm13 : public Branch + { + protected: + // Constructor + BranchImm13(const char *mnem, MachInst _machInst, OpClass __opClass) : + Branch(mnem, _machInst, __opClass), imm(sign_ext(SIMM13, 13)) + { + } + + std::string generateDisassembly(Addr pc, + const SymbolTable *symtab) const; + + int32_t imm; + }; }}; output decoder {{ - std::string Branch::generateDisassembly(Addr pc, const SymbolTable *symtab) const + std::string Branch::generateDisassembly(Addr pc, + const SymbolTable *symtab) const { - return "Branch instruction\n"; + std::stringstream response; + + printMnemonic(response, mnemonic); + + if (_numSrcRegs > 0) + { + printReg(response, _srcRegIdx[0]); + for(int x = 1; x < _numSrcRegs; x++) + { + response << ", "; + printReg(response, _srcRegIdx[x]); + } + } + + if (_numDestRegs > 0) + { + if(_numSrcRegs > 0) + response << ", "; + printReg(response, _destRegIdx[0]); + } + + return response.str(); + } + + std::string BranchImm13::generateDisassembly(Addr pc, + const SymbolTable *symtab) const + { + std::stringstream response; + + printMnemonic(response, mnemonic); + + if (_numSrcRegs > 0) + { + printReg(response, _srcRegIdx[0]); + for(int x = 1; x < _numSrcRegs; x++) + { + response << ", "; + printReg(response, _srcRegIdx[x]); + } + } + + if(_numSrcRegs > 0) + response << ", "; + + ccprintf(response, "0x%x", imm); + + if (_numDestRegs > 0) + { + response << ", "; + printReg(response, _destRegIdx[0]); + } + + return response.str(); + } + + std::string BranchDisp::generateDisassembly(Addr pc, + const SymbolTable *symtab) const + { + std::stringstream response; + std::string symbol; + Addr symbolAddr; + + Addr target = disp + pc; + + printMnemonic(response, mnemonic); + ccprintf(response, "0x%x", target); + + if(symtab->findNearestSymbol(target, symbol, symbolAddr)) + { + ccprintf(response, " <%s", symbol); + if(symbolAddr != target) + ccprintf(response, "+0x%x>", target - symbolAddr); + else + ccprintf(response, ">"); + } + + return response.str(); } }}; @@ -37,6 +212,8 @@ def template BranchExecute {{ %(op_decl)s; %(op_rd)s; + + NNPC = xc->readNextNPC(); %(code)s; if(fault == NoFault) @@ -49,13 +226,63 @@ def template BranchExecute {{ } }}; -// Primary format for integer operate instructions: +// Primary format for branch instructions: def format Branch(code, *opt_flags) {{ - orig_code = code - cblk = CodeBlock(code) - iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags) + (usesImm, code, immCode, + rString, iString) = splitOutImm(code) + codeBlk = CodeBlock(code) + iop = InstObjParams(name, Name, 'Branch', codeBlk, opt_flags) header_output = BasicDeclare.subst(iop) decoder_output = BasicConstructor.subst(iop) + exec_output = BranchExecute.subst(iop) + if usesImm: + imm_iop = InstObjParams(name, Name + 'Imm', 'BranchImm' + iString, + codeBlk, opt_flags) + header_output += BasicDeclare.subst(imm_iop) + decoder_output += BasicConstructor.subst(imm_iop) + exec_output += BranchExecute.subst(imm_iop) + decode_block = ROrImmDecode.subst(iop) + else: + decode_block = BasicDecode.subst(iop) +}}; + +// Primary format for branch instructions: +def format Branch19(code, *opt_flags) {{ + codeBlk = CodeBlock(code) + iop = InstObjParams(name, Name, 'Branch19', codeBlk, opt_flags) + header_output = BasicDeclare.subst(iop) + decoder_output = BasicConstructor.subst(iop) + exec_output = BranchExecute.subst(iop) decode_block = BasicDecode.subst(iop) +}}; + +// Primary format for branch instructions: +def format Branch22(code, *opt_flags) {{ + codeBlk = CodeBlock(code) + iop = InstObjParams(name, Name, 'Branch22', codeBlk, opt_flags) + header_output = BasicDeclare.subst(iop) + decoder_output = BasicConstructor.subst(iop) exec_output = BranchExecute.subst(iop) + decode_block = BasicDecode.subst(iop) +}}; + +// Primary format for branch instructions: +def format Branch30(code, *opt_flags) {{ + codeBlk = CodeBlock(code) + iop = InstObjParams(name, Name, 'Branch30', codeBlk, opt_flags) + header_output = BasicDeclare.subst(iop) + decoder_output = BasicConstructor.subst(iop) + exec_output = BranchExecute.subst(iop) + decode_block = BasicDecode.subst(iop) }}; + +// Primary format for branch instructions: +def format BranchSplit(code, *opt_flags) {{ + codeBlk = CodeBlock(code) + iop = InstObjParams(name, Name, 'BranchSplit', codeBlk, opt_flags) + header_output = BasicDeclare.subst(iop) + decoder_output = BasicConstructor.subst(iop) + exec_output = BranchExecute.subst(iop) + decode_block = BasicDecode.subst(iop) +}}; + diff --git a/arch/sparc/isa/formats/integerop.isa b/arch/sparc/isa/formats/integerop.isa index e7bd4c2a4..f14f9e858 100644 --- a/arch/sparc/isa/formats/integerop.isa +++ b/arch/sparc/isa/formats/integerop.isa @@ -11,103 +11,230 @@ output header {{ { protected: // Constructor - IntOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : + IntOp(const char *mnem, ExtMachInst _machInst, + OpClass __opClass) : SparcStaticInst(mnem, _machInst, __opClass) { } std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + + virtual bool printPseudoOps(std::ostream &os, Addr pc, + const SymbolTable *symtab) const; }; /** - * Base class for 10 bit immediate integer operations. + * Base class for immediate integer operations. */ - class IntOpImm10 : public IntOp + class IntOpImm : public IntOp { protected: // Constructor - IntOpImm10(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : - IntOp(mnem, _machInst, __opClass), imm(SIMM10) + IntOpImm(const char *mnem, ExtMachInst _machInst, + OpClass __opClass) : + IntOp(mnem, _machInst, __opClass) { } - uint32_t imm; + int32_t imm; + + std::string generateDisassembly(Addr pc, + const SymbolTable *symtab) const; + + virtual bool printPseudoOps(std::ostream &os, Addr pc, + const SymbolTable *symtab) const; + }; + + /** + * Base class for 10 bit immediate integer operations. + */ + class IntOpImm10 : public IntOpImm + { + protected: + // Constructor + IntOpImm10(const char *mnem, ExtMachInst _machInst, + OpClass __opClass) : + IntOpImm(mnem, _machInst, __opClass) + { + imm = sign_ext(SIMM10, 10); + } }; /** * Base class for 13 bit immediate integer operations. */ - class IntOpImm13 : public IntOp + class IntOpImm13 : public IntOpImm { protected: // Constructor - IntOpImm13(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : - IntOp(mnem, _machInst, __opClass), imm(SIMM13) + IntOpImm13(const char *mnem, ExtMachInst _machInst, + OpClass __opClass) : + IntOpImm(mnem, _machInst, __opClass) { + imm = sign_ext(SIMM13, 13); } + }; - uint32_t imm; + /** + * Base class for sethi. + */ + class SetHi : public IntOpImm + { + protected: + // Constructor + SetHi(const char *mnem, ExtMachInst _machInst, + OpClass __opClass) : + IntOpImm(mnem, _machInst, __opClass) + { + imm = (IMM22 << 10) & 0xFFFFFC00; + } + + std::string generateDisassembly(Addr pc, + const SymbolTable *symtab) const; }; }}; +def template SetHiDecode {{ + { + if(RD == 0 && IMM22 == 0) + return (SparcStaticInst *)(new Nop("nop", machInst, No_OpClass)); + else + return (SparcStaticInst *)(new %(class_name)s(machInst)); + } +}}; + output decoder {{ - std::string IntOp::generateDisassembly(Addr pc, - const SymbolTable *symtab) const + + bool IntOp::printPseudoOps(std::ostream &os, Addr pc, + const SymbolTable *symbab) const { - return "Integer instruction\n"; + if(!strcmp(mnemonic, "or") && _srcRegIdx[0] == 0) + { + printMnemonic(os, "mov"); + if(_numSrcRegs > 0) + printReg(os, _srcRegIdx[1]); + ccprintf(os, ", "); + if(_numDestRegs > 0) + printReg(os, _destRegIdx[0]); + + return true; + } + return false; } -}}; -def template IntOpExecute {{ - Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, - Trace::InstRecord *traceData) const + bool IntOpImm::printPseudoOps(std::ostream &os, Addr pc, + const SymbolTable *symbab) const { - Fault fault = NoFault; + if(!strcmp(mnemonic, "or")) + { + if(_srcRegIdx[0] == 0) + { + if(imm == 0) + { + printMnemonic(os, "clr"); + if(_numDestRegs > 0) + printReg(os, _destRegIdx[0]); + return true; + } + else + { + printMnemonic(os, "mov"); + ccprintf(os, ", 0x%x, ", imm); + if(_numDestRegs > 0) + printReg(os, _destRegIdx[0]); + return true; + } + } + else if(imm == 0) + { + printMnemonic(os, "mov"); + if(_numSrcRegs > 0) + printReg(os, _srcRegIdx[0]); + ccprintf(os, ", "); + if(_numDestRegs > 0) + printReg(os, _destRegIdx[0]); + return true; + } + } + return false; + } - %(op_decl)s; - %(op_rd)s; - %(code)s; + std::string IntOp::generateDisassembly(Addr pc, + const SymbolTable *symtab) const + { + std::stringstream response; - //Write the resulting state to the execution context - if(fault == NoFault) - %(op_wb)s; - return fault; + if(!printPseudoOps(response, pc, symtab)) + { + printMnemonic(response, mnemonic); + if (_numSrcRegs > 0) + { + printReg(response, _srcRegIdx[0]); + for(int x = 1; x < _numSrcRegs; x++) + { + response << ", "; + printReg(response, _srcRegIdx[x]); + } + } + if (_numDestRegs > 0) + { + if(_numSrcRegs > 0) + response << ", "; + printReg(response, _destRegIdx[0]); + } + } + return response.str(); } -}}; -def template IntOpCcExecute {{ - Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, - Trace::InstRecord *traceData) const + std::string IntOpImm::generateDisassembly(Addr pc, + const SymbolTable *symtab) const { - Fault fault; - - %(op_decl)s; - %(op_rd)s; - %(code)s; + std::stringstream response; - //Write the resulting state to the execution context - if(fault == NoFault) + if(!printPseudoOps(response, pc, symtab)) { - %(op_wb)s; - CcrIccN = Rd & (1 << 63); - CcrIccZ = (Rd == 0); - CcrIccV = ivValue; - CcrIccC = icValue; - CcrXccN = Rd & (1 << 31); - CcrXccZ = ((Rd & 0xFFFFFFFF) == 0); - CcrXccV = xvValue; - CcrXccC = xcValue; + printMnemonic(response, mnemonic); + if (_numSrcRegs > 0) + { + printReg(response, _srcRegIdx[0]); + for(int x = 1; x < _numSrcRegs - 1; x++) + { + response << ", "; + printReg(response, _srcRegIdx[x]); + } + } + if(_numSrcRegs > 0) + response << ", "; + ccprintf(response, "0x%x", imm); + if (_numDestRegs > 0) + { + response << ", "; + printReg(response, _destRegIdx[0]); + } } - return fault; + return response.str(); + } + + std::string SetHi::generateDisassembly(Addr pc, + const SymbolTable *symtab) const + { + std::stringstream response; + + printMnemonic(response, mnemonic); + if(_numSrcRegs > 0) + response << ", "; + ccprintf(response, "%%hi(0x%x), ", imm); + printReg(response, _destRegIdx[0]); + return response.str(); } }}; -def template IntOpCcResExecute {{ +def template IntOpExecute {{ Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const { - Fault fault; + Fault fault = NoFault; %(op_decl)s; %(op_rd)s; @@ -117,49 +244,83 @@ def template IntOpCcResExecute {{ if(fault == NoFault) { %(op_wb)s; - CcrIccN = Rd & (1 << 63); - CcrIccZ = (Rd == 0); - CcrXccN = Rd & (1 << 31); - CcrXccZ = ((Rd & 0xFFFFFFFF) == 0); - CcrIccV = CcrIccC = CcrXccV = CcrXccC = 0; + %(cc_code)s; } return fault; } }}; let {{ - def doIntFormat(code, execTemplate, name, Name, opt_flags): - (usesImm, cblk, immCblk, rString, iString) = splitOutImm(code) - iop = InstObjParams(name, Name, 'IntOp', cblk, opt_flags) + def doIntFormat(code, ccCode, name, Name, opt_flags): + (usesImm, code, immCode, + rString, iString) = splitOutImm(code) + iop = InstObjParams(name, Name, 'IntOp', code, + opt_flags, ("cc_code", ccCode)) header_output = BasicDeclare.subst(iop) decoder_output = BasicConstructor.subst(iop) - exec_output = execTemplate.subst(iop) + exec_output = IntOpExecute.subst(iop) if usesImm: imm_iop = InstObjParams(name, Name + 'Imm', 'IntOpImm' + iString, - immCblk, opt_flags) + immCode, opt_flags, ("cc_code", ccCode)) header_output += BasicDeclare.subst(imm_iop) decoder_output += BasicConstructor.subst(imm_iop) - exec_output += execTemplate.subst(imm_iop) + exec_output += IntOpExecute.subst(imm_iop) decode_block = ROrImmDecode.subst(iop) else: decode_block = BasicDecode.subst(iop) + return (header_output, decoder_output, exec_output, decode_block) + + calcCcCode = ''' + CcrIccN = (Rd >> 63) & 1; + CcrIccZ = (Rd == 0); + CcrXccN = (Rd >> 31) & 1; + CcrXccZ = ((Rd & 0xFFFFFFFF) == 0); + CcrIccV = %(ivValue)s; + CcrIccC = %(icValue)s; + CcrXccV = %(xvValue)s; + CcrXccC = %(xcValue)s; + ''' }}; // Primary format for integer operate instructions: def format IntOp(code, *opt_flags) {{ - doIntFormat(code, IntOpExecute, name, Name, opt_flags) + ccCode = '' + (header_output, + decoder_output, + exec_output, + decode_block) = doIntFormat(code, ccCode, + name, Name, opt_flags) }}; // Primary format for integer operate instructions: def format IntOpCc(code, icValue, ivValue, xcValue, xvValue, *opt_flags) {{ - for (marker, value) in (('ivValue', ivValue), ('icValue', icValue), - ('xvValue', xvValue), ('xcValue', xcValue)): - code.replace(marker, value) - doIntFormat(code, IntOpCcExecute, name, Name, opt_flags) + ccCode = calcCcCode % vars() + (header_output, + decoder_output, + exec_output, + decode_block) = doIntFormat(code, ccCode, + name, Name, opt_flags) }}; // Primary format for integer operate instructions: def format IntOpCcRes(code, *opt_flags) {{ - doIntFormat(code, IntOpCcResExecute, name, Name, opt_flags) + ccCode = calcCcCode % {"icValue":"0", + "ivValue":"0", + "xcValue":"0", + "xvValue":"0"} + (header_output, + decoder_output, + exec_output, + decode_block) = doIntFormat(code, ccCode, + name, Name, opt_flags) +}}; + +def format SetHi(code, *opt_flags) {{ + iop = InstObjParams(name, Name, 'SetHi', + code, opt_flags, ("cc_code", '')) + header_output = BasicDeclare.subst(iop) + decoder_output = BasicConstructor.subst(iop) + exec_output = IntOpExecute.subst(iop) + decode_block = SetHiDecode.subst(iop) }}; diff --git a/arch/sparc/isa/formats/mem.isa b/arch/sparc/isa/formats/mem.isa index f1162e24b..db2a4aaaa 100644 --- a/arch/sparc/isa/formats/mem.isa +++ b/arch/sparc/isa/formats/mem.isa @@ -5,7 +5,7 @@ output header {{ /** - * Base class for integer operations. + * Base class for memory operations. */ class Mem : public SparcStaticInst { @@ -20,12 +20,76 @@ output header {{ std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; }; + + /** + * Class for memory operations which use an immediate offset. + */ + class MemImm : public Mem + { + protected: + + // Constructor + MemImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : + Mem(mnem, _machInst, __opClass), imm(SIMM13) + { + } + + std::string generateDisassembly(Addr pc, + const SymbolTable *symtab) const; + + int32_t imm; + }; }}; output decoder {{ - std::string Mem::generateDisassembly(Addr pc, const SymbolTable *symtab) const + std::string Mem::generateDisassembly(Addr pc, + const SymbolTable *symtab) const + { + std::stringstream response; + bool load = flags[IsLoad]; + + printMnemonic(response, mnemonic); + if(!load) + { + printReg(response, _srcRegIdx[0]); + ccprintf(response, ", "); + } + ccprintf(response, "[ "); + printReg(response, _srcRegIdx[load ? 0 : 1]); + ccprintf(response, " + "); + printReg(response, _srcRegIdx[load ? 1 : 2]); + ccprintf(response, " ]"); + if(load) + { + ccprintf(response, ", "); + printReg(response, _destRegIdx[0]); + } + + return response.str(); + } + + std::string MemImm::generateDisassembly(Addr pc, + const SymbolTable *symtab) const { - return "Memory instruction\n"; + std::stringstream response; + bool load = flags[IsLoad]; + + printMnemonic(response, mnemonic); + if(!load) + { + printReg(response, _srcRegIdx[0]); + ccprintf(response, ", "); + } + ccprintf(response, "[ "); + printReg(response, _srcRegIdx[load ? 0 : 1]); + ccprintf(response, " + 0x%x ]", imm); + if(load) + { + ccprintf(response, ", "); + printReg(response, _destRegIdx[0]); + } + + return response.str(); } }}; @@ -38,7 +102,9 @@ def template MemExecute {{ %(op_decl)s; %(op_rd)s; %(ea_code)s; + %(load)s; %(code)s; + %(store)s; if(fault == NoFault) { @@ -50,19 +116,49 @@ def template MemExecute {{ } }}; -// Primary format for integer operate instructions: -def format Mem(code, *opt_flags) {{ - addrCalc = 'EA = I ? (Rs1 + SIMM13) : Rs1 + Rs2;' - composite = code + '\n' + addrCalc - origCodeBlk = CodeBlock(code) - compositeBlk = CodeBlock(composite) - addrCalcBlk = CodeBlock(addrCalc) - iop = InstObjParams(name, Name, 'SparcStaticInst', compositeBlk, opt_flags) - iop.code = origCodeBlk.code - iop.orig_code = origCodeBlk.orig_code - iop.ea_code = addrCalcBlk.code - header_output = BasicDeclare.subst(iop) - decoder_output = BasicConstructor.subst(iop) - decode_block = BasicDecode.subst(iop) - exec_output = MemExecute.subst(iop) +let {{ + # Leave memAccessFlags at 0 for now + loadString = "xc->read(EA, (uint%(width)s_t&)Mem, 0);" + storeString = "uint64_t write_result = 0; \ + xc->write((uint%(width)s_t)Mem, EA, 0, &write_result);" + + def doMemFormat(code, load, store, name, Name, opt_flags): + addrCalcReg = 'EA = Rs1 + Rs2;' + addrCalcImm = 'EA = Rs1 + SIMM13;' + iop = InstObjParams(name, Name, 'Mem', code, + opt_flags, ("ea_code", addrCalcReg), + ("load", load), ("store", store)) + iop_imm = InstObjParams(name, Name + 'Imm', 'MemImm', code, + opt_flags, ("ea_code", addrCalcImm), + ("load", load), ("store", store)) + header_output = BasicDeclare.subst(iop) + BasicDeclare.subst(iop_imm) + decoder_output = BasicConstructor.subst(iop) + BasicConstructor.subst(iop_imm) + decode_block = ROrImmDecode.subst(iop) + exec_output = MemExecute.subst(iop) + MemExecute.subst(iop_imm) + return (header_output, decoder_output, exec_output, decode_block) +}}; + +def format Load(code, width, *opt_flags) {{ + (header_output, + decoder_output, + exec_output, + decode_block) = doMemFormat(code, + loadString % {"width":width}, '', name, Name, opt_flags) +}}; + +def format Store(code, width, *opt_flags) {{ + (header_output, + decoder_output, + exec_output, + decode_block) = doMemFormat(code, '', + storeString % {"width":width}, name, Name, opt_flags) +}}; + +def format LoadStore(code, width, *opt_flags) {{ + (header_output, + decoder_output, + exec_output, + decode_block) = doMemFormat(code, + loadString % {"width":width}, storeString % {"width":width}, + name, Name, opt_flags) }}; diff --git a/arch/sparc/isa/formats/noop.isa b/arch/sparc/isa/formats/nop.isa index 5007f5bcb..df7503eee 100644 --- a/arch/sparc/isa/formats/noop.isa +++ b/arch/sparc/isa/formats/nop.isa @@ -1,35 +1,47 @@ //////////////////////////////////////////////////////////////////// // -// Noop instruction +// Nop instruction // output header {{ /** - * Noop class. + * Nop class. */ - class Noop : public SparcStaticInst + class Nop : public SparcStaticInst { - protected: + public: // Constructor - Noop(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : + Nop(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : SparcStaticInst(mnem, _machInst, __opClass) { } + // All Nop instructions do the same thing, so this can be + // defined here. Nops can be defined directly, so there needs + // to be a default implementation + Fault execute(%(CPU_exec_context)s *xc, + Trace::InstRecord *traceData) const + { + //Nothing to see here, move along + return NoFault; + } + std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; }; }}; output decoder {{ - std::string Noop::generateDisassembly(Addr pc, + std::string Nop::generateDisassembly(Addr pc, const SymbolTable *symtab) const { - return "Noop\n"; + std::stringstream response; + printMnemonic(response, mnemonic); + return response.str(); } }}; -def template NoopExecute {{ +def template NopExecute {{ Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const { @@ -39,12 +51,12 @@ def template NoopExecute {{ }}; // Primary format for integer operate instructions: -def format Noop(code, *opt_flags) {{ +def format Nop(code, *opt_flags) {{ orig_code = code cblk = CodeBlock(code) - iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags) + iop = InstObjParams(name, Name, 'Nop', cblk, opt_flags) header_output = BasicDeclare.subst(iop) decoder_output = BasicConstructor.subst(iop) decode_block = BasicDecode.subst(iop) - exec_output = NoopExecute.subst(iop) + exec_output = NopExecute.subst(iop) }}; diff --git a/arch/sparc/isa/formats/priv.isa b/arch/sparc/isa/formats/priv.isa index 162ad5ee0..f9fea01f2 100644 --- a/arch/sparc/isa/formats/priv.isa +++ b/arch/sparc/isa/formats/priv.isa @@ -50,7 +50,7 @@ output header {{ { } - uint32_t imm; + int32_t imm; }; /** @@ -66,7 +66,7 @@ output header {{ { } - uint32_t imm; + int32_t imm; }; }}; @@ -91,35 +91,8 @@ def template PrivExecute {{ %(op_decl)s; %(op_rd)s; - //Since these are processed inside templates and not in codeblocks, - //They aren't translated by the isa_parser. Their names begin with - //underscores so they don't cause conflicts. - uint32_t _PstatePriv = xc->readMiscReg(MISCREG_PSTATE_PRIV); - //If the processor isn't in privileged mode, fault out right away - if(!_PstatePriv) - return new PrivilegedOpcode; - - %(code)s; - %(op_wb)s; - return NoFault; - } -}}; - -def template PrivTickExecute {{ - Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, - Trace::InstRecord *traceData) const - { - %(op_decl)s; - %(op_rd)s; - - //Since these are processed inside templates and not in codeblocks, - //They aren't translated by the isa_parser. Their names begin with - //underscores so they don't cause conflicts. - uint32_t _PstatePriv = xc->readMiscReg(MISCREG_PSTATE_PRIV); - uint32_t _TickNpt = xc->readMiscReg(MISCREG_TICK_NPT); - //If the processor isn't in privileged mode, fault out right away - if(!_PstatePriv && _TickNpt) + if(%(check)s) return new PrivilegedAction; %(code)s; @@ -128,50 +101,39 @@ def template PrivTickExecute {{ } }}; -// Primary format for integer operate instructions: -def format Priv(code, *opt_flags) {{ - uses_imm = (code.find('Rs2_or_imm13') != -1) - if uses_imm: - orig_code = code - code = re.sub(r'Rs2_or_imm13', 'Rs2', orig_code) - imm_code = re.sub(r'Rs2_or_imm13(\.\w+)?', 'imm', orig_code) - cblk = CodeBlock(code) - iop = InstObjParams(name, Name, 'Priv', cblk, opt_flags) +let {{ + def doPrivFormat(code, checkCode, name, Name, opt_flags): + (usesImm, code, immCode, + rString, iString) = splitOutImm(code) + iop = InstObjParams(name, Name, 'Priv', code, + opt_flags, ("check", checkCode)) header_output = BasicDeclare.subst(iop) decoder_output = BasicConstructor.subst(iop) exec_output = PrivExecute.subst(iop) - if uses_imm: - imm_cblk = CodeBlock(imm_code) - imm_iop = InstObjParams(name, Name + 'Imm', 'PrivImm', imm_cblk, - opt_flags) + if usesImm: + imm_iop = InstObjParams(name, Name + 'Imm', 'PrivImm', + immCode, opt_flags, ("check", checkCode)) header_output += BasicDeclare.subst(imm_iop) decoder_output += BasicConstructor.subst(imm_iop) exec_output += PrivExecute.subst(imm_iop) decode_block = ROrImmDecode.subst(iop) else: decode_block = BasicDecode.subst(iop) + return (header_output, decoder_output, exec_output, decode_block) +}}; + +// Primary format for integer operate instructions: +def format Priv(code, *opt_flags) {{ + checkCode = "(!PstatePriv)" + (header_output, decoder_output, + exec_output, decode_block) = doPrivFormat(code, + checkCode, name, Name, opt_flags) }}; // Primary format for integer operate instructions: def format PrivTick(code, *opt_flags) {{ - uses_imm = (code.find('Rs2_or_imm13') != -1) - if uses_imm: - orig_code = code - code = re.sub(r'Rs2_or_imm13', 'Rs2', orig_code) - imm_code = re.sub(r'Rs2_or_imm13(\.\w+)?', 'imm', orig_code) - cblk = CodeBlock(code) - iop = InstObjParams(name, Name, 'PrivTick', cblk, opt_flags) - header_output = BasicDeclare.subst(iop) - decoder_output = BasicConstructor.subst(iop) - exec_output = PrivTickExecute.subst(iop) - if uses_imm: - imm_cblk = CodeBlock(imm_code) - imm_iop = InstObjParams(name, Name + 'Imm', 'PrivTickImm', imm_cblk, - opt_flags) - header_output += BasicDeclare.subst(imm_iop) - decoder_output += BasicConstructor.subst(imm_iop) - exec_output += PrivTickExecute.subst(imm_iop) - decode_block = Rb2OrImmDecode.subst(iop) - else: - decode_block = BasicDecode.subst(iop) + checkCode = "(!PstatePriv && TickNpt)" + (header_output, decoder_output, + exec_output, decode_block) = doPrivFormat(code, + checkCode, name, Name, opt_flags) }}; diff --git a/arch/sparc/isa/formats/trap.isa b/arch/sparc/isa/formats/trap.isa index db4494132..5608548bd 100644 --- a/arch/sparc/isa/formats/trap.isa +++ b/arch/sparc/isa/formats/trap.isa @@ -27,7 +27,7 @@ output decoder {{ std::string Trap::generateDisassembly(Addr pc, const SymbolTable *symtab) const { - return "Trap instruction\n"; + return "Trap instruction"; } }}; @@ -46,7 +46,7 @@ def template TrapExecute {{ def format Trap(code, *opt_flags) {{ orig_code = code cblk = CodeBlock(code) - iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags) + iop = InstObjParams(name, Name, 'Trap', cblk, opt_flags) header_output = BasicDeclare.subst(iop) decoder_output = BasicConstructor.subst(iop) decode_block = BasicDecode.subst(iop) diff --git a/arch/sparc/isa/formats/unknown.isa b/arch/sparc/isa/formats/unknown.isa index eeb2b9496..223111905 100644 --- a/arch/sparc/isa/formats/unknown.isa +++ b/arch/sparc/isa/formats/unknown.isa @@ -29,7 +29,7 @@ output decoder {{ std::string Unknown::generateDisassembly(Addr pc, const SymbolTable *symtab) const { - return "Unknown instruction\n"; + return "Unknown instruction"; } }}; diff --git a/arch/sparc/isa/includes.isa b/arch/sparc/isa/includes.isa index c39fc2ef9..ff4174899 100644 --- a/arch/sparc/isa/includes.isa +++ b/arch/sparc/isa/includes.isa @@ -12,6 +12,7 @@ output header {{ #include "arch/sparc/faults.hh" #include "mem/request.hh" // some constructors use MemReq flags #include "arch/sparc/isa_traits.hh" +#include "arch/sparc/regfile.hh" }}; output decoder {{ diff --git a/arch/sparc/isa/operands.isa b/arch/sparc/isa/operands.isa index 0d521fae0..17e58ad59 100644 --- a/arch/sparc/isa/operands.isa +++ b/arch/sparc/isa/operands.isa @@ -25,11 +25,13 @@ def operands {{ #'Fb': ('FloatReg', 'df', 'FB', 'IsFloating', 2), #'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3), 'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4), - #'NPC': ('NPC', 'uq', None, ( None, None, 'IsControl' ), 4), + 'NPC': ('NPC', 'udw', None, ( None, None, 'IsControl' ), 4), + 'NNPC': ('NNPC', 'udw', None, (None, None, 'IsControl' ), 4), #'Runiq': ('ControlReg', 'uq', 'Uniq', None, 1), #'FPCR': ('ControlReg', 'uq', 'Fpcr', None, 1), - 'R0': ('IntReg', 'udw', '0', None, 1), - 'R16': ('IntReg', 'udw', '16', None, 1), + 'R0': ('IntReg', 'udw', '0', None, 6), + 'R15': ('IntReg', 'udw', '15', 'IsInteger', 7), + 'R16': ('IntReg', 'udw', '16', None, 8), # Control registers 'Pstate': ('ControlReg', 'udw', 'MISCREG_PSTATE', None, 1), 'PstateAg': ('ControlReg', 'udw', 'MISCREG_PSTATE_AG', None, 2), @@ -57,7 +59,7 @@ def operands {{ 'CcrXccC': ('ControlReg', 'udw', 'MISCREG_CCR_XCC_C', None, 22), 'CcrXccV': ('ControlReg', 'udw', 'MISCREG_CCR_XCC_V', None, 23), 'CcrXccZ': ('ControlReg', 'udw', 'MISCREG_CCR_XCC_Z', None, 24), - 'CcrXccN': ('ControlReg', 'udw', 'MISCREG_XCC_N', None, 25), + 'CcrXccN': ('ControlReg', 'udw', 'MISCREG_CCR_XCC_N', None, 25), 'Asi': ('ControlReg', 'udw', 'MISCREG_ASI', None, 26), 'Tl': ('ControlReg', 'udw', 'MISCREG_TL', None, 27), #'Tpc': ('ControlReg', 'udw', 'MISCREG_TPC', None, 28), diff --git a/arch/sparc/isa_traits.hh b/arch/sparc/isa_traits.hh index 6cf77eb0e..57206c5e5 100644 --- a/arch/sparc/isa_traits.hh +++ b/arch/sparc/isa_traits.hh @@ -119,12 +119,12 @@ namespace SparcISA const int ArgumentReg4 = 12; const int ArgumentReg5 = 13; const int SyscallNumReg = 1; - // Some OS syscall sue a second register (o1) to return a second value + // Some OS syscall use a second register (o1) to return a second value const int SyscallPseudoReturnReg = ArgumentReg1; //XXX These numbers are bogus - const int MaxInstSrcRegs = 3; - const int MaxInstDestRegs = 2; + const int MaxInstSrcRegs = 8; + const int MaxInstDestRegs = 3; typedef uint64_t IntReg; @@ -174,12 +174,12 @@ namespace SparcISA // and put the return value itself in the standard return value reg (). if (return_value.successful()) { // no error - regs->miscRegs.setReg(MISCREG_CCR_ICC_C, 0); - regs->intRegFile[ReturnValueReg] = return_value.value(); + regs->setMiscReg(MISCREG_CCR_ICC_C, 0); + regs->setIntReg(ReturnValueReg, return_value.value()); } else { // got an error, return details - regs->miscRegs.setReg(MISCREG_CCR_ICC_C, 1); - regs->intRegFile[ReturnValueReg] = -return_value.value(); + regs->setMiscReg(MISCREG_CCR_ICC_C, 1); + regs->setIntReg(ReturnValueReg, return_value.value()); } } #endif diff --git a/arch/sparc/linux/process.cc b/arch/sparc/linux/process.cc index cb056eadc..c7e5f79ca 100644 --- a/arch/sparc/linux/process.cc +++ b/arch/sparc/linux/process.cc @@ -356,9 +356,9 @@ SparcLinuxProcess::SparcLinuxProcess(const std::string &name, stdin_fd, stdout_fd, stderr_fd, argv, envp), Num_Syscall_Descs(sizeof(syscallDescs) / sizeof(SyscallDesc)) { - // The sparc syscall table must be <= 283 entries because that is all there + // The sparc syscall table must be <= 284 entries because that is all there // is space for. - assert(Num_Syscall_Descs <= 283); + assert(Num_Syscall_Descs <= 284); } diff --git a/arch/sparc/regfile.hh b/arch/sparc/regfile.hh index 09b8e49d7..566cd1d1f 100644 --- a/arch/sparc/regfile.hh +++ b/arch/sparc/regfile.hh @@ -30,6 +30,7 @@ #define __ARCH_SPARC_REGFILE_HH__ #include "arch/sparc/faults.hh" +#include "base/trace.hh" #include "sim/byteswap.hh" #include "sim/host.hh" @@ -40,11 +41,112 @@ namespace SparcISA typedef uint8_t RegIndex; - // Maximum trap level + // MAXTL - maximum trap level const int MaxTL = 4; - //For right now, let's pretend the register file is flat - typedef IntReg IntRegFile[NumIntRegs]; + // NWINDOWS - number of register windows, can be 3 to 32 + const int NWindows = 6; + + class IntRegFile + { + protected: + static const int FrameOffsetBits = 3; + static const int FrameNumBits = 2; + + static const int RegsPerFrame = 1 << FrameOffsetBits; + static const int FrameNumMask = + (FrameNumBits == sizeof(int)) ? + (unsigned int)(-1) : + (1 << FrameNumBits) - 1; + static const int FrameOffsetMask = + (FrameOffsetBits == sizeof(int)) ? + (unsigned int)(-1) : + (1 << FrameOffsetBits) - 1; + + IntReg regGlobals[RegsPerFrame]; + IntReg altGlobals[RegsPerFrame]; + IntReg regSegments[2 * NWindows][RegsPerFrame]; + + enum regFrame {Globals, Outputs, Locals, Inputs, NumFrames}; + + IntReg * regView[NumFrames]; + + static const int RegGlobalOffset = 0; + static const int AltGlobalOffset = 8; + static const int FrameOffset = 16; + int offset[NumFrames]; + + public: + + int flattenIndex(int reg) + { + int flatIndex = offset[reg >> FrameOffsetBits] + | (reg & FrameOffsetMask); + DPRINTF(Sparc, "Flattened index %d into %d.\n", reg, flatIndex); + return flatIndex; + } + + void clear() + { + bzero(regGlobals, sizeof(regGlobals)); + bzero(altGlobals, sizeof(altGlobals)); + for(int x = 0; x < 2 * NWindows; x++) + bzero(regSegments[x], sizeof(regSegments[x])); + } + + IntRegFile() + { + offset[Globals] = 0; + regView[Globals] = regGlobals; + setCWP(0); + clear(); + } + + IntReg readReg(int intReg) + { + IntReg val = + regView[intReg >> FrameOffsetBits][intReg & FrameOffsetMask]; + DPRINTF(Sparc, "Read register %d = 0x%x\n", intReg, val); + return val; + } + + Fault setReg(int intReg, const IntReg &val) + { + if(intReg) + DPRINTF(Sparc, "Wrote register %d = 0x%x\n", intReg, val); + regView[intReg >> FrameOffsetBits][intReg & FrameOffsetMask] = val; + return NoFault; + } + + //This doesn't effect the actual CWP register. + //It's purpose is to adjust the view of the register file + //to what it would be if CWP = cwp. + void setCWP(int cwp) + { + int index = ((NWindows - cwp) % NWindows) * 2; + offset[Outputs] = FrameOffset + (index * RegsPerFrame); + offset[Locals] = FrameOffset + ((index+1) * RegsPerFrame); + offset[Inputs] = FrameOffset + + (((index+2) % (NWindows * 2)) * RegsPerFrame); + regView[Outputs] = regSegments[index]; + regView[Locals] = regSegments[index+1]; + regView[Inputs] = regSegments[(index+2) % (NWindows * 2)]; + + DPRINTF(Sparc, "Changed the CWP value to %d\n", cwp); + } + + void setAltGlobals(bool useAlt) + { + DPRINTF(Sparc, "Now using %s globals", + useAlt ? "alternate" : "regular"); + regView[Globals] = useAlt ? altGlobals : regGlobals; + offset[Globals] = useAlt ? AltGlobalOffset : RegGlobalOffset; + } + + void serialize(std::ostream &os); + + void unserialize(Checkpoint *cp, const std::string §ion); + }; typedef float float32_t; typedef double float64_t; @@ -54,11 +156,13 @@ namespace SparcISA class FloatRegFile { - protected: + public: static const int SingleWidth = 32; static const int DoubleWidth = 64; static const int QuadWidth = 128; + protected: + //Since the floating point registers overlap each other, //A generic storage space is used. The float to be returned is //pulled from the appropriate section of this region. @@ -66,6 +170,11 @@ namespace SparcISA public: + void clear() + { + bzero(regSpace, sizeof(regSpace)); + } + FloatReg readReg(int floatReg, int width) { //In each of these cases, we have to copy the value into a temporary @@ -90,12 +199,6 @@ namespace SparcISA } } - FloatReg readReg(int floatReg) - { - //Use the "natural" width of a single float - return readReg(floatReg, SingleWidth); - } - FloatRegBits readRegBits(int floatReg, int width) { //In each of these cases, we have to copy the value into a temporary @@ -120,12 +223,6 @@ namespace SparcISA } } - FloatRegBits readRegBits(int floatReg) - { - //Use the "natural" width of a single float - return readRegBits(floatReg, SingleWidth); - } - Fault setReg(int floatReg, const FloatReg &val, int width) { //In each of these cases, we have to copy the value into a temporary @@ -148,12 +245,6 @@ namespace SparcISA return NoFault; } - Fault setReg(int floatReg, const FloatReg &val) - { - //Use the "natural" width of a single float - return setReg(floatReg, val, SingleWidth); - } - Fault setRegBits(int floatReg, const FloatRegBits &val, int width) { //In each of these cases, we have to copy the value into a temporary @@ -176,12 +267,6 @@ namespace SparcISA return NoFault; } - Fault setRegBits(int floatReg, const FloatRegBits &val) - { - //Use the "natural" width of a single float - return setReg(floatReg, val, SingleWidth); - } - void serialize(std::ostream &os); void unserialize(Checkpoint *cp, const std::string §ion); @@ -474,14 +559,59 @@ namespace SparcISA }; public: + + void reset() + { + pstateFields.pef = 0; //No FPU + //pstateFields.pef = 1; //FPU +#if FULL_SYSTEM + //For SPARC, when a system is first started, there is a power + //on reset Trap which sets the processor into the following state. + //Bits that aren't set aren't defined on startup. + tl = MaxTL; + tt[tl] = PowerOnReset.trapType(); + pstateFields.mm = 0; //Total Store Order + pstateFields.red = 1; //Enter RED_State + pstateFields.am = 0; //Address Masking is turned off + pstateFields.priv = 1; //Processor enters privileged mode + pstateFields.ie = 0; //Interrupts are disabled + pstateFields.ag = 1; //Globals are replaced with alternate globals + pstateFields.tle = 0; //Big Endian mode for traps + pstateFields.cle = 0; //Big Endian mode for non-traps + tickFields.npt = 1; //The TICK register is unreadable by + //non-priveleged software +#else + //This sets up the initial state of the processor for usermode processes + pstateFields.priv = 0; //Process runs in user mode + pstateFields.ie = 1; //Interrupts are enabled + fsrFields.rd = 0; //Round to nearest + fsrFields.tem = 0; //Floating point traps not enabled + fsrFields.ns = 0; //Non standard mode off + fsrFields.qne = 0; //Floating point queue is empty + fsrFields.aexc = 0; //No accrued exceptions + fsrFields.cexc = 0; //No current exceptions + + //Register window management registers + otherwin = 0; //No windows contain info from other programs + canrestore = 0; //There are no windows to pop + cansave = MaxTL - 2; //All windows are available to save into + cleanwin = MaxTL; +#endif + } + + MiscRegFile() + { + reset(); + } + MiscReg readReg(int miscReg); MiscReg readRegWithEffect(int miscReg, Fault &fault, ExecContext *xc); Fault setReg(int miscReg, const MiscReg &val); - Fault setRegWithEffect(int miscReg, const MiscReg &val, - ExecContext *xc); + Fault setRegWithEffect(int miscReg, + const MiscReg &val, ExecContext * xc); void serialize(std::ostream & os); @@ -497,18 +627,171 @@ namespace SparcISA MiscReg ctrlreg; } AnyReg; - struct RegFile + class RegFile { - IntRegFile intRegFile; // (signed) integer register file - FloatRegFile floatRegFile; // floating point register file - MiscRegFile miscRegs; // control register file - + protected: Addr pc; // Program Counter Addr npc; // Next Program Counter Addr nnpc; + public: + Addr readPC() + { + return pc; + } + + void setPC(Addr val) + { + pc = val; + } + + Addr readNextPC() + { + return npc; + } + + void setNextPC(Addr val) + { + npc = val; + } + + Addr readNextNPC() + { + return nnpc; + } + + void setNextNPC(Addr val) + { + nnpc = val; + } + + protected: + IntRegFile intRegFile; // integer register file + FloatRegFile floatRegFile; // floating point register file + MiscRegFile miscRegFile; // control register file + + public: + + void clear() + { + intRegFile.clear(); + floatRegFile.clear(); + } + + int flattenIntIndex(int reg) + { + return intRegFile.flattenIndex(reg); + } + + MiscReg readMiscReg(int miscReg) + { + return miscRegFile.readReg(miscReg); + } + + MiscReg readMiscRegWithEffect(int miscReg, + Fault &fault, ExecContext *xc) + { + return miscRegFile.readRegWithEffect(miscReg, fault, xc); + } + + Fault setMiscReg(int miscReg, const MiscReg &val) + { + return miscRegFile.setReg(miscReg, val); + } + + Fault setMiscRegWithEffect(int miscReg, const MiscReg &val, + ExecContext * xc) + { + return miscRegFile.setRegWithEffect(miscReg, val, xc); + } + + FloatReg readFloatReg(int floatReg, int width) + { + return floatRegFile.readReg(floatReg, width); + } + + FloatReg readFloatReg(int floatReg) + { + //Use the "natural" width of a single float + return floatRegFile.readReg(floatReg, FloatRegFile::SingleWidth); + } + + FloatRegBits readFloatRegBits(int floatReg, int width) + { + return floatRegFile.readRegBits(floatReg, width); + } + + FloatRegBits readFloatRegBits(int floatReg) + { + //Use the "natural" width of a single float + return floatRegFile.readRegBits(floatReg, + FloatRegFile::SingleWidth); + } + + Fault setFloatReg(int floatReg, const FloatReg &val, int width) + { + return floatRegFile.setReg(floatReg, val, width); + } + + Fault setFloatReg(int floatReg, const FloatReg &val) + { + //Use the "natural" width of a single float + return setFloatReg(floatReg, val, FloatRegFile::SingleWidth); + } + + Fault setFloatRegBits(int floatReg, const FloatRegBits &val, int width) + { + return floatRegFile.setRegBits(floatReg, val, width); + } + + Fault setFloatRegBits(int floatReg, const FloatRegBits &val) + { + //Use the "natural" width of a single float + return floatRegFile.setRegBits(floatReg, val, + FloatRegFile::SingleWidth); + } + + IntReg readIntReg(int intReg) + { + return intRegFile.readReg(intReg); + } + + Fault setIntReg(int intReg, const IntReg &val) + { + return intRegFile.setReg(intReg, val); + } + void serialize(std::ostream &os); void unserialize(Checkpoint *cp, const std::string §ion); + + public: + + enum ContextParam + { + CONTEXT_CWP, + CONTEXT_GLOBALS + }; + + union ContextVal + { + MiscReg reg; + bool altGlobals; + }; + + void changeContext(ContextParam param, ContextVal val) + { + switch(param) + { + case CONTEXT_CWP: + intRegFile.setCWP(val.reg); + break; + case CONTEXT_GLOBALS: + intRegFile.setAltGlobals(val.altGlobals); + break; + default: + panic("Tried to set illegal context parameter in the SPARC regfile.\n"); + } + } }; void copyRegs(ExecContext *src, ExecContext *dest); diff --git a/base/loader/elf_object.cc b/base/loader/elf_object.cc index 58029bc3e..a104719af 100644 --- a/base/loader/elf_object.cc +++ b/base/loader/elf_object.cc @@ -77,11 +77,6 @@ ElfObject::tryFile(const string &fname, int fd, size_t len, uint8_t *data) return NULL; } else { //Detect the architecture - //Versioning issues in libelf need to be resolved to get the correct - //SPARC constants. - //If MIPS supports 32 bit executables, this may need to be changed. - //Also, there are other MIPS constants which may be used, like - //EM_MIPS_RS3_LE and EM_MIPS_X //Since we don't know how to check for alpha right now, we'll //just assume if it wasn't something else and it's 64 bit, that's //what it must be. diff --git a/base/traceflags.py b/base/traceflags.py index c3b878027..7dbaac60e 100644 --- a/base/traceflags.py +++ b/base/traceflags.py @@ -143,6 +143,7 @@ baseFlags = [ 'HWPrefetch', 'Stack', 'SimpleCPU', + 'Sparc', ] # diff --git a/configs/test/hello_sparc b/configs/test/hello_sparc Binary files differnew file mode 100755 index 000000000..e254ae33f --- /dev/null +++ b/configs/test/hello_sparc diff --git a/cpu/cpu_exec_context.cc b/cpu/cpu_exec_context.cc index e76c13fb0..62419adcf 100644 --- a/cpu/cpu_exec_context.cc +++ b/cpu/cpu_exec_context.cc @@ -63,7 +63,7 @@ CPUExecContext::CPUExecContext(BaseCPU *_cpu, int _thread_num, System *_sys, { proxy = new ProxyExecContext<CPUExecContext>(this); - memset(®s, 0, sizeof(RegFile)); + regs.clear(); if (cpu->params->profile) { profile = new FunctionProfile(system->kernelSymtab); @@ -105,7 +105,7 @@ CPUExecContext::CPUExecContext(BaseCPU *_cpu, int _thread_num, mem_port->setPeer(port); port->setPeer(mem_port); - memset(®s, 0, sizeof(RegFile)); + regs.clear(); proxy = new ProxyExecContext<CPUExecContext>(this); } diff --git a/cpu/cpu_exec_context.hh b/cpu/cpu_exec_context.hh index 22d2811d0..c74feec68 100644 --- a/cpu/cpu_exec_context.hh +++ b/cpu/cpu_exec_context.hh @@ -387,103 +387,103 @@ class CPUExecContext // uint64_t readIntReg(int reg_idx) { - return regs.intRegFile[reg_idx]; + return regs.readIntReg(reg_idx); } FloatReg readFloatReg(int reg_idx, int width) { - return regs.floatRegFile.readReg(reg_idx, width); + return regs.readFloatReg(reg_idx, width); } FloatReg readFloatReg(int reg_idx) { - return regs.floatRegFile.readReg(reg_idx); + return regs.readFloatReg(reg_idx); } FloatRegBits readFloatRegBits(int reg_idx, int width) { - return regs.floatRegFile.readRegBits(reg_idx, width); + return regs.readFloatRegBits(reg_idx, width); } FloatRegBits readFloatRegBits(int reg_idx) { - return regs.floatRegFile.readRegBits(reg_idx); + return regs.readFloatRegBits(reg_idx); } void setIntReg(int reg_idx, uint64_t val) { - regs.intRegFile[reg_idx] = val; + regs.setIntReg(reg_idx, val); } void setFloatReg(int reg_idx, FloatReg val, int width) { - regs.floatRegFile.setReg(reg_idx, val, width); + regs.setFloatReg(reg_idx, val, width); } void setFloatReg(int reg_idx, FloatReg val) { - regs.floatRegFile.setReg(reg_idx, val); + regs.setFloatReg(reg_idx, val); } void setFloatRegBits(int reg_idx, FloatRegBits val, int width) { - regs.floatRegFile.setRegBits(reg_idx, val, width); + regs.setFloatRegBits(reg_idx, val, width); } void setFloatRegBits(int reg_idx, FloatRegBits val) { - regs.floatRegFile.setRegBits(reg_idx, val); + regs.setFloatRegBits(reg_idx, val); } uint64_t readPC() { - return regs.pc; + return regs.readPC(); } void setPC(uint64_t val) { - regs.pc = val; + regs.setPC(val); } uint64_t readNextPC() { - return regs.npc; + return regs.readNextPC(); } void setNextPC(uint64_t val) { - regs.npc = val; + regs.setNextPC(val); } uint64_t readNextNPC() { - return regs.nnpc; + return regs.readNextNPC(); } void setNextNPC(uint64_t val) { - regs.nnpc = val; + regs.setNextNPC(val); } MiscReg readMiscReg(int misc_reg) { - return regs.miscRegs.readReg(misc_reg); + return regs.readMiscReg(misc_reg); } MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) { - return regs.miscRegs.readRegWithEffect(misc_reg, fault, proxy); + return regs.readMiscRegWithEffect(misc_reg, fault, proxy); } Fault setMiscReg(int misc_reg, const MiscReg &val) { - return regs.miscRegs.setReg(misc_reg, val); + return regs.setMiscReg(misc_reg, val); } Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) { - return regs.miscRegs.setRegWithEffect(misc_reg, val, proxy); + return regs.setMiscRegWithEffect(misc_reg, val, proxy); } unsigned readStCondFailures() { return storeCondFailures; } @@ -491,26 +491,26 @@ class CPUExecContext void setStCondFailures(unsigned sc_failures) { storeCondFailures = sc_failures; } - void clearArchRegs() { memset(®s, 0, sizeof(regs)); } + void clearArchRegs() { regs.clear(); } #if FULL_SYSTEM int readIntrFlag() { return regs.intrflag; } void setIntrFlag(int val) { regs.intrflag = val; } Fault hwrei(); - bool inPalMode() { return AlphaISA::PcPAL(regs.pc); } + bool inPalMode() { return AlphaISA::PcPAL(regs.readPC()); } bool simPalCheck(int palFunc); #endif #if !FULL_SYSTEM TheISA::IntReg getSyscallArg(int i) { - return regs.intRegFile[TheISA::ArgumentReg0 + i]; + return regs.readIntReg(TheISA::ArgumentReg0 + i); } // used to shift args for indirect syscall void setSyscallArg(int i, TheISA::IntReg val) { - regs.intRegFile[TheISA::ArgumentReg0 + i] = val; + regs.setIntReg(TheISA::ArgumentReg0 + i, val); } void setSyscallReturn(SyscallReturn return_value) @@ -527,6 +527,12 @@ class CPUExecContext void setFuncExeInst(Counter new_val) { func_exe_inst = new_val; } #endif + + void changeRegFileContext(RegFile::ContextParam param, + RegFile::ContextVal val) + { + regs.changeContext(param, val); + } }; diff --git a/cpu/exec_context.hh b/cpu/exec_context.hh index 85e4bfd4a..dd3d2cba1 100644 --- a/cpu/exec_context.hh +++ b/cpu/exec_context.hh @@ -241,6 +241,9 @@ class ExecContext virtual void setFuncExeInst(Counter new_val) = 0; #endif + + virtual void changeRegFileContext(RegFile::ContextParam param, + RegFile::ContextVal val) = 0; }; template <class XC> @@ -436,6 +439,12 @@ class ProxyExecContext : public ExecContext void setFuncExeInst(Counter new_val) { return actualXC->setFuncExeInst(new_val); } #endif + + void changeRegFileContext(RegFile::ContextParam param, + RegFile::ContextVal val) + { + actualXC->changeRegFileContext(param, val); + } }; #endif diff --git a/cpu/exetrace.cc b/cpu/exetrace.cc index 4db72320c..0ed3b43c4 100644 --- a/cpu/exetrace.cc +++ b/cpu/exetrace.cc @@ -128,10 +128,11 @@ Trace::InstRecord::dump(ostream &outs) outs << " A=0x" << hex << addr; if (flags[PRINT_INT_REGS] && regs_valid) { - for (int i = 0; i < 32;) + for (int i = 0; i < TheISA::NumIntRegs;) for (int j = i + 1; i <= j; i++) - ccprintf(outs, "r%02d = %#018x%s", i, iregs->regs[i], - ((i == j) ? "\n" : " ")); + ccprintf(outs, "r%02d = %#018x%s", i, + iregs->regs.readReg(i), + ((i == j) ? "\n" : " ")); outs << "\n"; } diff --git a/cpu/exetrace.hh b/cpu/exetrace.hh index 67d042ec8..a26cdc517 100644 --- a/cpu/exetrace.hh +++ b/cpu/exetrace.hh @@ -163,7 +163,7 @@ InstRecord::setRegs(const IntRegFile ®s) if (!iregs) iregs = new iRegFile; - memcpy(&iregs->regs, regs, sizeof(IntRegFile)); + memcpy(&iregs->regs, ®s, sizeof(IntRegFile)); regs_valid = true; } diff --git a/cpu/simple/cpu.cc b/cpu/simple/cpu.cc index 049606036..88c99c566 100644 --- a/cpu/simple/cpu.cc +++ b/cpu/simple/cpu.cc @@ -1094,7 +1094,7 @@ SimpleCPU::tick() #endif // FULL_SYSTEM } else { -#if THE_ISA != MIPS_ISA +#if THE_ISA == ALPHA_ISA // go to the next instruction cpuXC->setPC(cpuXC->readNextPC()); cpuXC->setNextPC(cpuXC->readNextPC() + sizeof(MachInst)); |