diff options
| -rw-r--r-- | src/arch/sparc/decoder.hh | 12 | ||||
| -rw-r--r-- | src/arch/sparc/isa.cc | 3 | ||||
| -rw-r--r-- | src/arch/sparc/process.cc | 2 | ||||
| -rw-r--r-- | src/arch/sparc/utility.cc | 2 | ||||
| -rw-r--r-- | src/sim/syscall_emul.cc | 2 |
5 files changed, 15 insertions, 6 deletions
diff --git a/src/arch/sparc/decoder.hh b/src/arch/sparc/decoder.hh index ea0793286..f85d5e4de 100644 --- a/src/arch/sparc/decoder.hh +++ b/src/arch/sparc/decoder.hh @@ -49,9 +49,10 @@ class Decoder // The extended machine instruction being generated ExtMachInst emi; bool instDone; + MiscReg asi; public: - Decoder(ThreadContext * _tc) : tc(_tc), instDone(false) + Decoder(ThreadContext * _tc) : tc(_tc), instDone(false), asi(0) {} ThreadContext * @@ -86,8 +87,7 @@ class Decoder // into all the execute functions if (inst & (1 << 13)) { emi |= (static_cast<ExtMachInst>( - tc->readMiscRegNoEffect(MISCREG_ASI)) - << (sizeof(MachInst) * 8)); + asi << (sizeof(MachInst) * 8))); } else { emi |= (static_cast<ExtMachInst>(bits(inst, 12, 5)) << (sizeof(MachInst) * 8)); @@ -107,6 +107,12 @@ class Decoder return instDone; } + void + setContext(MiscReg _asi) + { + asi = _asi; + } + protected: /// A cache of decoded instruction objects. static GenericISA::BasicDecodeCache defaultCache; diff --git a/src/arch/sparc/isa.cc b/src/arch/sparc/isa.cc index 291e25cec..4cfb93b0d 100644 --- a/src/arch/sparc/isa.cc +++ b/src/arch/sparc/isa.cc @@ -549,6 +549,9 @@ ISA::setMiscReg(int miscReg, MiscReg val, ThreadContext * tc) MiscReg new_val = val; switch (miscReg) { + case MISCREG_ASI: + tc->getDecodePtr()->setContext(val); + break; case MISCREG_STICK: case MISCREG_TICK: // stick and tick are same thing on niagra diff --git a/src/arch/sparc/process.cc b/src/arch/sparc/process.cc index 9377fe7d0..456b8b94a 100644 --- a/src/arch/sparc/process.cc +++ b/src/arch/sparc/process.cc @@ -145,7 +145,7 @@ SparcLiveProcess::initState() // Set the trap level to 0 tc->setMiscRegNoEffect(MISCREG_TL, 0); // Set the ASI register to something fixed - tc->setMiscRegNoEffect(MISCREG_ASI, ASI_PRIMARY); + tc->setMiscReg(MISCREG_ASI, ASI_PRIMARY); /* * T1 specific registers diff --git a/src/arch/sparc/utility.cc b/src/arch/sparc/utility.cc index b9a07b57b..d99ef4aa0 100644 --- a/src/arch/sparc/utility.cc +++ b/src/arch/sparc/utility.cc @@ -94,7 +94,7 @@ copyMiscRegs(ThreadContext *src, ThreadContext *dest) // src->readMiscRegNoEffect(MISCREG_Y)); // dest->setMiscRegNoEffect(MISCREG_CCR, // src->readMiscRegNoEffect(MISCREG_CCR)); - dest->setMiscRegNoEffect(MISCREG_ASI, + dest->setMiscReg(MISCREG_ASI, src->readMiscRegNoEffect(MISCREG_ASI)); dest->setMiscRegNoEffect(MISCREG_TICK, src->readMiscRegNoEffect(MISCREG_TICK)); diff --git a/src/sim/syscall_emul.cc b/src/sim/syscall_emul.cc index 9e53645f5..779e567f5 100644 --- a/src/sim/syscall_emul.cc +++ b/src/sim/syscall_emul.cc @@ -810,7 +810,7 @@ cloneFunc(SyscallDesc *desc, int callnum, LiveProcess *process, ctc->setMiscReg(MISCREG_CWP, 0); ctc->setIntReg(NumIntArchRegs + 7, 0); ctc->setMiscRegNoEffect(MISCREG_TL, 0); - ctc->setMiscRegNoEffect(MISCREG_ASI, ASI_PRIMARY); + ctc->setMiscReg(MISCREG_ASI, ASI_PRIMARY); for (int y = 8; y < 32; y++) ctc->setIntReg(y, tc->readIntReg(y)); |