diff options
| -rw-r--r-- | configs/common/Simulation.py | 16 | ||||
| -rw-r--r-- | configs/example/fs.py | 2 | ||||
| -rw-r--r-- | configs/example/se.py | 2 | ||||
| -rw-r--r-- | src/cpu/o3/cpu.cc | 6 | ||||
| -rw-r--r-- | src/cpu/simple/atomic.cc | 3 | ||||
| -rw-r--r-- | src/mem/bus.cc | 9 |
6 files changed, 23 insertions, 15 deletions
diff --git a/configs/common/Simulation.py b/configs/common/Simulation.py index a67159a50..374ff3fc2 100644 --- a/configs/common/Simulation.py +++ b/configs/common/Simulation.py @@ -85,10 +85,6 @@ def run(options, root, testsys, cpu_class): if not m5.build_env['FULL_SYSTEM']: switch_cpus[i].workload = testsys.cpu[i].workload switch_cpus[i].clock = testsys.cpu[0].clock - if options.caches: - switch_cpus[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), - L1Cache(size = '64kB')) - switch_cpus[i].connectMemPorts(testsys.membus) root.switch_cpus = switch_cpus switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)] @@ -108,19 +104,15 @@ def run(options, root, testsys, cpu_class): switch_cpus[i].clock = testsys.cpu[0].clock switch_cpus_1[i].clock = testsys.cpu[0].clock - if options.caches: - switch_cpus[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), - L1Cache(size = '64kB')) - switch_cpus[i].connectMemPorts(testsys.membus) - else: + if not options.caches: # O3 CPU must have a cache to work. switch_cpus_1[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), L1Cache(size = '64kB')) switch_cpus_1[i].connectMemPorts(testsys.membus) - root.switch_cpus = switch_cpus - root.switch_cpus_1 = switch_cpus_1 + testsys.switch_cpus = switch_cpus + testsys.switch_cpus_1 = switch_cpus_1 switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)] switch_cpu_list1 = [(switch_cpus[i], switch_cpus_1[i]) for i in xrange(np)] @@ -219,5 +211,5 @@ def run(options, root, testsys, cpu_class): if exit_cause == '': exit_cause = exit_event.getCause() - print 'Exiting @ cycle', m5.curTick(), 'because ', exit_cause + print 'Exiting @ cycle %i because %s' % (m5.curTick(), exit_cause) diff --git a/configs/example/fs.py b/configs/example/fs.py index 180cd2719..a9f1d579a 100644 --- a/configs/example/fs.py +++ b/configs/example/fs.py @@ -95,7 +95,7 @@ test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0]) np = options.num_cpus test_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)] for i in xrange(np): - if options.caches and not options.standard_switch and not FutureClass: + if options.caches: test_sys.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), L1Cache(size = '64kB')) test_sys.cpu[i].connectMemPorts(test_sys.membus) diff --git a/configs/example/se.py b/configs/example/se.py index 0a158244f..0944a030e 100644 --- a/configs/example/se.py +++ b/configs/example/se.py @@ -101,7 +101,7 @@ system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)], system.physmem.port = system.membus.port for i in xrange(np): - if options.caches and not options.standard_switch and not FutureClass: + if options.caches: system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), L1Cache(size = '64kB')) system.cpu[i].connectMemPorts(system.membus) diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc index dfe42d882..580816372 100644 --- a/src/cpu/o3/cpu.cc +++ b/src/cpu/o3/cpu.cc @@ -819,6 +819,12 @@ unsigned int FullO3CPU<Impl>::drain(Event *drain_event) { DPRINTF(O3CPU, "Switching out\n"); + + // If the CPU isn't doing anything, then return immediately. + if (_status == Idle || _status == SwitchedOut) { + return 0; + } + drainCount = 0; fetch.drain(); decode.drain(); diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index 4f68cfd6f..f94ea0917 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -213,6 +213,9 @@ AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU) break; } } + if (_status != Running) { + _status = Idle; + } } diff --git a/src/mem/bus.cc b/src/mem/bus.cc index 7b65d252b..8ea67a0e4 100644 --- a/src/mem/bus.cc +++ b/src/mem/bus.cc @@ -242,8 +242,11 @@ Bus::recvRetry(int id) } } //If we weren't able to drain before, we might be able to now. - if (drainEvent && retryList.size() == 0 && curTick >= tickNextIdle) + if (drainEvent && retryList.size() == 0 && curTick >= tickNextIdle) { drainEvent->process(); + // Clear the drain event once we're done with it. + drainEvent = NULL; + } } Port * @@ -367,6 +370,10 @@ Bus::recvAtomic(PacketPtr pkt) DPRINTF(Bus, "recvAtomic: packet src %d dest %d addr 0x%x cmd %s\n", pkt->getSrc(), pkt->getDest(), pkt->getAddr(), pkt->cmdString()); assert(pkt->getDest() == Packet::Broadcast); + + // Assume one bus cycle in order to get through. This may have + // some clock skew issues yet again... + pkt->finishTime = curTick + clock; Tick snoopTime = atomicSnoop(pkt); if (snoopTime) return snoopTime; //Snoop satisfies it |