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-rw-r--r--ext/sst/ExtMaster.cc2
-rw-r--r--src/arch/arm/isa.cc5
-rw-r--r--src/arch/arm/vtophys.cc2
-rw-r--r--src/cpu/base.hh4
-rw-r--r--src/cpu/base_dyn_inst.hh4
-rw-r--r--src/cpu/checker/cpu.cc4
-rw-r--r--src/cpu/checker/cpu_impl.hh3
-rw-r--r--src/cpu/kvm/base.cc2
-rw-r--r--src/cpu/kvm/x86_cpu.cc2
-rw-r--r--src/cpu/minor/fetch1.cc3
-rw-r--r--src/cpu/minor/lsq.cc7
-rw-r--r--src/cpu/o3/fetch_impl.hh6
-rw-r--r--src/cpu/o3/lsq.hh4
-rw-r--r--src/cpu/o3/lsq_impl.hh3
-rw-r--r--src/cpu/simple/atomic.cc12
-rw-r--r--src/cpu/simple/timing.cc14
-rw-r--r--src/cpu/testers/memtest/memtest.cc2
-rw-r--r--src/cpu/testers/networktest/networktest.cc4
-rw-r--r--src/cpu/testers/rubytest/Check.cc6
-rw-r--r--src/cpu/trace/trace_cpu.cc4
-rw-r--r--src/mem/cache/prefetch/queued.cc3
-rw-r--r--src/mem/request.hh44
22 files changed, 63 insertions, 77 deletions
diff --git a/ext/sst/ExtMaster.cc b/ext/sst/ExtMaster.cc
index 26a6c4a09..ce6f8ab7b 100644
--- a/ext/sst/ExtMaster.cc
+++ b/ext/sst/ExtMaster.cc
@@ -177,7 +177,7 @@ ExtMaster::handleEvent(SST::Event* event)
}
auto req = new Request(ev->getAddr(), ev->getSize(), flags, 0);
- req->setThreadContext(ev->getGroupId(), 0);
+ req->setContext(ev->getGroupId());
auto pkt = new Packet(req, cmdO);
pkt->allocate();
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 6f66e5ae1..d3286a6b0 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -1521,8 +1521,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
// with unexpected atomic snoop requests.
warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg);
Request req(0, val, 1, flags, Request::funcMasterId,
- tc->pcState().pc(), tc->contextId(),
- tc->threadId());
+ tc->pcState().pc(), tc->contextId());
fault = tc->getDTBPtr()->translateFunctional(&req, tc, mode, tranType);
TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
HCR hcr = readMiscRegNoEffect(MISCREG_HCR);
@@ -1768,7 +1767,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg);
req->setVirt(0, val, 1, flags, Request::funcMasterId,
tc->pcState().pc());
- req->setThreadContext(tc->contextId(), tc->threadId());
+ req->setContext(tc->contextId());
fault = tc->getDTBPtr()->translateFunctional(req, tc, mode,
tranType);
diff --git a/src/arch/arm/vtophys.cc b/src/arch/arm/vtophys.cc
index 3aad35818..24fc5a5c7 100644
--- a/src/arch/arm/vtophys.cc
+++ b/src/arch/arm/vtophys.cc
@@ -69,7 +69,7 @@ try_translate(ThreadContext *tc, Addr addr)
Fault fault;
// Set up a functional memory Request to pass to the TLB
// to get it to translate the vaddr to a paddr
- Request req(0, addr, 64, 0x40, -1, 0, 0, 0);
+ Request req(0, addr, 64, 0x40, -1, 0, 0);
ArmISA::TLB *tlb;
// Check the TLBs for a translation
diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index f01aa71f3..6622339e0 100644
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -297,6 +297,10 @@ class BaseCPU : public MemObject
/// Get the number of thread contexts available
unsigned numContexts() { return threadContexts.size(); }
+ /// Convert ContextID to threadID
+ ThreadID contextToThread(ContextID cid)
+ { return static_cast<ThreadID>(cid - threadContexts[0]->contextId()); }
+
public:
typedef BaseCPUParams Params;
const Params *params() const
diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index 031337aec..e846f6790 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -886,7 +886,7 @@ BaseDynInst<Impl>::initiateMemRead(Addr addr, unsigned size, unsigned flags)
sreqHigh = savedSreqHigh;
} else {
req = new Request(asid, addr, size, flags, masterId(), this->pc.instAddr(),
- thread->contextId(), threadNumber);
+ thread->contextId());
req->taskId(cpu->taskId());
@@ -942,7 +942,7 @@ BaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size,
sreqHigh = savedSreqHigh;
} else {
req = new Request(asid, addr, size, flags, masterId(), this->pc.instAddr(),
- thread->contextId(), threadNumber);
+ thread->contextId());
req->taskId(cpu->taskId());
diff --git a/src/cpu/checker/cpu.cc b/src/cpu/checker/cpu.cc
index ac476e5f4..4d5919cdf 100644
--- a/src/cpu/checker/cpu.cc
+++ b/src/cpu/checker/cpu.cc
@@ -155,7 +155,7 @@ CheckerCPU::readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags)
// Need to account for multiple accesses like the Atomic and TimingSimple
while (1) {
memReq = new Request(0, addr, size, flags, masterId,
- thread->pcState().instAddr(), tc->contextId(), 0);
+ thread->pcState().instAddr(), tc->contextId());
// translate to physical address
fault = dtb->translateFunctional(memReq, tc, BaseTLB::Read);
@@ -243,7 +243,7 @@ CheckerCPU::writeMem(uint8_t *data, unsigned size,
// Need to account for a multiple access like Atomic and Timing CPUs
while (1) {
memReq = new Request(0, addr, size, flags, masterId,
- thread->pcState().instAddr(), tc->contextId(), 0);
+ thread->pcState().instAddr(), tc->contextId());
// translate to physical address
fault = dtb->translateFunctional(memReq, tc, BaseTLB::Write);
diff --git a/src/cpu/checker/cpu_impl.hh b/src/cpu/checker/cpu_impl.hh
index 289861521..5d5900aae 100644
--- a/src/cpu/checker/cpu_impl.hh
+++ b/src/cpu/checker/cpu_impl.hh
@@ -248,8 +248,7 @@ Checker<Impl>::verify(DynInstPtr &completed_inst)
sizeof(MachInst),
0,
masterId,
- fetch_PC, thread->contextId(),
- unverifiedInst->threadNumber);
+ fetch_PC, thread->contextId());
memReq->setVirt(0, fetch_PC, sizeof(MachInst),
Request::INST_FETCH, masterId, thread->instAddr());
diff --git a/src/cpu/kvm/base.cc b/src/cpu/kvm/base.cc
index bf4d68603..0670f61c6 100644
--- a/src/cpu/kvm/base.cc
+++ b/src/cpu/kvm/base.cc
@@ -1027,7 +1027,7 @@ BaseKvmCPU::doMMIOAccess(Addr paddr, void *data, int size, bool write)
syncThreadContext();
Request mmio_req(paddr, size, Request::UNCACHEABLE, dataMasterId());
- mmio_req.setThreadContext(tc->contextId(), 0);
+ mmio_req.setContext(tc->contextId());
// Some architectures do need to massage physical addresses a bit
// before they are inserted into the memory system. This enables
// APIC accesses on x86 and m5ops where supported through a MMIO
diff --git a/src/cpu/kvm/x86_cpu.cc b/src/cpu/kvm/x86_cpu.cc
index c6c874dc4..9e9115ef5 100644
--- a/src/cpu/kvm/x86_cpu.cc
+++ b/src/cpu/kvm/x86_cpu.cc
@@ -1346,7 +1346,7 @@ X86KvmCPU::handleKvmExitIO()
Request io_req(pAddr, kvm_run.io.size, Request::UNCACHEABLE,
dataMasterId());
- io_req.setThreadContext(tc->contextId(), 0);
+ io_req.setContext(tc->contextId());
const MemCmd cmd(isWrite ? MemCmd::WriteReq : MemCmd::ReadReq);
// Temporarily lock and migrate to the event queue of the
diff --git a/src/cpu/minor/fetch1.cc b/src/cpu/minor/fetch1.cc
index 84aaf02f5..d19d7b042 100644
--- a/src/cpu/minor/fetch1.cc
+++ b/src/cpu/minor/fetch1.cc
@@ -135,8 +135,7 @@ Fetch1::fetchLine()
"%s addr: 0x%x pc: %s line_offset: %d request_size: %d\n",
request_id, aligned_pc, pc, line_offset, request_size);
- request->request.setThreadContext(cpu.threads[0]->getTC()->contextId(),
- /* thread id */ 0);
+ request->request.setContext(cpu.threads[0]->getTC()->contextId());
request->request.setVirt(0 /* asid */,
aligned_pc, request_size, Request::INST_FETCH, cpu.instMasterId(),
/* I've no idea why we need the PC, but give it */
diff --git a/src/cpu/minor/lsq.cc b/src/cpu/minor/lsq.cc
index e0c5796c8..b5c0bc974 100644
--- a/src/cpu/minor/lsq.cc
+++ b/src/cpu/minor/lsq.cc
@@ -422,7 +422,7 @@ LSQ::SplitDataRequest::makeFragmentRequests()
Request *fragment = new Request();
- fragment->setThreadContext(request.contextId(), /* thread id */ 0);
+ fragment->setContext(request.contextId());
fragment->setVirt(0 /* asid */,
fragment_addr, fragment_size, request.getFlags(),
request.masterId(),
@@ -1070,7 +1070,8 @@ LSQ::tryToSend(LSQRequestPtr request)
if (request->request.isMmappedIpr()) {
ThreadContext *thread =
- cpu.getContext(request->request.threadId());
+ cpu.getContext(cpu.contextToThread(
+ request->request.contextId()));
if (request->isLoad) {
DPRINTF(MinorMem, "IPR read inst: %s\n", *(request->inst));
@@ -1502,7 +1503,7 @@ LSQ::pushRequest(MinorDynInstPtr inst, bool isLoad, uint8_t *data,
inst->traceData->setMem(addr, size, flags);
int cid = cpu.threads[inst->id.threadId]->getTC()->contextId();
- request->request.setThreadContext(cid, /* thread id */ 0);
+ request->request.setContext(cid);
request->request.setVirt(0 /* asid */,
addr, size, flags, cpu.dataMasterId(),
/* I've no idea why we need the PC, but give it */
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index 4b1479bcb..3b29d87d4 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -378,7 +378,7 @@ template<class Impl>
void
DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt)
{
- ThreadID tid = pkt->req->threadId();
+ ThreadID tid = cpu->contextToThread(pkt->req->contextId());
DPRINTF(Fetch, "[tid:%u] Waking up from cache miss.\n", tid);
assert(!cpu->switchedOut());
@@ -622,7 +622,7 @@ DefaultFetch<Impl>::fetchCacheLine(Addr vaddr, ThreadID tid, Addr pc)
RequestPtr mem_req =
new Request(tid, fetchBufferBlockPC, fetchBufferSize,
Request::INST_FETCH, cpu->instMasterId(), pc,
- cpu->thread[tid]->contextId(), tid);
+ cpu->thread[tid]->contextId());
mem_req->taskId(cpu->taskId());
@@ -640,7 +640,7 @@ template <class Impl>
void
DefaultFetch<Impl>::finishTranslation(const Fault &fault, RequestPtr mem_req)
{
- ThreadID tid = mem_req->threadId();
+ ThreadID tid = cpu->contextToThread(mem_req->contextId());
Addr fetchBufferBlockPC = mem_req->getVaddr();
assert(!cpu->switchedOut());
diff --git a/src/cpu/o3/lsq.hh b/src/cpu/o3/lsq.hh
index dcd676221..6bc9b3d73 100644
--- a/src/cpu/o3/lsq.hh
+++ b/src/cpu/o3/lsq.hh
@@ -334,7 +334,7 @@ Fault
LSQ<Impl>::read(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh,
int load_idx)
{
- ThreadID tid = req->threadId();
+ ThreadID tid = cpu->contextToThread(req->contextId());
return thread[tid].read(req, sreqLow, sreqHigh, load_idx);
}
@@ -344,7 +344,7 @@ Fault
LSQ<Impl>::write(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh,
uint8_t *data, int store_idx)
{
- ThreadID tid = req->threadId();
+ ThreadID tid = cpu->contextToThread(req->contextId());
return thread[tid].write(req, sreqLow, sreqHigh, data, store_idx);
}
diff --git a/src/cpu/o3/lsq_impl.hh b/src/cpu/o3/lsq_impl.hh
index 06467243d..9080907fe 100644
--- a/src/cpu/o3/lsq_impl.hh
+++ b/src/cpu/o3/lsq_impl.hh
@@ -347,7 +347,8 @@ LSQ<Impl>::recvTimingResp(PacketPtr pkt)
DPRINTF(LSQ, "Got error packet back for address: %#X\n",
pkt->getAddr());
- thread[pkt->req->threadId()].completeDataAccess(pkt);
+ thread[cpu->contextToThread(pkt->req->contextId())]
+ .completeDataAccess(pkt);
if (pkt->isInvalidate()) {
// This response also contains an invalidate; e.g. this can be the case
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 3cd6c1666..a8e97f14c 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -87,9 +87,9 @@ AtomicSimpleCPU::init()
BaseSimpleCPU::init();
int cid = threadContexts[0]->contextId();
- ifetch_req.setThreadContext(cid, 0);
- data_read_req.setThreadContext(cid, 0);
- data_write_req.setThreadContext(cid, 0);
+ ifetch_req.setContext(cid);
+ data_read_req.setContext(cid);
+ data_write_req.setContext(cid);
}
AtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p)
@@ -557,9 +557,9 @@ AtomicSimpleCPU::tick()
if (numThreads > 1) {
ContextID cid = threadContexts[curThread]->contextId();
- ifetch_req.setThreadContext(cid, curThread);
- data_read_req.setThreadContext(cid, curThread);
- data_write_req.setThreadContext(cid, curThread);
+ ifetch_req.setContext(cid);
+ data_read_req.setContext(cid);
+ data_write_req.setContext(cid);
}
SimpleExecContext& t_info = *threadInfo[curThread];
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index c99f9c475..515d6b23c 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -423,7 +423,6 @@ TimingSimpleCPU::initiateMemRead(Addr addr, unsigned size, unsigned flags)
Fault fault;
const int asid = 0;
- const ThreadID tid = curThread;
const Addr pc = thread->instAddr();
unsigned block_size = cacheLineSize();
BaseTLB::Mode mode = BaseTLB::Read;
@@ -431,9 +430,8 @@ TimingSimpleCPU::initiateMemRead(Addr addr, unsigned size, unsigned flags)
if (traceData)
traceData->setMem(addr, size, flags);
- RequestPtr req = new Request(asid, addr, size,
- flags, dataMasterId(), pc,
- thread->contextId(), tid);
+ RequestPtr req = new Request(asid, addr, size, flags, dataMasterId(), pc,
+ thread->contextId());
req->taskId(taskId());
@@ -498,7 +496,6 @@ TimingSimpleCPU::writeMem(uint8_t *data, unsigned size,
uint8_t *newData = new uint8_t[size];
const int asid = 0;
- const ThreadID tid = curThread;
const Addr pc = thread->instAddr();
unsigned block_size = cacheLineSize();
BaseTLB::Mode mode = BaseTLB::Write;
@@ -514,9 +511,8 @@ TimingSimpleCPU::writeMem(uint8_t *data, unsigned size,
if (traceData)
traceData->setMem(addr, size, flags);
- RequestPtr req = new Request(asid, addr, size,
- flags, dataMasterId(), pc,
- thread->contextId(), tid);
+ RequestPtr req = new Request(asid, addr, size, flags, dataMasterId(), pc,
+ thread->contextId());
req->taskId(taskId());
@@ -618,7 +614,7 @@ TimingSimpleCPU::fetch()
_status = BaseSimpleCPU::Running;
Request *ifetch_req = new Request();
ifetch_req->taskId(taskId());
- ifetch_req->setThreadContext(thread->contextId(), curThread);
+ ifetch_req->setContext(thread->contextId());
setupFetchRequest(ifetch_req);
DPRINTF(SimpleCPU, "Translating address %#x\n", ifetch_req->getVaddr());
thread->itb->translateTiming(ifetch_req, thread->getTC(),
diff --git a/src/cpu/testers/memtest/memtest.cc b/src/cpu/testers/memtest/memtest.cc
index 223532088..c2c721bcf 100644
--- a/src/cpu/testers/memtest/memtest.cc
+++ b/src/cpu/testers/memtest/memtest.cc
@@ -245,7 +245,7 @@ MemTest::tick()
bool do_functional = (random_mt.random(0, 100) < percentFunctional) &&
!uncacheable;
Request *req = new Request(paddr, 1, flags, masterId);
- req->setThreadContext(id, 0);
+ req->setContext(id);
outstandingAddrs.insert(paddr);
diff --git a/src/cpu/testers/networktest/networktest.cc b/src/cpu/testers/networktest/networktest.cc
index 79a563f28..6ad26077c 100644
--- a/src/cpu/testers/networktest/networktest.cc
+++ b/src/cpu/testers/networktest/networktest.cc
@@ -243,7 +243,7 @@ NetworkTest::generatePkt()
// generate packet for virtual network 1
requestType = MemCmd::ReadReq;
flags.set(Request::INST_FETCH);
- req = new Request(0, 0x0, access_size, flags, masterId, 0x0, 0, 0);
+ req = new Request(0, 0x0, access_size, flags, masterId, 0x0, 0);
req->setPaddr(paddr);
} else { // if (randomReqType == 2)
// generate packet for virtual network 2
@@ -251,7 +251,7 @@ NetworkTest::generatePkt()
req = new Request(paddr, access_size, flags, masterId);
}
- req->setThreadContext(id,0);
+ req->setContext(id);
//No need to do functional simulation
//We just do timing simulation of the network
diff --git a/src/cpu/testers/rubytest/Check.cc b/src/cpu/testers/rubytest/Check.cc
index c8e7816c3..c869bd728 100644
--- a/src/cpu/testers/rubytest/Check.cc
+++ b/src/cpu/testers/rubytest/Check.cc
@@ -107,7 +107,7 @@ Check::initiatePrefetch()
// Prefetches are assumed to be 0 sized
Request *req = new Request(m_address, 0, flags,
m_tester_ptr->masterId(), curTick(), m_pc);
- req->setThreadContext(index, 0);
+ req->setContext(index);
PacketPtr pkt = new Packet(req, cmd);
// despite the oddity of the 0 size (questionable if this should
@@ -180,7 +180,7 @@ Check::initiateAction()
Request *req = new Request(writeAddr, 1, flags, m_tester_ptr->masterId(),
curTick(), m_pc);
- req->setThreadContext(index, 0);
+ req->setContext(index);
Packet::Command cmd;
// 1 out of 8 chance, issue an atomic rather than a write
@@ -245,7 +245,7 @@ Check::initiateCheck()
Request *req = new Request(m_address, CHECK_SIZE, flags,
m_tester_ptr->masterId(), curTick(), m_pc);
- req->setThreadContext(index, 0);
+ req->setContext(index);
PacketPtr pkt = new Packet(req, MemCmd::ReadReq);
uint8_t *dataArray = new uint8_t[CHECK_SIZE];
pkt->dataDynamic(dataArray);
diff --git a/src/cpu/trace/trace_cpu.cc b/src/cpu/trace/trace_cpu.cc
index d6aa9aaeb..e81a79818 100644
--- a/src/cpu/trace/trace_cpu.cc
+++ b/src/cpu/trace/trace_cpu.cc
@@ -627,7 +627,7 @@ TraceCPU::ElasticDataGen::executeMemReq(GraphNode* node_ptr)
// Create a request and the packet containing request
Request* req = new Request(node_ptr->physAddr, node_ptr->size,
node_ptr->flags, masterID, node_ptr->seqNum,
- ContextID(0), ThreadID(0));
+ ContextID(0));
req->setPC(node_ptr->pc);
// If virtual address is valid, set the asid and virtual address fields
// of the request.
@@ -1123,7 +1123,7 @@ TraceCPU::FixedRetryGen::send(Addr addr, unsigned size, const MemCmd& cmd,
req->setPC(pc);
// If this is not done it triggers assert in L1 cache for invalid contextId
- req->setThreadContext(ContextID(0), ThreadID(0));
+ req->setContext(ContextID(0));
// Embed it in a packet
PacketPtr pkt = new Packet(req, cmd);
diff --git a/src/mem/cache/prefetch/queued.cc b/src/mem/cache/prefetch/queued.cc
index 03ca3188f..4bc75acd6 100644
--- a/src/mem/cache/prefetch/queued.cc
+++ b/src/mem/cache/prefetch/queued.cc
@@ -122,8 +122,7 @@ QueuedPrefetcher::notify(const PacketPtr &pkt)
pf_pkt->allocate();
if (pkt->req->hasContextId()) {
- pf_req->setThreadContext(pkt->req->contextId(),
- pkt->req->threadId());
+ pf_req->setContext(pkt->req->contextId());
}
if (tagPrefetch && pkt->req->hasPC()) {
diff --git a/src/mem/request.hh b/src/mem/request.hh
index 0d2750a16..90363ea66 100644
--- a/src/mem/request.hh
+++ b/src/mem/request.hh
@@ -257,14 +257,13 @@ class Request
VALID_PC = 0x00000010,
/** Whether or not the context ID is valid. */
VALID_CONTEXT_ID = 0x00000020,
- VALID_THREAD_ID = 0x00000040,
/** Whether or not the sc result is valid. */
VALID_EXTRA_DATA = 0x00000080,
/**
* These flags are *not* cleared when a Request object is reused
* (assigned a new address).
*/
- STICKY_PRIVATE_FLAGS = VALID_CONTEXT_ID | VALID_THREAD_ID
+ STICKY_PRIVATE_FLAGS = VALID_CONTEXT_ID
};
private:
@@ -339,10 +338,8 @@ class Request
* store conditional or the compare value for a CAS. */
uint64_t _extraData;
- /** The context ID (for statistics, typically). */
+ /** The context ID (for statistics, locks, and wakeups). */
ContextID _contextId;
- /** The thread ID (id within this CPU) */
- ThreadID _threadId;
/** program counter of initiating access; for tracing/debugging */
Addr _pc;
@@ -363,21 +360,21 @@ class Request
Request()
: _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
_taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
- _extraData(0), _contextId(0), _threadId(0), _pc(0),
+ _extraData(0), _contextId(0), _pc(0),
_reqInstSeqNum(0), atomicOpFunctor(nullptr), translateDelta(0),
accessDelta(0), depth(0)
{}
Request(Addr paddr, unsigned size, Flags flags, MasterID mid,
- InstSeqNum seq_num, ContextID cid, ThreadID tid)
+ InstSeqNum seq_num, ContextID cid)
: _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
_taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
- _extraData(0), _contextId(0), _threadId(0), _pc(0),
+ _extraData(0), _contextId(0), _pc(0),
_reqInstSeqNum(seq_num), atomicOpFunctor(nullptr), translateDelta(0),
accessDelta(0), depth(0)
{
setPhys(paddr, size, flags, mid, curTick());
- setThreadContext(cid, tid);
+ setContext(cid);
privateFlags.set(VALID_INST_SEQ_NUM);
}
@@ -389,7 +386,7 @@ class Request
Request(Addr paddr, unsigned size, Flags flags, MasterID mid)
: _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
_taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
- _extraData(0), _contextId(0), _threadId(0), _pc(0),
+ _extraData(0), _contextId(0), _pc(0),
_reqInstSeqNum(0), atomicOpFunctor(nullptr), translateDelta(0),
accessDelta(0), depth(0)
{
@@ -399,7 +396,7 @@ class Request
Request(Addr paddr, unsigned size, Flags flags, MasterID mid, Tick time)
: _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
_taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
- _extraData(0), _contextId(0), _threadId(0), _pc(0),
+ _extraData(0), _contextId(0), _pc(0),
_reqInstSeqNum(0), atomicOpFunctor(nullptr), translateDelta(0),
accessDelta(0), depth(0)
{
@@ -410,7 +407,7 @@ class Request
Addr pc)
: _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
_taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
- _extraData(0), _contextId(0), _threadId(0), _pc(pc),
+ _extraData(0), _contextId(0), _pc(pc),
_reqInstSeqNum(0), atomicOpFunctor(nullptr), translateDelta(0),
accessDelta(0), depth(0)
{
@@ -419,15 +416,15 @@ class Request
}
Request(int asid, Addr vaddr, unsigned size, Flags flags, MasterID mid,
- Addr pc, ContextID cid, ThreadID tid)
+ Addr pc, ContextID cid)
: _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
_taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
- _extraData(0), _contextId(0), _threadId(0), _pc(0),
+ _extraData(0), _contextId(0), _pc(0),
_reqInstSeqNum(0), atomicOpFunctor(nullptr), translateDelta(0),
accessDelta(0), depth(0)
{
setVirt(asid, vaddr, size, flags, mid, pc);
- setThreadContext(cid, tid);
+ setContext(cid);
}
Request(int asid, Addr vaddr, int size, Flags flags, MasterID mid, Addr pc,
@@ -435,7 +432,7 @@ class Request
: atomicOpFunctor(atomic_op)
{
setVirt(asid, vaddr, size, flags, mid, pc);
- setThreadContext(cid, tid);
+ setContext(cid);
}
~Request()
@@ -446,14 +443,13 @@ class Request
}
/**
- * Set up CPU and thread numbers.
+ * Set up Context numbers.
*/
void
- setThreadContext(ContextID context_id, ThreadID tid)
+ setContext(ContextID context_id)
{
_contextId = context_id;
- _threadId = tid;
- privateFlags.set(VALID_CONTEXT_ID|VALID_THREAD_ID);
+ privateFlags.set(VALID_CONTEXT_ID);
}
/**
@@ -701,14 +697,6 @@ class Request
return _contextId;
}
- /** Accessor function for thread ID. */
- ThreadID
- threadId() const
- {
- assert(privateFlags.isSet(VALID_THREAD_ID));
- return _threadId;
- }
-
void
setPC(Addr pc)
{
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-27 11:17:16 +0000