diff options
-rw-r--r-- | src/arch/x86/isa/decoder/one_byte_opcodes.isa | 41 | ||||
-rw-r--r-- | src/arch/x86/isa/decoder/two_byte_opcodes.isa | 137 |
2 files changed, 121 insertions, 57 deletions
diff --git a/src/arch/x86/isa/decoder/one_byte_opcodes.isa b/src/arch/x86/isa/decoder/one_byte_opcodes.isa index bf19ed78e..c81aa666d 100644 --- a/src/arch/x86/isa/decoder/one_byte_opcodes.isa +++ b/src/arch/x86/isa/decoder/one_byte_opcodes.isa @@ -305,8 +305,8 @@ default: xchg_B_rAX(); } 0x13: decode OPCODE_OP_BOTTOM3 { - 0x0: cbw_or_cwde_or_cdqe_rAX(); - 0x1: cwd_or_cdq_or_cqo_rAX_rDX(); + 0x0: Inst::CDQE(rAv); + 0x1: Inst::CQO(rAv,rDv); 0x2: decode MODE_SUBMODE { 0x0: Inst::UD2(); default: call_far_Ap(); @@ -409,8 +409,33 @@ 0x1A: decode OPCODE_OP_BOTTOM3 { 0x0: group2_Eb_1(); 0x1: group2_Ev_1(); - 0x2: group2_Eb_Cl(); - 0x3: group2_Ev_Cl(); + format Inst { + //0x2: group2_Eb_Cl(); + 0x2: decode MODRM_REG { + 0x0: ROL(Eb,rCb); + 0x1: ROR(Eb,rCb); + 0x2: RCL(Eb,rCb); + 0x3: RCR(Eb,rCb); + 0x4: SAL(Eb,rCb); + 0x5: SHR(Eb,rCb); + 0x6: SAL(Eb,rCb); + 0x7: SAR(Eb,rCb); + } + //The second operand should have size "b", but to have + //consistent register sizes it's "v". This shouldn't have + //any affect on functionality. + //0x3: group2_Ev_Cl(); + 0x3: decode MODRM_REG { + 0x0: ROL(Ev,rCv); + 0x1: ROR(Ev,rCv); + 0x2: RCL(Ev,rCv); + 0x3: RCR(Ev,rCv); + 0x4: SAL(Ev,rCv); + 0x5: SHR(Ev,rCv); + 0x6: SAL(Ev,rCv); + 0x7: SAR(Ev,rCv); + } + } 0x4: decode MODE_SUBMODE { 0x0: Inst::UD2(); default: aam_Ib(); @@ -470,8 +495,8 @@ 0x5: cmc(); //0x6: group3_Eb(); 0x6: decode MODRM_REG { - 0x0: test_Eb_Iz(); - 0x1: test_Eb_Iz(); + 0x0: Inst::TEST(Eb,Iz); + 0x1: Inst::TEST(Eb,Iz); 0x2: not_Eb(); 0x3: Inst::NEG(Eb); 0x4: mul_Eb(); @@ -481,8 +506,8 @@ } //0x7: group3_Ev(); 0x7: decode MODRM_REG { - 0x0: test_Ev_Iz(); - 0x1: test_Ev_Iz(); + 0x0: Inst::TEST(Ev,Iz); + 0x1: Inst::TEST(Ev,Iz); 0x2: not_Ev(); 0x3: Inst::NEG(Ev); 0x4: mul_Ev(); diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa b/src/arch/x86/isa/decoder/two_byte_opcodes.isa index 3bda044c8..da4c82afa 100644 --- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa +++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa @@ -81,21 +81,58 @@ 0x0: invd(); 0x1: wbinvd(); 0x2: Inst::UD2(); - 0x3: UD2(); + 0x3: Inst::UD2(); 0x4: Inst::UD2(); 0x5: threednow(); 0x6: threednow(); 0x7: threednow(); } - 0x02: decode OPCODE_OP_BOTTOM3 { - 0x0: holder(); - 0x1: holder(); - 0x2: holder(); - 0x3: holder(); - 0x4: holder(); - 0x5: holder(); - 0x6: holder(); - 0x7: holder(); + 0x02: decode LEGACY_DECODEVAL { + // no prefix + 0x0: decode OPCODE_OP_BOTTOM3 { + 0x0: holder(); + 0x1: holder(); + 0x2: holder(); + 0x3: holder(); + 0x4: holder(); + 0x5: holder(); + 0x6: holder(); + 0x7: holder(); + } + // repe (0xF3) + 0x4: decode OPCODE_OP_BOTTOM3 { + 0x0: holder(); + 0x1: holder(); + 0x2: holder(); + 0x3: holder(); + 0x4: holder(); + 0x5: holder(); + 0x6: holder(); + 0x7: holder(); + } + // operand size (0x66) + 0x1: decode OPCODE_OP_BOTTOM3 { + 0x0: holder(); + 0x1: holder(); + 0x2: holder(); + 0x3: holder(); + 0x4: holder(); + 0x5: holder(); + 0x6: holder(); + 0x7: holder(); + } + // repne (0xF2) + 0x8: decode OPCODE_OP_BOTTOM3 { + 0x0: holder(); + 0x1: holder(); + 0x2: holder(); + 0x3: holder(); + 0x4: holder(); + 0x5: holder(); + 0x6: holder(); + 0x7: holder(); + } + default: Inst::UD2(); } 0x03: decode OPCODE_OP_BOTTOM3 { 0x0: group17(); @@ -147,25 +184,27 @@ 0x6: three_byte_opcode(); 0x7: three_byte_opcode(); } - 0x08: decode OPCODE_OP_BOTTOM3 { - 0x0: cmovo_Gv_Ev(); - 0x1: cmovno_Gv_Ev(); - 0x2: cmovb_Gv_Ev(); - 0x3: cmovnb_Gv_Ev(); - 0x4: cmovz_Gv_Ev(); - 0x5: cmovnz_Gv_Ev(); - 0x6: cmovbe_Gv_Ev(); - 0x7: cmovnbe_Gv_Ev(); - } - 0x09: decode OPCODE_OP_BOTTOM3 { - 0x0: cmovs_Gv_Ev(); - 0x1: cmovns_Gv_Ev(); - 0x2: cmovp_Gv_Ev(); - 0x3: cmovnp_Gv_Ev(); - 0x4: cmovl_Gv_Ev(); - 0x5: cmovnl_Gv_Ev(); - 0x6: cmovle_Gv_Ev(); - 0x7: cmovnle_Gv_Ev(); + format Inst { + 0x08: decode OPCODE_OP_BOTTOM3 { + 0x0: CMOVO(Gv,Ev); + 0x1: CMOVNO(Gv,Ev); + 0x2: CMOVB(Gv,Ev); + 0x3: CMOVNB(Gv,Ev); + 0x4: CMOVZ(Gv,Ev); + 0x5: CMOVNZ(Gv,Ev); + 0x6: CMOVBE(Gv,Ev); + 0x7: CMOVNBE(Gv,Ev); + } + 0x09: decode OPCODE_OP_BOTTOM3 { + 0x0: CMOVS(Gv,Ev); + 0x1: CMOVNS(Gv,Ev); + 0x2: CMOVP(Gv,Ev); + 0x3: CMOVNP(Gv,Ev); + 0x4: CMOVL(Gv,Ev); + 0x5: CMOVNL(Gv,Ev); + 0x6: CMOVLE(Gv,Ev); + 0x7: CMOVNLE(Gv,Ev); + } } 0x0A: decode OPCODE_OP_BOTTOM3 { 0x0: holder(); @@ -248,26 +287,26 @@ 0x6: JLE(Jz); 0x7: JNLE(Jz); } - } - 0x12: decode OPCODE_OP_BOTTOM3 { - 0x0: seto_Eb(); - 0x1: setno_Eb(); - 0x2: setb_Eb(); - 0x3: setnb_Eb(); - 0x4: setz_Eb(); - 0x5: setnz_Eb(); - 0x6: setbe_Eb(); - 0x7: setnbe_Eb(); - } - 0x13: decode OPCODE_OP_BOTTOM3 { - 0x0: sets_Eb(); - 0x1: setns_Eb(); - 0x2: setp_Eb(); - 0x3: setnp_Eb(); - 0x4: setl_Eb(); - 0x5: setnl_Eb(); - 0x6: setle_Eb(); - 0x7: setnle_Eb(); + 0x12: decode OPCODE_OP_BOTTOM3 { + 0x0: SETO(Eb); + 0x1: SETNO(Eb); + 0x2: SETB(Eb); + 0x3: SETNB(Eb); + 0x4: SETZ(Eb); + 0x5: SETNZ(Eb); + 0x6: SETBE(Eb); + 0x7: SETNBE(Eb); + } + 0x13: decode OPCODE_OP_BOTTOM3 { + 0x0: SETS(Eb); + 0x1: SETNS(Eb); + 0x2: SETP(Eb); + 0x3: SETNP(Eb); + 0x4: SETL(Eb); + 0x5: SETNL(Eb); + 0x6: SETLE(Eb); + 0x7: SETNLE(Eb); + } } 0x14: decode OPCODE_OP_BOTTOM3 { 0x0: push_fs(); |