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-rw-r--r--src/arch/alpha/isa.cc1
-rw-r--r--src/arch/arm/types.hh10
-rw-r--r--src/arch/arm/utility.hh10
-rw-r--r--src/arch/power/insts/branch.cc1
-rw-r--r--src/arch/power/types.hh12
-rw-r--r--src/arch/power/utility.hh14
-rw-r--r--src/arch/x86/types.hh21
-rw-r--r--src/arch/x86/utility.hh20
-rw-r--r--src/cpu/exetrace.cc1
-rw-r--r--src/cpu/exetrace.hh2
-rw-r--r--src/cpu/simple_thread.cc1
-rw-r--r--src/cpu/static_inst.hh3
-rw-r--r--src/cpu/thread_context.hh6
-rw-r--r--src/sim/syscall_emul.cc1
14 files changed, 54 insertions, 49 deletions
diff --git a/src/arch/alpha/isa.cc b/src/arch/alpha/isa.cc
index d89026ba7..5fd34a492 100644
--- a/src/arch/alpha/isa.cc
+++ b/src/arch/alpha/isa.cc
@@ -33,6 +33,7 @@
#include "arch/alpha/isa.hh"
#include "base/misc.hh"
#include "cpu/thread_context.hh"
+#include "sim/serialize.hh"
namespace AlphaISA
{
diff --git a/src/arch/arm/types.hh b/src/arch/arm/types.hh
index 78c9790f6..3c3b29494 100644
--- a/src/arch/arm/types.hh
+++ b/src/arch/arm/types.hh
@@ -44,6 +44,7 @@
#define __ARCH_ARM_TYPES_HH__
#include "base/bitunion.hh"
+#include "base/hashmap.hh"
#include "base/types.hh"
namespace ArmISA
@@ -269,4 +270,13 @@ namespace ArmISA
} // namespace ArmISA
+namespace __hash_namespace {
+ template<>
+ struct hash<ArmISA::ExtMachInst> : public hash<uint32_t> {
+ size_t operator()(const ArmISA::ExtMachInst &emi) const {
+ return hash<uint32_t>::operator()((uint32_t)emi);
+ };
+ };
+}
+
#endif
diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh
index 2a30c5de2..7d9365ab6 100644
--- a/src/arch/arm/utility.hh
+++ b/src/arch/arm/utility.hh
@@ -47,21 +47,11 @@
#include "arch/arm/miscregs.hh"
#include "arch/arm/types.hh"
-#include "base/hashmap.hh"
#include "base/misc.hh"
#include "base/trace.hh"
#include "base/types.hh"
#include "cpu/thread_context.hh"
-namespace __hash_namespace {
- template<>
- struct hash<ArmISA::ExtMachInst> : public hash<uint32_t> {
- size_t operator()(const ArmISA::ExtMachInst &emi) const {
- return hash<uint32_t>::operator()((uint32_t)emi);
- };
- };
-}
-
namespace ArmISA {
inline bool
diff --git a/src/arch/power/insts/branch.cc b/src/arch/power/insts/branch.cc
index 3f4346c97..c10f7c996 100644
--- a/src/arch/power/insts/branch.cc
+++ b/src/arch/power/insts/branch.cc
@@ -30,6 +30,7 @@
#include "arch/power/insts/branch.hh"
#include "base/loader/symtab.hh"
+#include "cpu/thread_context.hh"
using namespace PowerISA;
diff --git a/src/arch/power/types.hh b/src/arch/power/types.hh
index 7b994adc9..6a8d1e9d3 100644
--- a/src/arch/power/types.hh
+++ b/src/arch/power/types.hh
@@ -32,6 +32,7 @@
#define __ARCH_POWER_TYPES_HH__
#include "base/bitunion.hh"
+#include "base/hashmap.hh"
#include "base/types.hh"
namespace PowerISA
@@ -88,4 +89,15 @@ struct CoreSpecific {
} // PowerISA namspace
+namespace __hash_namespace {
+
+template<>
+struct hash<PowerISA::ExtMachInst> : public hash<uint32_t> {
+ size_t operator()(const PowerISA::ExtMachInst &emi) const {
+ return hash<uint32_t>::operator()((uint32_t)emi);
+ };
+};
+
+} // __hash_namespace namespace
+
#endif // __ARCH_POWER_TYPES_HH__
diff --git a/src/arch/power/utility.hh b/src/arch/power/utility.hh
index 7245db511..b3eed9de3 100644
--- a/src/arch/power/utility.hh
+++ b/src/arch/power/utility.hh
@@ -35,23 +35,9 @@
#ifndef __ARCH_POWER_UTILITY_HH__
#define __ARCH_POWER_UTILITY_HH__
-#include "arch/power/miscregs.hh"
-#include "arch/power/types.hh"
-#include "base/hashmap.hh"
#include "base/types.hh"
#include "cpu/thread_context.hh"
-namespace __hash_namespace {
-
-template<>
-struct hash<PowerISA::ExtMachInst> : public hash<uint32_t> {
- size_t operator()(const PowerISA::ExtMachInst &emi) const {
- return hash<uint32_t>::operator()((uint32_t)emi);
- };
-};
-
-} // __hash_namespace namespace
-
namespace PowerISA {
/**
diff --git a/src/arch/x86/types.hh b/src/arch/x86/types.hh
index 35799e0c9..2a0da7d65 100644
--- a/src/arch/x86/types.hh
+++ b/src/arch/x86/types.hh
@@ -44,6 +44,7 @@
#include "base/bitunion.hh"
#include "base/cprintf.hh"
+#include "base/hashmap.hh"
#include "base/types.hh"
#include "sim/serialize.hh"
@@ -225,6 +226,26 @@ namespace X86ISA
};
};
+namespace __hash_namespace {
+ template<>
+ struct hash<X86ISA::ExtMachInst> {
+ size_t operator()(const X86ISA::ExtMachInst &emi) const {
+ return (((uint64_t)emi.legacy << 56) |
+ ((uint64_t)emi.rex << 48) |
+ ((uint64_t)emi.modRM << 40) |
+ ((uint64_t)emi.sib << 32) |
+ ((uint64_t)emi.opcode.num << 24) |
+ ((uint64_t)emi.opcode.prefixA << 16) |
+ ((uint64_t)emi.opcode.prefixB << 8) |
+ ((uint64_t)emi.opcode.op)) ^
+ emi.immediate ^ emi.displacement ^
+ emi.mode ^
+ emi.opSize ^ emi.addrSize ^
+ emi.stackSize ^ emi.dispSize;
+ };
+ };
+}
+
// These two functions allow ExtMachInst to be used with SERIALIZE_SCALAR
// and UNSERIALIZE_SCALAR.
template <>
diff --git a/src/arch/x86/utility.hh b/src/arch/x86/utility.hh
index db03da7a0..bfa102529 100644
--- a/src/arch/x86/utility.hh
+++ b/src/arch/x86/utility.hh
@@ -50,26 +50,6 @@
class ThreadContext;
-namespace __hash_namespace {
- template<>
- struct hash<X86ISA::ExtMachInst> {
- size_t operator()(const X86ISA::ExtMachInst &emi) const {
- return (((uint64_t)emi.legacy << 56) |
- ((uint64_t)emi.rex << 48) |
- ((uint64_t)emi.modRM << 40) |
- ((uint64_t)emi.sib << 32) |
- ((uint64_t)emi.opcode.num << 24) |
- ((uint64_t)emi.opcode.prefixA << 16) |
- ((uint64_t)emi.opcode.prefixB << 8) |
- ((uint64_t)emi.opcode.op)) ^
- emi.immediate ^ emi.displacement ^
- emi.mode ^
- emi.opSize ^ emi.addrSize ^
- emi.stackSize ^ emi.dispSize;
- };
- };
-}
-
namespace X86ISA
{
uint64_t getArgument(ThreadContext *tc, int number, bool fp);
diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc
index 051ee57a0..4bab778ba 100644
--- a/src/cpu/exetrace.cc
+++ b/src/cpu/exetrace.cc
@@ -34,6 +34,7 @@
#include <iomanip>
#include "arch/isa_traits.hh"
+#include "arch/utility.hh"
#include "base/loader/symtab.hh"
#include "cpu/base.hh"
#include "cpu/exetrace.hh"
diff --git a/src/cpu/exetrace.hh b/src/cpu/exetrace.hh
index aa0831dfd..1982595eb 100644
--- a/src/cpu/exetrace.hh
+++ b/src/cpu/exetrace.hh
@@ -35,12 +35,12 @@
#include "base/trace.hh"
#include "base/types.hh"
#include "cpu/static_inst.hh"
+#include "cpu/thread_context.hh"
#include "params/ExeTracer.hh"
#include "sim/insttracer.hh"
class ThreadContext;
-
namespace Trace {
class ExeTracerRecord : public InstRecord
diff --git a/src/cpu/simple_thread.cc b/src/cpu/simple_thread.cc
index 40f7f3cdb..bd796428a 100644
--- a/src/cpu/simple_thread.cc
+++ b/src/cpu/simple_thread.cc
@@ -34,6 +34,7 @@
#include <string>
#include "arch/isa_traits.hh"
+#include "arch/utility.hh"
#include "config/the_isa.hh"
#include "cpu/base.hh"
#include "cpu/simple_thread.hh"
diff --git a/src/cpu/static_inst.hh b/src/cpu/static_inst.hh
index 0ae8653c5..6474bbf9c 100644
--- a/src/cpu/static_inst.hh
+++ b/src/cpu/static_inst.hh
@@ -35,9 +35,8 @@
#include <string>
#include "arch/isa_traits.hh"
-#include "arch/utility.hh"
+#include "arch/registers.hh"
#include "config/the_isa.hh"
-#include "base/bitfield.hh"
#include "base/hashmap.hh"
#include "base/misc.hh"
#include "base/refcnt.hh"
diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index 3d7be5256..753fa2146 100644
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -31,12 +31,14 @@
#ifndef __CPU_THREAD_CONTEXT_HH__
#define __CPU_THREAD_CONTEXT_HH__
+#include <string>
+#include <iostream>
+
#include "arch/registers.hh"
#include "arch/types.hh"
#include "base/types.hh"
#include "config/full_system.hh"
#include "config/the_isa.hh"
-#include "sim/serialize.hh"
// @todo: Figure out a more architecture independent way to obtain the ITB and
// DTB pointers.
@@ -45,8 +47,8 @@ namespace TheISA
class TLB;
}
class BaseCPU;
+class Checkpoint;
class EndQuiesceEvent;
-class Event;
class TranslatingPort;
class FunctionalPort;
class VirtualPort;
diff --git a/src/sim/syscall_emul.cc b/src/sim/syscall_emul.cc
index 7b12700e0..207c07309 100644
--- a/src/sim/syscall_emul.cc
+++ b/src/sim/syscall_emul.cc
@@ -36,6 +36,7 @@
#include <iostream>
#include <string>
+#include "arch/utility.hh"
#include "sim/syscall_emul.hh"
#include "base/chunk_generator.hh"
#include "base/trace.hh"
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-28 03:38:14 +0000