diff options
| -rw-r--r-- | src/mem/cache/cache.hh | 17 | ||||
| -rw-r--r-- | src/mem/cache/cache_impl.hh | 24 |
2 files changed, 29 insertions, 12 deletions
diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh index 1ed138bb5..8d30ed443 100644 --- a/src/mem/cache/cache.hh +++ b/src/mem/cache/cache.hh @@ -1,4 +1,16 @@ /* + * Copyright (c) 2012 ARM Limited + * All rights reserved. + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * * Copyright (c) 2002-2005 The Regents of The University of Michigan * All rights reserved. * @@ -225,10 +237,9 @@ class Cache : public BaseCache /** * Performs the access specified by the request. * @param pkt The request to perform. - * @return The result of the access. + * @param fromCpuSide from the CPU side port or the memory side port */ - void functionalAccess(PacketPtr pkt, CachePort *incomingPort, - CachePort *otherSidePort); + void functionalAccess(PacketPtr pkt, bool fromCpuSide); /** * Handles a response (cache line fill/write ack) from the bus. diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh index a56495abb..453e62b1a 100644 --- a/src/mem/cache/cache_impl.hh +++ b/src/mem/cache/cache_impl.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010 ARM Limited + * Copyright (c) 2010-2012 ARM Limited * All rights reserved. * * The license below extends only to copyright in the software and shall @@ -768,9 +768,7 @@ Cache<TagStore>::atomicAccess(PacketPtr pkt) template<class TagStore> void -Cache<TagStore>::functionalAccess(PacketPtr pkt, - CachePort *incomingPort, - CachePort *otherSidePort) +Cache<TagStore>::functionalAccess(PacketPtr pkt, bool fromCpuSide) { Addr blk_addr = blockAlign(pkt->getAddr()); BlkType *blk = tags->findBlock(pkt->getAddr()); @@ -796,10 +794,10 @@ Cache<TagStore>::functionalAccess(PacketPtr pkt, (mshr && mshr->inService && mshr->isPendingDirty())); bool done = have_dirty - || incomingPort->checkFunctional(pkt) + || cpuSidePort->checkFunctional(pkt) || mshrQueue.checkFunctional(pkt, blk_addr) || writeBuffer.checkFunctional(pkt, blk_addr) - || otherSidePort->checkFunctional(pkt); + || memSidePort->checkFunctional(pkt); DPRINTF(Cache, "functional %s %x %s%s%s\n", pkt->cmdString(), pkt->getAddr(), @@ -812,7 +810,15 @@ Cache<TagStore>::functionalAccess(PacketPtr pkt, if (done) { pkt->makeResponse(); } else { - otherSidePort->sendFunctional(pkt); + // if it came as a request from the CPU side then make sure it + // continues towards the memory side + if (fromCpuSide) { + memSidePort->sendFunctional(pkt); + } else if (forwardSnoops) { + // if it came from the memory side, it must be a snoop request + // and we should only forward it if we are forwarding snoops + cpuSidePort->sendFunctional(pkt); + } } } @@ -1598,7 +1604,7 @@ template<class TagStore> void Cache<TagStore>::CpuSidePort::recvFunctional(PacketPtr pkt) { - myCache()->functionalAccess(pkt, this, otherPort); + myCache()->functionalAccess(pkt, true); } @@ -1670,7 +1676,7 @@ template<class TagStore> void Cache<TagStore>::MemSidePort::recvFunctional(PacketPtr pkt) { - myCache()->functionalAccess(pkt, this, otherPort); + myCache()->functionalAccess(pkt, false); } |