diff options
| -rw-r--r-- | tests/SConscript | 2 | ||||
| -rw-r--r-- | tests/configs/base_config.py | 10 | ||||
| -rw-r--r-- | tests/configs/o3-timing-mt.py | 57 | ||||
| -rw-r--r-- | tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/config.ini (renamed from tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini) | 0 | ||||
| -rwxr-xr-x | tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simerr (renamed from tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simerr) | 0 | ||||
| -rwxr-xr-x | tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simout (renamed from tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout) | 0 | ||||
| -rw-r--r-- | tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt (renamed from tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt) | 0 | ||||
| -rw-r--r-- | tests/quick/se/01.hello-2T-smt/test.py | 2 |
8 files changed, 65 insertions, 6 deletions
diff --git a/tests/SConscript b/tests/SConscript index bbd6b1950..e9c9a6432 100644 --- a/tests/SConscript +++ b/tests/SConscript @@ -357,7 +357,7 @@ if env['TARGET_ISA'] == 'x86': configs += ['simple-atomic', 'simple-atomic-mp', 'simple-timing', 'simple-timing-mp', 'minor-timing', 'minor-timing-mp', - 'o3-timing', 'o3-timing-mp', + 'o3-timing', 'o3-timing-mt', 'o3-timing-mp', 'rubytest', 'memtest', 'memtest-filter', 'tgen-simple-mem', 'tgen-dram-ctrl'] diff --git a/tests/configs/base_config.py b/tests/configs/base_config.py index a3e1e0271..3f28ada5d 100644 --- a/tests/configs/base_config.py +++ b/tests/configs/base_config.py @@ -58,7 +58,8 @@ class BaseSystem(object): __metaclass__ = ABCMeta def __init__(self, mem_mode='timing', mem_class=SimpleMemory, - cpu_class=TimingSimpleCPU, num_cpus=1, checker=False, + cpu_class=TimingSimpleCPU, num_cpus=1, num_threads=1, + checker=False, mem_size=None): """Initialize a simple base system. @@ -74,11 +75,13 @@ class BaseSystem(object): self.mem_class = mem_class self.cpu_class = cpu_class self.num_cpus = num_cpus + self.num_threads = num_threads self.checker = checker def create_cpus(self, cpu_clk_domain): """Return a list of CPU objects to add to a system.""" - cpus = [ self.cpu_class(clk_domain = cpu_clk_domain, + cpus = [ self.cpu_class(clk_domain=cpu_clk_domain, + numThreads=self.num_threads, cpu_id=i) for i in range(self.num_cpus) ] if self.checker: @@ -187,7 +190,8 @@ class BaseSESystem(BaseSystem): def create_system(self): system = System(physmem = self.mem_class(), membus = SystemXBar(), - mem_mode = self.mem_mode) + mem_mode = self.mem_mode, + multi_thread = (self.num_threads > 1)) system.system_port = system.membus.slave system.physmem.port = system.membus.master self.init_system(system) diff --git a/tests/configs/o3-timing-mt.py b/tests/configs/o3-timing-mt.py new file mode 100644 index 000000000..5c6ca4800 --- /dev/null +++ b/tests/configs/o3-timing-mt.py @@ -0,0 +1,57 @@ +# Copyright (c) 2013, 2015 ARM Limited +# All rights reserved. +# +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# +# Copyright (c) 2006-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Andreas Hansson + +from m5.objects import * +from m5.defines import buildEnv +from base_config import * +from arm_generic import * +from O3_ARM_v7a import O3_ARM_v7a_3 + +# If we are running ARM regressions, use a more sensible CPU +# configuration. This makes the results more meaningful, and also +# increases the coverage of the regressions. +if buildEnv['TARGET_ISA'] == "arm": + root = ArmSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_x64, + cpu_class=O3_ARM_v7a_3, + num_threads=2).create_root() +else: + root = BaseSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_x64, + cpu_class=DerivO3CPU, + num_threads=2).create_root() diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/config.ini index 3b7f876e4..3b7f876e4 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/config.ini diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simerr b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simerr index 341b479f7..341b479f7 100755 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simerr +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simerr diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simout index 8bbada3f7..8bbada3f7 100755 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simout diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt index 9d107898a..9d107898a 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt diff --git a/tests/quick/se/01.hello-2T-smt/test.py b/tests/quick/se/01.hello-2T-smt/test.py index 7a8fbe0bd..6f8b18361 100644 --- a/tests/quick/se/01.hello-2T-smt/test.py +++ b/tests/quick/se/01.hello-2T-smt/test.py @@ -29,6 +29,4 @@ process1 = LiveProcess(cmd = 'hello', executable = binpath('hello')) process2 = LiveProcess(cmd = 'hello', executable = binpath('hello')) -root.system.multi_thread = True root.system.cpu[0].workload = [process1, process2] -root.system.cpu[0].numThreads = 2 |