diff options
119 files changed, 4006 insertions, 1725 deletions
diff --git a/SConscript b/SConscript index bd94ec430..a405d252f 100644 --- a/SConscript +++ b/SConscript @@ -212,6 +212,11 @@ mysql_sources = Split(''' # Full-system sources full_system_sources = Split(''' + arch/alpha/freebsd/system.cc + arch/alpha/linux/system.cc + arch/alpha/system.cc + arch/alpha/tru64/system.cc + base/crc.cc base/inet.cc base/remote_gdb.cc @@ -251,15 +256,13 @@ full_system_sources = Split(''' kern/kernel_binning.cc kern/kernel_stats.cc kern/system_events.cc - kern/freebsd/freebsd_system.cc + kern/linux/events.cc kern/linux/linux_syscalls.cc - kern/linux/linux_system.cc kern/linux/printk.cc kern/tru64/dump_mbuf.cc kern/tru64/printf.cc kern/tru64/tru64_events.cc kern/tru64/tru64_syscalls.cc - kern/tru64/tru64_system.cc mem/functional/memory_control.cc mem/functional/physical.cc @@ -300,29 +303,6 @@ syscall_emulation_sources = Split(''' sim/syscall_emul.cc ''') -# The following stuff (targetarch code and global define of THE_ISA) -# are legacy things that assume we're only compiling one ISA at a -# time. These will have to go away if we want to build a binary that -# supports multiple ISAs. - -targetarch_files = Split(''' - alpha_linux_process.hh - alpha_memory.hh - alpha_tru64_process.hh - aout_machdep.h - arguments.hh - ecoff_machdep.h - ev5.hh - faults.hh - stacktrace.hh - vtophys.hh - ''') - -# Set up bridging headers to the architecture specific versions -for f in targetarch_files: - env.Command('targetarch/' + f, 'arch/%s/%s' % (env['TARGET_ISA'], f), - '''echo '#include "arch/%s/%s"' > $TARGET''' % (env['TARGET_ISA'], f)) - # Add a flag defining what THE_ISA should be for all compilation env.Append(CPPDEFINES=[('THE_ISA','%s_ISA' % env['TARGET_ISA'].upper())]) @@ -397,6 +377,7 @@ def make_objs(sources, env): # the corresponding build directory to pick up generated include # files. env.Append(CPPPATH='.') +env.Append(CPPPATH='./libelf') # Debug binary debugEnv = env.Copy(OBJSUFFIX='.do') diff --git a/arch/SConscript b/arch/SConscript index 142bd763b..b4b7a1ddb 100644 --- a/arch/SConscript +++ b/arch/SConscript @@ -46,6 +46,15 @@ sources = [] # List of headers to generate isa_switch_hdrs = Split(''' isa_traits.hh + tlb.hh + process.hh + aout_machdep.h + ecoff_machdep.h + arguments.hh + stacktrace.hh + vtophys.hh + faults.hh + ev5.hh ''') # Generate the header. target[0] is the full path of the output diff --git a/arch/alpha/SConscript b/arch/alpha/SConscript index 050dfb9cf..03d73eef7 100644 --- a/arch/alpha/SConscript +++ b/arch/alpha/SConscript @@ -50,7 +50,7 @@ base_sources = Split(''' # Full-system sources full_system_sources = Split(''' - alpha_memory.cc + tlb.cc arguments.cc ev5.cc osfpal.cc @@ -61,9 +61,10 @@ full_system_sources = Split(''' # Syscall emulation (non-full-system) sources syscall_emulation_sources = Split(''' - alpha_common_syscall_emul.cc - alpha_linux_process.cc - alpha_tru64_process.cc + common_syscall_emul.cc + linux_process.cc + tru64_process.cc + process.cc ''') # Set up complete list of sources based on configuration. diff --git a/arch/alpha/ev5.cc b/arch/alpha/ev5.cc index 9d2ff4db7..11faf1850 100644 --- a/arch/alpha/ev5.cc +++ b/arch/alpha/ev5.cc @@ -26,7 +26,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#include "arch/alpha/alpha_memory.hh" +#include "arch/alpha/tlb.hh" #include "arch/alpha/isa_traits.hh" #include "arch/alpha/osfpal.hh" #include "base/kgdb.h" @@ -47,66 +47,22 @@ using namespace EV5; //////////////////////////////////////////////////////////////////////// // -// -// -void -AlphaISA::swap_palshadow(RegFile *regs, bool use_shadow) -{ - if (regs->pal_shadow == use_shadow) - panic("swap_palshadow: wrong PAL shadow state"); - - regs->pal_shadow = use_shadow; - - for (int i = 0; i < NumIntRegs; i++) { - if (reg_redir[i]) { - IntReg temp = regs->intRegFile[i]; - regs->intRegFile[i] = regs->palregs[i]; - regs->palregs[i] = temp; - } - } -} - -//////////////////////////////////////////////////////////////////////// -// // Machine dependent functions // void AlphaISA::initCPU(ExecContext *xc, int cpuId) { initIPRs(xc, cpuId); - // CPU comes up with PAL regs enabled - swap_palshadow(regs, true); xc->setIntReg(16, cpuId); xc->setIntReg(0, cpuId); - xc->setPC(xc->readMiscReg(IPR_PAL_BASE) + fault_addr(ResetFault)); + xc->setPC(xc->readMiscReg(IPR_PAL_BASE) + (new ResetFault)->vect()); xc->setNextPC(xc->readPC() + sizeof(MachInst)); } //////////////////////////////////////////////////////////////////////// // -// alpha exceptions - value equals trap address, update with MD_FAULT_TYPE -// -const Addr -AlphaISA::fault_addr(Fault fault) -{ - //Check for the system wide faults - if(fault == NoFault) return 0x0000; - else if(fault == MachineCheckFault) return 0x0401; - else if(fault == AlignmentFault) return 0x0301; - //Deal with the alpha specific faults - return ((AlphaFault*)fault)->vect; -}; - -const int AlphaISA::reg_redir[AlphaISA::NumIntRegs] = { - /* 0 */ 0, 0, 0, 0, 0, 0, 0, 0, - /* 8 */ 1, 1, 1, 1, 1, 1, 1, 0, - /* 16 */ 0, 0, 0, 0, 0, 0, 0, 0, - /* 24 */ 0, 1, 0, 0, 0, 0, 0, 0 }; - -//////////////////////////////////////////////////////////////////////// -// // // void @@ -163,7 +119,7 @@ AlphaISA::processInterrupts(CPU *cpu) if (ipl && ipl > cpu->readMiscReg(IPR_IPLR)) { cpu->setMiscReg(IPR_ISR, summary); cpu->setMiscReg(IPR_INTID, ipl); - cpu->trap(InterruptFault); + cpu->trap(new InterruptFault); DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n", cpu->readMiscReg(IPR_IPLR), ipl, summary); } @@ -181,78 +137,17 @@ AlphaISA::zeroRegisters(CPU *cpu) cpu->cpuXC->setFloatRegDouble(ZeroReg, 0.0); } -void -CPUExecContext::ev5_trap(Fault fault) -{ - DPRINTF(Fault, "Fault %s at PC: %#x\n", fault->name, regs.pc); - cpu->recordEvent(csprintf("Fault %s", fault->name)); - - assert(!misspeculating()); - cpu->kernelStats->fault(fault); - - if (fault == ArithmeticFault) - panic("Arithmetic traps are unimplemented!"); - - // exception restart address - if (fault != InterruptFault || !inPalMode()) - setMiscReg(AlphaISA::IPR_EXC_ADDR, regs.pc); - - if (fault == PalFault || fault == ArithmeticFault /* || - fault == InterruptFault && !inPalMode() */) { - // traps... skip faulting instruction - setMiscReg(AlphaISA::IPR_EXC_ADDR, - readMiscReg(AlphaISA::IPR_EXC_ADDR) + 4); - } - - if (!inPalMode()) - AlphaISA::swap_palshadow(®s, true); - - regs.pc = readMiscReg(AlphaISA::IPR_PAL_BASE) + AlphaISA::fault_addr(fault); - regs.npc = regs.pc + sizeof(MachInst); -} - - -void -AlphaISA::intr_post(RegFile *regs, Fault fault, Addr pc) -{ - bool use_pc = (fault == NoFault); - - if (fault == ArithmeticFault) - panic("arithmetic faults NYI..."); - - // compute exception restart address - if (use_pc || fault == PalFault || fault == ArithmeticFault) { - // traps... skip faulting instruction - regs->miscRegs.setReg(IPR_EXC_ADDR, regs->pc + 4); - } else { - // fault, post fault at excepting instruction - regs->miscRegs.setReg(IPR_EXC_ADDR, regs->pc); - } - - // jump to expection address (PAL PC bit set here as well...) - if (!use_pc) - regs->npc = regs->miscRegs.readReg(IPR_PAL_BASE) + - fault_addr(fault); - else - regs->npc = regs->miscRegs.readReg(IPR_PAL_BASE) + pc; - - // that's it! (orders of magnitude less painful than x86) -} - Fault CPUExecContext::hwrei() { if (!inPalMode()) - return UnimplementedOpcodeFault; + return new UnimplementedOpcodeFault; setNextPC(readMiscReg(AlphaISA::IPR_EXC_ADDR)); if (!misspeculating()) { cpu->kernelStats->hwrei(); - if ((readMiscReg(AlphaISA::IPR_EXC_ADDR) & 1) == 0) - AlphaISA::swap_palshadow(®s, false); - cpu->checkInterrupts = true; } @@ -354,12 +249,12 @@ AlphaISA::MiscRegFile::readIpr(int idx, Fault &fault, ExecContext *xc) case AlphaISA::IPR_DTB_IAP: case AlphaISA::IPR_ITB_IA: case AlphaISA::IPR_ITB_IAP: - fault = UnimplementedOpcodeFault; + fault = new UnimplementedOpcodeFault; break; default: // invalid IPR - fault = UnimplementedOpcodeFault; + fault = new UnimplementedOpcodeFault; break; } @@ -523,7 +418,7 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ExecContext *xc) case AlphaISA::IPR_ITB_PTE_TEMP: case AlphaISA::IPR_DTB_PTE_TEMP: // read-only registers - return UnimplementedOpcodeFault; + return new UnimplementedOpcodeFault; case AlphaISA::IPR_HWINT_CLR: case AlphaISA::IPR_SL_XMIT: @@ -627,7 +522,7 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ExecContext *xc) default: // invalid IPR - return UnimplementedOpcodeFault; + return new UnimplementedOpcodeFault; } // no error... diff --git a/arch/alpha/faults.cc b/arch/alpha/faults.cc index fa4950198..84f785c0a 100644 --- a/arch/alpha/faults.cc +++ b/arch/alpha/faults.cc @@ -27,37 +27,124 @@ */ #include "arch/alpha/faults.hh" +#include "cpu/exec_context.hh" +#include "cpu/base.hh" +#include "base/trace.hh" +#include "kern/kernel_stats.hh" -ResetFaultType * const ResetFault = - new ResetFaultType("reset", 1, 0x0001); -ArithmeticFaultType * const ArithmeticFault = - new ArithmeticFaultType("arith", 3, 0x0501); -InterruptFaultType * const InterruptFault = - new InterruptFaultType("interrupt", 4, 0x0101); -NDtbMissFaultType * const NDtbMissFault = - new NDtbMissFaultType("dtb_miss_single", 5, 0x0201); -PDtbMissFaultType * const PDtbMissFault = - new PDtbMissFaultType("dtb_miss_double", 6, 0x0281); -DtbPageFaultType * const DtbPageFault = - new DtbPageFaultType("dfault", 8, 0x0381); -DtbAcvFaultType * const DtbAcvFault = - new DtbAcvFaultType("dfault", 9, 0x0381); -ItbMissFaultType * const ItbMissFault = - new ItbMissFaultType("itbmiss", 10, 0x0181); -ItbPageFaultType * const ItbPageFault = - new ItbPageFaultType("itbmiss", 11, 0x0181); -ItbAcvFaultType * const ItbAcvFault = - new ItbAcvFaultType("iaccvio", 12, 0x0081); -UnimplementedOpcodeFaultType * const UnimplementedOpcodeFault = - new UnimplementedOpcodeFaultType("opdec", 13, 0x0481); -FloatEnableFaultType * const FloatEnableFault = - new FloatEnableFaultType("fen", 14, 0x0581); -PalFaultType * const PalFault = - new PalFaultType("pal", 15, 0x2001); -IntegerOverflowFaultType * const IntegerOverflowFault = - new IntegerOverflowFaultType("intover", 16, 0x0501); - -Fault * ListOfFaults[] = { +namespace AlphaISA +{ + +FaultName MachineCheckFault::_name = "mchk"; +FaultVect MachineCheckFault::_vect = 0x0401; +FaultStat MachineCheckFault::_stat; + +FaultName AlignmentFault::_name = "unalign"; +FaultVect AlignmentFault::_vect = 0x0301; +FaultStat AlignmentFault::_stat; + +FaultName ResetFault::_name = "reset"; +FaultVect ResetFault::_vect = 0x0001; +FaultStat ResetFault::_stat; + +FaultName ArithmeticFault::_name = "arith"; +FaultVect ArithmeticFault::_vect = 0x0501; +FaultStat ArithmeticFault::_stat; + +FaultName InterruptFault::_name = "interrupt"; +FaultVect InterruptFault::_vect = 0x0101; +FaultStat InterruptFault::_stat; + +FaultName NDtbMissFault::_name = "dtb_miss_single"; +FaultVect NDtbMissFault::_vect = 0x0201; +FaultStat NDtbMissFault::_stat; + +FaultName PDtbMissFault::_name = "dtb_miss_double"; +FaultVect PDtbMissFault::_vect = 0x0281; +FaultStat PDtbMissFault::_stat; + +FaultName DtbPageFault::_name = "dfault"; +FaultVect DtbPageFault::_vect = 0x0381; +FaultStat DtbPageFault::_stat; + +FaultName DtbAcvFault::_name = "dfault"; +FaultVect DtbAcvFault::_vect = 0x0381; +FaultStat DtbAcvFault::_stat; + +FaultName ItbMissFault::_name = "itbmiss"; +FaultVect ItbMissFault::_vect = 0x0181; +FaultStat ItbMissFault::_stat; + +FaultName ItbPageFault::_name = "itbmiss"; +FaultVect ItbPageFault::_vect = 0x0181; +FaultStat ItbPageFault::_stat; + +FaultName ItbAcvFault::_name = "iaccvio"; +FaultVect ItbAcvFault::_vect = 0x0081; +FaultStat ItbAcvFault::_stat; + +FaultName UnimplementedOpcodeFault::_name = "opdec"; +FaultVect UnimplementedOpcodeFault::_vect = 0x0481; +FaultStat UnimplementedOpcodeFault::_stat; + +FaultName FloatEnableFault::_name = "fen"; +FaultVect FloatEnableFault::_vect = 0x0581; +FaultStat FloatEnableFault::_stat; + +FaultName PalFault::_name = "pal"; +FaultVect PalFault::_vect = 0x2001; +FaultStat PalFault::_stat; + +FaultName IntegerOverflowFault::_name = "intover"; +FaultVect IntegerOverflowFault::_vect = 0x0501; +FaultStat IntegerOverflowFault::_stat; + +#if FULL_SYSTEM + +void AlphaFault::invoke(ExecContext * xc) +{ + DPRINTF(Fault, "Fault %s at PC: %#x\n", name(), xc->regs.pc); + xc->cpu->recordEvent(csprintf("Fault %s", name())); + + assert(!xc->misspeculating()); + xc->kernelStats->fault(this); + + // exception restart address + if (setRestartAddress() || !xc->inPalMode()) + xc->setMiscReg(AlphaISA::IPR_EXC_ADDR, xc->regs.pc); + + if (skipFaultingInstruction()) { + // traps... skip faulting instruction. + xc->setMiscReg(AlphaISA::IPR_EXC_ADDR, + xc->readMiscReg(AlphaISA::IPR_EXC_ADDR) + 4); + } + + xc->regs.pc = xc->readMiscReg(AlphaISA::IPR_PAL_BASE) + vect(); + xc->regs.npc = xc->regs.pc + sizeof(MachInst); +} + +void ArithmeticFault::invoke(ExecContext * xc) +{ + DPRINTF(Fault, "Fault %s at PC: %#x\n", name(), xc->regs.pc); + xc->cpu->recordEvent(csprintf("Fault %s", name())); + + assert(!xc->misspeculating()); + xc->kernelStats->fault(this); + + panic("Arithmetic traps are unimplemented!"); +} + + +/*void ArithmeticFault::invoke(ExecContext * xc) +{ + panic("Arithmetic traps are unimplemented!"); +}*/ + +#endif + +} // namespace AlphaISA + +/*Fault * ListOfFaults[] = { (Fault *)&NoFault, (Fault *)&ResetFault, (Fault *)&MachineCheckFault, @@ -77,4 +164,4 @@ Fault * ListOfFaults[] = { (Fault *)&IntegerOverflowFault, }; -int NumFaults = sizeof(ListOfFaults) / sizeof(Fault *); +int NumFaults = sizeof(ListOfFaults) / sizeof(Fault *);*/ diff --git a/arch/alpha/faults.hh b/arch/alpha/faults.hh index 3e25adc4e..c4a72e07c 100644 --- a/arch/alpha/faults.hh +++ b/arch/alpha/faults.hh @@ -30,131 +30,239 @@ #define __ALPHA_FAULTS_HH__ #include "sim/faults.hh" -#include "arch/isa_traits.hh" //For the Addr type -class AlphaFault : public FaultBase +// The design of the "name" and "vect" functions is in sim/faults.hh + +namespace AlphaISA +{ + +typedef const Addr FaultVect; + +class AlphaFault : public virtual FaultBase { + protected: + virtual bool skipFaultingInstruction() {return false;} + virtual bool setRestartAddress() {return true;} public: - AlphaFault(char * newName, int newId, Addr newVect) - : FaultBase(newName, newId), vect(newVect) - {;} +#if FULL_SYSTEM + void invoke(ExecContext * xc); +#endif + virtual FaultVect vect() = 0; +}; - Addr vect; +class MachineCheckFault : public AlphaFault +{ + private: + static FaultName _name; + static FaultVect _vect; + static FaultStat _stat; + public: + FaultName name() {return _name;} + FaultVect vect() {return _vect;} + FaultStat & stat() {return _stat;} + bool isMachineCheckFault() {return true;} }; -extern class ResetFaultType : public AlphaFault +class AlignmentFault : public AlphaFault { + private: + static FaultName _name; + static FaultVect _vect; + static FaultStat _stat; public: - ResetFaultType(char * newName, int newId, Addr newVect) - : AlphaFault(newName, newId, newVect) - {;} -} * const ResetFault; + FaultName name() {return _name;} + FaultVect vect() {return _vect;} + FaultStat & stat() {return _stat;} + bool isAlignmentFault() {return true;} +}; -extern class ArithmeticFaultType : public AlphaFault +static inline Fault genMachineCheckFault() { + return new MachineCheckFault; +} + +static inline Fault genAlignmentFault() +{ + return new AlignmentFault; +} + +class ResetFault : public AlphaFault +{ + private: + static FaultName _name; + static FaultVect _vect; + static FaultStat _stat; public: - ArithmeticFaultType(char * newName, int newId, Addr newVect) - : AlphaFault(newName, newId, newVect) - {;} -} * const ArithmeticFault; + FaultName name() {return _name;} + FaultVect vect() {return _vect;} + FaultStat & stat() {return _stat;} +}; -extern class InterruptFaultType : public AlphaFault +class ArithmeticFault : public AlphaFault { + protected: + bool skipFaultingInstruction() {return true;} + private: + static FaultName _name; + static FaultVect _vect; + static FaultStat _stat; public: - InterruptFaultType(char * newName, int newId, Addr newVect) - : AlphaFault(newName, newId, newVect) - {;} -} * const InterruptFault; + FaultName name() {return _name;} + FaultVect vect() {return _vect;} + FaultStat & stat() {return _stat;} +#if FULL_SYSTEM + void invoke(ExecContext * xc); +#endif +}; -extern class NDtbMissFaultType : public AlphaFault +class InterruptFault : public AlphaFault { + protected: + bool setRestartAddress() {return false;} + private: + static FaultName _name; + static FaultVect _vect; + static FaultStat _stat; public: - NDtbMissFaultType(char * newName, int newId, Addr newVect) - : AlphaFault(newName, newId, newVect) - {;} -} * const NDtbMissFault; + FaultName name() {return _name;} + FaultVect vect() {return _vect;} + FaultStat & stat() {return _stat;} +}; -extern class PDtbMissFaultType : public AlphaFault +class NDtbMissFault : public AlphaFault { + private: + static FaultName _name; + static FaultVect _vect; + static FaultStat _stat; public: - PDtbMissFaultType(char * newName, int newId, Addr newVect) - : AlphaFault(newName, newId, newVect) - {;} -} * const PDtbMissFault; + FaultName name() {return _name;} + FaultVect vect() {return _vect;} + FaultStat & stat() {return _stat;} +}; -extern class DtbPageFaultType : public AlphaFault +class PDtbMissFault : public AlphaFault { + private: + static FaultName _name; + static FaultVect _vect; + static FaultStat _stat; public: - DtbPageFaultType(char * newName, int newId, Addr newVect) - : AlphaFault(newName, newId, newVect) - {;} -} * const DtbPageFault; + FaultName name() {return _name;} + FaultVect vect() {return _vect;} + FaultStat & stat() {return _stat;} +}; -extern class DtbAcvFaultType : public AlphaFault +class DtbPageFault : public AlphaFault { + private: + static FaultName _name; + static FaultVect _vect; + static FaultStat _stat; public: - DtbAcvFaultType(char * newName, int newId, Addr newVect) - : AlphaFault(newName, newId, newVect) - {;} -} * const DtbAcvFault; + FaultName name() {return _name;} + FaultVect vect() {return _vect;} + FaultStat & stat() {return _stat;} +}; + +class DtbAcvFault : public AlphaFault +{ + private: + static FaultName _name; + static FaultVect _vect; + static FaultStat _stat; + public: + FaultName name() {return _name;} + FaultVect vect() {return _vect;} + FaultStat & stat() {return _stat;} +}; -extern class ItbMissFaultType : public AlphaFault +class ItbMissFault : public AlphaFault { + private: + static FaultName _name; + static FaultVect _vect; + static FaultStat _stat; public: - ItbMissFaultType(char * newName, int newId, Addr newVect) - : AlphaFault(newName, newId, newVect) - {;} -} * const ItbMissFault; + FaultName name() {return _name;} + FaultVect vect() {return _vect;} + FaultStat & stat() {return _stat;} +}; -extern class ItbPageFaultType : public AlphaFault +class ItbPageFault : public AlphaFault { + private: + static FaultName _name; + static FaultVect _vect; + static FaultStat _stat; public: - ItbPageFaultType(char * newName, int newId, Addr newVect) - : AlphaFault(newName, newId, newVect) - {;} -} * const ItbPageFault; + FaultName name() {return _name;} + FaultVect vect() {return _vect;} + FaultStat & stat() {return _stat;} +}; -extern class ItbAcvFaultType : public AlphaFault +class ItbAcvFault : public AlphaFault { + private: + static FaultName _name; + static FaultVect _vect; + static FaultStat _stat; public: - ItbAcvFaultType(char * newName, int newId, Addr newVect) - : AlphaFault(newName, newId, newVect) - {;} -} * const ItbAcvFault; + FaultName name() {return _name;} + FaultVect vect() {return _vect;} + FaultStat & stat() {return _stat;} +}; -extern class UnimplementedOpcodeFaultType : public AlphaFault +class UnimplementedOpcodeFault : public AlphaFault { + private: + static FaultName _name; + static FaultVect _vect; + static FaultStat _stat; public: - UnimplementedOpcodeFaultType(char * newName, int newId, Addr newVect) - : AlphaFault(newName, newId, newVect) - {;} -} * const UnimplementedOpcodeFault; + FaultName name() {return _name;} + FaultVect vect() {return _vect;} + FaultStat & stat() {return _stat;} +}; -extern class FloatEnableFaultType : public AlphaFault +class FloatEnableFault : public AlphaFault { + private: + static FaultName _name; + static FaultVect _vect; + static FaultStat _stat; public: - FloatEnableFaultType(char * newName, int newId, Addr newVect) - : AlphaFault(newName, newId, newVect) - {;} -} * const FloatEnableFault; + FaultName name() {return _name;} + FaultVect vect() {return _vect;} + FaultStat & stat() {return _stat;} +}; -extern class PalFaultType : public AlphaFault +class PalFault : public AlphaFault { + protected: + bool skipFaultingInstruction() {return true;} + private: + static FaultName _name; + static FaultVect _vect; + static FaultStat _stat; public: - PalFaultType(char * newName, int newId, Addr newVect) - : AlphaFault(newName, newId, newVect) - {;} -} * const PalFault; + FaultName name() {return _name;} + FaultVect vect() {return _vect;} + FaultStat & stat() {return _stat;} +}; -extern class IntegerOverflowFaultType : public AlphaFault +class IntegerOverflowFault : public AlphaFault { + private: + static FaultName _name; + static FaultVect _vect; + static FaultStat _stat; public: - IntegerOverflowFaultType(char * newName, int newId, Addr newVect) - : AlphaFault(newName, newId, newVect) - {;} -} * const IntegerOverflowFault; + FaultName name() {return _name;} + FaultVect vect() {return _vect;} + FaultStat & stat() {return _stat;} +}; -extern Fault * ListOfFaults[]; -extern int NumFaults; +} // AlphaISA namespace #endif // __FAULTS_HH__ diff --git a/kern/freebsd/freebsd_system.cc b/arch/alpha/freebsd/system.cc index 3db70a368..e32053afd 100644 --- a/kern/freebsd/freebsd_system.cc +++ b/arch/alpha/freebsd/system.cc @@ -33,23 +33,24 @@ * */ -#include "arch/isa_traits.hh" +#include "arch/alpha/system.hh" +#include "arch/alpha/freebsd/system.hh" #include "base/loader/symtab.hh" #include "cpu/exec_context.hh" -#include "kern/freebsd/freebsd_system.hh" #include "mem/functional/memory_control.hh" #include "mem/functional/physical.hh" +#include "arch/isa_traits.hh" #include "sim/builder.hh" #include "sim/byteswap.hh" -#include "targetarch/vtophys.hh" +#include "arch/vtophys.hh" #define TIMER_FREQUENCY 1193180 using namespace std; -using namespace TheISA; +using namespace AlphaISA; -FreebsdSystem::FreebsdSystem(Params *p) - : System(p) +FreebsdAlphaSystem::FreebsdAlphaSystem(Params *p) + : AlphaSystem(p) { /** * Any time DELAY is called just skip the function. @@ -61,7 +62,7 @@ FreebsdSystem::FreebsdSystem(Params *p) } -FreebsdSystem::~FreebsdSystem() +FreebsdAlphaSystem::~FreebsdAlphaSystem() { delete skipDelayEvent; delete skipCalibrateClocks; @@ -69,7 +70,7 @@ FreebsdSystem::~FreebsdSystem() void -FreebsdSystem::doCalibrateClocks(ExecContext *xc) +FreebsdAlphaSystem::doCalibrateClocks(ExecContext *xc) { Addr ppc_vaddr = 0; Addr timer_vaddr = 0; @@ -91,14 +92,14 @@ FreebsdSystem::doCalibrateClocks(ExecContext *xc) void -FreebsdSystem::SkipCalibrateClocksEvent::process(ExecContext *xc) +FreebsdAlphaSystem::SkipCalibrateClocksEvent::process(ExecContext *xc) { SkipFuncEvent::process(xc); - ((FreebsdSystem *)xc->getSystemPtr())->doCalibrateClocks(xc); + ((FreebsdAlphaSystem *)xc->getSystemPtr())->doCalibrateClocks(xc); } -BEGIN_DECLARE_SIM_OBJECT_PARAMS(FreebsdSystem) +BEGIN_DECLARE_SIM_OBJECT_PARAMS(FreebsdAlphaSystem) Param<Tick> boot_cpu_frequency; SimObjectParam<MemoryController *> memctrl; @@ -119,9 +120,9 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(FreebsdSystem) VectorParam<string> binned_fns; Param<bool> bin_int; -END_DECLARE_SIM_OBJECT_PARAMS(FreebsdSystem) +END_DECLARE_SIM_OBJECT_PARAMS(FreebsdAlphaSystem) -BEGIN_INIT_SIM_OBJECT_PARAMS(FreebsdSystem) +BEGIN_INIT_SIM_OBJECT_PARAMS(FreebsdAlphaSystem) INIT_PARAM(boot_cpu_frequency, "Frequency of the boot CPU"), INIT_PARAM(memctrl, "memory controller"), @@ -139,11 +140,11 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(FreebsdSystem) INIT_PARAM(binned_fns, "functions to be broken down and binned"), INIT_PARAM_DFLT(bin_int, "is interrupt code binned seperately?", true) -END_INIT_SIM_OBJECT_PARAMS(FreebsdSystem) +END_INIT_SIM_OBJECT_PARAMS(FreebsdAlphaSystem) -CREATE_SIM_OBJECT(FreebsdSystem) +CREATE_SIM_OBJECT(FreebsdAlphaSystem) { - System::Params *p = new System::Params; + AlphaSystem::Params *p = new AlphaSystem::Params; p->name = getInstanceName(); p->boot_cpu_frequency = boot_cpu_frequency; p->memctrl = memctrl; @@ -159,8 +160,8 @@ CREATE_SIM_OBJECT(FreebsdSystem) p->bin = bin; p->binned_fns = binned_fns; p->bin_int = bin_int; - return new FreebsdSystem(p); + return new FreebsdAlphaSystem(p); } -REGISTER_SIM_OBJECT("FreebsdSystem", FreebsdSystem) +REGISTER_SIM_OBJECT("FreebsdAlphaSystem", FreebsdAlphaSystem) diff --git a/kern/freebsd/freebsd_system.hh b/arch/alpha/freebsd/system.hh index ecb842ec6..5d996955e 100644 --- a/kern/freebsd/freebsd_system.hh +++ b/arch/alpha/freebsd/system.hh @@ -31,7 +31,7 @@ #include "kern/system_events.hh" -class FreebsdSystem : public System +class FreebsdAlphaSystem : public AlphaSystem { private: class SkipCalibrateClocksEvent : public SkipFuncEvent @@ -47,8 +47,8 @@ class FreebsdSystem : public System SkipCalibrateClocksEvent *skipCalibrateClocks; public: - FreebsdSystem(Params *p); - ~FreebsdSystem(); + FreebsdAlphaSystem(Params *p); + ~FreebsdAlphaSystem(); void doCalibrateClocks(ExecContext *xc); }; diff --git a/arch/alpha/isa/branch.isa b/arch/alpha/isa/branch.isa index 9a7fb9d79..b528df938 100644 --- a/arch/alpha/isa/branch.isa +++ b/arch/alpha/isa/branch.isa @@ -46,7 +46,7 @@ output header {{ mutable const SymbolTable *cachedSymtab; /// Constructor - PCDependentDisassembly(const char *mnem, MachInst _machInst, + PCDependentDisassembly(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : AlphaStaticInst(mnem, _machInst, __opClass), cachedPC(0), cachedSymtab(0) @@ -68,7 +68,7 @@ output header {{ int32_t disp; /// Constructor. - Branch(const char *mnem, MachInst _machInst, OpClass __opClass) + Branch(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : PCDependentDisassembly(mnem, _machInst, __opClass), disp(BRDISP << 2) { @@ -93,7 +93,7 @@ output header {{ public: /// Constructor - Jump(const char *mnem, MachInst _machInst, OpClass __opClass) + Jump(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : PCDependentDisassembly(mnem, _machInst, __opClass), disp(BRDISP) { diff --git a/arch/alpha/isa/decoder.isa b/arch/alpha/isa/decoder.isa index 1817f65f2..e09673269 100644 --- a/arch/alpha/isa/decoder.isa +++ b/arch/alpha/isa/decoder.isa @@ -1,6 +1,6 @@ // -*- mode:c++ -*- -// Copyright (c) 2003-2005 The Regents of The University of Michigan +// Copyright (c) 2003-2006 The Regents of The University of Michigan // All rights reserved. // // Redistribution and use in source and binary forms, with or without @@ -98,7 +98,7 @@ decode OPCODE default Unknown::unknown() { // signed overflow occurs when operands have same sign // and sign of result does not match. if (Ra.sl<31:> == Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>) - fault = IntegerOverflowFault; + fault = new IntegerOverflowFault; Rc.sl = tmp; }}); 0x02: s4addl({{ Rc.sl = (Ra.sl << 2) + Rb_or_imm.sl; }}); @@ -110,7 +110,7 @@ decode OPCODE default Unknown::unknown() { // signed overflow occurs when operands have same sign // and sign of result does not match. if (Ra<63:> == Rb_or_imm<63:> && tmp<63:> != Ra<63:>) - fault = IntegerOverflowFault; + fault = new IntegerOverflowFault; Rc = tmp; }}); 0x22: s4addq({{ Rc = (Ra << 2) + Rb_or_imm; }}); @@ -124,7 +124,7 @@ decode OPCODE default Unknown::unknown() { // sign bit of the subtrahend (Rb), i.e., if the initial // signs are the *same* then no overflow can occur if (Ra.sl<31:> != Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>) - fault = IntegerOverflowFault; + fault = new IntegerOverflowFault; Rc.sl = tmp; }}); 0x0b: s4subl({{ Rc.sl = (Ra.sl << 2) - Rb_or_imm.sl; }}); @@ -138,7 +138,7 @@ decode OPCODE default Unknown::unknown() { // sign bit of the subtrahend (Rb), i.e., if the initial // signs are the *same* then no overflow can occur if (Ra<63:> != Rb_or_imm<63:> && tmp<63:> != Ra<63:>) - fault = IntegerOverflowFault; + fault = new IntegerOverflowFault; Rc = tmp; }}); 0x2b: s4subq({{ Rc = (Ra << 2) - Rb_or_imm; }}); @@ -299,7 +299,7 @@ decode OPCODE default Unknown::unknown() { // checking the upper 33 bits for all 0s or all 1s. uint64_t sign_bits = tmp<63:31>; if (sign_bits != 0 && sign_bits != mask(33)) - fault = IntegerOverflowFault; + fault = new IntegerOverflowFault; Rc.sl = tmp<31:0>; }}, IntMultOp); 0x60: mulqv({{ @@ -310,7 +310,7 @@ decode OPCODE default Unknown::unknown() { // the lower 64 if (!((hi == 0 && lo<63:> == 0) || (hi == mask(64) && lo<63:> == 1))) - fault = IntegerOverflowFault; + fault = new IntegerOverflowFault; Rc = lo; }}, IntMultOp); } @@ -427,19 +427,19 @@ decode OPCODE default Unknown::unknown() { #if SS_COMPATIBLE_FP 0x0b: sqrts({{ if (Fb < 0.0) - fault = ArithmeticFault; + fault = new ArithmeticFault; Fc = sqrt(Fb); }}, FloatSqrtOp); #else 0x0b: sqrts({{ if (Fb.sf < 0.0) - fault = ArithmeticFault; + fault = new ArithmeticFault; Fc.sf = sqrt(Fb.sf); }}, FloatSqrtOp); #endif 0x2b: sqrtt({{ if (Fb < 0.0) - fault = ArithmeticFault; + fault = new ArithmeticFault; Fc = sqrt(Fb); }}, FloatSqrtOp); } @@ -570,7 +570,7 @@ decode OPCODE default Unknown::unknown() { // checking the upper 33 bits for all 0s or all 1s. uint64_t sign_bits = Fb.uq<63:31>; if (sign_bits != 0 && sign_bits != mask(33)) - fault = IntegerOverflowFault; + fault = new IntegerOverflowFault; Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29); }}); @@ -673,7 +673,7 @@ decode OPCODE default Unknown::unknown() { && xc->readMiscRegWithEffect(AlphaISA::IPR_ICM, fault) != AlphaISA::mode_kernel)) { // invalid pal function code, or attempt to do privileged // PAL call in non-kernel mode - fault = UnimplementedOpcodeFault; + fault = new UnimplementedOpcodeFault; } else { // check to see if simulator wants to do something special @@ -681,7 +681,6 @@ decode OPCODE default Unknown::unknown() { bool dopal = xc->simPalCheck(palFunc); if (dopal) { - AlphaISA::swap_palshadow(&xc->xcBase()->regs, true); xc->setMiscRegWithEffect(AlphaISA::IPR_EXC_ADDR, NPC); NPC = xc->readMiscRegWithEffect(AlphaISA::IPR_PAL_BASE, fault) + palOffset; } @@ -705,50 +704,56 @@ decode OPCODE default Unknown::unknown() { #endif #if FULL_SYSTEM - format HwLoad { - 0x1b: decode HW_LDST_QUAD { - 0: hw_ld({{ EA = (Rb + disp) & ~3; }}, {{ Ra = Mem.ul; }}, L); - 1: hw_ld({{ EA = (Rb + disp) & ~7; }}, {{ Ra = Mem.uq; }}, Q); + 0x1b: decode PALMODE { + 0: OpcdecFault::hw_st_quad(); + 1: decode HW_LDST_QUAD { + format HwLoad { + 0: hw_ld({{ EA = (Rb + disp) & ~3; }}, {{ Ra = Mem.ul; }}, L); + 1: hw_ld({{ EA = (Rb + disp) & ~7; }}, {{ Ra = Mem.uq; }}, Q); + } } } - format HwStore { - 0x1f: decode HW_LDST_COND { - 0: decode HW_LDST_QUAD { - 0: hw_st({{ EA = (Rb + disp) & ~3; }}, - {{ Mem.ul = Ra<31:0>; }}, L); - 1: hw_st({{ EA = (Rb + disp) & ~7; }}, - {{ Mem.uq = Ra.uq; }}, Q); - } + 0x1f: decode PALMODE { + 0: OpcdecFault::hw_st_cond(); + format HwStore { + 1: decode HW_LDST_COND { + 0: decode HW_LDST_QUAD { + 0: hw_st({{ EA = (Rb + disp) & ~3; }}, + {{ Mem.ul = Ra<31:0>; }}, L); + 1: hw_st({{ EA = (Rb + disp) & ~7; }}, + {{ Mem.uq = Ra.uq; }}, Q); + } - 1: FailUnimpl::hw_st_cond(); + 1: FailUnimpl::hw_st_cond(); + } } } - format HwMoveIPR { - 0x19: hw_mfpr({{ - // this instruction is only valid in PAL mode - if (!xc->inPalMode()) { - fault = UnimplementedOpcodeFault; - } - else { + 0x19: decode PALMODE { + 0: OpcdecFault::hw_mfpr(); + format HwMoveIPR { + 1: hw_mfpr({{ Ra = xc->readMiscRegWithEffect(ipr_index, fault); - } - }}); - 0x1d: hw_mtpr({{ - // this instruction is only valid in PAL mode - if (!xc->inPalMode()) { - fault = UnimplementedOpcodeFault; - } - else { + }}); + } + } + + 0x1d: decode PALMODE { + 0: OpcdecFault::hw_mtpr(); + format HwMoveIPR { + 1: hw_mtpr({{ xc->setMiscRegWithEffect(ipr_index, Ra); if (traceData) { traceData->setData(Ra); } - } - }}); + }}); + } } format BasicOperate { - 0x1e: hw_rei({{ xc->hwrei(); }}, IsSerializing); + 0x1e: decode PALMODE { + 0: OpcdecFault::hw_rei(); + 1:hw_rei({{ xc->hwrei(); }}, IsSerializing); + } // M5 special opcodes use the reserved 0x01 opcode space 0x01: decode M5FUNC { @@ -758,6 +763,15 @@ decode OPCODE default Unknown::unknown() { 0x01: quiesce({{ AlphaPseudo::quiesce(xc->xcBase()); }}, IsNonSpeculative); + 0x02: quiesceNs({{ + AlphaPseudo::quiesceNs(xc->xcBase(), R16); + }}, IsNonSpeculative); + 0x03: quiesceCycles({{ + AlphaPseudo::quiesceCycles(xc->xcBase(), R16); + }}, IsNonSpeculative); + 0x04: quiesceTime({{ + R0 = AlphaPseudo::quiesceTime(xc->xcBase()); + }}, IsNonSpeculative); 0x10: ivlb({{ AlphaPseudo::ivlb(xc->xcBase()); }}, No_OpClass, IsNonSpeculative); @@ -795,6 +809,9 @@ decode OPCODE default Unknown::unknown() { 0x53: m5addsymbol({{ AlphaPseudo::addsymbol(xc->xcBase(), R16, R17); }}, IsNonSpeculative); + 0x54: m5panic({{ + panic("M5 panic instruction called."); + }}, IsNonSpeculative); } } diff --git a/arch/alpha/isa/fp.isa b/arch/alpha/isa/fp.isa index 20a564045..f34c13c42 100644 --- a/arch/alpha/isa/fp.isa +++ b/arch/alpha/isa/fp.isa @@ -36,7 +36,7 @@ output exec {{ { Fault fault = NoFault; // dummy... this ipr access should not fault if (!EV5::ICSR_FPE(xc->readMiscRegWithEffect(AlphaISA::IPR_ICSR, fault))) { - fault = FloatEnableFault; + fault = new FloatEnableFault; } return fault; } @@ -106,7 +106,7 @@ output header {{ mutable bool warnedOnTrapping; /// Constructor - AlphaFP(const char *mnem, MachInst _machInst, OpClass __opClass) + AlphaFP(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : AlphaStaticInst(mnem, _machInst, __opClass), roundingMode((enum RoundingMode)FP_ROUNDMODE), trappingMode((enum TrappingMode)FP_TRAPMODE), diff --git a/arch/alpha/isa/int.isa b/arch/alpha/isa/int.isa index 049437f8c..17ecc1a51 100644 --- a/arch/alpha/isa/int.isa +++ b/arch/alpha/isa/int.isa @@ -37,7 +37,7 @@ output header {{ uint8_t imm; /// Constructor - IntegerImm(const char *mnem, MachInst _machInst, OpClass __opClass) + IntegerImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : AlphaStaticInst(mnem, _machInst, __opClass), imm(INTIMM) { } diff --git a/arch/alpha/isa/main.isa b/arch/alpha/isa/main.isa index ad9c2a55e..17c9989ab 100644 --- a/arch/alpha/isa/main.isa +++ b/arch/alpha/isa/main.isa @@ -79,6 +79,7 @@ namespace AlphaISA; // // Universal (format-independent) fields +def bitfield PALMODE <32:32>; def bitfield OPCODE <31:26>; def bitfield RA <25:21>; def bitfield RB <20:16>; @@ -153,9 +154,12 @@ def operands {{ # Int regs default to unsigned, but code should not count on this. # For clarity, descriptions that depend on unsigned behavior should # explicitly specify '.uq'. - 'Ra': ('IntReg', 'uq', 'RA', 'IsInteger', 1), - 'Rb': ('IntReg', 'uq', 'RB', 'IsInteger', 2), - 'Rc': ('IntReg', 'uq', 'RC', 'IsInteger', 3), + 'Ra': ('IntReg', 'uq', 'PALMODE ? AlphaISA::reg_redir[RA] : RA', + 'IsInteger', 1), + 'Rb': ('IntReg', 'uq', 'PALMODE ? AlphaISA::reg_redir[RB] : RB', + 'IsInteger', 2), + 'Rc': ('IntReg', 'uq', 'PALMODE ? AlphaISA::reg_redir[RC] : RC', + 'IsInteger', 3), 'Fa': ('FloatReg', 'df', 'FA', 'IsFloating', 1), 'Fb': ('FloatReg', 'df', 'FB', 'IsFloating', 2), 'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3), @@ -200,7 +204,7 @@ output header {{ }; /// Constructor. - AlphaStaticInst(const char *mnem, MachInst _machInst, + AlphaStaticInst(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : StaticInst(mnem, _machInst, __opClass) { @@ -272,7 +276,7 @@ def template BasicDeclare {{ { public: /// Constructor. - %(class_name)s(MachInst machInst); + %(class_name)s(ExtMachInst machInst); %(BasicExecDeclare)s }; @@ -280,7 +284,7 @@ def template BasicDeclare {{ // Basic instruction class constructor template. def template BasicConstructor {{ - inline %(class_name)s::%(class_name)s(MachInst machInst) + inline %(class_name)s::%(class_name)s(ExtMachInst machInst) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) { %(constructor)s; @@ -344,7 +348,7 @@ output header {{ public: /// Constructor - Nop(const std::string _originalDisassembly, MachInst _machInst) + Nop(const std::string _originalDisassembly, ExtMachInst _machInst) : AlphaStaticInst("nop", _machInst, No_OpClass), originalDisassembly(_originalDisassembly) { @@ -428,6 +432,9 @@ def format BasicOperateWithNopCheck(code, *opt_args) {{ // PAL instruction templates, formats, etc. ##include "m5/arch/alpha/isa/pal.isa" +// Opcdec fault instruction templates, formats, etc. +##include "m5/arch/alpha/isa/opcdec.isa" + // Unimplemented instruction templates, formats, etc. ##include "m5/arch/alpha/isa/unimp.isa" diff --git a/arch/alpha/isa/mem.isa b/arch/alpha/isa/mem.isa index 61d6ea8fa..3c8b4f755 100644 --- a/arch/alpha/isa/mem.isa +++ b/arch/alpha/isa/mem.isa @@ -42,7 +42,7 @@ output header {{ const StaticInstPtr memAccPtr; /// Constructor - Memory(const char *mnem, MachInst _machInst, OpClass __opClass, + Memory(const char *mnem, ExtMachInst _machInst, OpClass __opClass, StaticInstPtr _eaCompPtr = nullStaticInstPtr, StaticInstPtr _memAccPtr = nullStaticInstPtr) : AlphaStaticInst(mnem, _machInst, __opClass), @@ -70,7 +70,7 @@ output header {{ int32_t disp; /// Constructor. - MemoryDisp32(const char *mnem, MachInst _machInst, OpClass __opClass, + MemoryDisp32(const char *mnem, ExtMachInst _machInst, OpClass __opClass, StaticInstPtr _eaCompPtr = nullStaticInstPtr, StaticInstPtr _memAccPtr = nullStaticInstPtr) : Memory(mnem, _machInst, __opClass, _eaCompPtr, _memAccPtr), @@ -89,7 +89,7 @@ output header {{ { protected: /// Constructor - MemoryNoDisp(const char *mnem, MachInst _machInst, OpClass __opClass, + MemoryNoDisp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, StaticInstPtr _eaCompPtr = nullStaticInstPtr, StaticInstPtr _memAccPtr = nullStaticInstPtr) : Memory(mnem, _machInst, __opClass, _eaCompPtr, _memAccPtr) @@ -141,7 +141,7 @@ def template LoadStoreDeclare {{ { public: /// Constructor - EAComp(MachInst machInst); + EAComp(ExtMachInst machInst); %(BasicExecDeclare)s }; @@ -153,7 +153,7 @@ def template LoadStoreDeclare {{ { public: /// Constructor - MemAcc(MachInst machInst); + MemAcc(ExtMachInst machInst); %(BasicExecDeclare)s }; @@ -161,7 +161,7 @@ def template LoadStoreDeclare {{ public: /// Constructor. - %(class_name)s(MachInst machInst); + %(class_name)s(ExtMachInst machInst); %(BasicExecDeclare)s @@ -186,19 +186,19 @@ def template LoadStoreConstructor {{ /** TODO: change op_class to AddrGenOp or something (requires * creating new member of OpClass enum in op_class.hh, updating * config files, etc.). */ - inline %(class_name)s::EAComp::EAComp(MachInst machInst) + inline %(class_name)s::EAComp::EAComp(ExtMachInst machInst) : %(base_class)s("%(mnemonic)s (EAComp)", machInst, IntAluOp) { %(ea_constructor)s; } - inline %(class_name)s::MemAcc::MemAcc(MachInst machInst) + inline %(class_name)s::MemAcc::MemAcc(ExtMachInst machInst) : %(base_class)s("%(mnemonic)s (MemAcc)", machInst, %(op_class)s) { %(memacc_constructor)s; } - inline %(class_name)s::%(class_name)s(MachInst machInst) + inline %(class_name)s::%(class_name)s(ExtMachInst machInst) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, new EAComp(machInst), new MemAcc(machInst)) { diff --git a/arch/alpha/isa/opcdec.isa b/arch/alpha/isa/opcdec.isa new file mode 100644 index 000000000..bb2f91e5c --- /dev/null +++ b/arch/alpha/isa/opcdec.isa @@ -0,0 +1,72 @@ +// -*- mode:c++ -*- + +// Copyright (c) 2003-2005 The Regents of The University of Michigan +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are +// met: redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer; +// redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution; +// neither the name of the copyright holders nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +output header {{ + /** + * Static instruction class for instructions that cause an OPCDEC fault + * when executed. This is currently only for PAL mode instructions + * executed in non-PAL mode. + */ + class OpcdecFault : public AlphaStaticInst + { + public: + /// Constructor + OpcdecFault(ExtMachInst _machInst) + : AlphaStaticInst("opcdec fault", _machInst, No_OpClass) + { + } + + %(BasicExecDeclare)s + + std::string + generateDisassembly(Addr pc, const SymbolTable *symtab) const; + }; +}}; + +output decoder {{ + std::string + OpcdecFault::generateDisassembly(Addr pc, const SymbolTable *symtab) const + { + return csprintf("%-10s (inst 0x%x, opcode 0x%x)", + " OPCDEC fault", machInst, OPCODE); + } +}}; + +output exec {{ + Fault + OpcdecFault::execute(%(CPU_exec_context)s *xc, + Trace::InstRecord *traceData) const + { + return new UnimplementedOpcodeFault; + } +}}; + +def format OpcdecFault() {{ + decode_block = 'return new OpcdecFault(machInst);\n' +}}; + diff --git a/arch/alpha/isa/pal.isa b/arch/alpha/isa/pal.isa index 49e5bff12..e07bea5a8 100644 --- a/arch/alpha/isa/pal.isa +++ b/arch/alpha/isa/pal.isa @@ -36,7 +36,7 @@ output header {{ protected: /// Constructor. - EmulatedCallPal(const char *mnem, MachInst _machInst, + EmulatedCallPal(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : AlphaStaticInst(mnem, _machInst, __opClass) { @@ -83,7 +83,7 @@ output header {{ bool palPriv; ///< is this call privileged? /// Constructor. - CallPalBase(const char *mnem, MachInst _machInst, + CallPalBase(const char *mnem, ExtMachInst _machInst, OpClass __opClass); std::string @@ -93,7 +93,7 @@ output header {{ output decoder {{ inline - CallPalBase::CallPalBase(const char *mnem, MachInst _machInst, + CallPalBase::CallPalBase(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : AlphaStaticInst(mnem, _machInst, __opClass), palFunc(PALFUNC) @@ -148,7 +148,7 @@ output header {{ int16_t disp; /// Constructor - HwLoadStore(const char *mnem, MachInst _machInst, OpClass __opClass, + HwLoadStore(const char *mnem, ExtMachInst _machInst, OpClass __opClass, StaticInstPtr _eaCompPtr = nullStaticInstPtr, StaticInstPtr _memAccPtr = nullStaticInstPtr); @@ -160,7 +160,7 @@ output header {{ output decoder {{ inline - HwLoadStore::HwLoadStore(const char *mnem, MachInst _machInst, + HwLoadStore::HwLoadStore(const char *mnem, ExtMachInst _machInst, OpClass __opClass, StaticInstPtr _eaCompPtr, StaticInstPtr _memAccPtr) @@ -231,7 +231,7 @@ output header {{ int ipr_index; /// Constructor - HwMoveIPR(const char *mnem, MachInst _machInst, OpClass __opClass) + HwMoveIPR(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : AlphaStaticInst(mnem, _machInst, __opClass), ipr_index(HW_IPR_IDX) { diff --git a/arch/alpha/isa/unimp.isa b/arch/alpha/isa/unimp.isa index de4ac3eaf..392522801 100644 --- a/arch/alpha/isa/unimp.isa +++ b/arch/alpha/isa/unimp.isa @@ -38,7 +38,7 @@ output header {{ { public: /// Constructor - FailUnimplemented(const char *_mnemonic, MachInst _machInst) + FailUnimplemented(const char *_mnemonic, ExtMachInst _machInst) : AlphaStaticInst(_mnemonic, _machInst, No_OpClass) { // don't call execute() (which panics) if we're on a @@ -69,7 +69,7 @@ output header {{ public: /// Constructor - WarnUnimplemented(const char *_mnemonic, MachInst _machInst) + WarnUnimplemented(const char *_mnemonic, ExtMachInst _machInst) : AlphaStaticInst(_mnemonic, _machInst, No_OpClass), warned(false) { // don't call execute() (which panics) if we're on a @@ -111,7 +111,7 @@ output exec {{ { panic("attempt to execute unimplemented instruction '%s' " "(inst 0x%08x, opcode 0x%x)", mnemonic, machInst, OPCODE); - return UnimplementedOpcodeFault; + return new UnimplementedOpcodeFault; } Fault @@ -148,7 +148,7 @@ output header {{ { public: /// Constructor - Unknown(MachInst _machInst) + Unknown(ExtMachInst _machInst) : AlphaStaticInst("unknown", _machInst, No_OpClass) { // don't call execute() (which panics) if we're on a diff --git a/arch/alpha/isa/unknown.isa b/arch/alpha/isa/unknown.isa index 4601b3684..47d166255 100644 --- a/arch/alpha/isa/unknown.isa +++ b/arch/alpha/isa/unknown.isa @@ -42,7 +42,7 @@ output exec {{ { panic("attempt to execute unknown instruction " "(inst 0x%08x, opcode 0x%x)", machInst, OPCODE); - return UnimplementedOpcodeFault; + return new UnimplementedOpcodeFault; } }}; diff --git a/arch/alpha/isa_traits.hh b/arch/alpha/isa_traits.hh index a94777bee..b4084723f 100644 --- a/arch/alpha/isa_traits.hh +++ b/arch/alpha/isa_traits.hh @@ -57,16 +57,17 @@ namespace AlphaISA { typedef uint32_t MachInst; -// typedef uint64_t Addr; + typedef uint64_t ExtMachInst; typedef uint8_t RegIndex; enum { MemoryEnd = 0xffffffffffffffffULL, - NumIntRegs = 32, - NumFloatRegs = 32, + NumIntArchRegs = 32, + NumPALShadowRegs = 8, + NumFloatArchRegs = 32, // @todo: Figure out what this number really should be. - NumMiscRegs = 32, + NumMiscArchRegs = 32, MaxRegsOfAnyType = 32, // Static instruction parameters @@ -100,17 +101,23 @@ namespace AlphaISA DepNA = 0, }; + enum { + NumIntRegs = NumIntArchRegs + NumPALShadowRegs, + NumFloatRegs = NumFloatArchRegs, + NumMiscRegs = NumMiscArchRegs + }; + // These enumerate all the registers for dependence tracking. enum DependenceTags { // 0..31 are the integer regs 0..31 // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag) - FP_Base_DepTag = 32, - Ctrl_Base_DepTag = 64, - Fpcr_DepTag = 64, // floating point control register - Uniq_DepTag = 65, - Lock_Flag_DepTag = 66, - Lock_Addr_DepTag = 67, - IPR_Base_DepTag = 68 + FP_Base_DepTag = 40, + Ctrl_Base_DepTag = 72, + Fpcr_DepTag = 72, // floating point control register + Uniq_DepTag = 73, + Lock_Flag_DepTag = 74, + Lock_Addr_DepTag = 75, + IPR_Base_DepTag = 76 }; typedef uint64_t IntReg; @@ -132,6 +139,9 @@ extern const Addr PageBytes; extern const Addr PageMask; extern const Addr PageOffset; +// redirected register map, really only used for the full system case. +extern const int reg_redir[NumIntRegs]; + #if FULL_SYSTEM typedef uint64_t InternalProcReg; @@ -197,9 +207,7 @@ extern const Addr PageOffset; Addr pc; // program counter Addr npc; // next-cycle program counter #if FULL_SYSTEM - IntReg palregs[NumIntRegs]; // PAL shadow registers int intrflag; // interrupt flag - bool pal_shadow; // using pal_shadow registers inline int instAsid() { return EV5::ITB_ASN_ASN(miscRegs.ipr[IPR_ITB_ASN]); } inline int dataAsid() @@ -210,10 +218,12 @@ extern const Addr PageOffset; void unserialize(Checkpoint *cp, const std::string §ion); }; - StaticInstPtr decodeInst(MachInst); + static inline ExtMachInst makeExtMI(MachInst inst, const uint64_t &pc); + + StaticInstPtr decodeInst(ExtMachInst); // return a no-op instruction... used for instruction fetch faults - extern const MachInst NoopMachInst; + extern const ExtMachInst NoopMachInst; enum annotes { ANNOTE_NONE = 0, @@ -360,6 +370,18 @@ class SyscallReturn { #endif +static inline AlphaISA::ExtMachInst +AlphaISA::makeExtMI(AlphaISA::MachInst inst, const uint64_t &pc) { +#if FULL_SYSTEM + AlphaISA::ExtMachInst ext_inst = inst; + if (pc && 0x1) + return ext_inst|=(static_cast<AlphaISA::ExtMachInst>(pc & 0x1) << 32); + else + return ext_inst; +#else + return AlphaISA::ExtMachInst(inst); +#endif +} #if FULL_SYSTEM //typedef TheISA::InternalProcReg InternalProcReg; diff --git a/kern/linux/aligned.hh b/arch/alpha/linux/aligned.hh index 18d1b43c0..cabecb283 100644 --- a/kern/linux/aligned.hh +++ b/arch/alpha/linux/aligned.hh @@ -26,15 +26,15 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#ifndef __KERN_LINUX_ALIGNED_HH__ -#define __KERN_LINUX_ALIGNED_HH__ +#ifndef __ARCH_ALPHA_LINUX_ALIGNED_HH__ +#define __ARCH_ALPHA_LINUX_ALIGNED_HH__ /* GCC 3.3.X has a bug in which attributes+typedefs don't work. 3.2.X is fine * as in 3.4.X, but the bug is marked will not fix in 3.3.X so here is * the work around. */ -#if __GNUC__ == 3 && __GNUC_MINOR__ != 3 +#if (__GNUC__ == 3 && __GNUC_MINOR__ != 3) || __GNUC__ > 3 typedef uint64_t uint64_ta __attribute__ ((aligned (8))) ; typedef int64_t int64_ta __attribute__ ((aligned (8))) ; typedef Addr Addr_a __attribute__ ((aligned (8))) ; @@ -44,4 +44,4 @@ typedef Addr Addr_a __attribute__ ((aligned (8))) ; #define Addr_a Addr __attribute__ ((aligned (8))) #endif /* __GNUC__ __GNUC_MINOR__ */ -#endif /* __KERN_LINUX_ALIGNED_HH__ */ +#endif /* __ARCH_ALPHA_LINUX_ALIGNED_HH__ */ diff --git a/kern/linux/hwrpb.hh b/arch/alpha/linux/hwrpb.hh index 4c8ac32e8..869ce026b 100644 --- a/kern/linux/hwrpb.hh +++ b/arch/alpha/linux/hwrpb.hh @@ -22,10 +22,10 @@ * SOFTWARE. */ -#ifndef __KERN_LINUX_HWRPB_HH__ -#define __KERN_LINUX_HWRPB_HH__ +#ifndef __ARCH_ALPHA_LINUX_HWRPB_HH__ +#define __ARCH_ALPHA_LINUX_HWRPB_HH__ -#include "kern/linux/aligned.hh" +#include "arch/alpha/linux/aligned.hh" namespace Linux { struct pcb_struct { @@ -39,4 +39,4 @@ namespace Linux { uint64_ta res1, res2; }; } -#endif // __KERN_LINUX_HWRPB_HH__ +#endif // __ARCH_ALPHA_LINUX_HWRPB_HH__ diff --git a/kern/linux/linux_system.cc b/arch/alpha/linux/system.cc index a0da732f0..f9275d15e 100644 --- a/kern/linux/linux_system.cc +++ b/arch/alpha/linux/system.cc @@ -35,25 +35,28 @@ * up boot time. */ +#include "arch/arguments.hh" +#include "arch/vtophys.hh" +#include "arch/alpha/linux/system.hh" +#include "arch/alpha/linux/threadinfo.hh" +#include "arch/alpha/system.hh" #include "base/loader/symtab.hh" #include "cpu/exec_context.hh" #include "cpu/base.hh" -#include "kern/linux/linux_system.hh" -#include "kern/linux/linux_threadinfo.hh" +#include "dev/platform.hh" #include "kern/linux/printk.hh" +#include "kern/linux/events.hh" #include "mem/functional/memory_control.hh" #include "mem/functional/physical.hh" #include "sim/builder.hh" #include "sim/byteswap.hh" -#include "dev/platform.hh" -#include "targetarch/arguments.hh" -#include "targetarch/vtophys.hh" using namespace std; -using namespace TheISA; +using namespace AlphaISA; +using namespace Linux; -LinuxSystem::LinuxSystem(Params *p) - : System(p) +LinuxAlphaSystem::LinuxAlphaSystem(Params *p) + : AlphaSystem(p) { Addr addr = 0; Addr paddr = 0; @@ -73,7 +76,7 @@ LinuxSystem::LinuxSystem(Params *p) paddr = vtophys(physmem, CommandLine()); char *commandline = (char *)physmem->dma_addr(paddr, sizeof(uint64_t)); if (commandline) - strncpy(commandline, params->boot_osflags.c_str(), CommandLineSize); + strncpy(commandline, params()->boot_osflags.c_str(), CommandLineSize); /** * find the address of the est_cycle_freq variable and insert it @@ -146,7 +149,7 @@ LinuxSystem::LinuxSystem(Params *p) printThreadEvent = NULL; } - if (params->bin_int) { + if (params()->bin_int) { intStartEvent = addPalFuncEvent<InterruptStartEvent>("sys_int_21"); if (!intStartEvent) panic("could not find symbol: sys_int_21\n"); @@ -165,7 +168,7 @@ LinuxSystem::LinuxSystem(Params *p) } } -LinuxSystem::~LinuxSystem() +LinuxAlphaSystem::~LinuxAlphaSystem() { #ifndef NDEBUG delete kernelPanicEvent; @@ -183,7 +186,7 @@ LinuxSystem::~LinuxSystem() void -LinuxSystem::setDelayLoop(ExecContext *xc) +LinuxAlphaSystem::setDelayLoop(ExecContext *xc) { Addr addr = 0; if (kernelSymtab->findAddress("loops_per_jiffy", addr)) { @@ -199,31 +202,17 @@ LinuxSystem::setDelayLoop(ExecContext *xc) } } + void -LinuxSystem::SkipDelayLoopEvent::process(ExecContext *xc) +LinuxAlphaSystem::SkipDelayLoopEvent::process(ExecContext *xc) { SkipFuncEvent::process(xc); // calculate and set loops_per_jiffy - ((LinuxSystem *)xc->getSystemPtr())->setDelayLoop(xc); -} - -void -LinuxSystem::DebugPrintkEvent::process(ExecContext *xc) -{ - if (DTRACE(DebugPrintf)) { - if (!raw) { - StringWrap name(xc->getSystemPtr()->name() + ".dprintk"); - DPRINTFN(""); - } - - AlphaArguments args(xc); - Printk(args); - SkipFuncEvent::process(xc); - } + ((LinuxAlphaSystem *)xc->getSystemPtr())->setDelayLoop(xc); } void -LinuxSystem::PrintThreadInfo::process(ExecContext *xc) +LinuxAlphaSystem::PrintThreadInfo::process(ExecContext *xc) { Linux::ThreadInfo ti(xc); @@ -232,7 +221,7 @@ LinuxSystem::PrintThreadInfo::process(ExecContext *xc) } -BEGIN_DECLARE_SIM_OBJECT_PARAMS(LinuxSystem) +BEGIN_DECLARE_SIM_OBJECT_PARAMS(LinuxAlphaSystem) Param<Tick> boot_cpu_frequency; SimObjectParam<MemoryController *> memctrl; @@ -253,9 +242,9 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(LinuxSystem) VectorParam<string> binned_fns; Param<bool> bin_int; -END_DECLARE_SIM_OBJECT_PARAMS(LinuxSystem) +END_DECLARE_SIM_OBJECT_PARAMS(LinuxAlphaSystem) -BEGIN_INIT_SIM_OBJECT_PARAMS(LinuxSystem) +BEGIN_INIT_SIM_OBJECT_PARAMS(LinuxAlphaSystem) INIT_PARAM(boot_cpu_frequency, "Frequency of the boot CPU"), INIT_PARAM(memctrl, "memory controller"), @@ -273,11 +262,11 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(LinuxSystem) INIT_PARAM(binned_fns, "functions to be broken down and binned"), INIT_PARAM_DFLT(bin_int, "is interrupt code binned seperately?", true) -END_INIT_SIM_OBJECT_PARAMS(LinuxSystem) +END_INIT_SIM_OBJECT_PARAMS(LinuxAlphaSystem) -CREATE_SIM_OBJECT(LinuxSystem) +CREATE_SIM_OBJECT(LinuxAlphaSystem) { - System::Params *p = new System::Params; + AlphaSystem::Params *p = new AlphaSystem::Params; p->name = getInstanceName(); p->boot_cpu_frequency = boot_cpu_frequency; p->memctrl = memctrl; @@ -293,8 +282,8 @@ CREATE_SIM_OBJECT(LinuxSystem) p->bin = bin; p->binned_fns = binned_fns; p->bin_int = bin_int; - return new LinuxSystem(p); + return new LinuxAlphaSystem(p); } -REGISTER_SIM_OBJECT("LinuxSystem", LinuxSystem) +REGISTER_SIM_OBJECT("LinuxAlphaSystem", LinuxAlphaSystem) diff --git a/kern/linux/linux_system.hh b/arch/alpha/linux/system.hh index f883bef93..035e2a427 100644 --- a/kern/linux/linux_system.hh +++ b/arch/alpha/linux/system.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2004-2005 The Regents of The University of Michigan + * Copyright (c) 2004-2006 The Regents of The University of Michigan * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -26,21 +26,27 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#ifndef __KERN_LINUX_LINUX_SYSTEM_HH__ -#define __KERN_LINUX_LINUX_SYSTEM_HH__ +#ifndef __ARCH_ALPHA_LINUX_SYSTEM_HH__ +#define __ARCH_ALPHA_LINUX_SYSTEM_HH__ class ExecContext; class BreakPCEvent; class IdleStartEvent; -class PrintThreadInfo; + +#include "arch/alpha/system.hh" +#include "kern/linux/events.hh" + +using namespace AlphaISA; +using namespace Linux; +using namespace std; /** * This class contains linux specific system code (Loading, Events, Binning). * It points to objects that are the system binaries to load and patches them * appropriately to work in simulator. */ -class LinuxSystem : public System +class LinuxAlphaSystem : public AlphaSystem { private: class SkipDelayLoopEvent : public SkipFuncEvent @@ -51,18 +57,6 @@ class LinuxSystem : public System virtual void process(ExecContext *xc); }; - class DebugPrintkEvent : public SkipFuncEvent - { - private: - bool raw; - - public: - DebugPrintkEvent(PCEventQueue *q, const std::string &desc, Addr addr, - bool r = false) - : SkipFuncEvent(q, desc, addr), raw(r) {} - virtual void process(ExecContext *xc); - }; - class PrintThreadInfo : public PCEvent { public: @@ -71,6 +65,7 @@ class LinuxSystem : public System virtual void process(ExecContext *xc); }; + /** * Addresses defining where the kernel bootloader places various * elements. Details found in include/asm-alpha/system.h @@ -142,10 +137,10 @@ class LinuxSystem : public System IdleStartEvent *idleStartEvent; public: - LinuxSystem(Params *p); - ~LinuxSystem(); + LinuxAlphaSystem(Params *p); + ~LinuxAlphaSystem(); void setDelayLoop(ExecContext *xc); }; -#endif // __KERN_LINUX_LINUX_SYSTEM_HH__ +#endif // __ARCH_ALPHA_LINUX_SYSTEM_HH__ diff --git a/kern/linux/thread_info.hh b/arch/alpha/linux/thread_info.hh index cf24ef939..88791b00d 100644 --- a/kern/linux/thread_info.hh +++ b/arch/alpha/linux/thread_info.hh @@ -26,10 +26,10 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#ifndef __KERN_LINUX_THREAD_INFO_H__ -#define __KERN_LINUX_THREAD_INFO_H__ +#ifndef __ARCH_ALPHA_LINUX_THREAD_INFO_H__ +#define __ARCH_ALPHA_LINUX_THREAD_INFO_H__ -#include "kern/linux/hwrpb.hh" +#include "arch/alpha/linux/hwrpb.hh" namespace Linux { struct thread_info { @@ -38,4 +38,4 @@ namespace Linux { }; } -#endif // __KERN_LINUX_THREAD_INFO_H__ +#endif // __ARCH_ALPHA_LINUX_THREAD_INFO_H__ diff --git a/kern/linux/linux_threadinfo.hh b/arch/alpha/linux/threadinfo.hh index f2fb10483..8f03c9314 100644 --- a/kern/linux/linux_threadinfo.hh +++ b/arch/alpha/linux/threadinfo.hh @@ -26,10 +26,11 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#ifndef __KERN_LINUX_LINUX_TREADNIFO_HH__ -#define __KERN_LINUX_LINUX_TREADNIFO_HH__ +#ifndef __ARCH_ALPHA_LINUX_LINUX_TREADNIFO_HH__ +#define __ARCH_ALPHA_LINUX_LINUX_TREADNIFO_HH__ -#include "kern/linux/thread_info.hh" +#include "arch/alpha/linux/thread_info.hh" +#include "cpu/exec_context.hh" #include "kern/linux/sched.hh" #include "sim/vptr.hh" @@ -85,4 +86,4 @@ class ThreadInfo /* namespace Linux */ } -#endif // __KERN_LINUX_LINUX_THREADINFO_HH__ +#endif // __ARCH_ALPHA_LINUX_LINUX_THREADINFO_HH__ diff --git a/arch/alpha/alpha_linux_process.cc b/arch/alpha/linux_process.cc index 63913d68e..b80966133 100644 --- a/arch/alpha/alpha_linux_process.cc +++ b/arch/alpha/linux_process.cc @@ -26,8 +26,8 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#include "arch/alpha/alpha_common_syscall_emul.hh" -#include "arch/alpha/alpha_linux_process.hh" +#include "arch/alpha/common_syscall_emul.hh" +#include "arch/alpha/linux_process.hh" #include "arch/alpha/isa_traits.hh" #include "base/trace.hh" diff --git a/arch/alpha/alpha_linux_process.hh b/arch/alpha/linux_process.hh index 7de1b1ac1..7de1b1ac1 100644 --- a/arch/alpha/alpha_linux_process.hh +++ b/arch/alpha/linux_process.hh diff --git a/arch/alpha/process.cc b/arch/alpha/process.cc new file mode 100644 index 000000000..b2dbe7ad1 --- /dev/null +++ b/arch/alpha/process.cc @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2003-2004 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "arch/alpha/process.hh" + +namespace AlphaISA +{ + +LiveProcess * +createProcess(const std::string &nm, ObjectFile * objFile, + int stdin_fd, int stdout_fd, int stderr_fd, + std::vector<std::string> &argv, std::vector<std::string> &envp) +{ + LiveProcess * process = NULL; + if (objFile->getArch() != ObjectFile::Alpha) + fatal("Object file does not match architecture."); + switch (objFile->getOpSys()) { + case ObjectFile::Tru64: + process = new AlphaTru64Process(nm, objFile, + stdin_fd, stdout_fd, stderr_fd, + argv, envp); + break; + + case ObjectFile::Linux: + process = new AlphaLinuxProcess(nm, objFile, + stdin_fd, stdout_fd, stderr_fd, + argv, envp); + break; + + default: + fatal("Unknown/unsupported operating system."); + } + return process; +} + +} // namespace AlphaISA diff --git a/arch/alpha/process.hh b/arch/alpha/process.hh new file mode 100644 index 000000000..7b660ddd0 --- /dev/null +++ b/arch/alpha/process.hh @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2003-2004 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __ALPHA_PROCESS_HH__ +#define __ALPHA_PROCESS_HH__ + +#include <string> + +#include "arch/alpha/linux_process.hh" +#include "arch/alpha/tru64_process.hh" +#include "base/loader/object_file.hh" + +namespace AlphaISA +{ + +LiveProcess * +createProcess(const std::string &nm, ObjectFile * objFile, + int stdin_fd, int stdout_fd, int stderr_fd, + std::vector<std::string> &argv, std::vector<std::string> &envp); + +} // namespace AlphaISA + +#endif // __ALPHA_PROCESS_HH__ diff --git a/arch/alpha/system.cc b/arch/alpha/system.cc new file mode 100644 index 000000000..1e80c7768 --- /dev/null +++ b/arch/alpha/system.cc @@ -0,0 +1,298 @@ +/* + * Copyright (c) 2002-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "arch/alpha/system.hh" +#include "arch/vtophys.hh" +#include "base/remote_gdb.hh" +#include "base/loader/object_file.hh" +#include "base/loader/symtab.hh" +#include "base/trace.hh" +#include "mem/functional/memory_control.hh" +#include "mem/functional/physical.hh" +#include "sim/byteswap.hh" +#include "sim/builder.hh" + +using namespace LittleEndianGuest; + +AlphaSystem::AlphaSystem(Params *p) + : System(p) +{ + consoleSymtab = new SymbolTable; + palSymtab = new SymbolTable; + + + /** + * Load the pal, and console code into memory + */ + // Load Console Code + console = createObjectFile(params()->console_path); + if (console == NULL) + fatal("Could not load console file %s", params()->console_path); + + // Load pal file + pal = createObjectFile(params()->palcode); + if (pal == NULL) + fatal("Could not load PALcode file %s", params()->palcode); + + + // Load program sections into memory + pal->loadSections(physmem, true); + console->loadSections(physmem, true); + + // load symbols + if (!console->loadGlobalSymbols(consoleSymtab)) + panic("could not load console symbols\n"); + + if (!pal->loadGlobalSymbols(palSymtab)) + panic("could not load pal symbols\n"); + + if (!pal->loadLocalSymbols(palSymtab)) + panic("could not load pal symbols\n"); + + if (!console->loadGlobalSymbols(debugSymbolTable)) + panic("could not load console symbols\n"); + + if (!pal->loadGlobalSymbols(debugSymbolTable)) + panic("could not load pal symbols\n"); + + if (!pal->loadLocalSymbols(debugSymbolTable)) + panic("could not load pal symbols\n"); + + Addr addr = 0; +#ifndef NDEBUG + consolePanicEvent = addConsoleFuncEvent<BreakPCEvent>("panic"); +#endif + + /** + * Copy the osflags (kernel arguments) into the consoles + * memory. (Presently Linux does not use the console service + * routine to get these command line arguments, but Tru64 and + * others do.) + */ + if (consoleSymtab->findAddress("env_booted_osflags", addr)) { + Addr paddr = vtophys(physmem, addr); + char *osflags = (char *)physmem->dma_addr(paddr, sizeof(uint32_t)); + + if (osflags) + strcpy(osflags, params()->boot_osflags.c_str()); + } + + /** + * Set the hardware reset parameter block system type and revision + * information to Tsunami. + */ + if (consoleSymtab->findAddress("m5_rpb", addr)) { + Addr paddr = vtophys(physmem, addr); + char *hwrpb = (char *)physmem->dma_addr(paddr, sizeof(uint64_t)); + + if (!hwrpb) + panic("could not translate hwrpb addr\n"); + + *(uint64_t*)(hwrpb+0x50) = htog(params()->system_type); + *(uint64_t*)(hwrpb+0x58) = htog(params()->system_rev); + } else + panic("could not find hwrpb\n"); + +} + +AlphaSystem::~AlphaSystem() +{ + delete consoleSymtab; + delete console; + delete pal; +#ifdef DEBUG + delete consolePanicEvent; +#endif +} + +/** + * This function fixes up addresses that are used to match PCs for + * hooking simulator events on to target function executions. + * + * Alpha binaries may have multiple global offset table (GOT) + * sections. A function that uses the GOT starts with a + * two-instruction prolog which sets the global pointer (gp == r29) to + * the appropriate GOT section. The proper gp value is calculated + * based on the function address, which must be passed by the caller + * in the procedure value register (pv aka t12 == r27). This sequence + * looks like the following: + * + * opcode Ra Rb offset + * ldah gp,X(pv) 09 29 27 X + * lda gp,Y(gp) 08 29 29 Y + * + * for some constant offsets X and Y. The catch is that the linker + * (or maybe even the compiler, I'm not sure) may recognize that the + * caller and callee are using the same GOT section, making this + * prolog redundant, and modify the call target to skip these + * instructions. If we check for execution of the first instruction + * of a function (the one the symbol points to) to detect when to skip + * it, we'll miss all these modified calls. It might work to + * unconditionally check for the third instruction, but not all + * functions have this prolog, and there's some chance that those + * first two instructions could have undesired consequences. So we do + * the Right Thing and pattern-match the first two instructions of the + * function to decide where to patch. + * + * Eventually this code should be moved into an ISA-specific file. + */ +Addr +AlphaSystem::fixFuncEventAddr(Addr addr) +{ + // mask for just the opcode, Ra, and Rb fields (not the offset) + const uint32_t inst_mask = 0xffff0000; + // ldah gp,X(pv): opcode 9, Ra = 29, Rb = 27 + const uint32_t gp_ldah_pattern = (9 << 26) | (29 << 21) | (27 << 16); + // lda gp,Y(gp): opcode 8, Ra = 29, rb = 29 + const uint32_t gp_lda_pattern = (8 << 26) | (29 << 21) | (29 << 16); + // instruction size + const int sz = sizeof(uint32_t); + + Addr paddr = vtophys(physmem, addr); + uint32_t i1 = *(uint32_t *)physmem->dma_addr(paddr, sz); + uint32_t i2 = *(uint32_t *)physmem->dma_addr(paddr+sz, sz); + + if ((i1 & inst_mask) == gp_ldah_pattern && + (i2 & inst_mask) == gp_lda_pattern) { + Addr new_addr = addr + 2*sz; + DPRINTF(Loader, "fixFuncEventAddr: %p -> %p", addr, new_addr); + return new_addr; + } else { + return addr; + } +} + + +void +AlphaSystem::setAlphaAccess(Addr access) +{ + Addr addr = 0; + if (consoleSymtab->findAddress("m5AlphaAccess", addr)) { + Addr paddr = vtophys(physmem, addr); + uint64_t *m5AlphaAccess = + (uint64_t *)physmem->dma_addr(paddr, sizeof(uint64_t)); + + if (!m5AlphaAccess) + panic("could not translate m5AlphaAccess addr\n"); + + *m5AlphaAccess = htog(EV5::Phys2K0Seg(access)); + } else + panic("could not find m5AlphaAccess\n"); +} + +bool +AlphaSystem::breakpoint() +{ + return remoteGDB[0]->trap(ALPHA_KENTRY_INT); +} + +void +AlphaSystem::serialize(std::ostream &os) +{ + System::serialize(os); + consoleSymtab->serialize("console_symtab", os); + palSymtab->serialize("pal_symtab", os); +} + + +void +AlphaSystem::unserialize(Checkpoint *cp, const std::string §ion) +{ + System::unserialize(cp,section); + consoleSymtab->unserialize("console_symtab", cp, section); + palSymtab->unserialize("pal_symtab", cp, section); +} + + +BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaSystem) + + Param<Tick> boot_cpu_frequency; + SimObjectParam<MemoryController *> memctrl; + SimObjectParam<PhysicalMemory *> physmem; + + Param<std::string> kernel; + Param<std::string> console; + Param<std::string> pal; + + Param<std::string> boot_osflags; + Param<std::string> readfile; + Param<unsigned int> init_param; + + Param<uint64_t> system_type; + Param<uint64_t> system_rev; + + Param<bool> bin; + VectorParam<std::string> binned_fns; + Param<bool> bin_int; + +END_DECLARE_SIM_OBJECT_PARAMS(AlphaSystem) + +BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaSystem) + + INIT_PARAM(boot_cpu_frequency, "Frequency of the boot CPU"), + INIT_PARAM(memctrl, "memory controller"), + INIT_PARAM(physmem, "phsyical memory"), + INIT_PARAM(kernel, "file that contains the kernel code"), + INIT_PARAM(console, "file that contains the console code"), + INIT_PARAM(pal, "file that contains palcode"), + INIT_PARAM_DFLT(boot_osflags, "flags to pass to the kernel during boot", + "a"), + INIT_PARAM_DFLT(readfile, "file to read startup script from", ""), + INIT_PARAM_DFLT(init_param, "numerical value to pass into simulator", 0), + INIT_PARAM_DFLT(system_type, "Type of system we are emulating", 34), + INIT_PARAM_DFLT(system_rev, "Revision of system we are emulating", 1<<10), + INIT_PARAM_DFLT(bin, "is this system to be binned", false), + INIT_PARAM(binned_fns, "functions to be broken down and binned"), + INIT_PARAM_DFLT(bin_int, "is interrupt code binned seperately?", true) + +END_INIT_SIM_OBJECT_PARAMS(AlphaSystem) + +CREATE_SIM_OBJECT(AlphaSystem) +{ + AlphaSystem::Params *p = new AlphaSystem::Params; + p->name = getInstanceName(); + p->boot_cpu_frequency = boot_cpu_frequency; + p->memctrl = memctrl; + p->physmem = physmem; + p->kernel_path = kernel; + p->console_path = console; + p->palcode = pal; + p->boot_osflags = boot_osflags; + p->init_param = init_param; + p->readfile = readfile; + p->system_type = system_type; + p->system_rev = system_rev; + p->bin = bin; + p->binned_fns = binned_fns; + p->bin_int = bin_int; + return new AlphaSystem(p); +} + +REGISTER_SIM_OBJECT("AlphaSystem", AlphaSystem) + + diff --git a/arch/alpha/system.hh b/arch/alpha/system.hh new file mode 100644 index 000000000..fe1307ac3 --- /dev/null +++ b/arch/alpha/system.hh @@ -0,0 +1,109 @@ +/* + * Copyright (c) 2002-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __ARCH_ALPHA_SYSTEM_HH__ +#define __ARCH_ALPHA_SYSTEM_HH__ + +#include <string> +#include <vector> + +#include "sim/system.hh" +#include "base/loader/symtab.hh" +#include "cpu/pc_event.hh" +#include "kern/system_events.hh" +#include "sim/sim_object.hh" + +class AlphaSystem : public System +{ + public: + struct Params : public System::Params + { + std::string console_path; + std::string palcode; + std::string boot_osflags; + uint64_t system_type; + uint64_t system_rev; + }; + + AlphaSystem(Params *p); + + ~AlphaSystem(); + + virtual bool breakpoint(); + +/** + * Serialization stuff + */ + public: + virtual void serialize(std::ostream &os); + virtual void unserialize(Checkpoint *cp, const std::string §ion); + + /** + * Set the m5AlphaAccess pointer in the console + */ + void setAlphaAccess(Addr access); + + /** console symbol table */ + SymbolTable *consoleSymtab; + + /** pal symbol table */ + SymbolTable *palSymtab; + + /** Object pointer for the console code */ + ObjectFile *console; + + /** Object pointer for the PAL code */ + ObjectFile *pal; + +#ifndef NDEBUG + /** Event to halt the simulator if the console calls panic() */ + BreakPCEvent *consolePanicEvent; +#endif + protected: + const Params *params() const { return (const Params *)_params; } + + /** Add a function-based event to PALcode. */ + template <class T> + T *AlphaSystem::addPalFuncEvent(const char *lbl) + { + return addFuncEvent<T>(palSymtab, lbl); + } + + /** Add a function-based event to the console code. */ + template <class T> + T *AlphaSystem::addConsoleFuncEvent(const char *lbl) + { + return addFuncEvent<T>(consoleSymtab, lbl); + } + + virtual Addr fixFuncEventAddr(Addr addr); + +}; + +#endif + diff --git a/arch/alpha/alpha_memory.cc b/arch/alpha/tlb.cc index 9b43ad39e..e30a8e595 100644 --- a/arch/alpha/alpha_memory.cc +++ b/arch/alpha/tlb.cc @@ -30,7 +30,7 @@ #include <string> #include <vector> -#include "arch/alpha/alpha_memory.hh" +#include "arch/alpha/tlb.hh" #include "base/inifile.hh" #include "base/str.hh" #include "base/trace.hh" @@ -321,7 +321,7 @@ AlphaITB::translate(MemReqPtr &req) const if (!validVirtualAddress(req->vaddr)) { fault(req->vaddr, req->xc); acv++; - return ItbAcvFault; + return new ItbAcvFault; } @@ -338,7 +338,7 @@ AlphaITB::translate(MemReqPtr &req) const AlphaISA::mode_kernel) { fault(req->vaddr, req->xc); acv++; - return ItbAcvFault; + return new ItbAcvFault; } req->paddr = req->vaddr & PAddrImplMask; @@ -360,7 +360,7 @@ AlphaITB::translate(MemReqPtr &req) const if (!pte) { fault(req->vaddr, req->xc); misses++; - return ItbPageFault; + return new ItbPageFault; } req->paddr = (pte->ppn << AlphaISA::PageShift) + @@ -372,7 +372,7 @@ AlphaITB::translate(MemReqPtr &req) const // instruction access fault fault(req->vaddr, req->xc); acv++; - return ItbAcvFault; + return new ItbAcvFault; } hits++; @@ -381,7 +381,7 @@ AlphaITB::translate(MemReqPtr &req) const // check that the physical address is ok (catch bad physical addresses) if (req->paddr & ~PAddrImplMask) - return MachineCheckFault; + return genMachineCheckFault(); checkCacheability(req); @@ -510,7 +510,7 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const fault(req, write ? MM_STAT_WR_MASK : 0); DPRINTF(TLB, "Alignment Fault on %#x, size = %d", req->vaddr, req->size); - return AlignmentFault; + return genAlignmentFault(); } if (pc & 0x1) { @@ -530,7 +530,7 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const MM_STAT_ACV_MASK); if (write) { write_acv++; } else { read_acv++; } - return DtbPageFault; + return new DtbPageFault; } // Check for "superpage" mapping @@ -547,7 +547,7 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const fault(req, ((write ? MM_STAT_WR_MASK : 0) | MM_STAT_ACV_MASK)); if (write) { write_acv++; } else { read_acv++; } - return DtbAcvFault; + return new DtbAcvFault; } req->paddr = req->vaddr & PAddrImplMask; @@ -577,7 +577,9 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const fault(req, (write ? MM_STAT_WR_MASK : 0) | MM_STAT_DTB_MISS_MASK); if (write) { write_misses++; } else { read_misses++; } - return (req->flags & VPTE) ? (Fault)PDtbMissFault : (Fault)NDtbMissFault; + return (req->flags & VPTE) ? + (Fault)(new PDtbMissFault) : + (Fault)(new NDtbMissFault); } req->paddr = (pte->ppn << AlphaISA::PageShift) + @@ -590,25 +592,25 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const MM_STAT_ACV_MASK | (pte->fonw ? MM_STAT_FONW_MASK : 0)); write_acv++; - return DtbPageFault; + return new DtbPageFault; } if (pte->fonw) { fault(req, MM_STAT_WR_MASK | MM_STAT_FONW_MASK); write_acv++; - return DtbPageFault; + return new DtbPageFault; } } else { if (!(pte->xre & MODE2MASK(mode))) { fault(req, MM_STAT_ACV_MASK | (pte->fonr ? MM_STAT_FONR_MASK : 0)); read_acv++; - return DtbAcvFault; + return new DtbAcvFault; } if (pte->fonr) { fault(req, MM_STAT_FONR_MASK); read_acv++; - return DtbPageFault; + return new DtbPageFault; } } } @@ -621,7 +623,7 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const // check that the physical address is ok (catch bad physical addresses) if (req->paddr & ~PAddrImplMask) - return MachineCheckFault; + return genMachineCheckFault(); checkCacheability(req); diff --git a/arch/alpha/alpha_memory.hh b/arch/alpha/tlb.hh index de955fa46..de955fa46 100644 --- a/arch/alpha/alpha_memory.hh +++ b/arch/alpha/tlb.hh diff --git a/kern/tru64/tru64_system.cc b/arch/alpha/tru64/system.cc index ebcdc1553..d09a0c85d 100644 --- a/kern/tru64/tru64_system.cc +++ b/arch/alpha/tru64/system.cc @@ -26,23 +26,23 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +#include "arch/alpha/tru64/system.hh" +#include "arch/isa_traits.hh" +#include "arch/vtophys.hh" #include "base/loader/symtab.hh" #include "base/trace.hh" #include "cpu/base.hh" #include "cpu/exec_context.hh" #include "kern/tru64/tru64_events.hh" -#include "kern/tru64/tru64_system.hh" #include "kern/system_events.hh" #include "mem/functional/memory_control.hh" #include "mem/functional/physical.hh" #include "sim/builder.hh" -#include "arch/isa_traits.hh" -#include "targetarch/vtophys.hh" using namespace std; -Tru64System::Tru64System(Tru64System::Params *p) - : System(p) +Tru64AlphaSystem::Tru64AlphaSystem(Tru64AlphaSystem::Params *p) + : AlphaSystem(p) { Addr addr = 0; if (kernelSymtab->findAddress("enable_async_printf", addr)) { @@ -77,7 +77,7 @@ Tru64System::Tru64System(Tru64System::Params *p) #endif } -Tru64System::~Tru64System() +Tru64AlphaSystem::~Tru64AlphaSystem() { #ifdef DEBUG delete kernelPanicEvent; @@ -93,7 +93,7 @@ Tru64System::~Tru64System() #endif } -BEGIN_DECLARE_SIM_OBJECT_PARAMS(Tru64System) +BEGIN_DECLARE_SIM_OBJECT_PARAMS(Tru64AlphaSystem) Param<Tick> boot_cpu_frequency; SimObjectParam<MemoryController *> memctrl; @@ -113,9 +113,9 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(Tru64System) Param<bool> bin; VectorParam<string> binned_fns; -END_DECLARE_SIM_OBJECT_PARAMS(Tru64System) +END_DECLARE_SIM_OBJECT_PARAMS(Tru64AlphaSystem) -BEGIN_INIT_SIM_OBJECT_PARAMS(Tru64System) +BEGIN_INIT_SIM_OBJECT_PARAMS(Tru64AlphaSystem) INIT_PARAM(boot_cpu_frequency, "frequency of the boot cpu"), INIT_PARAM(memctrl, "memory controller"), @@ -132,11 +132,11 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(Tru64System) INIT_PARAM_DFLT(bin, "is this system to be binned", false), INIT_PARAM(binned_fns, "functions to be broken down and binned") -END_INIT_SIM_OBJECT_PARAMS(Tru64System) +END_INIT_SIM_OBJECT_PARAMS(Tru64AlphaSystem) -CREATE_SIM_OBJECT(Tru64System) +CREATE_SIM_OBJECT(Tru64AlphaSystem) { - System::Params *p = new System::Params; + AlphaSystem::Params *p = new AlphaSystem::Params; p->name = getInstanceName(); p->boot_cpu_frequency = boot_cpu_frequency; p->memctrl = memctrl; @@ -153,7 +153,7 @@ CREATE_SIM_OBJECT(Tru64System) p->binned_fns = binned_fns; p->bin_int = false; - return new Tru64System(p); + return new Tru64AlphaSystem(p); } -REGISTER_SIM_OBJECT("Tru64System", Tru64System) +REGISTER_SIM_OBJECT("Tru64AlphaSystem", Tru64AlphaSystem) diff --git a/kern/tru64/tru64_system.hh b/arch/alpha/tru64/system.hh index d4eb5a59a..0e0cc1bc8 100644 --- a/kern/tru64/tru64_system.hh +++ b/arch/alpha/tru64/system.hh @@ -26,11 +26,12 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#ifndef __KERN_TRU64_TRU64_SYSTEM_HH__ -#define __KERN_TRU64_TRU64_SYSTEM_HH__ +#ifndef __ARCH_ALPHA_TRU64_SYSTEM_HH__ +#define __ARCH_ALPHA_TRU64_SYSTEM_HH__ -#include "sim/system.hh" +#include "arch/alpha/system.hh" #include "arch/isa_traits.hh" +#include "sim/system.hh" class ExecContext; @@ -39,10 +40,11 @@ class BadAddrEvent; class SkipFuncEvent; class PrintfEvent; class DebugPrintfEvent; +class DebugPrintfrEvent; class DumpMbufEvent; class AlphaArguments; -class Tru64System : public System +class Tru64AlphaSystem : public AlphaSystem { private: #ifdef DEBUG @@ -59,11 +61,11 @@ class Tru64System : public System DumpMbufEvent *dumpMbufEvent; public: - Tru64System(Params *p); - ~Tru64System(); + Tru64AlphaSystem(Params *p); + ~Tru64AlphaSystem(); static void Printf(AlphaArguments args); static void DumpMbuf(AlphaArguments args); }; -#endif // __KERN_TRU64_TRU64_SYSTEM_HH__ +#endif // __ARCH_ALPHA_TRU64_SYSTEM_HH__ diff --git a/arch/alpha/alpha_tru64_process.cc b/arch/alpha/tru64_process.cc index 7c0bc49e9..5f6b802e9 100644 --- a/arch/alpha/alpha_tru64_process.cc +++ b/arch/alpha/tru64_process.cc @@ -27,8 +27,8 @@ */ #include "arch/alpha/isa_traits.hh" -#include "arch/alpha/alpha_common_syscall_emul.hh" -#include "arch/alpha/alpha_tru64_process.hh" +#include "arch/alpha/common_syscall_emul.hh" +#include "arch/alpha/tru64_process.hh" #include "cpu/exec_context.hh" #include "kern/tru64/tru64.hh" #include "mem/functional/functional.hh" diff --git a/arch/alpha/alpha_tru64_process.hh b/arch/alpha/tru64_process.hh index 051760702..051760702 100644 --- a/arch/alpha/alpha_tru64_process.hh +++ b/arch/alpha/tru64_process.hh diff --git a/arch/isa_parser.py b/arch/isa_parser.py index 5185ed573..570110d84 100755 --- a/arch/isa_parser.py +++ b/arch/isa_parser.py @@ -225,7 +225,7 @@ def p_specification(t): # wrap the decode block as a function definition t[4].wrap_decode_block(''' StaticInstPtr -%(isa_name)s::decodeInst(%(isa_name)s::MachInst machInst) +%(isa_name)s::decodeInst(%(isa_name)s::ExtMachInst machInst) { using namespace %(namespace)s; ''' % vars(), '}') diff --git a/arch/mips/faults.cc b/arch/mips/faults.cc new file mode 100644 index 000000000..e05b3fe59 --- /dev/null +++ b/arch/mips/faults.cc @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2003-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "arch/alpha/faults.hh" + +ResetFaultType * const ResetFault = + new ResetFaultType("reset", 1, 0x0001); +ArithmeticFaultType * const ArithmeticFault = + new ArithmeticFaultType("arith", 3, 0x0501); +InterruptFaultType * const InterruptFault = + new InterruptFaultType("interrupt", 4, 0x0101); +NDtbMissFaultType * const NDtbMissFault = + new NDtbMissFaultType("dtb_miss_single", 5, 0x0201); +PDtbMissFaultType * const PDtbMissFault = + new PDtbMissFaultType("dtb_miss_double", 6, 0x0281); +DtbPageFaultType * const DtbPageFault = + new DtbPageFaultType("dfault", 8, 0x0381); +DtbAcvFaultType * const DtbAcvFault = + new DtbAcvFaultType("dfault", 9, 0x0381); +ItbMissFaultType * const ItbMissFault = + new ItbMissFaultType("itbmiss", 10, 0x0181); +ItbPageFaultType * const ItbPageFault = + new ItbPageFaultType("itbmiss", 11, 0x0181); +ItbAcvFaultType * const ItbAcvFault = + new ItbAcvFaultType("iaccvio", 12, 0x0081); +UnimplementedOpcodeFaultType * const UnimplementedOpcodeFault = + new UnimplementedOpcodeFaultType("opdec", 13, 0x0481); +FloatEnableFaultType * const FloatEnableFault = + new FloatEnableFaultType("fen", 14, 0x0581); +PalFaultType * const PalFault = + new PalFaultType("pal", 15, 0x2001); +IntegerOverflowFaultType * const IntegerOverflowFault = + new IntegerOverflowFaultType("intover", 16, 0x0501); + +Fault ** ListOfFaults[] = { + (Fault **)&NoFault, + (Fault **)&ResetFault, + (Fault **)&MachineCheckFault, + (Fault **)&ArithmeticFault, + (Fault **)&InterruptFault, + (Fault **)&NDtbMissFault, + (Fault **)&PDtbMissFault, + (Fault **)&AlignmentFault, + (Fault **)&DtbPageFault, + (Fault **)&DtbAcvFault, + (Fault **)&ItbMissFault, + (Fault **)&ItbPageFault, + (Fault **)&ItbAcvFault, + (Fault **)&UnimplementedOpcodeFault, + (Fault **)&FloatEnableFault, + (Fault **)&PalFault, + (Fault **)&IntegerOverflowFault, + }; + +int NumFaults = sizeof(ListOfFaults) / sizeof(Fault **); diff --git a/arch/mips/faults.hh b/arch/mips/faults.hh new file mode 100644 index 000000000..60c9e735c --- /dev/null +++ b/arch/mips/faults.hh @@ -0,0 +1,160 @@ +/* + * Copyright (c) 2003-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __ALPHA_FAULTS_HH__ +#define __ALPHA_FAULTS_HH__ + +#include "sim/faults.hh" +#include "arch/isa_traits.hh" //For the Addr type + +class AlphaFault : public Fault +{ + public: + AlphaFault(char * newName, int newId, Addr newVect) + : Fault(newName, newId), vect(newVect) + {;} + + Addr vect; +}; + +extern class ResetFaultType : public AlphaFault +{ + public: + ResetFaultType(char * newName, int newId, Addr newVect) + : AlphaFault(newName, newId, newVect) + {;} +} * const ResetFault; + +extern class ArithmeticFaultType : public AlphaFault +{ + public: + ArithmeticFaultType(char * newName, int newId, Addr newVect) + : AlphaFault(newName, newId, newVect) + {;} +} * const ArithmeticFault; + +extern class InterruptFaultType : public AlphaFault +{ + public: + InterruptFaultType(char * newName, int newId, Addr newVect) + : AlphaFault(newName, newId, newVect) + {;} +} * const InterruptFault; + +extern class NDtbMissFaultType : public AlphaFault +{ + public: + NDtbMissFaultType(char * newName, int newId, Addr newVect) + : AlphaFault(newName, newId, newVect) + {;} +} * const NDtbMissFault; + +extern class PDtbMissFaultType : public AlphaFault +{ + public: + PDtbMissFaultType(char * newName, int newId, Addr newVect) + : AlphaFault(newName, newId, newVect) + {;} +} * const PDtbMissFault; + +extern class DtbPageFaultType : public AlphaFault +{ + public: + DtbPageFaultType(char * newName, int newId, Addr newVect) + : AlphaFault(newName, newId, newVect) + {;} +} * const DtbPageFault; + +extern class DtbAcvFaultType : public AlphaFault +{ + public: + DtbAcvFaultType(char * newName, int newId, Addr newVect) + : AlphaFault(newName, newId, newVect) + {;} +} * const DtbAcvFault; + +extern class ItbMissFaultType : public AlphaFault +{ + public: + ItbMissFaultType(char * newName, int newId, Addr newVect) + : AlphaFault(newName, newId, newVect) + {;} +} * const ItbMissFault; + +extern class ItbPageFaultType : public AlphaFault +{ + public: + ItbPageFaultType(char * newName, int newId, Addr newVect) + : AlphaFault(newName, newId, newVect) + {;} +} * const ItbPageFault; + +extern class ItbAcvFaultType : public AlphaFault +{ + public: + ItbAcvFaultType(char * newName, int newId, Addr newVect) + : AlphaFault(newName, newId, newVect) + {;} +} * const ItbAcvFault; + +extern class UnimplementedOpcodeFaultType : public AlphaFault +{ + public: + UnimplementedOpcodeFaultType(char * newName, int newId, Addr newVect) + : AlphaFault(newName, newId, newVect) + {;} +} * const UnimplementedOpcodeFault; + +extern class FloatEnableFaultType : public AlphaFault +{ + public: + FloatEnableFaultType(char * newName, int newId, Addr newVect) + : AlphaFault(newName, newId, newVect) + {;} +} * const FloatEnableFault; + +extern class PalFaultType : public AlphaFault +{ + public: + PalFaultType(char * newName, int newId, Addr newVect) + : AlphaFault(newName, newId, newVect) + {;} +} * const PalFault; + +extern class IntegerOverflowFaultType : public AlphaFault +{ + public: + IntegerOverflowFaultType(char * newName, int newId, Addr newVect) + : AlphaFault(newName, newId, newVect) + {;} +} * const IntegerOverflowFault; + +extern Fault ** ListOfFaults[]; +extern int NumFaults; + +#endif // __FAULTS_HH__ diff --git a/arch/mips/isa/base.isa b/arch/mips/isa/base.isa index 846d161b9..7600632d3 100644 --- a/arch/mips/isa/base.isa +++ b/arch/mips/isa/base.isa @@ -7,57 +7,83 @@ //Outputs to decoder.hh output header {{ - /** - * Base class for all MIPS static instructions. - */ - class MipsStaticInst : public StaticInst<MIPSISA> - { - protected: +#define R31 31 - // Constructor. - MipsStaticInst(const char *mnem, MachInst _machInst, OpClass __opClass) - : StaticInst<MIPSISA>(mnem, _machInst, __opClass) - { - } + /** + * Base class for all MIPS static instructions. + */ + class MipsStaticInst : public StaticInst + { + protected: - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + /// Make MipsISA register dependence tags directly visible in + /// this class and derived classes. Maybe these should really + /// live here and not in the MipsISA namespace. + enum DependenceTags { + FP_Base_DepTag = MipsISA::FP_Base_DepTag, + Fpcr_DepTag = MipsISA::Fpcr_DepTag, + Uniq_DepTag = MipsISA::Uniq_DepTag, + IPR_Base_DepTag = MipsISA::IPR_Base_DepTag }; + // Constructor + MipsStaticInst(const char *mnem, MachInst _machInst, OpClass __opClass) + : StaticInst(mnem, _machInst, __opClass) + { + } + + /// Print a register name for disassembly given the unique + /// dependence tag number (FP or int). + void printReg(std::ostream &os, int reg) const; + + std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + }; + }}; //Ouputs to decoder.cc output decoder {{ - std::string MipsStaticInst::generateDisassembly(Addr pc, const SymbolTable *symtab) const + void MipsStaticInst::printReg(std::ostream &os, int reg) const + { + if (reg < FP_Base_DepTag) { + ccprintf(os, "r%d", reg); + } + else { + ccprintf(os, "f%d", reg - FP_Base_DepTag); + } + } + + std::string MipsStaticInst::generateDisassembly(Addr pc, const SymbolTable *symtab) const + { + std::stringstream ss; + + ccprintf(ss, "%-10s ", mnemonic); + + // just print the first two source regs... if there's + // a third one, it's a read-modify-write dest (Rc), + // e.g. for CMOVxx + if(_numSrcRegs > 0) + { + printReg(ss, _srcRegIdx[0]); + } + if(_numSrcRegs > 1) { - std::stringstream ss; - - ccprintf(ss, "%-10s ", mnemonic); - - // just print the first two source regs... if there's - // a third one, it's a read-modify-write dest (Rc), - // e.g. for CMOVxx - if(_numSrcRegs > 0) - { - printReg(ss, _srcRegIdx[0]); - } - if(_numSrcRegs > 1) - { - ss << ","; - printReg(ss, _srcRegIdx[1]); - } - - // just print the first dest... if there's a second one, - // it's generally implicit - if(_numDestRegs > 0) - { - if(_numSrcRegs > 0) - ss << ","; - printReg(ss, _destRegIdx[0]); - } - - return ss.str(); + ss << ","; + printReg(ss, _srcRegIdx[1]); } + // just print the first dest... if there's a second one, + // it's generally implicit + if(_numDestRegs > 0) + { + if(_numSrcRegs > 0) + ss << ","; + printReg(ss, _destRegIdx[0]); + } + + return ss.str(); + } + }}; diff --git a/arch/mips/isa/bitfields.isa b/arch/mips/isa/bitfields.isa index 532b3793a..3a01b64ee 100644 --- a/arch/mips/isa/bitfields.isa +++ b/arch/mips/isa/bitfields.isa @@ -5,9 +5,15 @@ // Bitfield definitions. // +def bitfield OPCODE <31:26>; def bitfield OPCODE_HI <31:29>; def bitfield OPCODE_LO <28:26>; +def bitfield REGIMM <20:16>; +def bitfield REGIMM_HI <20:19>; +def bitfield REGIMM_LO <18:16>; + +def bitfield FUNCTION < 5: 0>; def bitfield FUNCTION_HI < 5: 3>; def bitfield FUNCTION_LO < 2: 0>; @@ -31,6 +37,8 @@ def bitfield FT <20:16>; def bitfield FS <15:11>; def bitfield FD <10:6>; +def bitfield ND <17:17>; +def bitfield TF <16:16>; def bitfield MOVCI <16:16>; def bitfield MOVCF <16:16>; def bitfield SRL <21:21>; @@ -45,7 +53,7 @@ def bitfield OFFSET <15: 0>; // displacement // Jmp format def bitfield JMPTARG <25: 0>; -def bitfield JMPHINT <10: 6>; +def bitfield HINT <10: 6>; def bitfield SYSCALLCODE <25: 6>; def bitfield TRAPCODE <15:13>; diff --git a/arch/mips/isa/decoder.isa b/arch/mips/isa/decoder.isa index 7dd08ac49..f16da7f87 100644 --- a/arch/mips/isa/decoder.isa +++ b/arch/mips/isa/decoder.isa @@ -96,13 +96,13 @@ decode OPCODE_HI default Unknown::unknown() { 0x3: decode FUNCTION_LO { format IntOp { 0x0: mult({{ - INT64 temp1 = Rs.sw * Rt.sw; + int64_t temp1 = Rs.sw * Rt.sw; xc->miscRegs.hi->temp1<63:32>; xc->miscRegs.lo->temp1<31:0>; }}); 0x1: multu({{ - INT64 temp1 = Rs.uw * Rt.uw; + int64_t temp1 = Rs.uw * Rt.uw; xc->miscRegs.hi->temp1<63:32>; xc->miscRegs.lo->temp1<31:0> Rd.sw = Rs.uw * Rt.uw; @@ -141,7 +141,7 @@ decode OPCODE_HI default Unknown::unknown() { } 0x6: decode FUNCTION_LO { - format Trap { + format BasicOp { 0x0: tge({{ cond = (Rs.sw >= Rt.sw); }}); 0x1: tgeu({{ cond = (Rs.uw >= Rt.uw); }}); 0x2: tlt({{ cond = (Rs.sw < Rt.sw); }}); @@ -167,7 +167,7 @@ decode OPCODE_HI default Unknown::unknown() { } 0x1: decode REGIMM_LO { - format Trap { + format BasicOp { 0x0: tgei( {{ cond = (Rs.sw >= INTIMM); }}); 0x1: tgeiu({{ cond = (Rs.uw >= INTIMM); }}); 0x2: tlti( {{ cond = (Rs.sw < INTIMM); }}); @@ -179,14 +179,14 @@ decode OPCODE_HI default Unknown::unknown() { 0x2: decode REGIMM_LO { format Branch { - 0x0: bltzal({{ cond = (Rs.sw < 0); }}, IsLink); - 0x1: bgezal({{ cond = (Rs.sw >= 0); }}, IsLink); + 0x0: bltzal({{ cond = (Rs.sw < 0); }}, IsCall,IsReturn); + 0x1: bgezal({{ cond = (Rs.sw >= 0); }}, IsCall,IsReturn); } format BranchLikely { //Will be removed in future MIPS releases - 0x2: bltzall({{ cond = (Rs.sw < 0); }}, IsLink); - 0x3: bgezall({{ cond = (Rs.sw >= 0); }}, IsLink); + 0x2: bltzall({{ cond = (Rs.sw < 0); }}, IsCall, IsReturn); + 0x3: bgezall({{ cond = (Rs.sw >= 0); }}, IsCall, IsReturn); } } @@ -336,7 +336,7 @@ decode OPCODE_HI default Unknown::unknown() { //Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO 0x1: decode FUNCTION { - format Trap { + format BasicOp { 0x01: tlbr({{ }}); 0x02: tlbwi({{ }}); 0x06: tlbwr({{ }}); @@ -433,8 +433,8 @@ decode OPCODE_HI default Unknown::unknown() { } format Float64Op { - 0x2: recips({{ Fd = 1 / Fs; }}); - 0x3: rsqrts({{ Fd = 1 / sqrt(Fs.ud);}}); + 0x5: recips({{ Fd = 1 / Fs; }}); + 0x6: rsqrts({{ Fd = 1 / sqrt(Fs.ud);}}); } } @@ -502,8 +502,8 @@ decode OPCODE_HI default Unknown::unknown() { } format BasicOp { - 0x2: movz({{ if (Rt == 0) Fd.df = Fs.df; }}); - 0x3: movn({{ if (Rt != 0) Fd.df = Fs.df; }}); + 0x2: movzd({{ if (Rt == 0) Fd.df = Fs.df; }}); + 0x3: movnd({{ if (Rt != 0) Fd.df = Fs.df; }}); } format Float64Op { @@ -538,12 +538,12 @@ decode OPCODE_HI default Unknown::unknown() { //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=W 0x4: decode FUNCTION { format FloatOp { - 0x10: cvt_s({{ + 0x20: cvt_s({{ int rnd_mode = xc->miscRegs.fcsr; Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_WORD); }}); - 0x10: cvt_d({{ + 0x21: cvt_d({{ int rnd_mode = xc->miscRegs.fcsr; Fd = convert_and_round(Fs.df,rnd_mode,FP_DOUBLE,FP_WORD); }}); @@ -613,6 +613,11 @@ decode OPCODE_HI default Unknown::unknown() { } } + format BasicOp { + 0x2: movzps({{ if ( FPConditionCode(CC) == 0) Fd = Fs; }}); + 0x3: movnps({{ if ( FPConditionCode(CC) == 0) Fd = Fs; }}); + } + } 0x4: decode RS_LO { @@ -763,14 +768,14 @@ decode OPCODE_HI default Unknown::unknown() { 0x0: decode FUNCTION_LO { format IntOp { 0x0: madd({{ - INT64 temp1 = Hi.sw << 32 | Lo.sw >> 32; + int64_t temp1 = Hi.sw << 32 | Lo.sw >> 32; temp1 = temp1 + (Rs.sw * Rt.sw); xc->miscRegs.hi->temp1<63:32>; xc->miscRegs.lo->temp1<31:0> }}); 0x1: maddu({{ - INT64 temp1 = Hi.uw << 32 | Lo.uw >> 32; + int64_t temp1 = Hi.uw << 32 | Lo.uw >> 32; temp1 = temp1 + (Rs.uw * Rt.uw); xc->miscRegs.hi->temp1<63:32>; xc->miscRegs.lo->temp1<31:0> @@ -779,14 +784,14 @@ decode OPCODE_HI default Unknown::unknown() { 0x2: mul({{ Rd.sw = Rs.sw * Rt.sw; }}); 0x4: msub({{ - INT64 temp1 = Hi.sw << 32 | Lo.sw >> 32; + int64_t temp1 = Hi.sw << 32 | Lo.sw >> 32; temp1 = temp1 - (Rs.sw * Rt.sw); xc->miscRegs.hi->temp1<63:32>; xc->miscRegs.lo->temp1<31:0> }}); 0x5: msubu({{ - INT64 temp1 = Hi.uw << 32 | Lo.uw >> 32; + int64_t temp1 = Hi.uw << 32 | Lo.uw >> 32; temp1 = temp1 - (Rs.uw * Rt.uw); xc->miscRegs.hi->temp1<63:32>; xc->miscRegs.lo->temp1<31:0> diff --git a/arch/mips/isa/formats.isa b/arch/mips/isa/formats.isa index c244013df..a6aec9437 100644 --- a/arch/mips/isa/formats.isa +++ b/arch/mips/isa/formats.isa @@ -10,7 +10,7 @@ //Include utility formats/functions ##include "m5/arch/mips/isa/formats/util.isa" -//Include the integerOp and integerOpCc format +//Include the integer formats ##include "m5/arch/mips/isa/formats/int.isa" //Include the floatOp format @@ -30,4 +30,3 @@ //Include the noop format ##include "m5/arch/mips/isa/formats/unknown.isa" - diff --git a/arch/mips/isa/formats/branch.isa b/arch/mips/isa/formats/branch.isa index fc207fd3f..c896e9b2d 100644 --- a/arch/mips/isa/formats/branch.isa +++ b/arch/mips/isa/formats/branch.isa @@ -70,7 +70,7 @@ output header {{ int32_t disp; /// Constructor. - Branch(const char *mnem, MachInst _machInst, OpClass __opClass) + BranchLikely(const char *mnem, MachInst _machInst, OpClass __opClass) : PCDependentDisassembly(mnem, _machInst, __opClass), disp(OFFSET << 2) { @@ -243,7 +243,7 @@ output decoder {{ ss << ","; } - ccprintf(ss, "(r%d)", RB); + ccprintf(ss, "(r%d)", RT); return ss.str(); } diff --git a/arch/mips/isa/formats/fp.isa b/arch/mips/isa/formats/fp.isa index 23fcbaa67..7dd1e8442 100644 --- a/arch/mips/isa/formats/fp.isa +++ b/arch/mips/isa/formats/fp.isa @@ -1,3 +1,5 @@ +// -*- mode:c++ -*- + //////////////////////////////////////////////////////////////////// // // Floating Point operate instructions @@ -5,7 +7,7 @@ output header {{ /** - * Base class for integer operations. + * Base class for FP operations. */ class FPOp : public MipsStaticInst { @@ -70,62 +72,19 @@ def template FloatingPointExecute {{ }}; // Primary format for integer operate instructions: -def format FloatOp(code, *opt_flags) {{ - orig_code = code - cblk = CodeBlock(code) - checkPriv = (code.find('checkPriv') != -1) - code.replace('checkPriv', '') - if checkPriv: - code.replace('checkPriv;', 'if(!xc->regs.miscRegFile.pstateFields.priv) throw privileged_opcode;') - else: - code.replace('checkPriv;', '') - for (marker, value) in (('ivValue', '0'), ('icValue', '0'), - ('xvValue', '0'), ('xcValue', '0')): - code.replace(marker, value) - iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags) +def format FloatOp(code, *flags) {{ + iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags) header_output = BasicDeclare.subst(iop) decoder_output = BasicConstructor.subst(iop) - decode_block = BasicDecodeWithMnemonic.subst(iop) - exec_output = FloatingPointExecute.subst(iop) + decode_block = BasicDecode.subst(iop) + exec_output = BasicExecute.subst(iop) }}; // Primary format for integer operate instructions: -def format Float64Op(code, *opt_flags) {{ - orig_code = code - cblk = CodeBlock(code) - checkPriv = (code.find('checkPriv') != -1) - code.replace('checkPriv', '') - if checkPriv: - code.replace('checkPriv;', 'if(!xc->regs.miscRegFile.pstateFields.priv) throw privileged_opcode;') - else: - code.replace('checkPriv;', '') - for (marker, value) in (('ivValue', '0'), ('icValue', '0'), - ('xvValue', '0'), ('xcValue', '0')): - code.replace(marker, value) - iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags) - header_output = BasicDeclare.subst(iop) - decoder_output = BasicConstructor.subst(iop) - decode_block = BasicDecodeWithMnemonic.subst(iop) - exec_output = FloatingPointExecute.subst(iop) -}}; - -// Primary format for integer operate instructions: -def format FPOpCc(code, icValue, ivValue, xcValue, xvValue, *opt_flags) {{ - orig_code = code - - cblk = CodeBlock(code) - checkPriv = (code.find('checkPriv') != -1) - code.replace('checkPriv', '') - if checkPriv: - code.replace('checkPriv;', 'if(!xc->regs.miscRegFile.pstateFields.priv) throw privileged_opcode;') - else: - code.replace('checkPriv;', '') - for (marker, value) in (('ivValue', ivValue), ('icValue', icValue), - ('xvValue', xvValue), ('xcValue', xcValue)): - code.replace(marker, value) - iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags) +def format Float64Op(code, *flags) {{ + iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags) header_output = BasicDeclare.subst(iop) decoder_output = BasicConstructor.subst(iop) - decode_block = BasicDecodeWithMnemonic.subst(iop) - exec_output = IntegerExecute.subst(iop) + decode_block = BasicDecode.subst(iop) + exec_output = BasicExecute.subst(iop) }}; diff --git a/arch/mips/isa/formats/mem.isa b/arch/mips/isa/formats/mem.isa index 134548746..fcdb577c6 100644 --- a/arch/mips/isa/formats/mem.isa +++ b/arch/mips/isa/formats/mem.isa @@ -70,7 +70,7 @@ output decoder {{ Memory::generateDisassembly(Addr pc, const SymbolTable *symtab) const { return csprintf("%-10s %c%d,%d(r%d)", mnemonic, - flags[IsFloating] ? 'f' : 'r', RA, MEMDISP, RB); + flags[IsFloating] ? 'f' : 'r', RS, JMPTARG, RT); } }}; diff --git a/arch/mips/isa/formats/noop.isa b/arch/mips/isa/formats/noop.isa index d366461e2..05c5ac10f 100644 --- a/arch/mips/isa/formats/noop.isa +++ b/arch/mips/isa/formats/noop.isa @@ -63,12 +63,12 @@ output exec {{ } }}; -// integer & FP operate instructions use Rc as dest, so check for -// Rc == 31 to detect nops +// integer & FP operate instructions use RT as dest, so check for +// RT == 0 to detect nops def template OperateNopCheckDecode {{ { MipsStaticInst *i = new %(class_name)s(machInst); - if (RC == 31) { + if (RD == 0) { i = makeNop(i); } return i; diff --git a/arch/mips/isa/formats/util.isa b/arch/mips/isa/formats/util.isa index f0671726c..c06877b35 100644 --- a/arch/mips/isa/formats/util.isa +++ b/arch/mips/isa/formats/util.isa @@ -122,4 +122,4 @@ output exec {{ { //CODE HERE } -} +}}; diff --git a/arch/mips/isa/includes.isa b/arch/mips/isa/includes.isa index ff7cb7d1d..da919be00 100644 --- a/arch/mips/isa/includes.isa +++ b/arch/mips/isa/includes.isa @@ -9,7 +9,6 @@ output header {{ #include <iomanip> #include "cpu/static_inst.hh" -#include "traps.hh" #include "mem/mem_req.hh" // some constructors use MemReq flags }}; diff --git a/arch/mips/isa_traits.cc b/arch/mips/isa_traits.cc index 90a85feb6..02a857af7 100644 --- a/arch/mips/isa_traits.cc +++ b/arch/mips/isa_traits.cc @@ -27,32 +27,121 @@ */ #include "arch/mips/isa_traits.hh" +#include "config/full_system.hh" #include "cpu/static_inst.hh" #include "sim/serialize.hh" -// Alpha UNOP (ldq_u r31,0(r0)) -// @todo: fix to MIPS specific +using namespace MipsISA; + +const Addr MipsISA::PageShift = 13; +const Addr MipsISA::PageBytes = ULL(1) << PageShift; +const Addr MipsISA::PageMask = ~(PageBytes - 1); +const Addr MipsISA::PageOffset = PageBytes - 1; + +#if FULL_SYSTEM + +//////////////////////////////////////////////////////////////////////// +// +// Translation stuff +// + +const Addr MipsISA::PteShift = 3; +const Addr MipsISA::NPtePageShift = PageShift - PteShift; +const Addr MipsISA::NPtePage = ULL(1) << NPtePageShift; +const Addr MipsISA::PteMask = NPtePage - 1; + +// User Virtual +const Addr MipsISA::USegBase = ULL(0x0); +const Addr MipsISA::USegEnd = ULL(0x000003ffffffffff); + +// Kernel Direct Mapped +const Addr MipsISA::K0SegBase = ULL(0xfffffc0000000000); +const Addr MipsISA::K0SegEnd = ULL(0xfffffdffffffffff); + +// Kernel Virtual +const Addr MipsISA::K1SegBase = ULL(0xfffffe0000000000); +const Addr MipsISA::K1SegEnd = ULL(0xffffffffffffffff); + +#endif + +// Mips UNOP (ldq_u r31,0(r0)) const MachInst MipsISA::NoopMachInst = 0x2ffe0000; +static inline Addr +TruncPage(Addr addr) +{ return addr & ~(MipsISA::PageBytes - 1); } + +static inline Addr +RoundPage(Addr addr) +{ return (addr + MipsISA::PageBytes - 1) & ~(MipsISA::PageBytes - 1); } void -MipsISA::RegFile::serialize(std::ostream &os) +RegFile::serialize(std::ostream &os) { - intRegFile.serialize(os); - floatRegFile.serialize(os); - miscRegs.serialize(os); + SERIALIZE_ARRAY(intRegFile, NumIntRegs); + SERIALIZE_ARRAY(floatRegFile.q, NumFloatRegs); + SERIALIZE_SCALAR(miscRegs.fpcr); + SERIALIZE_SCALAR(miscRegs.uniq); + SERIALIZE_SCALAR(miscRegs.lock_flag); + SERIALIZE_SCALAR(miscRegs.lock_addr); SERIALIZE_SCALAR(pc); SERIALIZE_SCALAR(npc); +#if FULL_SYSTEM + SERIALIZE_ARRAY(palregs, NumIntRegs); + SERIALIZE_ARRAY(ipr, NumInternalProcRegs); + SERIALIZE_SCALAR(intrflag); + SERIALIZE_SCALAR(pal_shadow); +#endif } void -MipsISA::RegFile::unserialize(Checkpoint *cp, const std::string §ion) +RegFile::unserialize(Checkpoint *cp, const std::string §ion) { - intRegFile.unserialize(cp, section); - floatRegFile.unserialize(cp, section); - miscRegs.unserialize(cp, section); + UNSERIALIZE_ARRAY(intRegFile, NumIntRegs); + UNSERIALIZE_ARRAY(floatRegFile.q, NumFloatRegs); + UNSERIALIZE_SCALAR(miscRegs.fpcr); + UNSERIALIZE_SCALAR(miscRegs.uniq); + UNSERIALIZE_SCALAR(miscRegs.lock_flag); + UNSERIALIZE_SCALAR(miscRegs.lock_addr); UNSERIALIZE_SCALAR(pc); UNSERIALIZE_SCALAR(npc); +#if FULL_SYSTEM + UNSERIALIZE_ARRAY(palregs, NumIntRegs); + UNSERIALIZE_ARRAY(ipr, NumInternalProcRegs); + UNSERIALIZE_SCALAR(intrflag); + UNSERIALIZE_SCALAR(pal_shadow); +#endif +} + + +#if FULL_SYSTEM +void +PTE::serialize(std::ostream &os) +{ + SERIALIZE_SCALAR(tag); + SERIALIZE_SCALAR(ppn); + SERIALIZE_SCALAR(xre); + SERIALIZE_SCALAR(xwe); + SERIALIZE_SCALAR(asn); + SERIALIZE_SCALAR(asma); + SERIALIZE_SCALAR(fonr); + SERIALIZE_SCALAR(fonw); + SERIALIZE_SCALAR(valid); +} + + +void +PTE::unserialize(Checkpoint *cp, const std::string §ion) +{ + UNSERIALIZE_SCALAR(tag); + UNSERIALIZE_SCALAR(ppn); + UNSERIALIZE_SCALAR(xre); + UNSERIALIZE_SCALAR(xwe); + UNSERIALIZE_SCALAR(asn); + UNSERIALIZE_SCALAR(asma); + UNSERIALIZE_SCALAR(fonr); + UNSERIALIZE_SCALAR(fonw); + UNSERIALIZE_SCALAR(valid); } #endif //FULL_SYSTEM diff --git a/arch/mips/isa_traits.hh b/arch/mips/isa_traits.hh index 603af60e2..71da82ffa 100644 --- a/arch/mips/isa_traits.hh +++ b/arch/mips/isa_traits.hh @@ -29,13 +29,14 @@ #ifndef __ARCH_MIPS_ISA_TRAITS_HH__ #define __ARCH_MIPS_ISA_TRAITS_HH__ -//This makes sure the big endian versions of certain functions are used. namespace LittleEndianGuest {} -using namespace LittleEndianGuest +using namespace LittleEndianGuest; -#include "arch/mips/faults.hh" +//#include "arch/mips/faults.hh" #include "base/misc.hh" +#include "config/full_system.hh" #include "sim/host.hh" +#include "sim/faults.hh" class FastCPU; class FullCPU; @@ -43,453 +44,260 @@ class Checkpoint; #define TARGET_MIPS -template <class ISA> class StaticInst; -template <class ISA> class StaticInstPtr; +class StaticInst; +class StaticInstPtr; -//namespace MIPS34K -//{ -// int DTB_ASN_ASN(uint64_t reg); -// int ITB_ASN_ASN(uint64_t reg); -//} +namespace MIPS34K { +int DTB_ASN_ASN(uint64_t reg); +int ITB_ASN_ASN(uint64_t reg); +} -class MipsISA +namespace MipsISA { - public: - - typedef uint32_t MachInst; - typedef uint64_t Addr; - typedef uint8_t RegIndex; - - enum - { - MemoryEnd = 0xffffffffffffffffULL, - - NumFloatRegs = 32, - NumMiscRegs = 32, - MaxRegsOfAnyType = 32, - // Static instruction parameters - MaxInstSrcRegs = 3, - MaxInstDestRegs = 2, - - // Maximum trap level - MaxTL = 4 + typedef uint32_t MachInst; +// typedef uint64_t Addr; + typedef uint8_t RegIndex; + + enum { + MemoryEnd = 0xffffffffffffffffULL, + + NumIntRegs = 32, + NumFloatRegs = 32, + NumMiscRegs = 32, + + MaxRegsOfAnyType = 32, + // Static instruction parameters + MaxInstSrcRegs = 3, + MaxInstDestRegs = 2, + + // semantically meaningful register indices + ZeroReg = 31, // architecturally meaningful + // the rest of these depend on the ABI + StackPointerReg = 30, + GlobalPointerReg = 29, + ProcedureValueReg = 27, + ReturnAddressReg = 26, + ReturnValueReg = 0, + FramePointerReg = 15, + ArgumentReg0 = 16, + ArgumentReg1 = 17, + ArgumentReg2 = 18, + ArgumentReg3 = 19, + ArgumentReg4 = 20, + ArgumentReg5 = 21, + + LogVMPageSize = 13, // 8K bytes + VMPageSize = (1 << LogVMPageSize), + + BranchPredAddrShiftAmt = 2, // instructions are 4-byte aligned + + WordBytes = 4, + HalfwordBytes = 2, + ByteBytes = 1, + DepNA = 0, + }; + + // These enumerate all the registers for dependence tracking. + enum DependenceTags { + // 0..31 are the integer regs 0..31 + // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag) + FP_Base_DepTag = 32, + Ctrl_Base_DepTag = 64, + Fpcr_DepTag = 64, // floating point control register + Uniq_DepTag = 65, + IPR_Base_DepTag = 66 + }; + + typedef uint64_t IntReg; + typedef IntReg IntRegFile[NumIntRegs]; + + // floating point register file entry type + typedef union { + uint64_t q; + double d; + } FloatReg; + + typedef union { + uint64_t q[NumFloatRegs]; // integer qword view + double d[NumFloatRegs]; // double-precision floating point view + } FloatRegFile; + + // control register file contents + typedef uint64_t MiscReg; + typedef struct { + uint64_t fpcr; // floating point condition codes + uint64_t uniq; // process-unique register + bool lock_flag; // lock flag for LL/SC + Addr lock_addr; // lock address for LL/SC + } MiscRegFile; + +extern const Addr PageShift; +extern const Addr PageBytes; +extern const Addr PageMask; +extern const Addr PageOffset; + +#if FULL_SYSTEM + + typedef uint64_t InternalProcReg; + +#include "arch/mips/isa_fullsys_traits.hh" + +#else + enum { + NumInternalProcRegs = 0 + }; +#endif - // semantically meaningful register indices - ZeroReg = 0, // architecturally meaningful - // the rest of these depend on the ABI - } - typedef uint64_t IntReg; + enum { + TotalNumRegs = + NumIntRegs + NumFloatRegs + NumMiscRegs + NumInternalProcRegs + }; + + enum { + TotalDataRegs = NumIntRegs + NumFloatRegs + }; + + typedef union { + IntReg intreg; + FloatReg fpreg; + MiscReg ctrlreg; + } AnyReg; + + struct RegFile { + IntRegFile intRegFile; // (signed) integer register file + FloatRegFile floatRegFile; // floating point register file + MiscRegFile miscRegs; // control register file + Addr pc; // program counter + Addr npc; // next-cycle program counter +#if FULL_SYSTEM + IntReg palregs[NumIntRegs]; // PAL shadow registers + InternalProcReg ipr[NumInternalProcRegs]; // internal processor regs + int intrflag; // interrupt flag + bool pal_shadow; // using pal_shadow registers + inline int instAsid() { return EV5::ITB_ASN_ASN(ipr[IPR_ITB_ASN]); } + inline int dataAsid() { return EV5::DTB_ASN_ASN(ipr[IPR_DTB_ASN]); } +#endif // FULL_SYSTEM + + void serialize(std::ostream &os); + void unserialize(Checkpoint *cp, const std::string §ion); + }; + + StaticInstPtr decodeInst(MachInst); + + // return a no-op instruction... used for instruction fetch faults + extern const MachInst NoopMachInst; + + enum annotes { + ANNOTE_NONE = 0, + // An impossible number for instruction annotations + ITOUCH_ANNOTE = 0xffffffff, + }; + + static inline bool isCallerSaveIntegerRegister(unsigned int reg) { + panic("register classification not implemented"); + return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27); + } + + static inline bool isCalleeSaveIntegerRegister(unsigned int reg) { + panic("register classification not implemented"); + return (reg >= 9 && reg <= 15); + } + + static inline bool isCallerSaveFloatRegister(unsigned int reg) { + panic("register classification not implemented"); + return false; + } + + static inline bool isCalleeSaveFloatRegister(unsigned int reg) { + panic("register classification not implemented"); + return false; + } + + static inline Addr alignAddress(const Addr &addr, + unsigned int nbytes) { + return (addr & ~(nbytes - 1)); + } + + // Instruction address compression hooks + static inline Addr realPCToFetchPC(const Addr &addr) { + return addr; + } + + static inline Addr fetchPCToRealPC(const Addr &addr) { + return addr; + } + + // the size of "fetched" instructions (not necessarily the size + // of real instructions for PISA) + static inline size_t fetchInstSize() { + return sizeof(MachInst); + } + + static inline MachInst makeRegisterCopy(int dest, int src) { + panic("makeRegisterCopy not implemented"); + return 0; + } + + // Machine operations + + void saveMachineReg(AnyReg &savereg, const RegFile ®_file, + int regnum); + + void restoreMachineReg(RegFile ®s, const AnyReg ®, + int regnum); + +#if 0 + static void serializeSpecialRegs(const Serializable::Proxy &proxy, + const RegFile ®s); + + static void unserializeSpecialRegs(const IniFile *db, + const std::string &category, + ConfigNode *node, + RegFile ®s); +#endif - class IntRegFile - { - private: - //For right now, let's pretend the register file is static - IntReg regs[32]; - public: - IntReg & operator [] (RegIndex index) - { - //Don't allow indexes outside of the 32 registers - index &= 0x1F - return regs[index]; - } - }; - - void inline serialize(std::ostream & os) - { - SERIALIZE_ARRAY(regs, 32); - } - - void inline unserialize(Checkpoint &*cp, const std::string §ion) - { - UNSERIALIZE_ARRAY(regs, 32); - } - - class FloatRegFile - { - private: - //By using the largest data type, we ensure everything - //is aligned correctly in memory - union - { - double double rawRegs[16]; - uint64_t regDump[32]; - }; - class QuadRegs - { - private: - FloatRegFile * parent; - public: - QuadRegs(FloatRegFile * p) : parent(p) {;} - double double & operator [] (RegIndex index) - { - //Quad floats are index by the single - //precision register the start on, - //and only 16 should be accessed - index = (index >> 2) & 0xF; - return parent->rawRegs[index]; - } - }; - class DoubleRegs - { - private: - FloatRegFile * parent; - public: - DoubleRegs(FloatRegFile * p) : parent(p) {;} - double & operator [] (RegIndex index) - { - //Double floats are index by the single - //precision register the start on, - //and only 32 should be accessed - index = (index >> 1) & 0x1F - return ((double [])parent->rawRegs)[index]; - } - } - class SingleRegs - { - private: - FloatRegFile * parent; - public: - SingleRegs(FloatRegFile * p) : parent(p) {;} - double & operator [] (RegFile index) - { - //Only 32 single floats should be accessed - index &= 0x1F - return ((float [])parent->rawRegs)[index]; - } - } - public: - void inline serialize(std::ostream & os) - { - SERIALIZE_ARRAY(regDump, 32); - } - - void inline unserialize(Checkpoint &* cp, std::string & section) - { - UNSERIALIZE_ARRAY(regDump, 32); - } - - QuadRegs quadRegs; - DoubleRegs doubleRegs; - SingleRegs singleRegs; - FloatRegFile() : quadRegs(this), doubleRegs(this), singleRegs(this) - {;} - }; - - // control register file contents - typedef uint64_t MiscReg; - // The control registers, broken out into fields - class MiscRegFile - { - public: - union - { - uint16_t pstate; // Process State Register - struct - { - uint16_t ag:1; // Alternate Globals - uint16_t ie:1; // Interrupt enable - uint16_t priv:1; // Privelege mode - uint16_t am:1; // Address mask - uint16_t pef:1; // PSTATE enable floating-point - uint16_t red:1; // RED (reset, error, debug) state - uint16_t mm:2; // Memory Model - uint16_t tle:1; // Trap little-endian - uint16_t cle:1; // Current little-endian - } pstateFields; - } - uint64_t tba; // Trap Base Address - union - { - uint64_t y; // Y (used in obsolete multiplication) - struct - { - uint64_t value:32; // The actual value stored in y - const uint64_t :32; // reserved bits - } yFields; - } - uint8_t pil; // Process Interrupt Register - uint8_t cwp; // Current Window Pointer - uint16_t tt[MaxTL]; // Trap Type (Type of trap which occured on the previous level) - union - { - uint8_t ccr; // Condition Code Register - struct - { - union - { - uint8_t icc:4; // 32-bit condition codes - struct - { - uint8_t c:1; // Carry - uint8_t v:1; // Overflow - uint8_t z:1; // Zero - uint8_t n:1; // Negative - } iccFields:4; - } :4; - union - { - uint8_t xcc:4; // 64-bit condition codes - struct - { - uint8_t c:1; // Carry - uint8_t v:1; // Overflow - uint8_t z:1; // Zero - uint8_t n:1; // Negative - } xccFields:4; - } :4; - } ccrFields; - } - uint8_t asi; // Address Space Identifier - uint8_t tl; // Trap Level - uint64_t tpc[MaxTL]; // Trap Program Counter (value from previous trap level) - uint64_t tnpc[MaxTL]; // Trap Next Program Counter (value from previous trap level) - union - { - uint64_t tstate[MaxTL]; // Trap State - struct - { - //Values are from previous trap level - uint64_t cwp:5; // Current Window Pointer - const uint64_t :2; // Reserved bits - uint64_t pstate:10; // Process State - const uint64_t :6; // Reserved bits - uint64_t asi:8; // Address Space Identifier - uint64_t ccr:8; // Condition Code Register - } tstateFields[MaxTL]; - } - union - { - uint64_t tick; // Hardware clock-tick counter - struct - { - uint64_t counter:63; // Clock-tick count - uint64_t npt:1; // Non-priveleged trap - } tickFields; - } - uint8_t cansave; // Savable windows - uint8_t canrestore; // Restorable windows - uint8_t otherwin; // Other windows - uint8_t cleanwin; // Clean windows - union - { - uint8_t wstate; // Window State - struct - { - uint8_t normal:3; // Bits TT<4:2> are set to on a normal - // register window trap - uint8_t other:3; // Bits TT<4:2> are set to on an "otherwin" - // register window trap - } wstateFields; - } - union - { - uint64_t ver; // Version - struct - { - uint64_t maxwin:5; // Max CWP value - const uint64_t :2; // Reserved bits - uint64_t maxtl:8; // Maximum trap level - const uint64_t :8; // Reserved bits - uint64_t mask:8; // Processor mask set revision number - uint64_t impl:16; // Implementation identification number - uint64_t manuf:16; // Manufacturer code - } verFields; - } - union - { - uint64_t fsr; // Floating-Point State Register - struct - { - union - { - uint64_t cexc:5; // Current excpetion - struct - { - uint64_t nxc:1; // Inexact - uint64_t dzc:1; // Divide by zero - uint64_t ufc:1; // Underflow - uint64_t ofc:1; // Overflow - uint64_t nvc:1; // Invalid operand - } cexecFields:5; - } :5; - union - { - uint64_t aexc:5; // Accrued exception - struct - { - uint64_t nxc:1; // Inexact - uint64_t dzc:1; // Divide by zero - uint64_t ufc:1; // Underflow - uint64_t ofc:1; // Overflow - uint64_t nvc:1; // Invalid operand - } aexecFields:5; - } :5; - uint64_t fcc0:2; // Floating-Point condtion codes - const uint64_t :1; // Reserved bits - uint64_t qne:1; // Deferred trap queue not empty - // with no queue, it should read 0 - uint64_t ftt:3; // Floating-Point trap type - uint64_t ver:3; // Version (of the FPU) - const uint64_t :2; // Reserved bits - uint64_t ns:1; // Nonstandard floating point - union - { - uint64_t tem:5; // Trap Enable Mask - struct - { - uint64_t nxm:1; // Inexact - uint64_t dzm:1; // Divide by zero - uint64_t ufm:1; // Underflow - uint64_t ofm:1; // Overflow - uint64_t nvm:1; // Invalid operand - } temFields:5; - } :5; - const uint64_t :2; // Reserved bits - uint64_t rd:2; // Rounding direction - uint64_t fcc1:2; // Floating-Point condition codes - uint64_t fcc2:2; // Floating-Point condition codes - uint64_t fcc3:2; // Floating-Point condition codes - const uint64_t :26; // Reserved bits - } fsrFields; - } - union - { - uint8_t fprs; // Floating-Point Register State - struct - { - dl:1; // Dirty lower - du:1; // Dirty upper - fef:1; // FPRS enable floating-Point - } fprsFields; - }; - - void serialize(std::ostream & os) - { - SERIALIZE_SCALAR(pstate); - SERIAlIZE_SCALAR(tba); - SERIALIZE_SCALAR(y); - SERIALIZE_SCALAR(pil); - SERIALIZE_SCALAR(cwp); - SERIALIZE_ARRAY(tt, MaxTL); - SERIALIZE_SCALAR(ccr); - SERIALIZE_SCALAR(asi); - SERIALIZE_SCALAR(tl); - SERIALIZE_SCALAR(tpc); - SERIALIZE_SCALAR(tnpc); - SERIALIZE_ARRAY(tstate, MaxTL); - SERIALIZE_SCALAR(tick); - SERIALIZE_SCALAR(cansave); - SERIALIZE_SCALAR(canrestore); - SERIALIZE_SCALAR(otherwin); - SERIALIZE_SCALAR(cleanwin); - SERIALIZE_SCALAR(wstate); - SERIALIZE_SCALAR(ver); - SERIALIZE_SCALAR(fsr); - SERIALIZE_SCALAR(fprs); - } - - void unserialize(Checkpoint &* cp, std::string & section) - { - UNSERIALIZE_SCALAR(pstate); - UNSERIAlIZE_SCALAR(tba); - UNSERIALIZE_SCALAR(y); - UNSERIALIZE_SCALAR(pil); - UNSERIALIZE_SCALAR(cwp); - UNSERIALIZE_ARRAY(tt, MaxTL); - UNSERIALIZE_SCALAR(ccr); - UNSERIALIZE_SCALAR(asi); - UNSERIALIZE_SCALAR(tl); - UNSERIALIZE_SCALAR(tpc); - UNSERIALIZE_SCALAR(tnpc); - UNSERIALIZE_ARRAY(tstate, MaxTL); - UNSERIALIZE_SCALAR(tick); - UNSERIALIZE_SCALAR(cansave); - UNSERIALIZE_SCALAR(canrestore); - UNSERIALIZE_SCALAR(otherwin); - UNSERIALIZE_SCALAR(cleanwin); - UNSERIALIZE_SCALAR(wstate); - UNSERIALIZE_SCALAR(ver); - UNSERIALIZE_SCALAR(fsr); - UNSERIALIZE_SCALAR(fprs); - } - }; - - typedef union - { - IntReg intreg; - FloatReg fpreg; - MiscReg ctrlreg; - } AnyReg; - - struct RegFile - { - IntRegFile intRegFile; // (signed) integer register file - FloatRegFile floatRegFile; // floating point register file - MiscRegFile miscRegFile; // control register file - - Addr pc; // Program Counter - Addr npc; // Next Program Counter - Addr nnpc; // Next next program Counter - - - void serialize(std::ostream &os); - void unserialize(Checkpoint *cp, const std::string §ion); - }; - - static StaticInstPtr<MipsISA> decodeInst(MachInst); - - // return a no-op instruction... used for instruction fetch faults - static const MachInst NoopMachInst; - - // Instruction address compression hooks - static inline Addr realPCToFetchPC(const Addr &addr) - { - return addr; - } - - static inline Addr fetchPCToRealPC(const Addr &addr) - { - return addr; - } - - // the size of "fetched" instructions (not necessarily the size - // of real instructions for PISA) - static inline size_t fetchInstSize() - { - return sizeof(MachInst); - } - - /** - * Function to insure ISA semantics about 0 registers. - * @param xc The execution context. - */ - template <class XC> - static void zeroRegisters(XC *xc); + /** + * Function to insure ISA semantics about 0 registers. + * @param xc The execution context. + */ + template <class XC> + void zeroRegisters(XC *xc); + + +//typedef MipsISA TheISA; + +//typedef TheISA::MachInst MachInst; +//typedef TheISA::Addr Addr; +//typedef TheISA::RegIndex RegIndex; +//typedef TheISA::IntReg IntReg; +//typedef TheISA::IntRegFile IntRegFile; +//typedef TheISA::FloatReg FloatReg; +//typedef TheISA::FloatRegFile FloatRegFile; +//typedef TheISA::MiscReg MiscReg; +//typedef TheISA::MiscRegFile MiscRegFile; +//typedef TheISA::AnyReg AnyReg; +//typedef TheISA::RegFile RegFile; + +//const int NumIntRegs = TheISA::NumIntRegs; +//const int NumFloatRegs = TheISA::NumFloatRegs; +//const int NumMiscRegs = TheISA::NumMiscRegs; +//const int TotalNumRegs = TheISA::TotalNumRegs; +//const int VMPageSize = TheISA::VMPageSize; +//const int LogVMPageSize = TheISA::LogVMPageSize; +//const int ZeroReg = TheISA::ZeroReg; +//const int StackPointerReg = TheISA::StackPointerReg; +//const int GlobalPointerReg = TheISA::GlobalPointerReg; +//const int ReturnAddressReg = TheISA::ReturnAddressReg; +//const int ReturnValueReg = TheISA::ReturnValueReg; +//const int ArgumentReg0 = TheISA::ArgumentReg0; +//const int ArgumentReg1 = TheISA::ArgumentReg1; +//const int ArgumentReg2 = TheISA::ArgumentReg2; +//const int BranchPredAddrShiftAmt = TheISA::BranchPredAddrShiftAmt; +const Addr MaxAddr = (Addr)-1; }; - -typedef MIPSISA TheISA; - -typedef TheISA::MachInst MachInst; -typedef TheISA::Addr Addr; -typedef TheISA::RegIndex RegIndex; -typedef TheISA::IntReg IntReg; -typedef TheISA::IntRegFile IntRegFile; -typedef TheISA::FloatReg FloatReg; -typedef TheISA::FloatRegFile FloatRegFile; -typedef TheISA::MiscReg MiscReg; -typedef TheISA::MiscRegFile MiscRegFile; -typedef TheISA::AnyReg AnyReg; -typedef TheISA::RegFile RegFile; - -const int VMPageSize = TheISA::VMPageSize; -const int LogVMPageSize = TheISA::LogVMPageSize; -const int ZeroReg = TheISA::ZeroReg; -const int BranchPredAddrShiftAmt = TheISA::BranchPredAddrShiftAmt; -const int MaxAddr = (Addr)-1; - -#ifndef FULL_SYSTEM +#if !FULL_SYSTEM class SyscallReturn { public: template <class T> @@ -526,7 +334,10 @@ class SyscallReturn { #endif -#ifdef FULL_SYSTEM +#if FULL_SYSTEM +//typedef TheISA::InternalProcReg InternalProcReg; +//const int NumInternalProcRegs = TheISA::NumInternalProcRegs; +//const int NumInterruptLevels = TheISA::NumInterruptLevels; #include "arch/mips/mips34k.hh" #endif diff --git a/arch/mips/linux_process.cc b/arch/mips/linux_process.cc new file mode 100644 index 000000000..d3aca15bc --- /dev/null +++ b/arch/mips/linux_process.cc @@ -0,0 +1,588 @@ +/* + * Copyright (c) 2003-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "arch/mips/mips_common_syscall_emul.hh" +#include "arch/mips/mips_linux_process.hh" +#include "arch/mips/isa_traits.hh" + +#include "base/trace.hh" +#include "cpu/exec_context.hh" +#include "kern/linux/linux.hh" +#include "mem/functional/functional.hh" + +#include "sim/process.hh" +#include "sim/syscall_emul.hh" + +using namespace std; +using namespace MipsISA; + +/// Target uname() handler. +static SyscallReturn +unameFunc(SyscallDesc *desc, int callnum, Process *process, + ExecContext *xc) +{ + TypedBufferArg<Linux::utsname> name(xc->getSyscallArg(0)); + + strcpy(name->sysname, "Linux"); + strcpy(name->nodename, "m5.eecs.umich.edu"); + strcpy(name->release, "2.4.20"); + strcpy(name->version, "#1 Mon Aug 18 11:32:15 EDT 2003"); + strcpy(name->machine, "mips"); + + name.copyOut(xc->mem); + return 0; +} + +/// Target osf_getsysyinfo() handler. Even though this call is +/// borrowed from Tru64, the subcases that get used appear to be +/// different in practice from those used by Tru64 processes. +static SyscallReturn +osf_getsysinfoFunc(SyscallDesc *desc, int callnum, Process *process, + ExecContext *xc) +{ + unsigned op = xc->getSyscallArg(0); + // unsigned nbytes = xc->getSyscallArg(2); + + switch (op) { + + case 45: { // GSI_IEEE_FP_CONTROL + TypedBufferArg<uint64_t> fpcr(xc->getSyscallArg(1)); + // I don't think this exactly matches the HW FPCR + *fpcr = 0; + fpcr.copyOut(xc->mem); + return 0; + } + + default: + cerr << "osf_getsysinfo: unknown op " << op << endl; + abort(); + break; + } + + return 1; +} + +/// Target osf_setsysinfo() handler. +static SyscallReturn +osf_setsysinfoFunc(SyscallDesc *desc, int callnum, Process *process, + ExecContext *xc) +{ + unsigned op = xc->getSyscallArg(0); + // unsigned nbytes = xc->getSyscallArg(2); + + switch (op) { + + case 14: { // SSI_IEEE_FP_CONTROL + TypedBufferArg<uint64_t> fpcr(xc->getSyscallArg(1)); + // I don't think this exactly matches the HW FPCR + fpcr.copyIn(xc->mem); + DPRINTFR(SyscallVerbose, "osf_setsysinfo(SSI_IEEE_FP_CONTROL): " + " setting FPCR to 0x%x\n", gtoh(*(uint64_t*)fpcr)); + return 0; + } + + default: + cerr << "osf_setsysinfo: unknown op " << op << endl; + abort(); + break; + } + + return 1; +} + + +SyscallDesc MipsLinuxProcess::syscallDescs[] = { + /* 0 */ SyscallDesc("osf_syscall", unimplementedFunc), + /* 1 */ SyscallDesc("exit", exitFunc), + /* 2 */ SyscallDesc("fork", unimplementedFunc), + /* 3 */ SyscallDesc("read", readFunc), + /* 4 */ SyscallDesc("write", writeFunc), + /* 5 */ SyscallDesc("osf_old_open", unimplementedFunc), + /* 6 */ SyscallDesc("close", closeFunc), + /* 7 */ SyscallDesc("osf_wait4", unimplementedFunc), + /* 8 */ SyscallDesc("osf_old_creat", unimplementedFunc), + /* 9 */ SyscallDesc("link", unimplementedFunc), + /* 10 */ SyscallDesc("unlink", unlinkFunc), + /* 11 */ SyscallDesc("osf_execve", unimplementedFunc), + /* 12 */ SyscallDesc("chdir", unimplementedFunc), + /* 13 */ SyscallDesc("fchdir", unimplementedFunc), + /* 14 */ SyscallDesc("mknod", unimplementedFunc), + /* 15 */ SyscallDesc("chmod", chmodFunc<Linux>), + /* 16 */ SyscallDesc("chown", chownFunc), + /* 17 */ SyscallDesc("brk", obreakFunc), + /* 18 */ SyscallDesc("osf_getfsstat", unimplementedFunc), + /* 19 */ SyscallDesc("lseek", lseekFunc), + /* 20 */ SyscallDesc("getxpid", getpidFunc), + /* 21 */ SyscallDesc("osf_mount", unimplementedFunc), + /* 22 */ SyscallDesc("umount", unimplementedFunc), + /* 23 */ SyscallDesc("setuid", setuidFunc), + /* 24 */ SyscallDesc("getxuid", getuidFunc), + /* 25 */ SyscallDesc("exec_with_loader", unimplementedFunc), + /* 26 */ SyscallDesc("osf_ptrace", unimplementedFunc), + /* 27 */ SyscallDesc("osf_nrecvmsg", unimplementedFunc), + /* 28 */ SyscallDesc("osf_nsendmsg", unimplementedFunc), + /* 29 */ SyscallDesc("osf_nrecvfrom", unimplementedFunc), + /* 30 */ SyscallDesc("osf_naccept", unimplementedFunc), + /* 31 */ SyscallDesc("osf_ngetpeername", unimplementedFunc), + /* 32 */ SyscallDesc("osf_ngetsockname", unimplementedFunc), + /* 33 */ SyscallDesc("access", unimplementedFunc), + /* 34 */ SyscallDesc("osf_chflags", unimplementedFunc), + /* 35 */ SyscallDesc("osf_fchflags", unimplementedFunc), + /* 36 */ SyscallDesc("sync", unimplementedFunc), + /* 37 */ SyscallDesc("kill", unimplementedFunc), + /* 38 */ SyscallDesc("osf_old_stat", unimplementedFunc), + /* 39 */ SyscallDesc("setpgid", unimplementedFunc), + /* 40 */ SyscallDesc("osf_old_lstat", unimplementedFunc), + /* 41 */ SyscallDesc("dup", unimplementedFunc), + /* 42 */ SyscallDesc("pipe", unimplementedFunc), + /* 43 */ SyscallDesc("osf_set_program_attributes", unimplementedFunc), + /* 44 */ SyscallDesc("osf_profil", unimplementedFunc), + /* 45 */ SyscallDesc("open", openFunc<Linux>), + /* 46 */ SyscallDesc("osf_old_sigaction", unimplementedFunc), + /* 47 */ SyscallDesc("getxgid", getgidFunc), + /* 48 */ SyscallDesc("osf_sigprocmask", ignoreFunc), + /* 49 */ SyscallDesc("osf_getlogin", unimplementedFunc), + /* 50 */ SyscallDesc("osf_setlogin", unimplementedFunc), + /* 51 */ SyscallDesc("acct", unimplementedFunc), + /* 52 */ SyscallDesc("sigpending", unimplementedFunc), + /* 53 */ SyscallDesc("osf_classcntl", unimplementedFunc), + /* 54 */ SyscallDesc("ioctl", ioctlFunc<Linux>), + /* 55 */ SyscallDesc("osf_reboot", unimplementedFunc), + /* 56 */ SyscallDesc("osf_revoke", unimplementedFunc), + /* 57 */ SyscallDesc("symlink", unimplementedFunc), + /* 58 */ SyscallDesc("readlink", unimplementedFunc), + /* 59 */ SyscallDesc("execve", unimplementedFunc), + /* 60 */ SyscallDesc("umask", unimplementedFunc), + /* 61 */ SyscallDesc("chroot", unimplementedFunc), + /* 62 */ SyscallDesc("osf_old_fstat", unimplementedFunc), + /* 63 */ SyscallDesc("getpgrp", unimplementedFunc), + /* 64 */ SyscallDesc("getpagesize", getpagesizeFunc), + /* 65 */ SyscallDesc("osf_mremap", unimplementedFunc), + /* 66 */ SyscallDesc("vfork", unimplementedFunc), + /* 67 */ SyscallDesc("stat", statFunc<Linux>), + /* 68 */ SyscallDesc("lstat", lstatFunc<Linux>), + /* 69 */ SyscallDesc("osf_sbrk", unimplementedFunc), + /* 70 */ SyscallDesc("osf_sstk", unimplementedFunc), + /* 71 */ SyscallDesc("mmap", mmapFunc<Linux>), + /* 72 */ SyscallDesc("osf_old_vadvise", unimplementedFunc), + /* 73 */ SyscallDesc("munmap", munmapFunc), + /* 74 */ SyscallDesc("mprotect", ignoreFunc), + /* 75 */ SyscallDesc("madvise", unimplementedFunc), + /* 76 */ SyscallDesc("vhangup", unimplementedFunc), + /* 77 */ SyscallDesc("osf_kmodcall", unimplementedFunc), + /* 78 */ SyscallDesc("osf_mincore", unimplementedFunc), + /* 79 */ SyscallDesc("getgroups", unimplementedFunc), + /* 80 */ SyscallDesc("setgroups", unimplementedFunc), + /* 81 */ SyscallDesc("osf_old_getpgrp", unimplementedFunc), + /* 82 */ SyscallDesc("setpgrp", unimplementedFunc), + /* 83 */ SyscallDesc("osf_setitimer", unimplementedFunc), + /* 84 */ SyscallDesc("osf_old_wait", unimplementedFunc), + /* 85 */ SyscallDesc("osf_table", unimplementedFunc), + /* 86 */ SyscallDesc("osf_getitimer", unimplementedFunc), + /* 87 */ SyscallDesc("gethostname", gethostnameFunc), + /* 88 */ SyscallDesc("sethostname", unimplementedFunc), + /* 89 */ SyscallDesc("getdtablesize", unimplementedFunc), + /* 90 */ SyscallDesc("dup2", unimplementedFunc), + /* 91 */ SyscallDesc("fstat", fstatFunc<Linux>), + /* 92 */ SyscallDesc("fcntl", fcntlFunc), + /* 93 */ SyscallDesc("osf_select", unimplementedFunc), + /* 94 */ SyscallDesc("poll", unimplementedFunc), + /* 95 */ SyscallDesc("fsync", unimplementedFunc), + /* 96 */ SyscallDesc("setpriority", unimplementedFunc), + /* 97 */ SyscallDesc("socket", unimplementedFunc), + /* 98 */ SyscallDesc("connect", unimplementedFunc), + /* 99 */ SyscallDesc("accept", unimplementedFunc), + /* 100 */ SyscallDesc("getpriority", unimplementedFunc), + /* 101 */ SyscallDesc("send", unimplementedFunc), + /* 102 */ SyscallDesc("recv", unimplementedFunc), + /* 103 */ SyscallDesc("sigreturn", unimplementedFunc), + /* 104 */ SyscallDesc("bind", unimplementedFunc), + /* 105 */ SyscallDesc("setsockopt", unimplementedFunc), + /* 106 */ SyscallDesc("listen", unimplementedFunc), + /* 107 */ SyscallDesc("osf_plock", unimplementedFunc), + /* 108 */ SyscallDesc("osf_old_sigvec", unimplementedFunc), + /* 109 */ SyscallDesc("osf_old_sigblock", unimplementedFunc), + /* 110 */ SyscallDesc("osf_old_sigsetmask", unimplementedFunc), + /* 111 */ SyscallDesc("sigsuspend", unimplementedFunc), + /* 112 */ SyscallDesc("osf_sigstack", ignoreFunc), + /* 113 */ SyscallDesc("recvmsg", unimplementedFunc), + /* 114 */ SyscallDesc("sendmsg", unimplementedFunc), + /* 115 */ SyscallDesc("osf_old_vtrace", unimplementedFunc), + /* 116 */ SyscallDesc("osf_gettimeofday", unimplementedFunc), + /* 117 */ SyscallDesc("osf_getrusage", unimplementedFunc), + /* 118 */ SyscallDesc("getsockopt", unimplementedFunc), + /* 119 */ SyscallDesc("numa_syscalls", unimplementedFunc), + /* 120 */ SyscallDesc("readv", unimplementedFunc), + /* 121 */ SyscallDesc("writev", writevFunc<Linux>), + /* 122 */ SyscallDesc("osf_settimeofday", unimplementedFunc), + /* 123 */ SyscallDesc("fchown", fchownFunc), + /* 124 */ SyscallDesc("fchmod", fchmodFunc<Linux>), + /* 125 */ SyscallDesc("recvfrom", unimplementedFunc), + /* 126 */ SyscallDesc("setreuid", unimplementedFunc), + /* 127 */ SyscallDesc("setregid", unimplementedFunc), + /* 128 */ SyscallDesc("rename", renameFunc), + /* 129 */ SyscallDesc("truncate", unimplementedFunc), + /* 130 */ SyscallDesc("ftruncate", unimplementedFunc), + /* 131 */ SyscallDesc("flock", unimplementedFunc), + /* 132 */ SyscallDesc("setgid", unimplementedFunc), + /* 133 */ SyscallDesc("sendto", unimplementedFunc), + /* 134 */ SyscallDesc("shutdown", unimplementedFunc), + /* 135 */ SyscallDesc("socketpair", unimplementedFunc), + /* 136 */ SyscallDesc("mkdir", unimplementedFunc), + /* 137 */ SyscallDesc("rmdir", unimplementedFunc), + /* 138 */ SyscallDesc("osf_utimes", unimplementedFunc), + /* 139 */ SyscallDesc("osf_old_sigreturn", unimplementedFunc), + /* 140 */ SyscallDesc("osf_adjtime", unimplementedFunc), + /* 141 */ SyscallDesc("getpeername", unimplementedFunc), + /* 142 */ SyscallDesc("osf_gethostid", unimplementedFunc), + /* 143 */ SyscallDesc("osf_sethostid", unimplementedFunc), + /* 144 */ SyscallDesc("getrlimit", getrlimitFunc<Linux>), + /* 145 */ SyscallDesc("setrlimit", ignoreFunc), + /* 146 */ SyscallDesc("osf_old_killpg", unimplementedFunc), + /* 147 */ SyscallDesc("setsid", unimplementedFunc), + /* 148 */ SyscallDesc("quotactl", unimplementedFunc), + /* 149 */ SyscallDesc("osf_oldquota", unimplementedFunc), + /* 150 */ SyscallDesc("getsockname", unimplementedFunc), + /* 151 */ SyscallDesc("osf_pread", unimplementedFunc), + /* 152 */ SyscallDesc("osf_pwrite", unimplementedFunc), + /* 153 */ SyscallDesc("osf_pid_block", unimplementedFunc), + /* 154 */ SyscallDesc("osf_pid_unblock", unimplementedFunc), + /* 155 */ SyscallDesc("osf_signal_urti", unimplementedFunc), + /* 156 */ SyscallDesc("sigaction", ignoreFunc), + /* 157 */ SyscallDesc("osf_sigwaitprim", unimplementedFunc), + /* 158 */ SyscallDesc("osf_nfssvc", unimplementedFunc), + /* 159 */ SyscallDesc("osf_getdirentries", unimplementedFunc), + /* 160 */ SyscallDesc("osf_statfs", unimplementedFunc), + /* 161 */ SyscallDesc("osf_fstatfs", unimplementedFunc), + /* 162 */ SyscallDesc("unknown #162", unimplementedFunc), + /* 163 */ SyscallDesc("osf_async_daemon", unimplementedFunc), + /* 164 */ SyscallDesc("osf_getfh", unimplementedFunc), + /* 165 */ SyscallDesc("osf_getdomainname", unimplementedFunc), + /* 166 */ SyscallDesc("setdomainname", unimplementedFunc), + /* 167 */ SyscallDesc("unknown #167", unimplementedFunc), + /* 168 */ SyscallDesc("unknown #168", unimplementedFunc), + /* 169 */ SyscallDesc("osf_exportfs", unimplementedFunc), + /* 170 */ SyscallDesc("unknown #170", unimplementedFunc), + /* 171 */ SyscallDesc("unknown #171", unimplementedFunc), + /* 172 */ SyscallDesc("unknown #172", unimplementedFunc), + /* 173 */ SyscallDesc("unknown #173", unimplementedFunc), + /* 174 */ SyscallDesc("unknown #174", unimplementedFunc), + /* 175 */ SyscallDesc("unknown #175", unimplementedFunc), + /* 176 */ SyscallDesc("unknown #176", unimplementedFunc), + /* 177 */ SyscallDesc("unknown #177", unimplementedFunc), + /* 178 */ SyscallDesc("unknown #178", unimplementedFunc), + /* 179 */ SyscallDesc("unknown #179", unimplementedFunc), + /* 180 */ SyscallDesc("unknown #180", unimplementedFunc), + /* 181 */ SyscallDesc("osf_alt_plock", unimplementedFunc), + /* 182 */ SyscallDesc("unknown #182", unimplementedFunc), + /* 183 */ SyscallDesc("unknown #183", unimplementedFunc), + /* 184 */ SyscallDesc("osf_getmnt", unimplementedFunc), + /* 185 */ SyscallDesc("unknown #185", unimplementedFunc), + /* 186 */ SyscallDesc("unknown #186", unimplementedFunc), + /* 187 */ SyscallDesc("osf_alt_sigpending", unimplementedFunc), + /* 188 */ SyscallDesc("osf_alt_setsid", unimplementedFunc), + /* 189 */ SyscallDesc("unknown #189", unimplementedFunc), + /* 190 */ SyscallDesc("unknown #190", unimplementedFunc), + /* 191 */ SyscallDesc("unknown #191", unimplementedFunc), + /* 192 */ SyscallDesc("unknown #192", unimplementedFunc), + /* 193 */ SyscallDesc("unknown #193", unimplementedFunc), + /* 194 */ SyscallDesc("unknown #194", unimplementedFunc), + /* 195 */ SyscallDesc("unknown #195", unimplementedFunc), + /* 196 */ SyscallDesc("unknown #196", unimplementedFunc), + /* 197 */ SyscallDesc("unknown #197", unimplementedFunc), + /* 198 */ SyscallDesc("unknown #198", unimplementedFunc), + /* 199 */ SyscallDesc("osf_swapon", unimplementedFunc), + /* 200 */ SyscallDesc("msgctl", unimplementedFunc), + /* 201 */ SyscallDesc("msgget", unimplementedFunc), + /* 202 */ SyscallDesc("msgrcv", unimplementedFunc), + /* 203 */ SyscallDesc("msgsnd", unimplementedFunc), + /* 204 */ SyscallDesc("semctl", unimplementedFunc), + /* 205 */ SyscallDesc("semget", unimplementedFunc), + /* 206 */ SyscallDesc("semop", unimplementedFunc), + /* 207 */ SyscallDesc("osf_utsname", unimplementedFunc), + /* 208 */ SyscallDesc("lchown", unimplementedFunc), + /* 209 */ SyscallDesc("osf_shmat", unimplementedFunc), + /* 210 */ SyscallDesc("shmctl", unimplementedFunc), + /* 211 */ SyscallDesc("shmdt", unimplementedFunc), + /* 212 */ SyscallDesc("shmget", unimplementedFunc), + /* 213 */ SyscallDesc("osf_mvalid", unimplementedFunc), + /* 214 */ SyscallDesc("osf_getaddressconf", unimplementedFunc), + /* 215 */ SyscallDesc("osf_msleep", unimplementedFunc), + /* 216 */ SyscallDesc("osf_mwakeup", unimplementedFunc), + /* 217 */ SyscallDesc("msync", unimplementedFunc), + /* 218 */ SyscallDesc("osf_signal", unimplementedFunc), + /* 219 */ SyscallDesc("osf_utc_gettime", unimplementedFunc), + /* 220 */ SyscallDesc("osf_utc_adjtime", unimplementedFunc), + /* 221 */ SyscallDesc("unknown #221", unimplementedFunc), + /* 222 */ SyscallDesc("osf_security", unimplementedFunc), + /* 223 */ SyscallDesc("osf_kloadcall", unimplementedFunc), + /* 224 */ SyscallDesc("unknown #224", unimplementedFunc), + /* 225 */ SyscallDesc("unknown #225", unimplementedFunc), + /* 226 */ SyscallDesc("unknown #226", unimplementedFunc), + /* 227 */ SyscallDesc("unknown #227", unimplementedFunc), + /* 228 */ SyscallDesc("unknown #228", unimplementedFunc), + /* 229 */ SyscallDesc("unknown #229", unimplementedFunc), + /* 230 */ SyscallDesc("unknown #230", unimplementedFunc), + /* 231 */ SyscallDesc("unknown #231", unimplementedFunc), + /* 232 */ SyscallDesc("unknown #232", unimplementedFunc), + /* 233 */ SyscallDesc("getpgid", unimplementedFunc), + /* 234 */ SyscallDesc("getsid", unimplementedFunc), + /* 235 */ SyscallDesc("sigaltstack", ignoreFunc), + /* 236 */ SyscallDesc("osf_waitid", unimplementedFunc), + /* 237 */ SyscallDesc("osf_priocntlset", unimplementedFunc), + /* 238 */ SyscallDesc("osf_sigsendset", unimplementedFunc), + /* 239 */ SyscallDesc("osf_set_speculative", unimplementedFunc), + /* 240 */ SyscallDesc("osf_msfs_syscall", unimplementedFunc), + /* 241 */ SyscallDesc("osf_sysinfo", unimplementedFunc), + /* 242 */ SyscallDesc("osf_uadmin", unimplementedFunc), + /* 243 */ SyscallDesc("osf_fuser", unimplementedFunc), + /* 244 */ SyscallDesc("osf_proplist_syscall", unimplementedFunc), + /* 245 */ SyscallDesc("osf_ntp_adjtime", unimplementedFunc), + /* 246 */ SyscallDesc("osf_ntp_gettime", unimplementedFunc), + /* 247 */ SyscallDesc("osf_pathconf", unimplementedFunc), + /* 248 */ SyscallDesc("osf_fpathconf", unimplementedFunc), + /* 249 */ SyscallDesc("unknown #249", unimplementedFunc), + /* 250 */ SyscallDesc("osf_uswitch", unimplementedFunc), + /* 251 */ SyscallDesc("osf_usleep_thread", unimplementedFunc), + /* 252 */ SyscallDesc("osf_audcntl", unimplementedFunc), + /* 253 */ SyscallDesc("osf_audgen", unimplementedFunc), + /* 254 */ SyscallDesc("sysfs", unimplementedFunc), + /* 255 */ SyscallDesc("osf_subsys_info", unimplementedFunc), + /* 256 */ SyscallDesc("osf_getsysinfo", osf_getsysinfoFunc), + /* 257 */ SyscallDesc("osf_setsysinfo", osf_setsysinfoFunc), + /* 258 */ SyscallDesc("osf_afs_syscall", unimplementedFunc), + /* 259 */ SyscallDesc("osf_swapctl", unimplementedFunc), + /* 260 */ SyscallDesc("osf_memcntl", unimplementedFunc), + /* 261 */ SyscallDesc("osf_fdatasync", unimplementedFunc), + /* 262 */ SyscallDesc("unknown #262", unimplementedFunc), + /* 263 */ SyscallDesc("unknown #263", unimplementedFunc), + /* 264 */ SyscallDesc("unknown #264", unimplementedFunc), + /* 265 */ SyscallDesc("unknown #265", unimplementedFunc), + /* 266 */ SyscallDesc("unknown #266", unimplementedFunc), + /* 267 */ SyscallDesc("unknown #267", unimplementedFunc), + /* 268 */ SyscallDesc("unknown #268", unimplementedFunc), + /* 269 */ SyscallDesc("unknown #269", unimplementedFunc), + /* 270 */ SyscallDesc("unknown #270", unimplementedFunc), + /* 271 */ SyscallDesc("unknown #271", unimplementedFunc), + /* 272 */ SyscallDesc("unknown #272", unimplementedFunc), + /* 273 */ SyscallDesc("unknown #273", unimplementedFunc), + /* 274 */ SyscallDesc("unknown #274", unimplementedFunc), + /* 275 */ SyscallDesc("unknown #275", unimplementedFunc), + /* 276 */ SyscallDesc("unknown #276", unimplementedFunc), + /* 277 */ SyscallDesc("unknown #277", unimplementedFunc), + /* 278 */ SyscallDesc("unknown #278", unimplementedFunc), + /* 279 */ SyscallDesc("unknown #279", unimplementedFunc), + /* 280 */ SyscallDesc("unknown #280", unimplementedFunc), + /* 281 */ SyscallDesc("unknown #281", unimplementedFunc), + /* 282 */ SyscallDesc("unknown #282", unimplementedFunc), + /* 283 */ SyscallDesc("unknown #283", unimplementedFunc), + /* 284 */ SyscallDesc("unknown #284", unimplementedFunc), + /* 285 */ SyscallDesc("unknown #285", unimplementedFunc), + /* 286 */ SyscallDesc("unknown #286", unimplementedFunc), + /* 287 */ SyscallDesc("unknown #287", unimplementedFunc), + /* 288 */ SyscallDesc("unknown #288", unimplementedFunc), + /* 289 */ SyscallDesc("unknown #289", unimplementedFunc), + /* 290 */ SyscallDesc("unknown #290", unimplementedFunc), + /* 291 */ SyscallDesc("unknown #291", unimplementedFunc), + /* 292 */ SyscallDesc("unknown #292", unimplementedFunc), + /* 293 */ SyscallDesc("unknown #293", unimplementedFunc), + /* 294 */ SyscallDesc("unknown #294", unimplementedFunc), + /* 295 */ SyscallDesc("unknown #295", unimplementedFunc), + /* 296 */ SyscallDesc("unknown #296", unimplementedFunc), + /* 297 */ SyscallDesc("unknown #297", unimplementedFunc), + /* 298 */ SyscallDesc("unknown #298", unimplementedFunc), + /* 299 */ SyscallDesc("unknown #299", unimplementedFunc), +/* + * Linux-specific system calls begin at 300 + */ + /* 300 */ SyscallDesc("bdflush", unimplementedFunc), + /* 301 */ SyscallDesc("sethae", unimplementedFunc), + /* 302 */ SyscallDesc("mount", unimplementedFunc), + /* 303 */ SyscallDesc("old_adjtimex", unimplementedFunc), + /* 304 */ SyscallDesc("swapoff", unimplementedFunc), + /* 305 */ SyscallDesc("getdents", unimplementedFunc), + /* 306 */ SyscallDesc("create_module", unimplementedFunc), + /* 307 */ SyscallDesc("init_module", unimplementedFunc), + /* 308 */ SyscallDesc("delete_module", unimplementedFunc), + /* 309 */ SyscallDesc("get_kernel_syms", unimplementedFunc), + /* 310 */ SyscallDesc("syslog", unimplementedFunc), + /* 311 */ SyscallDesc("reboot", unimplementedFunc), + /* 312 */ SyscallDesc("clone", unimplementedFunc), + /* 313 */ SyscallDesc("uselib", unimplementedFunc), + /* 314 */ SyscallDesc("mlock", unimplementedFunc), + /* 315 */ SyscallDesc("munlock", unimplementedFunc), + /* 316 */ SyscallDesc("mlockall", unimplementedFunc), + /* 317 */ SyscallDesc("munlockall", unimplementedFunc), + /* 318 */ SyscallDesc("sysinfo", unimplementedFunc), + /* 319 */ SyscallDesc("_sysctl", unimplementedFunc), + /* 320 */ SyscallDesc("was sys_idle", unimplementedFunc), + /* 321 */ SyscallDesc("oldumount", unimplementedFunc), + /* 322 */ SyscallDesc("swapon", unimplementedFunc), + /* 323 */ SyscallDesc("times", ignoreFunc), + /* 324 */ SyscallDesc("personality", unimplementedFunc), + /* 325 */ SyscallDesc("setfsuid", unimplementedFunc), + /* 326 */ SyscallDesc("setfsgid", unimplementedFunc), + /* 327 */ SyscallDesc("ustat", unimplementedFunc), + /* 328 */ SyscallDesc("statfs", unimplementedFunc), + /* 329 */ SyscallDesc("fstatfs", unimplementedFunc), + /* 330 */ SyscallDesc("sched_setparam", unimplementedFunc), + /* 331 */ SyscallDesc("sched_getparam", unimplementedFunc), + /* 332 */ SyscallDesc("sched_setscheduler", unimplementedFunc), + /* 333 */ SyscallDesc("sched_getscheduler", unimplementedFunc), + /* 334 */ SyscallDesc("sched_yield", unimplementedFunc), + /* 335 */ SyscallDesc("sched_get_priority_max", unimplementedFunc), + /* 336 */ SyscallDesc("sched_get_priority_min", unimplementedFunc), + /* 337 */ SyscallDesc("sched_rr_get_interval", unimplementedFunc), + /* 338 */ SyscallDesc("afs_syscall", unimplementedFunc), + /* 339 */ SyscallDesc("uname", unameFunc), + /* 340 */ SyscallDesc("nanosleep", unimplementedFunc), + /* 341 */ SyscallDesc("mremap", unimplementedFunc), + /* 342 */ SyscallDesc("nfsservctl", unimplementedFunc), + /* 343 */ SyscallDesc("setresuid", unimplementedFunc), + /* 344 */ SyscallDesc("getresuid", unimplementedFunc), + /* 345 */ SyscallDesc("pciconfig_read", unimplementedFunc), + /* 346 */ SyscallDesc("pciconfig_write", unimplementedFunc), + /* 347 */ SyscallDesc("query_module", unimplementedFunc), + /* 348 */ SyscallDesc("prctl", unimplementedFunc), + /* 349 */ SyscallDesc("pread", unimplementedFunc), + /* 350 */ SyscallDesc("pwrite", unimplementedFunc), + /* 351 */ SyscallDesc("rt_sigreturn", unimplementedFunc), + /* 352 */ SyscallDesc("rt_sigaction", ignoreFunc), + /* 353 */ SyscallDesc("rt_sigprocmask", unimplementedFunc), + /* 354 */ SyscallDesc("rt_sigpending", unimplementedFunc), + /* 355 */ SyscallDesc("rt_sigtimedwait", unimplementedFunc), + /* 356 */ SyscallDesc("rt_sigqueueinfo", unimplementedFunc), + /* 357 */ SyscallDesc("rt_sigsuspend", unimplementedFunc), + /* 358 */ SyscallDesc("select", unimplementedFunc), + /* 359 */ SyscallDesc("gettimeofday", gettimeofdayFunc<Linux>), + /* 360 */ SyscallDesc("settimeofday", unimplementedFunc), + /* 361 */ SyscallDesc("getitimer", unimplementedFunc), + /* 362 */ SyscallDesc("setitimer", unimplementedFunc), + /* 363 */ SyscallDesc("utimes", utimesFunc<Linux>), + /* 364 */ SyscallDesc("getrusage", getrusageFunc<Linux>), + /* 365 */ SyscallDesc("wait4", unimplementedFunc), + /* 366 */ SyscallDesc("adjtimex", unimplementedFunc), + /* 367 */ SyscallDesc("getcwd", unimplementedFunc), + /* 368 */ SyscallDesc("capget", unimplementedFunc), + /* 369 */ SyscallDesc("capset", unimplementedFunc), + /* 370 */ SyscallDesc("sendfile", unimplementedFunc), + /* 371 */ SyscallDesc("setresgid", unimplementedFunc), + /* 372 */ SyscallDesc("getresgid", unimplementedFunc), + /* 373 */ SyscallDesc("dipc", unimplementedFunc), + /* 374 */ SyscallDesc("pivot_root", unimplementedFunc), + /* 375 */ SyscallDesc("mincore", unimplementedFunc), + /* 376 */ SyscallDesc("pciconfig_iobase", unimplementedFunc), + /* 377 */ SyscallDesc("getdents64", unimplementedFunc), + /* 378 */ SyscallDesc("gettid", unimplementedFunc), + /* 379 */ SyscallDesc("readahead", unimplementedFunc), + /* 380 */ SyscallDesc("security", unimplementedFunc), + /* 381 */ SyscallDesc("tkill", unimplementedFunc), + /* 382 */ SyscallDesc("setxattr", unimplementedFunc), + /* 383 */ SyscallDesc("lsetxattr", unimplementedFunc), + /* 384 */ SyscallDesc("fsetxattr", unimplementedFunc), + /* 385 */ SyscallDesc("getxattr", unimplementedFunc), + /* 386 */ SyscallDesc("lgetxattr", unimplementedFunc), + /* 387 */ SyscallDesc("fgetxattr", unimplementedFunc), + /* 388 */ SyscallDesc("listxattr", unimplementedFunc), + /* 389 */ SyscallDesc("llistxattr", unimplementedFunc), + /* 390 */ SyscallDesc("flistxattr", unimplementedFunc), + /* 391 */ SyscallDesc("removexattr", unimplementedFunc), + /* 392 */ SyscallDesc("lremovexattr", unimplementedFunc), + /* 393 */ SyscallDesc("fremovexattr", unimplementedFunc), + /* 394 */ SyscallDesc("futex", unimplementedFunc), + /* 395 */ SyscallDesc("sched_setaffinity", unimplementedFunc), + /* 396 */ SyscallDesc("sched_getaffinity", unimplementedFunc), + /* 397 */ SyscallDesc("tuxcall", unimplementedFunc), + /* 398 */ SyscallDesc("io_setup", unimplementedFunc), + /* 399 */ SyscallDesc("io_destroy", unimplementedFunc), + /* 400 */ SyscallDesc("io_getevents", unimplementedFunc), + /* 401 */ SyscallDesc("io_submit", unimplementedFunc), + /* 402 */ SyscallDesc("io_cancel", unimplementedFunc), + /* 403 */ SyscallDesc("unknown #403", unimplementedFunc), + /* 404 */ SyscallDesc("unknown #404", unimplementedFunc), + /* 405 */ SyscallDesc("exit_group", exitFunc), // exit all threads... + /* 406 */ SyscallDesc("lookup_dcookie", unimplementedFunc), + /* 407 */ SyscallDesc("sys_epoll_create", unimplementedFunc), + /* 408 */ SyscallDesc("sys_epoll_ctl", unimplementedFunc), + /* 409 */ SyscallDesc("sys_epoll_wait", unimplementedFunc), + /* 410 */ SyscallDesc("remap_file_pages", unimplementedFunc), + /* 411 */ SyscallDesc("set_tid_address", unimplementedFunc), + /* 412 */ SyscallDesc("restart_syscall", unimplementedFunc), + /* 413 */ SyscallDesc("fadvise64", unimplementedFunc), + /* 414 */ SyscallDesc("timer_create", unimplementedFunc), + /* 415 */ SyscallDesc("timer_settime", unimplementedFunc), + /* 416 */ SyscallDesc("timer_gettime", unimplementedFunc), + /* 417 */ SyscallDesc("timer_getoverrun", unimplementedFunc), + /* 418 */ SyscallDesc("timer_delete", unimplementedFunc), + /* 419 */ SyscallDesc("clock_settime", unimplementedFunc), + /* 420 */ SyscallDesc("clock_gettime", unimplementedFunc), + /* 421 */ SyscallDesc("clock_getres", unimplementedFunc), + /* 422 */ SyscallDesc("clock_nanosleep", unimplementedFunc), + /* 423 */ SyscallDesc("semtimedop", unimplementedFunc), + /* 424 */ SyscallDesc("tgkill", unimplementedFunc), + /* 425 */ SyscallDesc("stat64", unimplementedFunc), + /* 426 */ SyscallDesc("lstat64", lstat64Func<Linux>), + /* 427 */ SyscallDesc("fstat64", fstat64Func<Linux>), + /* 428 */ SyscallDesc("vserver", unimplementedFunc), + /* 429 */ SyscallDesc("mbind", unimplementedFunc), + /* 430 */ SyscallDesc("get_mempolicy", unimplementedFunc), + /* 431 */ SyscallDesc("set_mempolicy", unimplementedFunc), + /* 432 */ SyscallDesc("mq_open", unimplementedFunc), + /* 433 */ SyscallDesc("mq_unlink", unimplementedFunc), + /* 434 */ SyscallDesc("mq_timedsend", unimplementedFunc), + /* 435 */ SyscallDesc("mq_timedreceive", unimplementedFunc), + /* 436 */ SyscallDesc("mq_notify", unimplementedFunc), + /* 437 */ SyscallDesc("mq_getsetattr", unimplementedFunc), + /* 438 */ SyscallDesc("waitid", unimplementedFunc), + /* 439 */ SyscallDesc("add_key", unimplementedFunc), + /* 440 */ SyscallDesc("request_key", unimplementedFunc), + /* 441 */ SyscallDesc("keyctl", unimplementedFunc) +}; + +MipsLinuxProcess::MipsLinuxProcess(const std::string &name, + ObjectFile *objFile, + int stdin_fd, + int stdout_fd, + int stderr_fd, + std::vector<std::string> &argv, + std::vector<std::string> &envp) + : LiveProcess(name, objFile, stdin_fd, stdout_fd, stderr_fd, argv, envp), + Num_Syscall_Descs(sizeof(syscallDescs) / sizeof(SyscallDesc)) +{ + init_regs->intRegFile[0] = 0; +} + + + +SyscallDesc* +MipsLinuxProcess::getDesc(int callnum) +{ + if (callnum < 0 || callnum > Num_Syscall_Descs) + return NULL; + return &syscallDescs[callnum]; +} diff --git a/arch/mips/linux_process.hh b/arch/mips/linux_process.hh new file mode 100644 index 000000000..5408a6c44 --- /dev/null +++ b/arch/mips/linux_process.hh @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2003-2004 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __MIPS_LINUX_PROCESS_HH__ +#define __MIPS_LINUX_PROCESS_HH__ + +#include "sim/process.hh" + + +/// A process with emulated Mips/Linux syscalls. +class MipsLinuxProcess : public LiveProcess +{ + public: + /// Constructor. + MipsLinuxProcess(const std::string &name, + ObjectFile *objFile, + int stdin_fd, int stdout_fd, int stderr_fd, + std::vector<std::string> &argv, + std::vector<std::string> &envp); + + virtual SyscallDesc* getDesc(int callnum); + + /// The target system's hostname. + static const char *hostname; + + /// Array of syscall descriptors, indexed by call number. + static SyscallDesc syscallDescs[]; + + const int Num_Syscall_Descs; +}; + + +#endif // __MIPS_LINUX_PROCESS_HH__ diff --git a/arch/mips/process.cc b/arch/mips/process.cc new file mode 100644 index 000000000..6de44fe9f --- /dev/null +++ b/arch/mips/process.cc @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2003-2004 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "arch/mips/process.hh" + +namespace MipsISA +{ + +LiveProcess * +createProcess(const string &nm, ObjectFile * objFile, + int stdin_fd, int stdout_fd, int stderr_fd, + vector<string> &argv, vector<string> &envp) +{ + LiveProcess * process = NULL; + if (objFile->getArch() != ObjectFile::MIPS) + fatal("Object file does not match architecture."); + switch (objFile->getOpSys()) { + case ObjectFile::Linux: + process = new MipsLinuxProcess(nm, objFile, + stdin_fd, stdout_fd, stderr_fd, + argv, envp); + break; + + default: + fatal("Unknown/unsupported operating system."); + } + return process; +} + +} // namespace MipsISA + diff --git a/arch/mips/process.hh b/arch/mips/process.hh new file mode 100644 index 000000000..ab4323107 --- /dev/null +++ b/arch/mips/process.hh @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2003-2004 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __MIPS_PROCESS_HH__ +#define __MIPS_PROCESS_HH__ + +#include "arch/mips/linux_process.hh" +#include "base/loader/object_file.hh" + +namespace MipsISA +{ + +LiveProcess * +createProcess(const string &nm, ObjectFile * objFile, + int stdin_fd, int stdout_fd, int stderr_fd, + vector<string> &argv, vector<string> &envp); + +} // namespace MipsISA + +#endif // __MIPS_PROCESS_HH__ diff --git a/arch/sparc/SConscript b/arch/sparc/SConscript index fea31fd5d..edff5821e 100644 --- a/arch/sparc/SConscript +++ b/arch/sparc/SConscript @@ -47,7 +47,7 @@ base_sources = Split(''' # Full-system sources full_system_sources = Split(''' - alpha_memory.cc + tlb.cc arguments.cc ev5.cc osfpal.cc @@ -57,9 +57,9 @@ full_system_sources = Split(''' # Syscall emulation (non-full-system) sources syscall_emulation_sources = Split(''' - alpha_common_syscall_emul.cc - alpha_linux_process.cc - alpha_tru64_process.cc + common_syscall_emul.cc + linux_process.cc + process.cc ''') sources = base_sources diff --git a/arch/sparc/linux_process.cc b/arch/sparc/linux_process.cc new file mode 100644 index 000000000..d1c439d72 --- /dev/null +++ b/arch/sparc/linux_process.cc @@ -0,0 +1,451 @@ +/* + * Copyright (c) 2003-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "arch/sparc/common_syscall_emul.hh" +#include "arch/sparc/linux_process.hh" +#include "arch/sparc/isa_traits.hh" + +#include "base/trace.hh" +#include "cpu/exec_context.hh" +#include "kern/linux/linux.hh" +#include "mem/functional/functional.hh" + +#include "sim/process.hh" +#include "sim/syscall_emul.hh" + +using namespace std; +using namespace SparcISA; + +/// Target pipe() handler. Even though this is a generic Posix call, +/// the Alpha return convention is funky, so that makes it +/// Alpha-specific. +SyscallReturn +pipeFunc(SyscallDesc *desc, int callnum, Process *process, + ExecContext *xc) +{ + int fds[2], sim_fds[2]; + int pipe_retval = pipe(fds); + + if (pipe_retval < 0) { + // error + return pipe_retval; + } + + sim_fds[0] = process->alloc_fd(fds[0]); + sim_fds[1] = process->alloc_fd(fds[1]); + + // Alpha Linux convention for pipe() is that fd[0] is returned as + // the return value of the function, and fd[1] is returned in r20. + xc->regs.intRegFile[20] = sim_fds[1]; + return sim_fds[0]; +} + + +/// Target uname() handler. +static SyscallReturn +unameFunc(SyscallDesc *desc, int callnum, Process *process, + ExecContext *xc) +{ + TypedBufferArg<Linux::utsname> name(xc->getSyscallArg(0)); + + strcpy(name->sysname, "Linux"); + strcpy(name->nodename, "m5.eecs.umich.edu"); + strcpy(name->release, "2.4.20"); + strcpy(name->version, "#1 Mon Aug 18 11:32:15 EDT 2003"); + strcpy(name->machine, "alpha"); + + name.copyOut(xc->mem); + return 0; +} + +/// Target osf_getsysyinfo() handler. Even though this call is +/// borrowed from Tru64, the subcases that get used appear to be +/// different in practice from those used by Tru64 processes. +static SyscallReturn +osf_getsysinfoFunc(SyscallDesc *desc, int callnum, Process *process, + ExecContext *xc) +{ + unsigned op = xc->getSyscallArg(0); + // unsigned nbytes = xc->getSyscallArg(2); + + switch (op) { + + case 45: { // GSI_IEEE_FP_CONTROL + TypedBufferArg<uint64_t> fpcr(xc->getSyscallArg(1)); + // I don't think this exactly matches the HW FPCR + *fpcr = 0; + fpcr.copyOut(xc->mem); + return 0; + } + + default: + cerr << "osf_getsysinfo: unknown op " << op << endl; + abort(); + break; + } + + return 1; +} + +/// Target osf_setsysinfo() handler. +static SyscallReturn +osf_setsysinfoFunc(SyscallDesc *desc, int callnum, Process *process, + ExecContext *xc) +{ + unsigned op = xc->getSyscallArg(0); + // unsigned nbytes = xc->getSyscallArg(2); + + switch (op) { + + case 14: { // SSI_IEEE_FP_CONTROL + TypedBufferArg<uint64_t> fpcr(xc->getSyscallArg(1)); + // I don't think this exactly matches the HW FPCR + fpcr.copyIn(xc->mem); + DPRINTFR(SyscallVerbose, "osf_setsysinfo(SSI_IEEE_FP_CONTROL): " + " setting FPCR to 0x%x\n", gtoh(*(uint64_t*)fpcr)); + return 0; + } + + default: + cerr << "osf_setsysinfo: unknown op " << op << endl; + abort(); + break; + } + + return 1; +} + +SyscallDesc SparcLinuxProcess::syscallDescs[] = { + /* 0 */ SyscallDesc("restart_syscall", unimplimentedFunc); + /* 1 */ SyscallDesc("exit", unimplimentedFunc); + /* 2 */ SyscallDesc("fork", unimplimentedFunc); + /* 3 */ SyscallDesc("read", unimplimentedFunc); + /* 4 */ SyscallDesc("write", unimplimentedFunc); + /* 5 */ SyscallDesc("open", unimplimentedFunc); + /* 6 */ SyscallDesc("close", unimplimentedFunc); + /* 7 */ SyscallDesc("wait4", unimplimentedFunc); + /* 8 */ SyscallDesc("creat", unimplimentedFunc); + /* 9 */ SyscallDesc("link", unimplimentedFunc); + /* 10 */ SyscallDesc("unlink", unimplimentedFunc); + /* 11 */ SyscallDesc("execv", unimplimentedFunc); + /* 12 */ SyscallDesc("chdir", unimplimentedFunc); + /* 13 */ SyscallDesc("chown", unimplimentedFunc); + /* 14 */ SyscallDesc("mknod", unimplimentedFunc); + /* 15 */ SyscallDesc("chmod", unimplimentedFunc); + /* 16 */ SyscallDesc("lchown", unimplimentedFunc); + /* 17 */ SyscallDesc("brk", unimplimentedFunc); + /* 18 */ SyscallDesc("perfctr", unimplimentedFunc); + /* 19 */ SyscallDesc("lseek", unimplimentedFunc); + /* 20 */ SyscallDesc("getpid", unimplimentedFunc); + /* 21 */ SyscallDesc("capget", unimplimentedFunc); + /* 22 */ SyscallDesc("capset", unimplimentedFunc); + /* 23 */ SyscallDesc("setuid", unimplimentedFunc); + /* 24 */ SyscallDesc("getuid", unimplimentedFunc); + /* 25 */ SyscallDesc("time", unimplimentedFunc); + /* 26 */ SyscallDesc("ptrace", unimplimentedFunc); + /* 27 */ SyscallDesc("alarm", unimplimentedFunc); + /* 28 */ SyscallDesc("sigaltstack", unimplimentedFunc); + /* 29 */ SyscallDesc("pause", unimplimentedFunc); + /* 30 */ SyscallDesc("utime", unimplimentedFunc); + /* 31 */ SyscallDesc("lchown32", unimplimentedFunc); + /* 32 */ SyscallDesc("fchown32", unimplimentedFunc); + /* 33 */ SyscallDesc("access", unimplimentedFunc); + /* 34 */ SyscallDesc("nice", unimplimentedFunc); + /* 35 */ SyscallDesc("chown32", unimplimentedFunc); + /* 36 */ SyscallDesc("sync", unimplimentedFunc); + /* 37 */ SyscallDesc("kill", unimplimentedFunc); + /* 38 */ SyscallDesc("stat", unimplimentedFunc); + /* 39 */ SyscallDesc("sendfile", unimplimentedFunc); + /* 40 */ SyscallDesc("lstat", unimplimentedFunc); + /* 41 */ SyscallDesc("dup", unimplimentedFunc); + /* 42 */ SyscallDesc("pipe", unimplimentedFunc); + /* 43 */ SyscallDesc("times", unimplimentedFunc); + /* 44 */ SyscallDesc("getuid32", unimplimentedFunc); + /* 45 */ SyscallDesc("umount2", unimplimentedFunc); + /* 46 */ SyscallDesc("setgid", unimplimentedFunc); + /* 47 */ SyscallDesc("getgid", unimplimentedFunc); + /* 48 */ SyscallDesc("signal", unimplimentedFunc); + /* 49 */ SyscallDesc("geteuid", unimplimentedFunc); + /* 50 */ SyscallDesc("getegid", unimplimentedFunc); + /* 51 */ SyscallDesc("acct", unimplimentedFunc); + /* 52 */ SyscallDesc("memory_ordering", unimplimentedFunc); + /* 53 */ SyscallDesc("getgid32", unimplimentedFunc); + /* 54 */ SyscallDesc("ioctl", unimplimentedFunc); + /* 55 */ SyscallDesc("reboot", unimplimentedFunc); + /* 56 */ SyscallDesc("mmap2", unimplimentedFunc); + /* 57 */ SyscallDesc("symlink", unimplimentedFunc); + /* 58 */ SyscallDesc("readlink", unimplimentedFunc); + /* 59 */ SyscallDesc("execve", unimplimentedFunc); + /* 60 */ SyscallDesc("umask", unimplimentedFunc); + /* 61 */ SyscallDesc("chroot", unimplimentedFunc); + /* 62 */ SyscallDesc("fstat", unimplimentedFunc); + /* 63 */ SyscallDesc("fstat64", unimplimentedFunc); + /* 64 */ SyscallDesc("getpagesize", unimplimentedFunc); + /* 65 */ SyscallDesc("msync", unimplimentedFunc); + /* 66 */ SyscallDesc("vfork", unimplimentedFunc); + /* 67 */ SyscallDesc("pread64", unimplimentedFunc); + /* 68 */ SyscallDesc("pwrite64", unimplimentedFunc); + /* 69 */ SyscallDesc("geteuid32", unimplimentedFunc); + /* 70 */ SyscallDesc("getdgid32", unimplimentedFunc); + /* 71 */ SyscallDesc("mmap", unimplimentedFunc); + /* 72 */ SyscallDesc("setreuid32", unimplimentedFunc); + /* 73 */ SyscallDesc("munmap", unimplimentedFunc); + /* 74 */ SyscallDesc("mprotect", unimplimentedFunc); + /* 75 */ SyscallDesc("madvise", unimplimentedFunc); + /* 76 */ SyscallDesc("vhangup", unimplimentedFunc); + /* 77 */ SyscallDesc("truncate64", unimplimentedFunc); + /* 78 */ SyscallDesc("mincore", unimplimentedFunc); + /* 79 */ SyscallDesc("getgroups", unimplimentedFunc); + /* 80 */ SyscallDesc("setgroups", unimplimentedFunc); + /* 81 */ SyscallDesc("getpgrp", unimplimentedFunc); + /* 82 */ SyscallDesc("setgroups32", unimplimentedFunc); + /* 83 */ SyscallDesc("setitimer", unimplimentedFunc); + /* 84 */ SyscallDesc("ftruncate64", unimplimentedFunc); + /* 85 */ SyscallDesc("swapon", unimplimentedFunc); + /* 86 */ SyscallDesc("getitimer", unimplimentedFunc); + /* 87 */ SyscallDesc("setuid32", unimplimentedFunc); + /* 88 */ SyscallDesc("sethostname", unimplimentedFunc); + /* 89 */ SyscallDesc("setgid32", unimplimentedFunc); + /* 90 */ SyscallDesc("dup2", unimplimentedFunc); + /* 91 */ SyscallDesc("setfsuid32", unimplimentedFunc); + /* 92 */ SyscallDesc("fcntl", unimplimentedFunc); + /* 93 */ SyscallDesc("select", unimplimentedFunc); + /* 94 */ SyscallDesc("setfsgid32", unimplimentedFunc); + /* 95 */ SyscallDesc("fsync", unimplimentedFunc); + /* 96 */ SyscallDesc("setpriority", unimplimentedFunc); + /* 97 */ SyscallDesc("socket", unimplimentedFunc); + /* 98 */ SyscallDesc("connect", unimplimentedFunc); + /* 99 */ SyscallDesc("accept", unimplimentedFunc); + /* 100 */ SyscallDesc("getpriority", unimplimentedFunc); + /* 101 */ SyscallDesc("rt_sigreturn", unimplimentedFunc); + /* 102 */ SyscallDesc("rt_sigaction", unimplimentedFunc); + /* 103 */ SyscallDesc("rt_sigprocmask", unimplimentedFunc); + /* 104 */ SyscallDesc("rt_sigpending", unimplimentedFunc); + /* 105 */ SyscallDesc("rt_sigtimedwait", unimplimentedFunc); + /* 106 */ SyscallDesc("rt_sigqueueinfo", unimplimentedFunc); + /* 107 */ SyscallDesc("rt_sigsuspend", unimplimentedFunc); + /* 108 */ SyscallDesc("setresuid", unimplimentedFunc); + /* 109 */ SyscallDesc("getresuid", unimplimentedFunc); + /* 110 */ SyscallDesc("setresgid", unimplimentedFunc); + /* 111 */ SyscallDesc("getresgid", unimplimentedFunc); + /* 112 */ SyscallDesc("setregid32", unimplimentedFunc); + /* 113 */ SyscallDesc("recvmsg", unimplimentedFunc); + /* 114 */ SyscallDesc("sendmsg", unimplimentedFunc); + /* 115 */ SyscallDesc("getgroups32", unimplimentedFunc); + /* 116 */ SyscallDesc("gettimeofday", unimplimentedFunc); + /* 117 */ SyscallDesc("getrusage", unimplimentedFunc); + /* 118 */ SyscallDesc("getsockopt", unimplimentedFunc); + /* 119 */ SyscallDesc("getcwd", unimplimentedFunc); + /* 120 */ SyscallDesc("readv", unimplimentedFunc); + /* 121 */ SyscallDesc("writev", unimplimentedFunc); + /* 122 */ SyscallDesc("settimeofday", unimplimentedFunc); + /* 123 */ SyscallDesc("fchown", unimplimentedFunc); + /* 124 */ SyscallDesc("fchmod", unimplimentedFunc); + /* 125 */ SyscallDesc("recvfrom", unimplimentedFunc); + /* 126 */ SyscallDesc("setreuid", unimplimentedFunc); + /* 127 */ SyscallDesc("setregid", unimplimentedFunc); + /* 128 */ SyscallDesc("rename", unimplimentedFunc); + /* 129 */ SyscallDesc("truncate", unimplimentedFunc); + /* 130 */ SyscallDesc("ftruncate", unimplimentedFunc); + /* 131 */ SyscallDesc("flock", unimplimentedFunc); + /* 132 */ SyscallDesc("lstat64", unimplimentedFunc); + /* 133 */ SyscallDesc("sendto", unimplimentedFunc); + /* 134 */ SyscallDesc("shutdown", unimplimentedFunc); + /* 135 */ SyscallDesc("socketpair", unimplimentedFunc); + /* 136 */ SyscallDesc("mkdir", unimplimentedFunc); + /* 137 */ SyscallDesc("rmdir", unimplimentedFunc); + /* 138 */ SyscallDesc("utimes", unimplimentedFunc); + /* 139 */ SyscallDesc("stat64", unimplimentedFunc); + /* 140 */ SyscallDesc("sendfile64", unimplimentedFunc); + /* 141 */ SyscallDesc("getpeername", unimplimentedFunc); + /* 142 */ SyscallDesc("futex", unimplimentedFunc); + /* 143 */ SyscallDesc("gettid", unimplimentedFunc); + /* 144 */ SyscallDesc("getrlimit", unimplimentedFunc); + /* 145 */ SyscallDesc("setrlimit", unimplimentedFunc); + /* 146 */ SyscallDesc("pivot_root", unimplimentedFunc); + /* 147 */ SyscallDesc("prctl", unimplimentedFunc); + /* 148 */ SyscallDesc("pciconfig_read", unimplimentedFunc); + /* 149 */ SyscallDesc("pciconfig_write", unimplimentedFunc); + /* 150 */ SyscallDesc("getsockname", unimplimentedFunc); + /* 151 */ SyscallDesc("inotify_init", unimplimentedFunc); + /* 152 */ SyscallDesc("inotify_add_watch", unimplimentedFunc); + /* 153 */ SyscallDesc("poll", unimplimentedFunc); + /* 154 */ SyscallDesc("getdents64", unimplimentedFunc); + /* 155 */ SyscallDesc("fcntl64", unimplimentedFunc); + /* 156 */ SyscallDesc("inotify_rm_watch", unimplimentedFunc); + /* 157 */ SyscallDesc("statfs", unimplimentedFunc); + /* 158 */ SyscallDesc("fstatfs", unimplimentedFunc); + /* 159 */ SyscallDesc("umount", unimplimentedFunc); + /* 160 */ SyscallDesc("sched_set_affinity", unimplimentedFunc); + /* 161 */ SyscallDesc("sched_get_affinity", unimplimentedFunc); + /* 162 */ SyscallDesc("getdomainname", unimplimentedFunc); + /* 163 */ SyscallDesc("setdomainname", unimplimentedFunc); + /* 164 */ SyscallDesc("utrap_install", unimplimentedFunc); + /* 165 */ SyscallDesc("quotactl", unimplimentedFunc); + /* 166 */ SyscallDesc("set_tid_address", unimplimentedFunc); + /* 167 */ SyscallDesc("mount", unimplimentedFunc); + /* 168 */ SyscallDesc("ustat", unimplimentedFunc); + /* 169 */ SyscallDesc("setxattr", unimplimentedFunc); + /* 170 */ SyscallDesc("lsetxattr", unimplimentedFunc); + /* 171 */ SyscallDesc("fsetxattr", unimplimentedFunc); + /* 172 */ SyscallDesc("getxattr", unimplimentedFunc); + /* 173 */ SyscallDesc("lgetxattr", unimplimentedFunc); + /* 174 */ SyscallDesc("getdents", unimplimentedFunc); + /* 175 */ SyscallDesc("setsid", unimplimentedFunc); + /* 176 */ SyscallDesc("fchdir", unimplimentedFunc); + /* 177 */ SyscallDesc("fgetxattr", unimplimentedFunc); + /* 178 */ SyscallDesc("listxattr", unimplimentedFunc); + /* 179 */ SyscallDesc("llistxattr", unimplimentedFunc); + /* 180 */ SyscallDesc("flistxattr", unimplimentedFunc); + /* 181 */ SyscallDesc("removexattr", unimplimentedFunc); + /* 182 */ SyscallDesc("lremovexattr", unimplimentedFunc); + /* 183 */ SyscallDesc("sigpending", unimplimentedFunc); + /* 184 */ SyscallDesc("query_module", unimplimentedFunc); + /* 185 */ SyscallDesc("setpgid", unimplimentedFunc); + /* 186 */ SyscallDesc("fremovexattr", unimplimentedFunc); + /* 187 */ SyscallDesc("tkill", unimplimentedFunc); + /* 188 */ SyscallDesc("exit_group", unimplimentedFunc); + /* 189 */ SyscallDesc("uname", unimplimentedFunc); + /* 190 */ SyscallDesc("init_module", unimplimentedFunc); + /* 191 */ SyscallDesc("personality", unimplimentedFunc); + /* 192 */ SyscallDesc("remap_file_pages", unimplimentedFunc); + /* 193 */ SyscallDesc("epoll_create", unimplimentedFunc); + /* 194 */ SyscallDesc("epoll_ctl", unimplimentedFunc); + /* 195 */ SyscallDesc("epoll_wait", unimplimentedFunc); + /* 196 */ SyscallDesc("ioprio_set", unimplimentedFunc); + /* 197 */ SyscallDesc("getppid", unimplimentedFunc); + /* 198 */ SyscallDesc("sigaction", unimplimentedFunc); + /* 199 */ SyscallDesc("sgetmask", unimplimentedFunc); + /* 200 */ SyscallDesc("ssetmask", unimplimentedFunc); + /* 201 */ SyscallDesc("sigsuspend", unimplimentedFunc); + /* 202 */ SyscallDesc("oldlstat", unimplimentedFunc); + /* 203 */ SyscallDesc("uselib", unimplimentedFunc); + /* 204 */ SyscallDesc("readdir", unimplimentedFunc); + /* 205 */ SyscallDesc("readahead", unimplimentedFunc); + /* 206 */ SyscallDesc("socketcall", unimplimentedFunc); + /* 207 */ SyscallDesc("syslog", unimplimentedFunc); + /* 208 */ SyscallDesc("lookup_dcookie", unimplimentedFunc); + /* 209 */ SyscallDesc("fadvise64", unimplimentedFunc); + /* 210 */ SyscallDesc("fadvise64_64", unimplimentedFunc); + /* 211 */ SyscallDesc("tgkill", unimplimentedFunc); + /* 212 */ SyscallDesc("waitpid", unimplimentedFunc); + /* 213 */ SyscallDesc("swapoff", unimplimentedFunc); + /* 214 */ SyscallDesc("sysinfo", unimplimentedFunc); + /* 215 */ SyscallDesc("ipc", unimplimentedFunc); + /* 216 */ SyscallDesc("sigreturn", unimplimentedFunc); + /* 217 */ SyscallDesc("clone", unimplimentedFunc); + /* 218 */ SyscallDesc("ioprio_get", unimplimentedFunc); + /* 219 */ SyscallDesc("adjtimex", unimplimentedFunc); + /* 220 */ SyscallDesc("sigprocmask", unimplimentedFunc); + /* 221 */ SyscallDesc("create_module", unimplimentedFunc); + /* 222 */ SyscallDesc("delete_module", unimplimentedFunc); + /* 223 */ SyscallDesc("get_kernel_syms", unimplimentedFunc); + /* 224 */ SyscallDesc("getpgid", unimplimentedFunc); + /* 225 */ SyscallDesc("bdflush", unimplimentedFunc); + /* 226 */ SyscallDesc("sysfs", unimplimentedFunc); + /* 227 */ SyscallDesc("afs_syscall", unimplimentedFunc); + /* 228 */ SyscallDesc("setfsuid", unimplimentedFunc); + /* 229 */ SyscallDesc("setfsgid", unimplimentedFunc); + /* 230 */ SyscallDesc("_newselect", unimplimentedFunc); + /* 231 */ SyscallDesc("time", unimplimentedFunc); + /* 232 */ SyscallDesc("oldstat", unimplimentedFunc); + /* 233 */ SyscallDesc("stime", unimplimentedFunc); + /* 234 */ SyscallDesc("statfs64", unimplimentedFunc); + /* 235 */ SyscallDesc("fstatfs64", unimplimentedFunc); + /* 236 */ SyscallDesc("_llseek", unimplimentedFunc); + /* 237 */ SyscallDesc("mlock", unimplimentedFunc); + /* 238 */ SyscallDesc("munlock", unimplimentedFunc); + /* 239 */ SyscallDesc("mlockall", unimplimentedFunc); + /* 240 */ SyscallDesc("munlockall", unimplimentedFunc); + /* 241 */ SyscallDesc("sched_setparam", unimplimentedFunc); + /* 242 */ SyscallDesc("sched_getparam", unimplimentedFunc); + /* 243 */ SyscallDesc("sched_setscheduler", unimplimentedFunc); + /* 244 */ SyscallDesc("sched_getscheduler", unimplimentedFunc); + /* 245 */ SyscallDesc("sched_yield", unimplimentedFunc); + /* 246 */ SyscallDesc("sched_get_priority_max", unimplimented); + /* 247 */ SyscallDesc("sched_get_priority_min", unimplimented); + /* 248 */ SyscallDesc("sched_rr_get_interval", unimplimented); + /* 249 */ SyscallDesc("nanosleep", unimplimentedFunc); + /* 250 */ SyscallDesc("mremap", unimplimentedFunc); + /* 251 */ SyscallDesc("_sysctl", unimplimentedFunc); + /* 252 */ SyscallDesc("getsid", unimplimentedFunc); + /* 253 */ SyscallDesc("fdatasync", unimplimentedFunc); + /* 254 */ SyscallDesc("nfsservctl", unimplimentedFunc); + /* 255 */ SyscallDesc("aplib", unimplimentedFunc); + /* 256 */ SyscallDesc("clock_settime", unimplimentedFunc); + /* 257 */ SyscallDesc("clock_gettime", unimplimentedFunc); + /* 258 */ SyscallDesc("clock_getres", unimplimentedFunc); + /* 259 */ SyscallDesc("clock_nanosleep", unimplimentedFunc); + /* 260 */ SyscallDesc("sched_getaffinity", unimplimentedFunc); + /* 261 */ SyscallDesc("sched_setaffinity", unimplimentedFunc); + /* 262 */ SyscallDesc("timer_settime", unimplimentedFunc); + /* 263 */ SyscallDesc("timer_gettime", unimplimentedFunc); + /* 264 */ SyscallDesc("timer_getoverrun", unimplimentedFunc); + /* 265 */ SyscallDesc("timer_delete", unimplimentedFunc); + /* 266 */ SyscallDesc("timer_create", unimplimentedFunc); + /* 267 */ SyscallDesc("vserver", unimplimentedFunc); + /* 268 */ SyscallDesc("io_setup", unimplimentedFunc); + /* 269 */ SyscallDesc("io_destroy", unimplimentedFunc); + /* 270 */ SyscallDesc("io_submit", unimplimentedFunc); + /* 271 */ SyscallDesc("io_cancel", unimplimentedFunc); + /* 272 */ SyscallDesc("io_getevents", unimplimentedFunc); + /* 273 */ SyscallDesc("mq_open", unimplimentedFunc); + /* 274 */ SyscallDesc("mq_unlink", unimplimentedFunc); + /* 275 */ SyscallDesc("mq_timedsend", unimplimentedFunc); + /* 276 */ SyscallDesc("mq_timedreceive", unimplimentedFunc); + /* 277 */ SyscallDesc("mq_notify", unimplimentedFunc); + /* 278 */ SyscallDesc("mq_getsetattr", unimplimentedFunc); + /* 279 */ SyscallDesc("waitid", unimplimentedFunc); + /* 280 */ SyscallDesc("sys_setaltroot", unimplimentedFunc); + /* 281 */ SyscallDesc("add_key", unimplimentedFunc); + /* 282 */ SyscallDesc("request_key", unimplimentedFunc); + /* 283 */ SyscallDesc("keyctl", unimplimentedFunc); +}; + +SparcLinuxProcess::SparcLinuxProcess(const std::string &name, + ObjectFile *objFile, + int stdin_fd, + int stdout_fd, + int stderr_fd, + std::vector<std::string> &argv, + std::vector<std::string> &envp) + : LiveProcess(name, objFile, stdin_fd, stdout_fd, stderr_fd, argv, envp), + Num_Syscall_Descs(sizeof(syscallDescs) / sizeof(SyscallDesc)) +{ + init_regs->intRegFile[0] = 0; +} + + + +SyscallDesc* +AlphaLinuxProcess::getDesc(int callnum) +{ + if (callnum < 0 || callnum > Num_Syscall_Descs) + return NULL; + return &syscallDescs[callnum]; +} diff --git a/arch/sparc/linux_process.hh b/arch/sparc/linux_process.hh new file mode 100644 index 000000000..c41406b4b --- /dev/null +++ b/arch/sparc/linux_process.hh @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2003-2004 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __SPARC_LINUX_PROCESS_HH__ +#define __SPARC_LINUX_PROCESS_HH__ + +#include "sim/process.hh" + + +/// A process with emulated SPARC/Linux syscalls. +class SparcLinuxProcess : public LiveProcess +{ + public: + /// Constructor. + SparcLinuxProcess(const std::string &name, + ObjectFile *objFile, + int stdin_fd, int stdout_fd, int stderr_fd, + std::vector<std::string> &argv, + std::vector<std::string> &envp); + + virtual SyscallDesc* getDesc(int callnum); + + /// The target system's hostname. + static const char *hostname; + + /// Array of syscall descriptors, indexed by call number. + static SyscallDesc syscallDescs[]; + + const int Num_Syscall_Descs; +}; + + +#endif // __ALPHA_LINUX_PROCESS_HH__ diff --git a/arch/sparc/process.cc b/arch/sparc/process.cc new file mode 100644 index 000000000..53a215379 --- /dev/null +++ b/arch/sparc/process.cc @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2003-2004 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "arch/sparc/process.hh" + +namespace SparcISA +{ + +LiveProcess * +createProcess(const string &nm, ObjectFile * objFile, + int stdin_fd, int stdout_fd, int stderr_fd, + vector<string> &argv, vector<string> &envp) +{ + LiveProcess * process = NULL; + if (objFile->getArch() != ObjectFile::SPARC) + fatal("Object file does not match architecture."); + switch (objFile->getOpSys()) { + case ObjectFile::Linux: + process = new SparcLinuxProcess(nm, objFile, + stdin_fd, stdout_fd, stderr_fd, + argv, envp); + break; + + case ObjectFile::Solaris: + default: + fatal("Unknown/unsupported operating system."); + } + return process; +} + +} // namespace SparcISA diff --git a/arch/sparc/process.hh b/arch/sparc/process.hh new file mode 100644 index 000000000..387649d47 --- /dev/null +++ b/arch/sparc/process.hh @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2003-2004 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __SPARC_PROCESS_HH__ +#define __SPARC_PROCESS_HH__ + +#include "arch/sparc/linux_process.hh" +#include "base/loader/object_file.hh" + +namespace SparcISA +{ + +LiveProcess * +createProcess(const string &nm, ObjectFile * objFile, + int stdin_fd, int stdout_fd, int stderr_fd, + vector<string> &argv, vector<string> &envp); + +} // namespace SparcISA + +#endif // __SPARC_PROCESS_HH__ diff --git a/base/loader/elf_object.cc b/base/loader/elf_object.cc index b74d537af..fd69c9e56 100644 --- a/base/loader/elf_object.cc +++ b/base/loader/elf_object.cc @@ -38,8 +38,8 @@ #define __LIBELF_NEED_LINK_H 0 #define __LIBELF_SYMBOL_VERSIONS 0 -#include <libelf/libelf.h> -#include <libelf/gelf.h> +#include "libelf/libelf.h" +#include "libelf/gelf.h" #include "base/loader/elf_object.hh" @@ -56,6 +56,8 @@ ElfObject::tryFile(const string &fname, int fd, size_t len, uint8_t *data) { Elf *elf; GElf_Ehdr ehdr; + Arch arch = UnknownArch; + OpSys opSys = UnknownOpSys; // check that header matches library version if (elf_version(EV_CURRENT) == EV_NONE) @@ -73,8 +75,8 @@ ElfObject::tryFile(const string &fname, int fd, size_t len, uint8_t *data) return NULL; } else { - if (ehdr.e_ident[EI_CLASS] == ELFCLASS32) - panic("32 bit ELF Binary, Not Supported"); +// if (ehdr.e_ident[EI_CLASS] == ELFCLASS32) +// panic("32 bit ELF Binary, Not Supported"); /* @todo this emachine value isn't offical yet. * so we probably shouldn't check it. */ // if (ehdr.e_machine != EM_ALPHA) @@ -82,8 +84,43 @@ ElfObject::tryFile(const string &fname, int fd, size_t len, uint8_t *data) elf_end(elf); - return new ElfObject(fname, fd, len, data, - ObjectFile::Alpha, ObjectFile::Linux); + //Detect the architecture + //Versioning issues in libelf need to be resolved to get the correct + //SPARC constants. + //If MIPS supports 32 bit executables, this may need to be changed. + //Also, there are other MIPS constants which may be used, like + //EM_MIPS_RS3_LE and EM_MIPS_X + //Since we don't know how to check for alpha right now, we'll + //just assume if it wasn't something else and it's 64 bit, that's + //what it must be. + if (ehdr.e_machine == EM_SPARC64 || + ehdr.e_machine == EM_SPARC || + ehdr.e_machine == EM_SPARCV9) { + arch = ObjectFile::SPARC; + } else if (ehdr.e_machine == EM_MIPS + && ehdr.e_ident[EI_CLASS] == ELFCLASS32) { + arch = ObjectFile::MIPS; + } else if (ehdr.e_ident[EI_CLASS] == ELFCLASS64) { + arch = ObjectFile::Alpha; + } else { + arch = ObjectFile::UnknownArch; + } + + //Detect the operating system + switch (ehdr.e_ident[EI_OSABI]) + { + case ELFOSABI_LINUX: + opSys = ObjectFile::Linux; + break; + case ELFOSABI_SOLARIS: + opSys = ObjectFile::Solaris; + case ELFOSABI_TRU64: + opSys = ObjectFile::Tru64; + default: + opSys = ObjectFile::UnknownOpSys; + } + + return new ElfObject(fname, fd, len, data, arch, opSys); } } diff --git a/base/loader/exec_aout.h b/base/loader/exec_aout.h index 76ebe9bb5..3863a92fb 100644 --- a/base/loader/exec_aout.h +++ b/base/loader/exec_aout.h @@ -55,6 +55,6 @@ (N_GETMAGIC(ex) != NMAGIC && N_GETMAGIC(ex) != OMAGIC && \ N_GETMAGIC(ex) != ZMAGIC) -#include "targetarch/aout_machdep.h" +#include "arch/aout_machdep.h" #endif /* !_SYS_EXEC_AOUT_H_ */ diff --git a/base/loader/exec_ecoff.h b/base/loader/exec_ecoff.h index 4eece4318..79cd22a6e 100644 --- a/base/loader/exec_ecoff.h +++ b/base/loader/exec_ecoff.h @@ -37,7 +37,7 @@ #ifndef _SYS_EXEC_ECOFF_H_ #define _SYS_EXEC_ECOFF_H_ -#include "targetarch/ecoff_machdep.h" +#include "arch/ecoff_machdep.h" struct ecoff_filehdr { coff_ushort f_magic; /* magic number */ diff --git a/base/loader/object_file.hh b/base/loader/object_file.hh index 3c8659e18..1b44ae14f 100644 --- a/base/loader/object_file.hh +++ b/base/loader/object_file.hh @@ -29,7 +29,9 @@ #ifndef __OBJECT_FILE_HH__ #define __OBJECT_FILE_HH__ -#include "arch/isa_traits.hh" // for Addr +#include <string> + +#include "sim/host.hh" // for Addr class FunctionalMemory; class SymbolTable; @@ -40,13 +42,16 @@ class ObjectFile enum Arch { UnknownArch, - Alpha + Alpha, + SPARC, + MIPS }; enum OpSys { UnknownOpSys, Tru64, - Linux + Linux, + Solaris }; protected: diff --git a/base/refcnt.hh b/base/refcnt.hh index 9d9ed4337..de589f7c5 100644 --- a/base/refcnt.hh +++ b/base/refcnt.hh @@ -29,6 +29,8 @@ #ifndef __REFCNT_HH__ #define __REFCNT_HH__ +#include <stddef.h> //For the NULL macro definition + class RefCounted { private: diff --git a/base/remote_gdb.cc b/base/remote_gdb.cc index 50c4798c4..84093459c 100644 --- a/base/remote_gdb.cc +++ b/base/remote_gdb.cc @@ -129,7 +129,7 @@ #include "cpu/static_inst.hh" #include "mem/functional/physical.hh" #include "sim/system.hh" -#include "targetarch/vtophys.hh" +#include "arch/vtophys.hh" using namespace std; using namespace TheISA; @@ -424,12 +424,25 @@ void RemoteGDB::getregs() { memset(gdbregs, 0, sizeof(gdbregs)); - memcpy(&gdbregs[KGDB_REG_V0], context->regs.intRegFile, 32 * sizeof(uint64_t)); + + gdbregs[KGDB_REG_PC] = context->readPC(); + + // @todo: Currently this is very Alpha specific. + if (AlphaISA::PcPAL(gdbregs[KGDB_REG_PC])) { + for (int i = 0; i < TheISA::NumIntArchRegs; ++i) { + gdbregs[i] = context->readIntReg(AlphaISA::reg_redir[i]); + } + } else { + for (int i = 0; i < TheISA::NumIntArchRegs; ++i) { + gdbregs[i] = context->readIntReg(i); + } + } + #ifdef KGDB_FP_REGS - memcpy(&gdbregs[KGDB_REG_F0], context->regs.floatRegFile.q, - 32 * sizeof(uint64_t)); + for (int i = 0; i < TheISA::NumFloatArchRegs; ++i) { + gdbregs[i + KGDB_REG_F0] = context->readFloatRegInt(i); + } #endif - gdbregs[KGDB_REG_PC] = context->readPC(); } /////////////////////////////////////////////////////////// @@ -441,11 +454,21 @@ RemoteGDB::getregs() void RemoteGDB::setregs() { - memcpy(context->regs.intRegFile, &gdbregs[KGDB_REG_V0], - 32 * sizeof(uint64_t)); + // @todo: Currently this is very Alpha specific. + if (AlphaISA::PcPAL(gdbregs[KGDB_REG_PC])) { + for (int i = 0; i < TheISA::NumIntArchRegs; ++i) { + context->setIntReg(AlphaISA::reg_redir[i], gdbregs[i]); + } + } else { + for (int i = 0; i < TheISA::NumIntArchRegs; ++i) { + context->setIntReg(i, gdbregs[i]); + } + } + #ifdef KGDB_FP_REGS - memcpy(context->regs.floatRegFile.q, &gdbregs[KGDB_REG_F0], - 32 * sizeof(uint64_t)); + for (int i = 0; i < TheISA::NumFloatArchRegs; ++i) { + context->setFloatRegInt(i, gdbregs[i + KGDB_REG_F0]); + } #endif context->setPC(gdbregs[KGDB_REG_PC]); } diff --git a/cpu/base_dyn_inst.cc b/cpu/base_dyn_inst.cc index a40b4a1dd..bf7c35cad 100644 --- a/cpu/base_dyn_inst.cc +++ b/cpu/base_dyn_inst.cc @@ -36,7 +36,7 @@ #include "base/cprintf.hh" #include "base/trace.hh" -#include "arch/alpha/faults.hh" +#include "arch/faults.hh" #include "cpu/exetrace.hh" #include "mem/mem_req.hh" @@ -45,6 +45,7 @@ #include "cpu/o3/alpha_cpu.hh" using namespace std; +using namespace TheISA; #define NOHASH #ifndef NOHASH @@ -113,7 +114,7 @@ BaseDynInst<Impl>::initVars() asid = 0; // Initialize the fault to be unimplemented opcode. - fault = UnimplementedOpcodeFault; + fault = new UnimplementedOpcodeFault; ++instcount; @@ -325,7 +326,7 @@ BaseDynInst<Impl>::mem_access(mem_cmd cmd, Addr addr, void *p, int nbytes) break; default: - fault = MachineCheckFault; + fault = genMachineCheckFault(); break; } diff --git a/cpu/cpu_exec_context.cc b/cpu/cpu_exec_context.cc index 2fb3d5d53..ae428646d 100644 --- a/cpu/cpu_exec_context.cc +++ b/cpu/cpu_exec_context.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2001-2005 The Regents of The University of Michigan + * Copyright (c) 2001-2006 The Regents of The University of Michigan * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -36,12 +36,13 @@ #include "base/callback.hh" #include "base/cprintf.hh" #include "base/output.hh" +#include "base/trace.hh" #include "cpu/profile.hh" #include "kern/kernel_stats.hh" #include "sim/serialize.hh" #include "sim/sim_exit.hh" #include "sim/system.hh" -#include "targetarch/stacktrace.hh" +#include "arch/stacktrace.hh" #else #include "sim/process.hh" #endif @@ -54,8 +55,9 @@ CPUExecContext::CPUExecContext(BaseCPU *_cpu, int _thread_num, System *_sys, AlphaITB *_itb, AlphaDTB *_dtb, FunctionalMemory *_mem) : _status(ExecContext::Unallocated), cpu(_cpu), thread_num(_thread_num), - cpu_id(-1), mem(_mem), itb(_itb), dtb(_dtb), system(_sys), - memctrl(_sys->memctrl), physmem(_sys->physmem), profile(NULL), + cpu_id(-1), lastActivate(0), lastSuspend(0), mem(_mem), itb(_itb), + dtb(_dtb), system(_sys), memctrl(_sys->memctrl), physmem(_sys->physmem), + fnbin(kernelBinning->fnbin), profile(NULL), quiesceEvent(this), func_exe_inst(0), storeCondFailures(0) { proxy = new ProxyExecContext<CPUExecContext>(this); @@ -80,8 +82,8 @@ CPUExecContext::CPUExecContext(BaseCPU *_cpu, int _thread_num, System *_sys, CPUExecContext::CPUExecContext(BaseCPU *_cpu, int _thread_num, Process *_process, int _asid) : _status(ExecContext::Unallocated), - cpu(_cpu), thread_num(_thread_num), cpu_id(-1), - process(_process), mem(process->getMemory()), asid(_asid), + cpu(_cpu), thread_num(_thread_num), cpu_id(-1), lastActivate(0), + lastSuspend(0), process(_process), mem(process->getMemory()), asid(_asid), func_exe_inst(0), storeCondFailures(0) { memset(®s, 0, sizeof(RegFile)); @@ -117,7 +119,23 @@ void CPUExecContext::dumpFuncProfile() { std::ostream *os = simout.create(csprintf("profile.%s.dat", cpu->name())); - profile->dump(proxy, *os); +} + +ExecContext::EndQuiesceEvent::EndQuiesceEvent(ExecContext *_xc) + : Event(&mainEventQueue), xc(_xc) +{ +} + +void +ExecContext::EndQuiesceEvent::process() +{ + xc->activate(); +} + +const char* +ExecContext::EndQuiesceEvent::description() +{ + return "End Quiesce Event."; } #endif @@ -153,6 +171,14 @@ CPUExecContext::serialize(ostream &os) // thread_num and cpu_id are deterministic from the config SERIALIZE_SCALAR(func_exe_inst); SERIALIZE_SCALAR(inst); + +#if FULL_SYSTEM + Tick quiesceEndTick = 0; + if (quiesceEvent.scheduled()) + quiesceEndTick = quiesceEvent.when(); + SERIALIZE_SCALAR(quiesceEndTick); + +#endif } @@ -164,6 +190,13 @@ CPUExecContext::unserialize(Checkpoint *cp, const std::string §ion) // thread_num and cpu_id are deterministic from the config UNSERIALIZE_SCALAR(func_exe_inst); UNSERIALIZE_SCALAR(inst); + +#if FULL_SYSTEM + Tick quiesceEndTick; + UNSERIALIZE_SCALAR(quiesceEndTick); + if (quiesceEndTick) + quiesceEvent.schedule(quiesceEndTick); +#endif } @@ -173,6 +206,8 @@ CPUExecContext::activate(int delay) if (status() == ExecContext::Active) return; + lastActivate = curTick; + _status = ExecContext::Active; cpu->activateContext(thread_num, delay); } @@ -183,6 +218,9 @@ CPUExecContext::suspend() if (status() == ExecContext::Suspended) return; + lastActivate = curTick; + lastSuspend = curTick; +/* #if FULL_SYSTEM // Don't change the status from active if there are pending interrupts if (cpu->check_interrupts()) { @@ -190,7 +228,7 @@ CPUExecContext::suspend() return; } #endif - +*/ _status = ExecContext::Suspended; cpu->suspendContext(thread_num); } @@ -248,15 +286,3 @@ CPUExecContext::copyArchRegs(ExecContext *xc) setNextPC(xc->readNextPC()); } -void -CPUExecContext::trap(Fault fault) -{ - //TheISA::trap(fault); //One possible way to do it... - - /** @todo: Going to hack it for now. Do a true fixup later. */ -#if FULL_SYSTEM - ev5_trap(fault); -#else - fatal("fault (%d) detected @ PC 0x%08p", fault, readPC()); -#endif -} diff --git a/cpu/cpu_exec_context.hh b/cpu/cpu_exec_context.hh index 1ae24582d..a40253d4b 100644 --- a/cpu/cpu_exec_context.hh +++ b/cpu/cpu_exec_context.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2001-2005 The Regents of The University of Michigan + * Copyright (c) 2001-2006 The Regents of The University of Michigan * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -35,6 +35,7 @@ #include "mem/functional/functional.hh" #include "mem/mem_req.hh" #include "sim/byteswap.hh" +#include "sim/eventq.hh" #include "sim/host.hh" #include "sim/serialize.hh" @@ -46,7 +47,7 @@ class BaseCPU; #if FULL_SYSTEM #include "sim/system.hh" -#include "targetarch/alpha_memory.hh" +#include "arch/tlb.hh" class FunctionProfile; class ProfileNode; @@ -114,6 +115,9 @@ class CPUExecContext // it belongs. For full-system mode, this is the system CPU ID. int cpu_id; + Tick lastActivate; + Tick lastSuspend; + #if FULL_SYSTEM FunctionalMemory *mem; AlphaITB *itb; @@ -131,6 +135,22 @@ class CPUExecContext Addr profilePC; void dumpFuncProfile(); + /** Event for timing out quiesce instruction */ + struct EndQuiesceEvent : public Event + { + /** A pointer to the execution context that is quiesced */ + ExecContext *xc; + + EndQuiesceEvent(ExecContext *_xc); + + /** Event process to occur at interrupt*/ + virtual void process(); + + /** Event description */ + virtual const char *description(); + }; + EndQuiesceEvent quiesceEvent; + #else Process *process; @@ -447,18 +467,9 @@ class CPUExecContext void setIntrFlag(int val) { regs.intrflag = val; } Fault hwrei(); bool inPalMode() { return AlphaISA::PcPAL(regs.pc); } - void ev5_trap(Fault fault); bool simPalCheck(int palFunc); #endif - /** Meant to be more generic trap function to be - * called when an instruction faults. - * @param fault The fault generated by executing the instruction. - * @todo How to do this properly so it's dependent upon ISA only? - */ - - void trap(Fault fault); - #if !FULL_SYSTEM TheISA::IntReg getSyscallArg(int i) { diff --git a/cpu/o3/alpha_cpu.hh b/cpu/o3/alpha_cpu.hh index 75a4d72c2..531f6aa45 100644 --- a/cpu/o3/alpha_cpu.hh +++ b/cpu/o3/alpha_cpu.hh @@ -275,7 +275,7 @@ class AlphaFullCPU : public FullO3CPU<Impl> #endif - return this->mem->write(req, (T)::htog(data)); + return this->mem->write(req, (T)htog(data)); } template <class T> diff --git a/cpu/o3/alpha_cpu_builder.cc b/cpu/o3/alpha_cpu_builder.cc index 7e687ad2b..6025b8ef2 100644 --- a/cpu/o3/alpha_cpu_builder.cc +++ b/cpu/o3/alpha_cpu_builder.cc @@ -49,8 +49,8 @@ #include "mem/functional/memory_control.hh" #include "mem/functional/physical.hh" #include "sim/system.hh" -#include "targetarch/alpha_memory.hh" -#include "targetarch/vtophys.hh" +#include "arch/tlb.hh" +#include "arch/vtophys.hh" #else // !FULL_SYSTEM #include "mem/functional/functional.hh" #endif // FULL_SYSTEM diff --git a/cpu/o3/alpha_cpu_impl.hh b/cpu/o3/alpha_cpu_impl.hh index 271b542ab..33e363d4f 100644 --- a/cpu/o3/alpha_cpu_impl.hh +++ b/cpu/o3/alpha_cpu_impl.hh @@ -260,7 +260,7 @@ Fault AlphaFullCPU<Impl>::hwrei() { if (!inPalMode()) - return UnimplementedOpcodeFault; + return new UnimplementedOpcodeFault; this->setNextPC(this->regFile.miscRegs.readReg(AlphaISA::IPR_EXC_ADDR)); @@ -305,24 +305,25 @@ template <class Impl> void AlphaFullCPU<Impl>::trap(Fault fault) { - // Keep in mind that a trap may be initiated by fetch if there's a TLB +/* // Keep in mind that a trap may be initiated by fetch if there's a TLB // miss uint64_t PC = this->commit.readCommitPC(); - DPRINTF(Fault, "Fault %s\n", fault ? fault->name : "name"); - this->recordEvent(csprintf("Fault %s", fault ? fault->name : "name")); + DPRINTF(Fault, "Fault %s\n", fault->name()); + this->recordEvent(csprintf("Fault %s", fault->name())); -// kernelStats.fault(fault); + //kernelStats.fault(fault); - if (fault == ArithmeticFault) + if (fault->isA<ArithmeticFault>()) panic("Arithmetic traps are unimplemented!"); // exception restart address - Get the commit PC - if (fault != InterruptFault || !inPalMode(PC)) + if (!fault->isA<InterruptFault>() || !inPalMode(PC)) this->regFile.miscRegs.setReg(AlphaISA::IPR_EXC_ADDR, PC); - if (fault == PalFault || fault == ArithmeticFault /* || - fault == InterruptFault && !PC_PAL(regs.pc) */) { + if (fault->isA<PalFault>() || fault->isA<ArithmeticFault>()) + // || fault == InterruptFault && !PC_PAL(regs.pc) + { // traps... skip faulting instruction AlphaISA::MiscReg ipr_exc_addr = this->regFile.miscRegs.readReg(AlphaISA::IPR_EXC_ADDR); @@ -334,8 +335,8 @@ AlphaFullCPU<Impl>::trap(Fault fault) swapPALShadow(true); this->regFile.setPC(this->regFile.miscRegs.readReg(AlphaISA::IPR_PAL_BASE) + - AlphaISA::fault_addr(fault) ); - this->regFile.setNextPC(PC + sizeof(MachInst)); + (dynamic_cast<AlphaFault *>(fault.get()))->vect()); + this->regFile.setNextPC(PC + sizeof(MachInst));*/ } template <class Impl> diff --git a/cpu/o3/bpred_unit.hh b/cpu/o3/bpred_unit.hh index 0a77b83dc..2725684f7 100644 --- a/cpu/o3/bpred_unit.hh +++ b/cpu/o3/bpred_unit.hh @@ -30,7 +30,7 @@ #define __BPRED_UNIT_HH__ // For Addr type. -#include "arch/alpha/isa_traits.hh" +#include "arch/isa_traits.hh" #include "base/statistics.hh" #include "cpu/inst_seq.hh" diff --git a/cpu/o3/comm.hh b/cpu/o3/comm.hh index e4de1d304..c74c77ddf 100644 --- a/cpu/o3/comm.hh +++ b/cpu/o3/comm.hh @@ -31,7 +31,7 @@ #include <vector> -#include "arch/alpha/isa_traits.hh" +#include "arch/isa_traits.hh" #include "cpu/inst_seq.hh" #include "sim/host.hh" diff --git a/cpu/o3/cpu.hh b/cpu/o3/cpu.hh index 45e21db7f..8f29a25fb 100644 --- a/cpu/o3/cpu.hh +++ b/cpu/o3/cpu.hh @@ -50,7 +50,7 @@ #include "sim/process.hh" #if FULL_SYSTEM -#include "arch/alpha/ev5.hh" +#include "arch/ev5.hh" using namespace EV5; #endif diff --git a/cpu/o3/regfile.hh b/cpu/o3/regfile.hh index 1bc7159f6..03ad2da46 100644 --- a/cpu/o3/regfile.hh +++ b/cpu/o3/regfile.hh @@ -31,14 +31,14 @@ // @todo: Destructor -#include "arch/alpha/isa_traits.hh" -#include "arch/alpha/faults.hh" +#include "arch/isa_traits.hh" +#include "arch/faults.hh" #include "base/trace.hh" #include "config/full_system.hh" #include "cpu/o3/comm.hh" #if FULL_SYSTEM -#include "arch/alpha/ev5.hh" +#include "arch/ev5.hh" #include "kern/kernel_stats.hh" using namespace EV5; @@ -236,7 +236,7 @@ class PhysRegFile #if FULL_SYSTEM private: // This is ISA specifc stuff; remove it eventually once ISAImpl is used - IntReg palregs[NumIntRegs]; // PAL shadow registers +// IntReg palregs[NumIntRegs]; // PAL shadow registers InternalProcReg ipr[NumInternalProcRegs]; // internal processor regs int intrflag; // interrupt flag bool pal_shadow; // using pal_shadow registers diff --git a/cpu/ozone/cpu.hh b/cpu/ozone/cpu.hh index 667e2b3f8..f5d84d656 100644 --- a/cpu/ozone/cpu.hh +++ b/cpu/ozone/cpu.hh @@ -517,7 +517,7 @@ class OoOCPU : public BaseCPU int readIntrFlag() { return xc->readIntrFlag(); } void setIntrFlag(int val) { xc->setIntrFlag(val); } bool inPalMode() { return xc->inPalMode(); } - void ev5_trap(Fault fault) { xc->ev5_trap(fault); } + void trap(Fault fault) { fault->invoke(xc); } bool simPalCheck(int palFunc) { return xc->simPalCheck(palFunc); } #else void syscall() { xc->syscall(); } diff --git a/cpu/ozone/cpu_impl.hh b/cpu/ozone/cpu_impl.hh index 009a81b98..e7ed3cfe0 100644 --- a/cpu/ozone/cpu_impl.hh +++ b/cpu/ozone/cpu_impl.hh @@ -29,7 +29,7 @@ #ifndef __CPU_OOO_CPU_OOO_IMPL_HH__ #define __CPU_OOO_CPU_OOO_IMPL_HH__ -#include "arch/alpha/isa_traits.hh" +#include "arch/isa_traits.hh" template <class Impl> class OoOCPU; diff --git a/cpu/ozone/ea_list.cc b/cpu/ozone/ea_list.cc index 80cf80fb8..6114a0ca1 100644 --- a/cpu/ozone/ea_list.cc +++ b/cpu/ozone/ea_list.cc @@ -26,7 +26,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#include "arch/alpha/isa_traits.hh" +#include "arch/isa_traits.hh" #include "cpu/inst_seq.hh" #include "cpu/ooo_cpu/ea_list.hh" diff --git a/cpu/ozone/ea_list.hh b/cpu/ozone/ea_list.hh index def7e67d5..c0eee4bb8 100644 --- a/cpu/ozone/ea_list.hh +++ b/cpu/ozone/ea_list.hh @@ -32,7 +32,7 @@ #include <list> #include <utility> -#include "arch/alpha/isa_traits.hh" +#include "arch/isa_traits.hh" #include "cpu/inst_seq.hh" /** diff --git a/cpu/profile.hh b/cpu/profile.hh index 18061f9bf..1eb012a27 100644 --- a/cpu/profile.hh +++ b/cpu/profile.hh @@ -33,7 +33,7 @@ #include "cpu/static_inst.hh" #include "sim/host.hh" -#include "targetarch/stacktrace.hh" +#include "arch/stacktrace.hh" class ProfileNode { diff --git a/cpu/simple/cpu.cc b/cpu/simple/cpu.cc index 7c60b242f..38b43fef5 100644 --- a/cpu/simple/cpu.cc +++ b/cpu/simple/cpu.cc @@ -68,9 +68,9 @@ #include "mem/functional/memory_control.hh" #include "mem/functional/physical.hh" #include "sim/system.hh" -#include "targetarch/alpha_memory.hh" -#include "targetarch/stacktrace.hh" -#include "targetarch/vtophys.hh" +#include "arch/tlb.hh" +#include "arch/stacktrace.hh" +#include "arch/vtophys.hh" #else // !FULL_SYSTEM #include "mem/functional/functional.hh" #endif // FULL_SYSTEM @@ -350,12 +350,12 @@ SimpleCPU::copySrcTranslate(Addr src) // translate to physical address Fault fault = cpuXC->translateDataReadReq(memReq); - assert(fault != AlignmentFault); - if (fault == NoFault) { cpuXC->copySrcAddr = src; cpuXC->copySrcPhysAddr = memReq->paddr + offset; } else { + assert(!fault->isAlignmentFault()); + cpuXC->copySrcAddr = 0; cpuXC->copySrcPhysAddr = 0; } @@ -385,8 +385,6 @@ SimpleCPU::copy(Addr dest) // translate to physical address Fault fault = cpuXC->translateDataWriteReq(memReq); - assert(fault != AlignmentFault); - if (fault == NoFault) { Addr dest_addr = memReq->paddr + offset; // Need to read straight from memory since we have more than 8 bytes. @@ -405,6 +403,9 @@ SimpleCPU::copy(Addr dest) dcacheInterface->access(memReq); } } + else + assert(!fault->isAlignmentFault()); + return fault; } @@ -690,7 +691,8 @@ SimpleCPU::tick() if (ipl && ipl > cpuXC->readMiscReg(IPR_IPLR)) { cpuXC->setMiscReg(IPR_ISR, summary); cpuXC->setMiscReg(IPR_INTID, ipl); - cpuXC->ev5_trap(InterruptFault); + + Fault(new InterruptFault)->invoke(xcProxy); DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n", cpuXC->readMiscReg(IPR_IPLR), ipl, summary); @@ -764,7 +766,7 @@ SimpleCPU::tick() // decode the instruction inst = gtoh(inst); - curStaticInst = StaticInst::decode(inst); + curStaticInst = StaticInst::decode(makeExtMI(inst, xc->readPC())); traceData = Trace::getInstRecord(curTick, xcProxy, this, curStaticInst, cpuXC->readPC()); @@ -815,7 +817,7 @@ SimpleCPU::tick() if (fault != NoFault) { #if FULL_SYSTEM - cpuXC->ev5_trap(fault); + fault->invoke(xcProxy); #else // !FULL_SYSTEM fatal("fault (%d) detected @ PC 0x%08p", fault, cpuXC->readPC()); #endif // FULL_SYSTEM diff --git a/cpu/simple/cpu.hh b/cpu/simple/cpu.hh index 1441a8fcd..4ab9a1c3e 100644 --- a/cpu/simple/cpu.hh +++ b/cpu/simple/cpu.hh @@ -350,7 +350,7 @@ class SimpleCPU : public BaseCPU int readIntrFlag() { return cpuXC->readIntrFlag(); } void setIntrFlag(int val) { cpuXC->setIntrFlag(val); } bool inPalMode() { return cpuXC->inPalMode(); } - void ev5_trap(Fault fault) { cpuXC->ev5_trap(fault); } + void ev5_trap(Fault fault) { fault->invoke(xcProxy); } bool simPalCheck(int palFunc) { return cpuXC->simPalCheck(palFunc); } #else void syscall() { cpuXC->syscall(); } diff --git a/cpu/static_inst.hh b/cpu/static_inst.hh index a0287a2de..20116554e 100644 --- a/cpu/static_inst.hh +++ b/cpu/static_inst.hh @@ -109,6 +109,8 @@ class StaticInstBase : public RefCounted IsCall, ///< Subroutine call. IsReturn, ///< Subroutine return. + IsCondDelaySlot,///< Conditional Delay-Slot Instruction + IsThreadSync, ///< Thread synchronization operation. IsSerializing, ///< Serializes pipeline: won't execute until all @@ -229,6 +231,8 @@ class StaticInst : public StaticInstBase /// Binary machine instruction type. typedef TheISA::MachInst MachInst; + /// Binary extended machine instruction type. + typedef TheISA::ExtMachInst ExtMachInst; /// Logical register index type. typedef TheISA::RegIndex RegIndex; @@ -270,7 +274,7 @@ class StaticInst : public StaticInstBase StaticInstPtr &memAccInst() const { return nullStaticInstPtr; } /// The binary machine instruction. - const MachInst machInst; + const ExtMachInst machInst; protected: @@ -300,7 +304,7 @@ class StaticInst : public StaticInstBase generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0; /// Constructor. - StaticInst(const char *_mnemonic, MachInst _machInst, OpClass __opClass) + StaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass) : StaticInstBase(__opClass), machInst(_machInst), mnemonic(_mnemonic), cachedDisassembly(0) { @@ -370,7 +374,7 @@ class StaticInst : public StaticInstBase /// Decoded instruction cache type. /// For now we're using a generic hash_map; this seems to work /// pretty well. - typedef m5::hash_map<MachInst, StaticInstPtr> DecodeCache; + typedef m5::hash_map<ExtMachInst, StaticInstPtr> DecodeCache; /// A cache of decoded instruction objects. static DecodeCache decodeCache; @@ -385,7 +389,7 @@ class StaticInst : public StaticInstBase /// @param mach_inst The binary instruction to decode. /// @retval A pointer to the corresponding StaticInst object. //This is defined as inline below. - static StaticInstPtr decode(MachInst mach_inst); + static StaticInstPtr decode(ExtMachInst mach_inst); }; typedef RefCountingPtr<StaticInstBase> StaticInstBasePtr; @@ -416,7 +420,7 @@ class StaticInstPtr : public RefCountingPtr<StaticInst> /// Construct directly from machine instruction. /// Calls StaticInst::decode(). - StaticInstPtr(TheISA::MachInst mach_inst) + StaticInstPtr(TheISA::ExtMachInst mach_inst) : RefCountingPtr<StaticInst>(StaticInst::decode(mach_inst)) { } @@ -429,7 +433,7 @@ class StaticInstPtr : public RefCountingPtr<StaticInst> }; inline StaticInstPtr -StaticInst::decode(StaticInst::MachInst mach_inst) +StaticInst::decode(StaticInst::ExtMachInst mach_inst) { #ifdef DECODE_CACHE_HASH_STATS // Simple stats on decode hash_map. Turns out the default diff --git a/dev/alpha_console.cc b/dev/alpha_console.cc index 2e8bbd1dd..6ca5e3a06 100644 --- a/dev/alpha_console.cc +++ b/dev/alpha_console.cc @@ -34,6 +34,7 @@ #include <cstdio> #include <string> +#include "arch/alpha/system.hh" #include "base/inifile.hh" #include "base/str.hh" #include "base/trace.hh" @@ -50,13 +51,12 @@ #include "mem/functional/physical.hh" #include "sim/builder.hh" #include "sim/sim_object.hh" -#include "sim/system.hh" using namespace std; using namespace AlphaISA; AlphaConsole::AlphaConsole(const string &name, SimConsole *cons, SimpleDisk *d, - System *s, BaseCPU *c, Platform *p, + AlphaSystem *s, BaseCPU *c, Platform *p, MemoryController *mmu, Addr a, HierParams *hier, Bus *pio_bus) : PioDevice(name, p), disk(d), console(cons), system(s), cpu(c), addr(a) @@ -182,7 +182,7 @@ AlphaConsole::read(MemReqPtr &req, uint8_t *data) } break; default: - return MachineCheckFault; + return genMachineCheckFault(); } return NoFault; @@ -202,7 +202,7 @@ AlphaConsole::write(MemReqPtr &req, const uint8_t *data) val = *(uint64_t *)data; break; default: - return MachineCheckFault; + return genMachineCheckFault(); } Addr daddr = req->paddr - (addr & EV5::PAddrImplMask); @@ -323,7 +323,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaConsole) SimObjectParam<SimpleDisk *> disk; SimObjectParam<MemoryController *> mmu; Param<Addr> addr; - SimObjectParam<System *> system; + SimObjectParam<AlphaSystem *> system; SimObjectParam<BaseCPU *> cpu; SimObjectParam<Platform *> platform; SimObjectParam<Bus*> pio_bus; diff --git a/dev/alpha_console.hh b/dev/alpha_console.hh index 2d1c1e634..86ef021e9 100644 --- a/dev/alpha_console.hh +++ b/dev/alpha_console.hh @@ -41,7 +41,7 @@ class BaseCPU; class SimConsole; -class System; +class AlphaSystem; class SimpleDisk; /** @@ -90,7 +90,7 @@ class AlphaConsole : public PioDevice SimConsole *console; /** a pointer to the system we are running in */ - System *system; + AlphaSystem *system; /** a pointer to the CPU boot cpu */ BaseCPU *cpu; @@ -101,7 +101,7 @@ class AlphaConsole : public PioDevice public: /** Standard Constructor */ AlphaConsole(const std::string &name, SimConsole *cons, SimpleDisk *d, - System *s, BaseCPU *c, Platform *platform, + AlphaSystem *s, BaseCPU *c, Platform *platform, MemoryController *mmu, Addr addr, HierParams *hier, Bus *pio_bus); diff --git a/dev/ns_gige.cc b/dev/ns_gige.cc index 4b08d8497..ed8c794f9 100644 --- a/dev/ns_gige.cc +++ b/dev/ns_gige.cc @@ -49,7 +49,7 @@ #include "sim/debug.hh" #include "sim/host.hh" #include "sim/stats.hh" -#include "targetarch/vtophys.hh" +#include "arch/vtophys.hh" const char *NsRxStateStrings[] = { @@ -767,6 +767,8 @@ NSGigE::read(MemReqPtr &req, uint8_t *data) reg |= M5REG_RX_THREAD; if (params()->tx_thread) reg |= M5REG_TX_THREAD; + if (params()->rss) + reg |= M5REG_RSS; break; default: @@ -3009,6 +3011,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(NSGigE) Param<string> hardware_address; Param<bool> rx_thread; Param<bool> tx_thread; + Param<bool> rss; END_DECLARE_SIM_OBJECT_PARAMS(NSGigE) @@ -3048,7 +3051,8 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(NSGigE) INIT_PARAM(rx_filter, "Enable Receive Filter"), INIT_PARAM(hardware_address, "Ethernet Hardware Address"), INIT_PARAM(rx_thread, ""), - INIT_PARAM(tx_thread, "") + INIT_PARAM(tx_thread, ""), + INIT_PARAM(rss, "") END_INIT_SIM_OBJECT_PARAMS(NSGigE) @@ -3093,6 +3097,7 @@ CREATE_SIM_OBJECT(NSGigE) params->eaddr = hardware_address; params->rx_thread = rx_thread; params->tx_thread = tx_thread; + params->rss = rss; return new NSGigE(params); } diff --git a/dev/ns_gige.hh b/dev/ns_gige.hh index cdd8e4b9e..59c55056e 100644 --- a/dev/ns_gige.hh +++ b/dev/ns_gige.hh @@ -385,6 +385,7 @@ class NSGigE : public PciDev uint32_t rx_fifo_size; bool rx_thread; bool tx_thread; + bool rss; bool dma_no_allocate; }; diff --git a/dev/ns_gige_reg.h b/dev/ns_gige_reg.h index eadc60d03..5f6fa2cc5 100644 --- a/dev/ns_gige_reg.h +++ b/dev/ns_gige_reg.h @@ -306,6 +306,7 @@ /* M5 control register */ #define M5REG_RESERVED 0xfffffffc +#define M5REG_RSS 0x00000004 #define M5REG_RX_THREAD 0x00000002 #define M5REG_TX_THREAD 0x00000001 diff --git a/dev/pcidev.hh b/dev/pcidev.hh index 9427463bf..bdfc6b932 100644 --- a/dev/pcidev.hh +++ b/dev/pcidev.hh @@ -260,6 +260,7 @@ class PciDev : public DmaDevice inline Fault PciDev::readBar(MemReqPtr &req, uint8_t *data) { + using namespace TheISA; if (isBAR(req->paddr, 0)) return readBar0(req, req->paddr - BARAddrs[0], data); if (isBAR(req->paddr, 1)) @@ -272,12 +273,13 @@ PciDev::readBar(MemReqPtr &req, uint8_t *data) return readBar4(req, req->paddr - BARAddrs[4], data); if (isBAR(req->paddr, 5)) return readBar5(req, req->paddr - BARAddrs[5], data); - return MachineCheckFault; + return genMachineCheckFault(); } inline Fault PciDev::writeBar(MemReqPtr &req, const uint8_t *data) { + using namespace TheISA; if (isBAR(req->paddr, 0)) return writeBar0(req, req->paddr - BARAddrs[0], data); if (isBAR(req->paddr, 1)) @@ -290,7 +292,7 @@ PciDev::writeBar(MemReqPtr &req, const uint8_t *data) return writeBar4(req, req->paddr - BARAddrs[4], data); if (isBAR(req->paddr, 5)) return writeBar5(req, req->paddr - BARAddrs[5], data); - return MachineCheckFault; + return genMachineCheckFault(); } #endif // __DEV_PCIDEV_HH__ diff --git a/dev/sinic.cc b/dev/sinic.cc index 1b950c191..363994919 100644 --- a/dev/sinic.cc +++ b/dev/sinic.cc @@ -47,7 +47,7 @@ #include "sim/eventq.hh" #include "sim/host.hh" #include "sim/stats.hh" -#include "targetarch/vtophys.hh" +#include "arch/vtophys.hh" using namespace Net; using namespace TheISA; @@ -363,11 +363,11 @@ Device::read(MemReqPtr &req, uint8_t *data) assert(config.command & PCI_CMD_MSE); Fault fault = readBar(req, data); - if (fault == MachineCheckFault) { + if (fault->isMachineCheckFault()) { panic("address does not map to a BAR pa=%#x va=%#x size=%d", req->paddr, req->vaddr, req->size); - return MachineCheckFault; + return genMachineCheckFault(); } return fault; @@ -459,11 +459,11 @@ Device::write(MemReqPtr &req, const uint8_t *data) assert(config.command & PCI_CMD_MSE); Fault fault = writeBar(req, data); - if (fault == MachineCheckFault) { + if (fault->isMachineCheckFault()) { panic("address does not map to a BAR pa=%#x va=%#x size=%d", req->paddr, req->vaddr, req->size); - return MachineCheckFault; + return genMachineCheckFault(); } return fault; @@ -495,8 +495,8 @@ Device::writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data) DPRINTF(EthernetPIO, "write %s: cpu=%d val=%#x da=%#x pa=%#x va=%#x size=%d\n", - info.name, cpu, info.size == 4 ? reg32 : reg64, daddr, - req->paddr, req->vaddr, req->size); + info.name, cpu, info.size == 4 ? reg32 : reg64, + daddr, req->paddr, req->vaddr, req->size); prepareWrite(cpu, index); @@ -761,6 +761,8 @@ Device::reset() regs.Config |= Config_RxThread; if (params()->tx_thread) regs.Config |= Config_TxThread; + if (params()->rss) + regs.Config |= Config_RSS; regs.IntrMask = Intr_Soft | Intr_RxHigh | Intr_RxPacket | Intr_TxLow; regs.RxMaxCopy = params()->rx_max_copy; regs.TxMaxCopy = params()->tx_max_copy; @@ -1624,6 +1626,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(Device) Param<string> hardware_address; Param<bool> rx_thread; Param<bool> tx_thread; + Param<bool> rss; END_DECLARE_SIM_OBJECT_PARAMS(Device) @@ -1666,7 +1669,8 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(Device) INIT_PARAM(rx_filter, "Enable Receive Filter"), INIT_PARAM(hardware_address, "Ethernet Hardware Address"), INIT_PARAM(rx_thread, ""), - INIT_PARAM(tx_thread, "") + INIT_PARAM(tx_thread, ""), + INIT_PARAM(rss, "") END_INIT_SIM_OBJECT_PARAMS(Device) @@ -1714,6 +1718,7 @@ CREATE_SIM_OBJECT(Device) params->eaddr = hardware_address; params->rx_thread = rx_thread; params->tx_thread = tx_thread; + params->rss = rss; return new Device(params); } diff --git a/dev/sinic.hh b/dev/sinic.hh index c4027be86..25172fa45 100644 --- a/dev/sinic.hh +++ b/dev/sinic.hh @@ -355,6 +355,7 @@ class Device : public Base bool dma_no_allocate; bool rx_thread; bool tx_thread; + bool rss; }; protected: diff --git a/dev/sinicreg.hh b/dev/sinicreg.hh index fc1f4c06b..f90432398 100644 --- a/dev/sinicreg.hh +++ b/dev/sinicreg.hh @@ -81,6 +81,7 @@ __SINIC_REG32(HwAddr, 0x60); // 64: mac address __SINIC_REG32(Size, 0x68); // register addres space size // Config register bits +__SINIC_VAL32(Config_RSS, 10, 1); // enable receive side scaling __SINIC_VAL32(Config_RxThread, 9, 1); // enable receive threads __SINIC_VAL32(Config_TxThread, 8, 1); // enable transmit thread __SINIC_VAL32(Config_Filter, 7, 1); // enable receive filter diff --git a/kern/kernel_stats.cc b/kern/kernel_stats.cc index ddf1058e6..988b0f639 100644 --- a/kern/kernel_stats.cc +++ b/kern/kernel_stats.cc @@ -47,7 +47,7 @@ Statistics::Statistics(System *system) : idleProcess((Addr)-1), themode(kernel), lastModeTick(0), iplLast(0), iplLastTick(0) { - bin_int = system->params->bin_int; + bin_int = system->params()->bin_int; } void @@ -136,7 +136,7 @@ Statistics::regStats(const string &_name) } } - _faults +/* _faults .init(NumFaults) .name(name() + ".faults") .desc("number of faults") @@ -147,7 +147,7 @@ Statistics::regStats(const string &_name) const char *str = (*ListOfFaults[i])->name; if (str) _faults.subname(i, str); - } + }*/ _mode .init(cpu_mode_num) diff --git a/kern/kernel_stats.hh b/kern/kernel_stats.hh index 6689dad01..c0a7fb858 100644 --- a/kern/kernel_stats.hh +++ b/kern/kernel_stats.hh @@ -150,7 +150,7 @@ class Statistics : public Serializable Stats::Vector<> _callpal; Stats::Vector<> _syscall; - Stats::Vector<> _faults; +// Stats::Vector<> _faults; Stats::Vector<> _mode; Stats::Vector<> _modeGood; @@ -177,10 +177,8 @@ class Statistics : public Serializable void hwrei() { _hwrei++; } void fault(Fault fault) { - if(fault == NoFault) _faults[0]++; - else if(fault == MachineCheckFault) _faults[2]++; - else if(fault == AlignmentFault) _faults[7]++; - else _faults[fault->id]++; + if(fault != NoFault) + fault->stat()++; }// FIXME: When there are no generic system fault objects, this will go back to _faults[fault]++; } void swpipl(int ipl); void mode(cpu_mode newmode, ExecContext *xc); diff --git a/kern/linux/events.cc b/kern/linux/events.cc new file mode 100644 index 000000000..a781165ac --- /dev/null +++ b/kern/linux/events.cc @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2004-2006 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "arch/arguments.hh" +#include "base/trace.hh" +#include "cpu/exec_context.hh" +#include "kern/linux/events.hh" +#include "kern/linux/printk.hh" +#include "kern/system_events.hh" + + +namespace Linux { + +void +DebugPrintkEvent::process(ExecContext *xc) +{ + if (DTRACE(DebugPrintf)) { + if (!raw) { + StringWrap name(xc->system->name() + ".dprintk"); + DPRINTFN(""); + } + + AlphaArguments args(xc); + Printk(args); + SkipFuncEvent::process(xc); + } +} + +} // namespace linux diff --git a/kern/linux/events.hh b/kern/linux/events.hh new file mode 100644 index 000000000..95c268976 --- /dev/null +++ b/kern/linux/events.hh @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2004-2006 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __KERN_LINUX_EVENTS_HH__ +#define __KERN_LINUX_EVENTS_HH__ + +#include "kern/system_events.hh" + +namespace Linux { + +class DebugPrintkEvent : public SkipFuncEvent +{ + private: + bool raw; + + public: + DebugPrintkEvent(PCEventQueue *q, const std::string &desc, Addr addr, + bool r = false) + : SkipFuncEvent(q, desc, addr), raw(r) {} + virtual void process(ExecContext *xc); +}; + +} + +#endif diff --git a/kern/linux/printk.cc b/kern/linux/printk.cc index fbc8bdad1..f5313759b 100644 --- a/kern/linux/printk.cc +++ b/kern/linux/printk.cc @@ -30,7 +30,7 @@ #include <algorithm> #include "base/trace.hh" -#include "targetarch/arguments.hh" +#include "arch/arguments.hh" using namespace std; diff --git a/kern/tru64/dump_mbuf.cc b/kern/tru64/dump_mbuf.cc index 5ce7570ca..25ed82ef3 100644 --- a/kern/tru64/dump_mbuf.cc +++ b/kern/tru64/dump_mbuf.cc @@ -34,9 +34,9 @@ #include "cpu/exec_context.hh" #include "kern/tru64/mbuf.hh" #include "sim/host.hh" -#include "targetarch/arguments.hh" +#include "arch/arguments.hh" #include "arch/isa_traits.hh" -#include "targetarch/vtophys.hh" +#include "arch/vtophys.hh" using namespace TheISA; diff --git a/kern/tru64/printf.cc b/kern/tru64/printf.cc index 12a089c40..77ac17c3a 100644 --- a/kern/tru64/printf.cc +++ b/kern/tru64/printf.cc @@ -32,8 +32,8 @@ #include "base/cprintf.hh" #include "base/trace.hh" #include "sim/host.hh" -#include "targetarch/arguments.hh" -#include "targetarch/vtophys.hh" +#include "arch/arguments.hh" +#include "arch/vtophys.hh" using namespace std; diff --git a/kern/tru64/tru64.hh b/kern/tru64/tru64.hh index 70abfaf6b..112f00f31 100644 --- a/kern/tru64/tru64.hh +++ b/kern/tru64/tru64.hh @@ -155,15 +155,16 @@ class Tru64 { /// implementing another set of stat functions using the old /// structure definition and binding them to the old syscall /// numbers. + struct pre_F64_stat { dev_t st_dev; ino_t st_ino; mode_t st_mode; nlink_t st_nlink; - uid_t st_uid; + uid_t st_uid __attribute__ ((aligned(sizeof(uid_t)))); gid_t st_gid; dev_t st_rdev; - off_t st_size; + off_t st_size __attribute__ ((aligned(sizeof(off_t)))); time_t st_atimeX; int32_t st_uatime; time_t st_mtimeX; diff --git a/kern/tru64/tru64_events.cc b/kern/tru64/tru64_events.cc index d41aa5f61..12aae6950 100644 --- a/kern/tru64/tru64_events.cc +++ b/kern/tru64/tru64_events.cc @@ -33,7 +33,7 @@ #include "kern/tru64/dump_mbuf.hh" #include "kern/tru64/printf.hh" #include "mem/functional/memory_control.hh" -#include "targetarch/arguments.hh" +#include "arch/arguments.hh" #include "arch/isa_traits.hh" using namespace TheISA; diff --git a/python/m5/objects/Ethernet.py b/python/m5/objects/Ethernet.py index 3a7f88d04..6113e656f 100644 --- a/python/m5/objects/Ethernet.py +++ b/python/m5/objects/Ethernet.py @@ -86,6 +86,7 @@ class EtherDevBase(PciDevice): intr_delay = Param.Latency('10us', "Interrupt propagation delay") rx_thread = Param.Bool(False, "dedicated kernel thread for transmit") tx_thread = Param.Bool(False, "dedicated kernel threads for receive") + rss = Param.Bool(False, "Receive Side Scaling") class NSGigE(EtherDevBase): type = 'NSGigE' diff --git a/python/m5/objects/System.py b/python/m5/objects/System.py index 6d1d6a68c..5925cadf5 100644 --- a/python/m5/objects/System.py +++ b/python/m5/objects/System.py @@ -1,17 +1,21 @@ from m5 import * + class System(SimObject): type = 'System' boot_cpu_frequency = Param.Frequency(Self.cpu[0].clock.frequency, "boot processor frequency") memctrl = Param.MemoryController(Parent.any, "memory controller") physmem = Param.PhysicalMemory(Parent.any, "phsyical memory") + init_param = Param.UInt64(0, "numerical value to pass into simulator") + bin = Param.Bool(False, "is this system binned") + binned_fns = VectorParam.String([], "functions broken down and binned") kernel = Param.String("file that contains the kernel code") + readfile = Param.String("", "file to read startup script from") + +class AlphaSystem(System): + type = 'AlphaSystem' console = Param.String("file that contains the console code") pal = Param.String("file that contains palcode") - readfile = Param.String("", "file to read startup script from") - init_param = Param.UInt64(0, "numerical value to pass into simulator") boot_osflags = Param.String("a", "boot flags to pass to the kernel") system_type = Param.UInt64("Type of system we are emulating") system_rev = Param.UInt64("Revision of system we are emulating") - bin = Param.Bool(False, "is this system binned") - binned_fns = VectorParam.String([], "functions broken down and binned") diff --git a/sim/faults.cc b/sim/faults.cc index 58a631263..9b4a0ea7f 100644 --- a/sim/faults.cc +++ b/sim/faults.cc @@ -27,10 +27,11 @@ */ #include "sim/faults.hh" +#include "cpu/exec_context.hh" -NoFaultType * const NoFault = new NoFaultType("none"); -MachineCheckFaultType * const MachineCheckFault = - new MachineCheckFaultType("mchk"); -AlignmentFaultType * const AlignmentFault = - new AlignmentFaultType("unalign"); - +#if !FULL_SYSTEM +void FaultBase::invoke(ExecContext * xc) +{ + fatal("fault (%s) detected @ PC 0x%08p", name(), xc->readPC()); +} +#endif diff --git a/sim/faults.hh b/sim/faults.hh index dbec399af..9e8d224cd 100644 --- a/sim/faults.hh +++ b/sim/faults.hh @@ -29,34 +29,40 @@ #ifndef __FAULTS_HH__ #define __FAULTS_HH__ +#include "base/refcnt.hh" +#include "sim/stats.hh" +#include "config/full_system.hh" + +class ExecContext; class FaultBase; -typedef FaultBase * Fault; +typedef RefCountingPtr<FaultBase> Fault; -class FaultBase -{ -public: - FaultBase(char * newName, int newId = 0) : name(newName), id(newId) {;} - const char * name; - int id; -}; +typedef const char * FaultName; +typedef Stats::Scalar<> FaultStat; -extern class NoFaultType : public FaultBase -{ -public: - NoFaultType(char * newName) : FaultBase(newName) {;} -} * const NoFault; +// Each class has it's name statically define in _name, +// and has a virtual function to access it's name. +// The function is necessary because otherwise, all objects +// which are being accessed cast as a FaultBase * (namely +// all faults returned using the Fault type) will use the +// generic FaultBase name. -extern class MachineCheckFaultType : public FaultBase +class FaultBase : public RefCounted { -public: - MachineCheckFaultType(char * newName) : FaultBase(newName) {;} -} * const MachineCheckFault; - -extern class AlignmentFaultType : public FaultBase -{ -public: - AlignmentFaultType(char * newName) : FaultBase(newName) {;} -} * const AlignmentFault; + public: + virtual FaultName name() = 0; + virtual FaultStat & stat() = 0; +#if FULL_SYSTEM + virtual void invoke(ExecContext * xc) = 0; +#else + virtual void invoke(ExecContext * xc); +#endif +// template<typename T> +// bool isA() {return dynamic_cast<T *>(this);} + virtual bool isMachineCheckFault() {return false;} + virtual bool isAlignmentFault() {return false;} +}; +FaultBase * const NoFault = 0; #endif // __FAULTS_HH__ diff --git a/sim/process.cc b/sim/process.cc index 9da93488e..851192dcd 100644 --- a/sim/process.cc +++ b/sim/process.cc @@ -49,10 +49,7 @@ #include "sim/stats.hh" #include "sim/syscall_emul.hh" -#ifdef TARGET_ALPHA -#include "arch/alpha/alpha_tru64_process.hh" -#include "arch/alpha/alpha_linux_process.hh" -#endif +#include "arch/process.hh" using namespace std; using namespace TheISA; @@ -381,27 +378,10 @@ LiveProcess::create(const string &nm, fatal("Can't load object file %s", executable); } - // check object type & set up syscall emulation pointer - if (objFile->getArch() == ObjectFile::Alpha) { - switch (objFile->getOpSys()) { - case ObjectFile::Tru64: - process = new AlphaTru64Process(nm, objFile, - stdin_fd, stdout_fd, stderr_fd, - argv, envp); - break; - - case ObjectFile::Linux: - process = new AlphaLinuxProcess(nm, objFile, - stdin_fd, stdout_fd, stderr_fd, - argv, envp); - break; - - default: - fatal("Unknown/unsupported operating system."); - } - } else { - fatal("Unknown object file architecture."); - } + // set up syscall emulation pointer for the current ISA + process = createProcess(nm, objFile, + stdin_fd, stdout_fd, stderr_fd, + argv, envp); delete objFile; diff --git a/sim/pseudo_inst.cc b/sim/pseudo_inst.cc index f46f6acf4..85b26ef23 100644 --- a/sim/pseudo_inst.cc +++ b/sim/pseudo_inst.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2003-2005 The Regents of The University of Michigan + * Copyright (c) 2003-2006 The Regents of The University of Michigan * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -34,7 +34,7 @@ #include <string> #include "sim/pseudo_inst.hh" -#include "targetarch/vtophys.hh" +#include "arch/vtophys.hh" #include "cpu/base.hh" #include "cpu/sampler/sampler.hh" #include "cpu/exec_context.hh" @@ -78,6 +78,42 @@ namespace AlphaPseudo } void + quiesceNs(ExecContext *xc, uint64_t ns) + { + if (!doQuiesce || ns == 0) + return; + + if (xc->quiesceEvent.scheduled()) + xc->quiesceEvent.reschedule(curTick + Clock::Int::ns * ns); + else + xc->quiesceEvent.schedule(curTick + Clock::Int::ns * ns); + + xc->suspend(); + xc->kernelStats->quiesce(); + } + + void + quiesceCycles(ExecContext *xc, uint64_t cycles) + { + if (!doQuiesce || cycles == 0) + return; + + if (xc->quiesceEvent.scheduled()) + xc->quiesceEvent.reschedule(curTick + xc->cpu->cycles(cycles)); + else + xc->quiesceEvent.schedule(curTick + xc->cpu->cycles(cycles)); + + xc->suspend(); + xc->kernelStats->quiesce(); + } + + uint64_t + quiesceTime(ExecContext *xc) + { + return (xc->lastActivate - xc->lastSuspend) / Clock::Int::ns ; + } + + void ivlb(ExecContext *xc) { xc->getCpuPtr()->kernelStats->ivlb(); @@ -171,7 +207,7 @@ namespace AlphaPseudo uint64_t readfile(ExecContext *xc, Addr vaddr, uint64_t len, uint64_t offset) { - const string &file = xc->getCpuPtr()->system->params->readfile; + const string &file = xc->getCpuPtr()->system->params()->readfile; if (file.empty()) { return ULL(0); } diff --git a/sim/pseudo_inst.hh b/sim/pseudo_inst.hh index 3857f2050..4dd427c99 100644 --- a/sim/pseudo_inst.hh +++ b/sim/pseudo_inst.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2003-2005 The Regents of The University of Michigan + * Copyright (c) 2003-2006 The Regents of The University of Michigan * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -44,6 +44,9 @@ namespace AlphaPseudo void arm(ExecContext *xc); void quiesce(ExecContext *xc); + void quiesceNs(ExecContext *xc, uint64_t ns); + void quiesceCycles(ExecContext *xc, uint64_t cycles); + uint64_t quiesceTime(ExecContext *xc); void ivlb(ExecContext *xc); void ivle(ExecContext *xc); void m5exit(ExecContext *xc, Tick delay); diff --git a/sim/syscall_emul.hh b/sim/syscall_emul.hh index 32f98600c..cadaa1cd3 100644 --- a/sim/syscall_emul.hh +++ b/sim/syscall_emul.hh @@ -380,7 +380,7 @@ chmodFunc(SyscallDesc *desc, int callnum, Process *process, // do the chmod int result = chmod(path.c_str(), hostMode); if (result < 0) - return errno; + return -errno; return 0; } @@ -407,7 +407,7 @@ fchmodFunc(SyscallDesc *desc, int callnum, Process *process, // do the fchmod int result = fchmod(process->sim_fd(fd), hostMode); if (result < 0) - return errno; + return -errno; return 0; } @@ -428,7 +428,7 @@ statFunc(SyscallDesc *desc, int callnum, Process *process, int result = stat(path.c_str(), &hostBuf); if (result < 0) - return errno; + return -errno; OS::copyOutStatBuf(xc->getMemPtr(), xc->getSyscallArg(1), &hostBuf); @@ -457,7 +457,7 @@ fstat64Func(SyscallDesc *desc, int callnum, Process *process, #endif if (result < 0) - return errno; + return -errno; OS::copyOutStat64Buf(xc->getMemPtr(), fd, xc->getSyscallArg(1), &hostBuf); @@ -553,7 +553,7 @@ statfsFunc(SyscallDesc *desc, int callnum, Process *process, int result = statfs(path.c_str(), &hostBuf); if (result < 0) - return errno; + return -errno; OS::copyOutStatfsBuf(xc->getMemPtr(), xc->getSyscallArg(1), &hostBuf); @@ -576,7 +576,7 @@ fstatfsFunc(SyscallDesc *desc, int callnum, Process *process, int result = fstatfs(fd, &hostBuf); if (result < 0) - return errno; + return -errno; OS::copyOutStatfsBuf(xc->getMemPtr(), xc->getSyscallArg(1), &hostBuf); @@ -618,7 +618,7 @@ writevFunc(SyscallDesc *desc, int callnum, Process *process, } if (result < 0) - return errno; + return -errno; return 0; } diff --git a/sim/system.cc b/sim/system.cc index 41de8cee4..8820922c1 100644 --- a/sim/system.cc +++ b/sim/system.cc @@ -1,31 +1,3 @@ -/* - * Copyright (c) 2002-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - #include "base/loader/object_file.hh" #include "base/loader/symtab.hh" #include "base/remote_gdb.hh" @@ -33,7 +5,7 @@ #include "kern/kernel_stats.hh" #include "mem/functional/memory_control.hh" #include "mem/functional/physical.hh" -#include "targetarch/vtophys.hh" +#include "arch/vtophys.hh" #include "sim/builder.hh" #include "arch/isa_traits.hh" #include "sim/byteswap.hh" @@ -49,38 +21,23 @@ int System::numSystemsRunning = 0; System::System(Params *p) : SimObject(p->name), memctrl(p->memctrl), physmem(p->physmem), - init_param(p->init_param), numcpus(0), params(p) + init_param(p->init_param), numcpus(0), _params(p) { // add self to global system list systemList.push_back(this); kernelSymtab = new SymbolTable; - consoleSymtab = new SymbolTable; - palSymtab = new SymbolTable; debugSymbolTable = new SymbolTable; /** - * Load the kernel, pal, and console code into memory + * Load the kernel code into memory */ // Load kernel code - kernel = createObjectFile(params->kernel_path); + kernel = createObjectFile(params()->kernel_path); if (kernel == NULL) - fatal("Could not load kernel file %s", params->kernel_path); - - // Load Console Code - console = createObjectFile(params->console_path); - if (console == NULL) - fatal("Could not load console file %s", params->console_path); - - // Load pal file - pal = createObjectFile(params->palcode); - if (pal == NULL) - fatal("Could not load PALcode file %s", params->palcode); - + fatal("Could not load kernel file %s", params()->kernel_path); // Load program sections into memory - pal->loadSections(physmem, true); - console->loadSections(physmem, true); kernel->loadSections(physmem, true); // setup entry points @@ -95,71 +52,17 @@ System::System(Params *p) if (!kernel->loadLocalSymbols(kernelSymtab)) panic("could not load kernel local symbols\n"); - if (!console->loadGlobalSymbols(consoleSymtab)) - panic("could not load console symbols\n"); - - if (!pal->loadGlobalSymbols(palSymtab)) - panic("could not load pal symbols\n"); - - if (!pal->loadLocalSymbols(palSymtab)) - panic("could not load pal symbols\n"); - if (!kernel->loadGlobalSymbols(debugSymbolTable)) panic("could not load kernel symbols\n"); if (!kernel->loadLocalSymbols(debugSymbolTable)) panic("could not load kernel local symbols\n"); - if (!console->loadGlobalSymbols(debugSymbolTable)) - panic("could not load console symbols\n"); - - if (!pal->loadGlobalSymbols(debugSymbolTable)) - panic("could not load pal symbols\n"); - - if (!pal->loadLocalSymbols(debugSymbolTable)) - panic("could not load pal symbols\n"); - - DPRINTF(Loader, "Kernel start = %#x\n", kernelStart); DPRINTF(Loader, "Kernel end = %#x\n", kernelEnd); DPRINTF(Loader, "Kernel entry = %#x\n", kernelEntry); DPRINTF(Loader, "Kernel loaded...\n"); - Addr addr = 0; -#ifndef NDEBUG - consolePanicEvent = addConsoleFuncEvent<BreakPCEvent>("panic"); -#endif - - /** - * Copy the osflags (kernel arguments) into the consoles - * memory. (Presently Linux does not use the console service - * routine to get these command line arguments, but Tru64 and - * others do.) - */ - if (consoleSymtab->findAddress("env_booted_osflags", addr)) { - Addr paddr = vtophys(physmem, addr); - char *osflags = (char *)physmem->dma_addr(paddr, sizeof(uint32_t)); - - if (osflags) - strcpy(osflags, params->boot_osflags.c_str()); - } - - /** - * Set the hardware reset parameter block system type and revision - * information to Tsunami. - */ - if (consoleSymtab->findAddress("m5_rpb", addr)) { - Addr paddr = vtophys(physmem, addr); - char *hwrpb = (char *)physmem->dma_addr(paddr, sizeof(uint64_t)); - - if (!hwrpb) - panic("could not translate hwrpb addr\n"); - - *(uint64_t*)(hwrpb+0x50) = htog(params->system_type); - *(uint64_t*)(hwrpb+0x58) = htog(params->system_rev); - } else - panic("could not find hwrpb\n"); - // increment the number of running systms numSystemsRunning++; @@ -169,100 +72,13 @@ System::System(Params *p) System::~System() { delete kernelSymtab; - delete consoleSymtab; delete kernel; - delete console; - delete pal; delete kernelBinning; - -#ifdef DEBUG - delete consolePanicEvent; -#endif } -/** - * This function fixes up addresses that are used to match PCs for - * hooking simulator events on to target function executions. - * - * Alpha binaries may have multiple global offset table (GOT) - * sections. A function that uses the GOT starts with a - * two-instruction prolog which sets the global pointer (gp == r29) to - * the appropriate GOT section. The proper gp value is calculated - * based on the function address, which must be passed by the caller - * in the procedure value register (pv aka t12 == r27). This sequence - * looks like the following: - * - * opcode Ra Rb offset - * ldah gp,X(pv) 09 29 27 X - * lda gp,Y(gp) 08 29 29 Y - * - * for some constant offsets X and Y. The catch is that the linker - * (or maybe even the compiler, I'm not sure) may recognize that the - * caller and callee are using the same GOT section, making this - * prolog redundant, and modify the call target to skip these - * instructions. If we check for execution of the first instruction - * of a function (the one the symbol points to) to detect when to skip - * it, we'll miss all these modified calls. It might work to - * unconditionally check for the third instruction, but not all - * functions have this prolog, and there's some chance that those - * first two instructions could have undesired consequences. So we do - * the Right Thing and pattern-match the first two instructions of the - * function to decide where to patch. - * - * Eventually this code should be moved into an ISA-specific file. - */ -Addr -System::fixFuncEventAddr(Addr addr) -{ - // mask for just the opcode, Ra, and Rb fields (not the offset) - const uint32_t inst_mask = 0xffff0000; - // ldah gp,X(pv): opcode 9, Ra = 29, Rb = 27 - const uint32_t gp_ldah_pattern = (9 << 26) | (29 << 21) | (27 << 16); - // lda gp,Y(gp): opcode 8, Ra = 29, rb = 29 - const uint32_t gp_lda_pattern = (8 << 26) | (29 << 21) | (29 << 16); - // instruction size - const int sz = sizeof(uint32_t); - - Addr paddr = vtophys(physmem, addr); - uint32_t i1 = *(uint32_t *)physmem->dma_addr(paddr, sz); - uint32_t i2 = *(uint32_t *)physmem->dma_addr(paddr+sz, sz); - - if ((i1 & inst_mask) == gp_ldah_pattern && - (i2 & inst_mask) == gp_lda_pattern) { - Addr new_addr = addr + 2*sz; - DPRINTF(Loader, "fixFuncEventAddr: %p -> %p", addr, new_addr); - return new_addr; - } else { - return addr; - } -} - - -void -System::setAlphaAccess(Addr access) -{ - Addr addr = 0; - if (consoleSymtab->findAddress("m5AlphaAccess", addr)) { - Addr paddr = vtophys(physmem, addr); - uint64_t *m5AlphaAccess = - (uint64_t *)physmem->dma_addr(paddr, sizeof(uint64_t)); - - if (!m5AlphaAccess) - panic("could not translate m5AlphaAccess addr\n"); - - *m5AlphaAccess = htog(EV5::Phys2K0Seg(access)); - } else - panic("could not find m5AlphaAccess\n"); -} - -bool -System::breakpoint() -{ - return remoteGDB[0]->trap(ALPHA_KENTRY_INT); -} int rgdb_wait = -1; @@ -336,8 +152,6 @@ System::serialize(ostream &os) kernelBinning->serialize(os); kernelSymtab->serialize("kernel_symtab", os); - consoleSymtab->serialize("console_symtab", os); - palSymtab->serialize("pal_symtab", os); } @@ -347,8 +161,6 @@ System::unserialize(Checkpoint *cp, const string §ion) kernelBinning->unserialize(cp, section); kernelSymtab->unserialize("kernel_symtab", cp, section); - consoleSymtab->unserialize("console_symtab", cp, section); - palSymtab->unserialize("pal_symtab", cp, section); } void @@ -369,69 +181,5 @@ printSystems() System::printSystems(); } -BEGIN_DECLARE_SIM_OBJECT_PARAMS(System) - - Param<Tick> boot_cpu_frequency; - SimObjectParam<MemoryController *> memctrl; - SimObjectParam<PhysicalMemory *> physmem; - - Param<string> kernel; - Param<string> console; - Param<string> pal; - - Param<string> boot_osflags; - Param<string> readfile; - Param<unsigned int> init_param; - - Param<uint64_t> system_type; - Param<uint64_t> system_rev; - - Param<bool> bin; - VectorParam<string> binned_fns; - Param<bool> bin_int; - -END_DECLARE_SIM_OBJECT_PARAMS(System) - -BEGIN_INIT_SIM_OBJECT_PARAMS(System) - - INIT_PARAM(boot_cpu_frequency, "Frequency of the boot CPU"), - INIT_PARAM(memctrl, "memory controller"), - INIT_PARAM(physmem, "phsyical memory"), - INIT_PARAM(kernel, "file that contains the kernel code"), - INIT_PARAM(console, "file that contains the console code"), - INIT_PARAM(pal, "file that contains palcode"), - INIT_PARAM_DFLT(boot_osflags, "flags to pass to the kernel during boot", - "a"), - INIT_PARAM_DFLT(readfile, "file to read startup script from", ""), - INIT_PARAM_DFLT(init_param, "numerical value to pass into simulator", 0), - INIT_PARAM_DFLT(system_type, "Type of system we are emulating", 34), - INIT_PARAM_DFLT(system_rev, "Revision of system we are emulating", 1<<10), - INIT_PARAM_DFLT(bin, "is this system to be binned", false), - INIT_PARAM(binned_fns, "functions to be broken down and binned"), - INIT_PARAM_DFLT(bin_int, "is interrupt code binned seperately?", true) - -END_INIT_SIM_OBJECT_PARAMS(System) - -CREATE_SIM_OBJECT(System) -{ - System::Params *p = new System::Params; - p->name = getInstanceName(); - p->boot_cpu_frequency = boot_cpu_frequency; - p->memctrl = memctrl; - p->physmem = physmem; - p->kernel_path = kernel; - p->console_path = console; - p->palcode = pal; - p->boot_osflags = boot_osflags; - p->init_param = init_param; - p->readfile = readfile; - p->system_type = system_type; - p->system_rev = system_rev; - p->bin = bin; - p->binned_fns = binned_fns; - p->bin_int = bin_int; - return new System(p); -} - -REGISTER_SIM_OBJECT("System", System) +DEFINE_SIM_OBJECT_CLASS_NAME("System", System) diff --git a/sim/system.hh b/sim/system.hh index aa697c040..ea482a102 100644 --- a/sim/system.hh +++ b/sim/system.hh @@ -71,21 +71,9 @@ class System : public SimObject /** kernel symbol table */ SymbolTable *kernelSymtab; - /** console symbol table */ - SymbolTable *consoleSymtab; - - /** pal symbol table */ - SymbolTable *palSymtab; - /** Object pointer for the kernel code */ ObjectFile *kernel; - /** Object pointer for the console code */ - ObjectFile *console; - - /** Object pointer for the PAL code */ - ObjectFile *pal; - /** Begining of kernel code */ Addr kernelStart; @@ -97,11 +85,6 @@ class System : public SimObject Kernel::Binning *kernelBinning; -#ifndef NDEBUG - /** Event to halt the simulator if the console calls panic() */ - BreakPCEvent *consolePanicEvent; -#endif - protected: /** @@ -109,7 +92,7 @@ class System : public SimObject * events on to target function executions. See comment in * system.cc for details. */ - Addr fixFuncEventAddr(Addr addr); + virtual Addr fixFuncEventAddr(Addr addr) = 0; /** * Add a function-based event to the given function, to be looked @@ -135,24 +118,10 @@ class System : public SimObject return addFuncEvent<T>(kernelSymtab, lbl); } - /** Add a function-based event to PALcode. */ - template <class T> - T *System::addPalFuncEvent(const char *lbl) - { - return addFuncEvent<T>(palSymtab, lbl); - } - - /** Add a function-based event to the console code. */ - template <class T> - T *System::addConsoleFuncEvent(const char *lbl) - { - return addFuncEvent<T>(consoleSymtab, lbl); - } - public: std::vector<RemoteGDB *> remoteGDB; std::vector<GDBListener *> gdbListen; - bool breakpoint(); + virtual bool breakpoint() = 0; public: struct Params @@ -167,27 +136,21 @@ class System : public SimObject bool bin_int; std::string kernel_path; - std::string console_path; - std::string palcode; - std::string boot_osflags; - std::string readfile; - uint64_t system_type; - uint64_t system_rev; }; - Params *params; + protected: + Params *_params; + + public: System(Params *p); ~System(); void startup(); - public: - /** - * Set the m5AlphaAccess pointer in the console - */ - void setAlphaAccess(Addr access); + const Params *params() const { return (const Params *)_params; } + public: /** * Returns the addess the kernel starts at. * @return address the kernel starts at @@ -224,6 +187,8 @@ class System : public SimObject static int numSystemsRunning; static void printSystems(); + + }; #endif // __SYSTEM_HH__ diff --git a/sim/vptr.hh b/sim/vptr.hh index 7ec43602d..0ec452f25 100644 --- a/sim/vptr.hh +++ b/sim/vptr.hh @@ -29,7 +29,7 @@ #ifndef __ARCH_ALPHA_VPTR_HH__ #define __ARCH_ALPHA_VPTR_HH__ -#include "targetarch/vtophys.hh" +#include "arch/vtophys.hh" #include "arch/isa_traits.hh" class ExecContext; diff --git a/util/m5/Makefile b/util/m5/Makefile index 6e4ad31a3..518542322 100644 --- a/util/m5/Makefile +++ b/util/m5/Makefile @@ -1,26 +1,50 @@ -AS=as -CC=cc -LD=cc +# Copyright (c) 2005-2006 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -CCFLAGS=-O2 -#LDFLAGS=-non_shared +### If we are not compiling on an alpha, we must use cross tools ### +ifneq ($(shell uname -m), alpha) +CROSS_COMPILE?=alpha-unknown-linux-gnu- +endif +CC=$(CROSS_COMPILE)gcc +AS=$(CROSS_COMPILE)as +LD=$(CROSS_COMPILE)ld -all: m5 +CFLAGS=-O2 +OBJS=m5.o m5op.o -m5: m5op.o m5.o - $(LD) $(LDFLAGS) -o $@ $> - strip $@ +all: m5 -clean: - @rm -f m5 *.o *.d *~ .#* +%.o: %.S + $(CC) $(CFLAGS) -o $@ -c $< -.SUFFIXES: -.SUFFIXES:.o .c .s +%.o: %.c + $(CC) $(CFLAGS) -o $@ -c $< -# C Compilation -.c.o: - $(CC) $(CCFLAGS) -o $@ -c $< +m5: $(OBJS) + $(CC) -o $@ $(OBJS) -# Assembly -.s.o: - $(AS) $(ASFLAGS) -o $@ $< +clean: + rm -f *.o m5 diff --git a/util/m5/m5.c b/util/m5/m5.c index 942ad5ba4..6fdbc0500 100644 --- a/util/m5/m5.c +++ b/util/m5/m5.c @@ -73,7 +73,7 @@ main(int argc, char *argv[]) usage(); arg1 = strtoul(argv[2], NULL, 0); - ivlb(arg1); + m5_ivlb(arg1); return 0; } @@ -82,7 +82,7 @@ main(int argc, char *argv[]) usage(); arg1 = strtoul(argv[2], NULL, 0); - ivle(arg1); + m5_ivle(arg1); return 0; } @@ -90,7 +90,7 @@ main(int argc, char *argv[]) if (argc != 2) usage(); - printf("%ld", initparam()); + printf("%ld", m5_initparam()); return 0; } @@ -98,7 +98,7 @@ main(int argc, char *argv[]) if (argc != 2) usage(); - param = initparam(); + param = m5_initparam(); // run-time, rampup-time, rampdown-time, warmup-time, connections printf("%d %d %d %d %d", (param >> 48) & 0xfff, (param >> 36) & 0xfff, (param >> 24) & 0xfff, @@ -112,7 +112,7 @@ main(int argc, char *argv[]) case 3: arg1 = strtoul(argv[2], NULL, 0); case 2: - m5exit(arg1); + m5_exit(arg1); return 0; default: @@ -127,7 +127,7 @@ main(int argc, char *argv[]) case 3: arg1 = strtoul(argv[2], NULL, 0); case 2: - reset_stats(arg1, arg2); + m5_reset_stats(arg1, arg2); return 0; default: @@ -142,7 +142,7 @@ main(int argc, char *argv[]) case 3: arg1 = strtoul(argv[2], NULL, 0); case 2: - dump_stats(arg1, arg2); + m5_dump_stats(arg1, arg2); return 0; default: @@ -157,7 +157,7 @@ main(int argc, char *argv[]) case 3: arg1 = strtoul(argv[2], NULL, 0); case 2: - dumpreset_stats(arg1, arg2); + m5_dumpreset_stats(arg1, arg2); return 0; default: @@ -172,7 +172,7 @@ main(int argc, char *argv[]) case 3: arg1 = strtoul(argv[2], NULL, 0); case 2: - checkpoint(arg1, arg2); + m5_checkpoint(arg1, arg2); return 0; default: diff --git a/util/m5/m5op.S b/util/m5/m5op.S new file mode 100644 index 000000000..a53c45277 --- /dev/null +++ b/util/m5/m5op.S @@ -0,0 +1,196 @@ +/* + * Copyright (c) 2003-2006 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#define m5_op 0x01 + +#define arm_func 0x00 +#define quiesce_func 0x01 +#define quiescens_func 0x02 +#define quiescecycle_func 0x03 +#define quiescetime_func 0x04 +#define ivlb_func 0x10 +#define ivle_func 0x11 +#define exit_old_func 0x20 // deprectated! +#define exit_func 0x21 +#define initparam_func 0x30 +#define resetstats_func 0x40 +#define dumpstats_func 0x41 +#define dumprststats_func 0x42 +#define ckpt_func 0x43 +#define readfile_func 0x50 +#define debugbreak_func 0x51 +#define switchcpu_func 0x52 +#define addsymbol_func 0x53 +#define panic_func 0x54 + +#define INST(op, ra, rb, func) \ + .long (((op) << 26) | ((ra) << 21) | ((rb) << 16) | (func)) + +#define LEAF(func) \ + .align 3; \ + .globl func; \ + .ent func; \ +func: + +#define RET \ + ret ($26) + +#define END(func) \ + .end func + +#define ARM(reg) INST(m5_op, reg, 0, arm_func) +#define QUIESCE INST(m5_op, 0, 0, quiesce_func) +#define QUIESCENS(r1) INST(m5_op, r1, 0, quiescens_func) +#define QUIESCECYC(r1) INST(m5_op, r1, 0, quiescecycle_func) +#define QUIESCETIME INST(m5_op, 0, 0, quiescetime_func) +#define IVLB(reg) INST(m5_op, reg, 0, ivlb_func) +#define IVLE(reg) INST(m5_op, reg, 0, ivle_func) +#define M5EXIT(reg) INST(m5_op, reg, 0, exit_func) +#define INITPARAM(reg) INST(m5_op, reg, 0, initparam_func) +#define RESET_STATS(r1, r2) INST(m5_op, r1, r2, resetstats_func) +#define DUMP_STATS(r1, r2) INST(m5_op, r1, r2, dumpstats_func) +#define DUMPRST_STATS(r1, r2) INST(m5_op, r1, r2, dumprststats_func) +#define CHECKPOINT(r1, r2) INST(m5_op, r1, r2, ckpt_func) +#define READFILE INST(m5_op, 0, 0, readfile_func) +#define DEBUGBREAK INST(m5_op, 0, 0, debugbreak_func) +#define SWITCHCPU INST(m5_op, 0, 0, switchcpu_func) +#define ADDSYMBOL(r1,r2) INST(m5_op, r1, r2, addsymbol_func) +#define PANIC INST(m5_op, 0, 0, panic_func) + + .set noreorder + + .align 4 +LEAF(arm) + ARM(16) + RET +END(arm) + + .align 4 +LEAF(quiesce) + QUIESCE + RET +END(quiesce) + + .align 4 +LEAF(quiesceNs) + QUIESCENS(16) + RET +END(quiesceNs) + + .align 4 +LEAF(quiesceCycle) + QUIESCECYC(16) + RET +END(quiesceCycle) + + .align 4 +LEAF(quiesceTime) + QUIESCETIME + RET +END(quiesceTime) + + + .align 4 +LEAF(m5_ivlb) + IVLB(16) + RET +END(m5_ivlb) + + .align 4 +LEAF(m5_ivle) + IVLE(16) + RET +END(m5_ivle) + + .align 4 +LEAF(m5_exit) + M5EXIT(16) + RET +END(m5_exit) + + .align 4 +LEAF(m5_initparam) + INITPARAM(0) + RET +END(m5_initparam) + + .align 4 +LEAF(m5_reset_stats) + RESET_STATS(16, 17) + RET +END(m5_reset_stats) + + .align 4 +LEAF(m5_dump_stats) + DUMP_STATS(16, 17) + RET +END(m5_dump_stats) + + .align 4 +LEAF(m5_dumpreset_stats) + DUMPRST_STATS(16, 17) + RET +END(m5_dumpreset_stats) + + .align 4 +LEAF(m5_checkpoint) + CHECKPOINT(16, 17) + RET +END(m5_checkpoint) + + .align 4 +LEAF(m5_readfile) + READFILE + RET +END(m5_readfile) + + .align 4 +LEAF(m5_debugbreak) + DEBUGBREAK + RET +END(m5_debugbreak) + + .align 4 +LEAF(m5_switchcpu) + SWITCHCPU + RET +END(m5_switchcpu) + + .align 4 +LEAF(m5_addsymbol) + ADDSYMBOL(16, 17) + RET +END(m5_addsymbol) + + .align 4 +LEAF(m5_panic) + PANIC + RET +END(m5_panic) + + diff --git a/util/m5/m5op.h b/util/m5/m5op.h index 91dc4cc8b..34ac7760d 100644 --- a/util/m5/m5op.h +++ b/util/m5/m5op.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2003-2005 The Regents of The University of Michigan + * Copyright (c) 2003-2006 The Regents of The University of Michigan * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -29,17 +29,26 @@ #ifndef __M5OP_H__ #define __M5OP_H__ -#include <inttypes.h> +#include <asm/types.h> void arm(uint64_t address); -void quiesce(); -void ivlb(uint64_t interval); -void ivle(uint64_t interval); -void m5exit(uint64_t ns_delay); -uint64_t initparam(); -void checkpoint(uint64_t ns_delay, uint64_t ns_period); -void reset_stats(uint64_t ns_delay, uint64_t ns_period); -void dump_stats(uint64_t ns_delay, uint64_t ns_period); -void dumpreset_stats(uint64_t ns_delay, uint64_t ns_period); +void quiesce(void); +void quiesceNs(uint64_t ns); +void quiesceCycle(uint64_t cycles); +uint64_t quiesceTime(void); + +void m5_ivlb(uint64_t interval); +void m5_ivle(uint64_t interval); +void m5_exit(uint64_t ns_delay); +uint64_t m5_initparam(void); +void m5_checkpoint(uint64_t ns_delay, uint64_t ns_period); +void m5_reset_stats(uint64_t ns_delay, uint64_t ns_period); +void m5_dump_stats(uint64_t ns_delay, uint64_t ns_period); +void m5_dumpreset_stats(uint64_t ns_delay, uint64_t ns_period); +uint64_t m5_readfile(void *buffer, uint64_t len, uint64_t offset); +void m5_debugbreak(void); +void m5_switchcpu(void); +void m5_addsymbol(uint64_t addr, char *symbol); +void m5_panic(void); #endif // __M5OP_H__ diff --git a/util/m5/m5op.s b/util/m5/m5op.s deleted file mode 100644 index e779e4209..000000000 --- a/util/m5/m5op.s +++ /dev/null @@ -1,121 +0,0 @@ -/* - * Copyright (c) 2003, 2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include <machine/asm.h> -#include <regdef.h> - -#define m5_op 0x01 - -#define arm_func 0x00 -#define quiesce_func 0x01 -#define ivlb_func 0x10 -#define ivle_func 0x11 -#define exit_old_func 0x20 // deprectated! -#define exit_func 0x21 -#define initparam_func 0x30 -#define resetstats_func 0x40 -#define dumpstats_func 0x41 -#define dumprststats_func 0x42 -#define ckpt_func 0x43 - -#define INST(op, ra, rb, func) \ - .long (((op) << 26) | ((ra) << 21) | ((rb) << 16) | (func)) - -#define ARM(reg) INST(m5_op, reg, 0, arm_func) -#define QUIESCE() INST(m5_op, 0, 0, quiesce_func) -#define IVLB(reg) INST(m5_op, reg, 0, ivlb_func) -#define IVLE(reg) INST(m5_op, reg, 0, ivle_func) -#define M5EXIT(reg) INST(m5_op, reg, 0, exit_func) -#define INITPARAM(reg) INST(m5_op, reg, 0, initparam_func) -#define RESET_STATS(r1, r2) INST(m5_op, r1, r2, resetstats_func) -#define DUMP_STATS(r1, r2) INST(m5_op, r1, r2, dumpstats_func) -#define DUMPRST_STATS(r1, r2) INST(m5_op, r1, r2, dumprststats_func) -#define CHECKPOINT(r1, r2) INST(m5_op, r1, r2, ckpt_func) - - .set noreorder - - .align 4 -LEAF(arm) - ARM(16) - RET -END(arm) - - .align 4 -LEAF(quiesce) - QUIESCE() - RET -END(quiesce) - - .align 4 -LEAF(ivlb) - IVLB(16) - RET -END(ivlb) - - .align 4 -LEAF(ivle) - IVLE(16) - RET -END(ivle) - - .align 4 -LEAF(m5exit) - M5EXIT(16) - RET -END(m5exit) - - .align 4 -LEAF(initparam) - INITPARAM(0) - RET -END(initparam) - - .align 4 -LEAF(reset_stats) - RESET_STATS(16, 17) - RET -END(reset_stats) - - .align 4 -LEAF(dump_stats) - DUMP_STATS(16, 17) - RET -END(dump_stats) - - .align 4 -LEAF(dumpreset_stats) - DUMPRST_STATS(16, 17) - RET -END(dumpreset_stats) - - .align 4 -LEAF(checkpoint) - CHECKPOINT(16, 17) - RET -END(checkpoint) - |