diff options
| -rw-r--r-- | src/arch/x86/insts/microregop.cc | 10 | ||||
| -rw-r--r-- | src/arch/x86/insts/microregop.hh | 4 | ||||
| -rw-r--r-- | src/arch/x86/isa/decoder/one_byte_opcodes.isa | 4 | ||||
| -rw-r--r-- | src/arch/x86/isa/insts/string/scan_string.py | 65 | ||||
| -rw-r--r-- | src/arch/x86/isa/microasm.isa | 6 |
5 files changed, 66 insertions, 23 deletions
diff --git a/src/arch/x86/insts/microregop.cc b/src/arch/x86/insts/microregop.cc index e67a82d4f..42c540b7a 100644 --- a/src/arch/x86/insts/microregop.cc +++ b/src/arch/x86/insts/microregop.cc @@ -112,8 +112,9 @@ namespace X86ISA panic("This condition is not implemented!"); case ConditionTests::MSTRC: panic("This condition is not implemented!"); - case ConditionTests::STRZnZF: - panic("This condition is not implemented!"); + case ConditionTests::STRZnEZF: + return !ccflags.EZF & ccflags.ZF; + //And no interrupts or debug traps are waiting case ConditionTests::OF: return ccflags.OF; case ConditionTests::CF: @@ -144,8 +145,9 @@ namespace X86ISA panic("This condition is not implemented!"); case ConditionTests::NotMSTRC: panic("This condition is not implemented!"); - case ConditionTests::NotSTRZnZF: - panic("This condition is not implemented!"); + case ConditionTests::STRnZnEZF: + return !ccflags.EZF & !ccflags.ZF; + //And no interrupts or debug traps are waiting case ConditionTests::NotOF: return !ccflags.OF; case ConditionTests::NotCF: diff --git a/src/arch/x86/insts/microregop.hh b/src/arch/x86/insts/microregop.hh index f465ac651..f6bebb763 100644 --- a/src/arch/x86/insts/microregop.hh +++ b/src/arch/x86/insts/microregop.hh @@ -73,7 +73,7 @@ namespace X86ISA MSTRZ, STRZ, MSTRC, - STRZnZF, + STRZnEZF, OF, CF, ZF, @@ -91,7 +91,7 @@ namespace X86ISA NotMSTRZ, NotSTRZ, NotMSTRC, - NotSTRZnZF, + STRnZnEZF, NotOF, NotCF, NotZF, diff --git a/src/arch/x86/isa/decoder/one_byte_opcodes.isa b/src/arch/x86/isa/decoder/one_byte_opcodes.isa index cce07d6fe..ee7fbc683 100644 --- a/src/arch/x86/isa/decoder/one_byte_opcodes.isa +++ b/src/arch/x86/isa/decoder/one_byte_opcodes.isa @@ -342,8 +342,8 @@ 0x3: stos_Yv_rAX(); 0x4: lods_Al_Xb(); 0x5: lods_rAX_Xv(); - 0x6: scas_Yb_Al(); - 0x7: scas_Yv_rAX(); + 0x6: StringInst::SCAS(Yb); + 0x7: StringInst::SCAS(Yv); } format Inst { 0x16: MOV(Bb,Ib); diff --git a/src/arch/x86/isa/insts/string/scan_string.py b/src/arch/x86/isa/insts/string/scan_string.py index cd3d5b549..b038cc00a 100644 --- a/src/arch/x86/isa/insts/string/scan_string.py +++ b/src/arch/x86/isa/insts/string/scan_string.py @@ -53,16 +53,55 @@ # # Authors: Gabe Black -microcode = "" -#let {{ -# class SCAS(Inst): -# "GenFault ${new UnimpInstFault}" -# class SCASB(Inst): -# "GenFault ${new UnimpInstFault}" -# class SCASW(Inst): -# "GenFault ${new UnimpInstFault}" -# class SCASD(Inst): -# "GenFault ${new UnimpInstFault}" -# class SCASQ(Inst): -# "GenFault ${new UnimpInstFault}" -#}}; +microcode = ''' +def macroop SCAS_M { + # Find the constant we need to either add or subtract from rdi + ruflag t0, 10 + movi t2, t2, dsz, flags=(CEZF,), dataSize=asz + subi t3, t0, dsz, dataSize=asz + mov t2, t2, t3, flags=(nCEZF,), dataSize=asz + + ld t1, es, [1, t0, rdi] + sub t0, t1, rax, flags=(OF, SF, ZF, AF, PF, CF) + + add rdi, rdi, t2, dataSize=asz +}; + +# +# Versions which have the rep prefix. These could benefit from some loop +# unrolling. +# + +def macroop SCAS_E_M { + # Find the constant we need to either add or subtract from rdi + ruflag t0, 10 + movi t2, t2, dsz, flags=(CEZF,), dataSize=asz + subi t3, t0, dsz, dataSize=asz + mov t2, t2, t3, flags=(nCEZF,), dataSize=asz + + ld t1, es, [1, t0, rdi] + sub t0, t1, rax, flags=(OF, SF, ZF, AF, PF, CF) + + subi rcx, rcx, 1, flags=(EZF,), dataSize=asz + add rdi, rdi, t2, dataSize=asz + bri t0, 4, flags=(CSTRZnEZF,) + fault "NoFault" +}; + +def macroop SCAS_N_M { + # Find the constant we need to either add or subtract from rdi + ruflag t0, 10 + movi t2, t2, dsz, flags=(CEZF,), dataSize=asz + subi t3, t0, dsz, dataSize=asz + mov t2, t2, t3, flags=(nCEZF,), dataSize=asz + + ld t1, es, [1, t0, rdi] + sub t0, t1, rax, flags=(OF, SF, ZF, AF, PF, CF) + + subi rcx, rcx, 1, flags=(EZF,), dataSize=asz + add rdi, rdi, t2, dataSize=asz + bri t0, 4, flags=(CSTRnZnEZF,) + fault "NoFault" +}; + +''' diff --git a/src/arch/x86/isa/microasm.isa b/src/arch/x86/isa/microasm.isa index 5c567a30c..af3148631 100644 --- a/src/arch/x86/isa/microasm.isa +++ b/src/arch/x86/isa/microasm.isa @@ -89,7 +89,7 @@ let {{ "index" : "env.index", "base" : "env.base", "dsz" : "env.dataSize", - "osz" : "env.operandSize", + "asz" : "env.addressSize", "ssz" : "env.stackSize" } assembler.symbols.update(symbols) @@ -107,11 +107,13 @@ let {{ assembler.symbols[flag] = flag + "Bit" for cond in ('True', 'False', 'ECF', 'EZF', 'SZnZF', - 'MSTRZ', 'STRZ', 'MSTRC', 'STRZnZF', + 'MSTRZ', 'STRZ', 'MSTRC', 'OF', 'CF', 'ZF', 'CvZF', 'SF', 'PF', 'SxOF', 'SxOvZF'): assembler.symbols["C%s" % cond] = "ConditionTests::%s" % cond assembler.symbols["nC%s" % cond] = "ConditionTests::Not%s" % cond + assembler.symbols["CSTRZnEZF"] = "ConditionTests::STRZnEZF" + assembler.symbols["CSTRnZnEZF"] = "ConditionTests::STRnZnEZF" assembler.symbols["CTrue"] = "ConditionTests::True" assembler.symbols["CFalse"] = "ConditionTests::False" |