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-rw-r--r--SConscript16
-rw-r--r--arch/SConscript19
-rw-r--r--arch/alpha/faults.cc45
-rw-r--r--arch/alpha/faults.hh97
-rw-r--r--arch/alpha/isa/main.isa20
-rw-r--r--arch/alpha/isa/mem.isa6
-rw-r--r--arch/alpha/linux/system.hh1
-rw-r--r--arch/alpha/tlb.cc104
-rw-r--r--arch/alpha/tlb.hh6
-rwxr-xr-xarch/isa_parser.py110
-rw-r--r--arch/mips/isa/formats.isa35
-rw-r--r--arch/mips/isa/formats/formats.isa35
-rw-r--r--arch/mips/isa/formats/mem.isa6
-rw-r--r--arch/mips/isa/main.isa12
-rw-r--r--arch/sparc/isa/decoder.isa42
-rw-r--r--arch/sparc/isa/formats.isa18
-rw-r--r--arch/sparc/isa/formats/mem.isa16
-rw-r--r--arch/sparc/isa/formats/priv.isa20
-rw-r--r--arch/sparc/isa/formats/trap.isa2
-rw-r--r--arch/sparc/isa/main.isa12
-rw-r--r--arch/sparc/isa/operands.isa14
-rw-r--r--arch/sparc/isa_traits.hh33
-rw-r--r--arch/sparc/regfile.hh10
-rw-r--r--arch/sparc/utility.hh89
-rw-r--r--base/timebuf.hh4
-rw-r--r--build/SConstruct11
-rw-r--r--kern/tru64/tru64.hh13
27 files changed, 481 insertions, 315 deletions
diff --git a/SConscript b/SConscript
index d891f0d6d..008c794e3 100644
--- a/SConscript
+++ b/SConscript
@@ -219,13 +219,17 @@ full_system_sources = Split('''
kern/linux/events.cc
kern/linux/linux_syscalls.cc
kern/linux/printk.cc
+
+ mem/functional/memory_control.cc
+ sim/pseudo_inst.cc
+ ''')
+
+if env['TARGET_ISA'] == 'alpha':
+ full_system_sources += Split('''
kern/tru64/dump_mbuf.cc
kern/tru64/printf.cc
kern/tru64/tru64_events.cc
kern/tru64/tru64_syscalls.cc
-
- mem/functional/memory_control.cc
- sim/pseudo_inst.cc
''')
# turbolaser encumbered sources
@@ -251,11 +255,15 @@ turbolaser_sources = Split('''
# Syscall emulation (non-full-system) sources
syscall_emulation_sources = Split('''
kern/linux/linux.cc
- kern/tru64/tru64.cc
sim/process.cc
sim/syscall_emul.cc
''')
+if env['TARGET_ISA'] == 'alpha':
+ syscall_emulation_sources += Split('''
+ kern/tru64/tru64.cc
+ ''')
+
alpha_eio_sources = Split('''
encumbered/eio/exolex.cc
encumbered/eio/libexo.cc
diff --git a/arch/SConscript b/arch/SConscript
index d88d10368..99c861568 100644
--- a/arch/SConscript
+++ b/arch/SConscript
@@ -100,18 +100,12 @@ for hdr in isa_switch_hdrs:
#
import SCons.Scanner
-def ISAScan():
- return SCons.Scanner.Classic("ISAScan",
- "$ISASUFFIXES",
- "SRCDIR",
- '^[ \t]*##[ \t]*include[ \t]*"([^>"]+)"')
+isa_scanner = SCons.Scanner.Classic("ISAScan",
+ [".isa", ".ISA"],
+ "SRCDIR",
+ r'^\s*##include\s+"([\w/.-]*)"')
-def ISAPath(env, dir, target=None, source=None, a=None):
- return (Dir(env['SRCDIR']), Dir('.'))
-
-iscan = Scanner(function = ISAScan().scan, skeys = [".isa", ".ISA"],
- path_function = ISAPath)
-env.Append(SCANNERS = iscan)
+env.Append(SCANNERS = isa_scanner)
#
# Now create a Builder object that uses isa_parser.py to generate C++
@@ -138,8 +132,7 @@ def isa_desc_emitter(target, source, env):
return (isa_desc_gen_files, [isa_parser, cpu_models_file] + source)
# Pieces are in place, so create the builder.
-isa_desc_builder = Builder(action='$SOURCES $TARGET.dir $CPU_MODELS',
- source_scanner = iscan,
+isa_desc_builder = Builder(action='python $SOURCES $TARGET.dir $CPU_MODELS',
emitter = isa_desc_emitter)
env.Append(BUILDERS = { 'ISADesc' : isa_desc_builder })
diff --git a/arch/alpha/faults.cc b/arch/alpha/faults.cc
index e0918da21..0083aa9f3 100644
--- a/arch/alpha/faults.cc
+++ b/arch/alpha/faults.cc
@@ -30,6 +30,9 @@
#include "cpu/exec_context.hh"
#include "cpu/base.hh"
#include "base/trace.hh"
+#if FULL_SYSTEM
+#include "arch/alpha/ev5.hh"
+#endif
namespace AlphaISA
{
@@ -70,6 +73,10 @@ FaultName DtbAcvFault::_name = "dfault";
FaultVect DtbAcvFault::_vect = 0x0381;
FaultStat DtbAcvFault::_count;
+FaultName DtbAlignmentFault::_name = "unalign";
+FaultVect DtbAlignmentFault::_vect = 0x0301;
+FaultStat DtbAlignmentFault::_count;
+
FaultName ItbMissFault::_name = "itbmiss";
FaultVect ItbMissFault::_vect = 0x0181;
FaultStat ItbMissFault::_count;
@@ -125,6 +132,44 @@ void ArithmeticFault::invoke(ExecContext * xc)
panic("Arithmetic traps are unimplemented!");
}
+void DtbFault::invoke(ExecContext * xc)
+{
+ // Set fault address and flags. Even though we're modeling an
+ // EV5, we use the EV6 technique of not latching fault registers
+ // on VPTE loads (instead of locking the registers until IPR_VA is
+ // read, like the EV5). The EV6 approach is cleaner and seems to
+ // work with EV5 PAL code, but not the other way around.
+ if (!xc->misspeculating()
+ && !(reqFlags & VPTE) && !(reqFlags & NO_FAULT)) {
+ // set VA register with faulting address
+ xc->setMiscReg(AlphaISA::IPR_VA, vaddr);
+
+ // set MM_STAT register flags
+ xc->setMiscReg(AlphaISA::IPR_MM_STAT,
+ (((EV5::Opcode(xc->getInst()) & 0x3f) << 11)
+ | ((EV5::Ra(xc->getInst()) & 0x1f) << 6)
+ | (flags & 0x3f)));
+
+ // set VA_FORM register with faulting formatted address
+ xc->setMiscReg(AlphaISA::IPR_VA_FORM,
+ xc->readMiscReg(AlphaISA::IPR_MVPTBR) | (vaddr.vpn() << 3));
+ }
+
+ AlphaFault::invoke(xc);
+}
+
+void ItbFault::invoke(ExecContext * xc)
+{
+ if (!xc->misspeculating()) {
+ xc->setMiscReg(AlphaISA::IPR_ITB_TAG, pc);
+ xc->setMiscReg(AlphaISA::IPR_IFAULT_VA_FORM,
+ xc->readMiscReg(AlphaISA::IPR_IVPTBR) |
+ (AlphaISA::VAddr(pc).vpn() << 3));
+ }
+
+ AlphaFault::invoke(xc);
+}
+
#endif
} // namespace AlphaISA
diff --git a/arch/alpha/faults.hh b/arch/alpha/faults.hh
index 1a196cc94..e8ccc6b79 100644
--- a/arch/alpha/faults.hh
+++ b/arch/alpha/faults.hh
@@ -29,6 +29,7 @@
#ifndef __ALPHA_FAULTS_HH__
#define __ALPHA_FAULTS_HH__
+#include "arch/alpha/isa_traits.hh"
#include "sim/faults.hh"
// The design of the "name" and "vect" functions is in sim/faults.hh
@@ -130,85 +131,167 @@ class InterruptFault : public AlphaFault
FaultStat & countStat() {return _count;}
};
-class NDtbMissFault : public AlphaFault
+class DtbFault : public AlphaFault
+{
+#if FULL_SYSTEM
+ private:
+ AlphaISA::VAddr vaddr;
+ uint32_t reqFlags;
+ uint64_t flags;
+ public:
+ DtbFault(AlphaISA::VAddr _vaddr, uint32_t _reqFlags, uint64_t _flags)
+ : vaddr(_vaddr), reqFlags(_reqFlags), flags(_flags)
+ { }
+#endif
+ FaultName name() = 0;
+ FaultVect vect() = 0;
+ FaultStat & countStat() = 0;
+#if FULL_SYSTEM
+ void invoke(ExecContext * xc);
+#endif
+};
+
+class NDtbMissFault : public DtbFault
{
private:
static FaultName _name;
static FaultVect _vect;
static FaultStat _count;
public:
+#if FULL_SYSTEM
+ NDtbMissFault(AlphaISA::VAddr vaddr, uint32_t reqFlags, uint64_t flags)
+ : DtbFault(vaddr, reqFlags, flags)
+ { }
+#endif
FaultName name() {return _name;}
FaultVect vect() {return _vect;}
FaultStat & countStat() {return _count;}
};
-class PDtbMissFault : public AlphaFault
+class PDtbMissFault : public DtbFault
{
private:
static FaultName _name;
static FaultVect _vect;
static FaultStat _count;
public:
+#if FULL_SYSTEM
+ PDtbMissFault(AlphaISA::VAddr vaddr, uint32_t reqFlags, uint64_t flags)
+ : DtbFault(vaddr, reqFlags, flags)
+ { }
+#endif
FaultName name() {return _name;}
FaultVect vect() {return _vect;}
FaultStat & countStat() {return _count;}
};
-class DtbPageFault : public AlphaFault
+class DtbPageFault : public DtbFault
{
private:
static FaultName _name;
static FaultVect _vect;
static FaultStat _count;
public:
+#if FULL_SYSTEM
+ DtbPageFault(AlphaISA::VAddr vaddr, uint32_t reqFlags, uint64_t flags)
+ : DtbFault(vaddr, reqFlags, flags)
+ { }
+#endif
FaultName name() {return _name;}
FaultVect vect() {return _vect;}
FaultStat & countStat() {return _count;}
};
-class DtbAcvFault : public AlphaFault
+class DtbAcvFault : public DtbFault
{
private:
static FaultName _name;
static FaultVect _vect;
static FaultStat _count;
public:
+#if FULL_SYSTEM
+ DtbAcvFault(AlphaISA::VAddr vaddr, uint32_t reqFlags, uint64_t flags)
+ : DtbFault(vaddr, reqFlags, flags)
+ { }
+#endif
FaultName name() {return _name;}
FaultVect vect() {return _vect;}
FaultStat & countStat() {return _count;}
};
-class ItbMissFault : public AlphaFault
+class DtbAlignmentFault : public DtbFault
+{
+ private:
+ static FaultName _name;
+ static FaultVect _vect;
+ static FaultStat _count;
+ public:
+#if FULL_SYSTEM
+ DtbAlignmentFault(AlphaISA::VAddr vaddr, uint32_t reqFlags, uint64_t flags)
+ : DtbFault(vaddr, reqFlags, flags)
+ { }
+#endif
+ FaultName name() {return _name;}
+ FaultVect vect() {return _vect;}
+ FaultStat & countStat() {return _count;}
+};
+
+class ItbFault : public AlphaFault
+{
+ private:
+ Addr pc;
+ public:
+ ItbFault(Addr _pc)
+ : pc(_pc)
+ { }
+ FaultName name() = 0;
+ FaultVect vect() = 0;
+ FaultStat & countStat() = 0;
+#if FULL_SYSTEM
+ void invoke(ExecContext * xc);
+#endif
+};
+
+class ItbMissFault : public ItbFault
{
private:
static FaultName _name;
static FaultVect _vect;
static FaultStat _count;
public:
+ ItbMissFault(Addr pc)
+ : ItbFault(pc)
+ { }
FaultName name() {return _name;}
FaultVect vect() {return _vect;}
FaultStat & countStat() {return _count;}
};
-class ItbPageFault : public AlphaFault
+class ItbPageFault : public ItbFault
{
private:
static FaultName _name;
static FaultVect _vect;
static FaultStat _count;
public:
+ ItbPageFault(Addr pc)
+ : ItbFault(pc)
+ { }
FaultName name() {return _name;}
FaultVect vect() {return _vect;}
FaultStat & countStat() {return _count;}
};
-class ItbAcvFault : public AlphaFault
+class ItbAcvFault : public ItbFault
{
private:
static FaultName _name;
static FaultVect _vect;
static FaultStat _count;
public:
+ ItbAcvFault(Addr pc)
+ : ItbFault(pc)
+ { }
FaultName name() {return _name;}
FaultVect vect() {return _vect;}
FaultStat & countStat() {return _count;}
diff --git a/arch/alpha/isa/main.isa b/arch/alpha/isa/main.isa
index d4c744fbc..746fe776d 100644
--- a/arch/alpha/isa/main.isa
+++ b/arch/alpha/isa/main.isa
@@ -418,31 +418,31 @@ def format BasicOperateWithNopCheck(code, *opt_args) {{
}};
// Integer instruction templates, formats, etc.
-##include "m5/arch/alpha/isa/int.isa"
+##include "int.isa"
// Floating-point instruction templates, formats, etc.
-##include "m5/arch/alpha/isa/fp.isa"
+##include "fp.isa"
// Memory instruction templates, formats, etc.
-##include "m5/arch/alpha/isa/mem.isa"
+##include "mem.isa"
// Branch/jump instruction templates, formats, etc.
-##include "m5/arch/alpha/isa/branch.isa"
+##include "branch.isa"
// PAL instruction templates, formats, etc.
-##include "m5/arch/alpha/isa/pal.isa"
+##include "pal.isa"
// Opcdec fault instruction templates, formats, etc.
-##include "m5/arch/alpha/isa/opcdec.isa"
+##include "opcdec.isa"
// Unimplemented instruction templates, formats, etc.
-##include "m5/arch/alpha/isa/unimp.isa"
+##include "unimp.isa"
// Unknown instruction templates, formats, etc.
-##include "m5/arch/alpha/isa/unknown.isa"
+##include "unknown.isa"
// Execution utility functions
-##include "m5/arch/alpha/isa/util.isa"
+##include "util.isa"
// The actual decoder
-##include "m5/arch/alpha/isa/decoder.isa"
+##include "decoder.isa"
diff --git a/arch/alpha/isa/mem.isa b/arch/alpha/isa/mem.isa
index 3c8b4f755..8742d308f 100644
--- a/arch/alpha/isa/mem.isa
+++ b/arch/alpha/isa/mem.isa
@@ -311,8 +311,7 @@ def template LoadCompleteAcc {{
Fault fault = NoFault;
%(fp_enable_check)s;
- %(op_src_decl)s;
- %(op_dest_decl)s;
+ %(op_decl)s;
memcpy(&Mem, data, sizeof(Mem));
@@ -410,8 +409,7 @@ def template StoreInitiateAcc {{
uint64_t write_result = 0;
%(fp_enable_check)s;
- %(op_src_decl)s;
- %(op_dest_decl)s;
+ %(op_decl)s;
%(op_rd)s;
%(ea_code)s;
diff --git a/arch/alpha/linux/system.hh b/arch/alpha/linux/system.hh
index 035e2a427..0c1fb037e 100644
--- a/arch/alpha/linux/system.hh
+++ b/arch/alpha/linux/system.hh
@@ -39,7 +39,6 @@ class IdleStartEvent;
using namespace AlphaISA;
using namespace Linux;
-using namespace std;
/**
* This class contains linux specific system code (Loading, Events, Binning).
diff --git a/arch/alpha/tlb.cc b/arch/alpha/tlb.cc
index e30a8e595..562235ef8 100644
--- a/arch/alpha/tlb.cc
+++ b/arch/alpha/tlb.cc
@@ -290,17 +290,6 @@ AlphaITB::regStats()
accesses = hits + misses;
}
-void
-AlphaITB::fault(Addr pc, ExecContext *xc) const
-{
- if (!xc->misspeculating()) {
- xc->setMiscReg(AlphaISA::IPR_ITB_TAG, pc);
- xc->setMiscReg(AlphaISA::IPR_IFAULT_VA_FORM,
- xc->readMiscReg(AlphaISA::IPR_IVPTBR) |
- (AlphaISA::VAddr(pc).vpn() << 3));
- }
-}
-
Fault
AlphaITB::translate(MemReqPtr &req) const
@@ -319,9 +308,8 @@ AlphaITB::translate(MemReqPtr &req) const
} else {
// verify that this is a good virtual address
if (!validVirtualAddress(req->vaddr)) {
- fault(req->vaddr, req->xc);
acv++;
- return new ItbAcvFault;
+ return new ItbAcvFault(req->vaddr);
}
@@ -336,9 +324,8 @@ AlphaITB::translate(MemReqPtr &req) const
// only valid in kernel mode
if (ICM_CM(xc->readMiscReg(AlphaISA::IPR_ICM)) !=
AlphaISA::mode_kernel) {
- fault(req->vaddr, req->xc);
acv++;
- return new ItbAcvFault;
+ return new ItbAcvFault(req->vaddr);
}
req->paddr = req->vaddr & PAddrImplMask;
@@ -358,9 +345,8 @@ AlphaITB::translate(MemReqPtr &req) const
asn);
if (!pte) {
- fault(req->vaddr, req->xc);
misses++;
- return new ItbPageFault;
+ return new ItbPageFault(req->vaddr);
}
req->paddr = (pte->ppn << AlphaISA::PageShift) +
@@ -370,9 +356,8 @@ AlphaITB::translate(MemReqPtr &req) const
if (!(pte->xre &
(1 << ICM_CM(xc->readMiscReg(AlphaISA::IPR_ICM))))) {
// instruction access fault
- fault(req->vaddr, req->xc);
acv++;
- return new ItbAcvFault;
+ return new ItbAcvFault(req->vaddr);
}
hits++;
@@ -465,34 +450,6 @@ AlphaDTB::regStats()
accesses = read_accesses + write_accesses;
}
-void
-AlphaDTB::fault(MemReqPtr &req, uint64_t flags) const
-{
- ExecContext *xc = req->xc;
- AlphaISA::VAddr vaddr = req->vaddr;
-
- // Set fault address and flags. Even though we're modeling an
- // EV5, we use the EV6 technique of not latching fault registers
- // on VPTE loads (instead of locking the registers until IPR_VA is
- // read, like the EV5). The EV6 approach is cleaner and seems to
- // work with EV5 PAL code, but not the other way around.
- if (!xc->misspeculating()
- && !(req->flags & VPTE) && !(req->flags & NO_FAULT)) {
- // set VA register with faulting address
- xc->setMiscReg(AlphaISA::IPR_VA, req->vaddr);
-
- // set MM_STAT register flags
- xc->setMiscReg(AlphaISA::IPR_MM_STAT,
- (((Opcode(xc->getInst()) & 0x3f) << 11)
- | ((Ra(xc->getInst()) & 0x1f) << 6)
- | (flags & 0x3f)));
-
- // set VA_FORM register with faulting formatted address
- xc->setMiscReg(AlphaISA::IPR_VA_FORM,
- xc->readMiscReg(AlphaISA::IPR_MVPTBR) | (vaddr.vpn() << 3));
- }
-}
-
Fault
AlphaDTB::translate(MemReqPtr &req, bool write) const
{
@@ -507,10 +464,10 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const
* Check for alignment faults
*/
if (req->vaddr & (req->size - 1)) {
- fault(req, write ? MM_STAT_WR_MASK : 0);
DPRINTF(TLB, "Alignment Fault on %#x, size = %d", req->vaddr,
req->size);
- return genAlignmentFault();
+ uint64_t flags = write ? MM_STAT_WR_MASK : 0;
+ return new DtbAlignmentFault(req->vaddr, req->flags, flags);
}
if (pc & 0x1) {
@@ -525,12 +482,11 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const
} else {
// verify that this is a good virtual address
if (!validVirtualAddress(req->vaddr)) {
- fault(req, (write ? MM_STAT_WR_MASK : 0) |
- MM_STAT_BAD_VA_MASK |
- MM_STAT_ACV_MASK);
-
if (write) { write_acv++; } else { read_acv++; }
- return new DtbPageFault;
+ uint64_t flags = (write ? MM_STAT_WR_MASK : 0) |
+ MM_STAT_BAD_VA_MASK |
+ MM_STAT_ACV_MASK;
+ return new DtbPageFault(req->vaddr, req->flags, flags);
}
// Check for "superpage" mapping
@@ -544,10 +500,10 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const
// only valid in kernel mode
if (DTB_CM_CM(xc->readMiscReg(AlphaISA::IPR_DTB_CM)) !=
AlphaISA::mode_kernel) {
- fault(req, ((write ? MM_STAT_WR_MASK : 0) |
- MM_STAT_ACV_MASK));
if (write) { write_acv++; } else { read_acv++; }
- return new DtbAcvFault;
+ uint64_t flags = ((write ? MM_STAT_WR_MASK : 0) |
+ MM_STAT_ACV_MASK);
+ return new DtbAcvFault(req->vaddr, req->flags, flags);
}
req->paddr = req->vaddr & PAddrImplMask;
@@ -574,12 +530,14 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const
if (!pte) {
// page fault
- fault(req, (write ? MM_STAT_WR_MASK : 0) |
- MM_STAT_DTB_MISS_MASK);
if (write) { write_misses++; } else { read_misses++; }
+ uint64_t flags = (write ? MM_STAT_WR_MASK : 0) |
+ MM_STAT_DTB_MISS_MASK;
return (req->flags & VPTE) ?
- (Fault)(new PDtbMissFault) :
- (Fault)(new NDtbMissFault);
+ (Fault)(new PDtbMissFault(req->vaddr, req->flags,
+ flags)) :
+ (Fault)(new NDtbMissFault(req->vaddr, req->flags,
+ flags));
}
req->paddr = (pte->ppn << AlphaISA::PageShift) +
@@ -588,29 +546,29 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const
if (write) {
if (!(pte->xwe & MODE2MASK(mode))) {
// declare the instruction access fault
- fault(req, MM_STAT_WR_MASK |
- MM_STAT_ACV_MASK |
- (pte->fonw ? MM_STAT_FONW_MASK : 0));
write_acv++;
- return new DtbPageFault;
+ uint64_t flags = MM_STAT_WR_MASK |
+ MM_STAT_ACV_MASK |
+ (pte->fonw ? MM_STAT_FONW_MASK : 0);
+ return new DtbPageFault(req->vaddr, req->flags, flags);
}
if (pte->fonw) {
- fault(req, MM_STAT_WR_MASK |
- MM_STAT_FONW_MASK);
write_acv++;
- return new DtbPageFault;
+ uint64_t flags = MM_STAT_WR_MASK |
+ MM_STAT_FONW_MASK;
+ return new DtbPageFault(req->vaddr, req->flags, flags);
}
} else {
if (!(pte->xre & MODE2MASK(mode))) {
- fault(req, MM_STAT_ACV_MASK |
- (pte->fonr ? MM_STAT_FONR_MASK : 0));
read_acv++;
- return new DtbAcvFault;
+ uint64_t flags = MM_STAT_ACV_MASK |
+ (pte->fonr ? MM_STAT_FONR_MASK : 0);
+ return new DtbAcvFault(req->vaddr, req->flags, flags);
}
if (pte->fonr) {
- fault(req, MM_STAT_FONR_MASK);
read_acv++;
- return new DtbPageFault;
+ uint64_t flags = MM_STAT_FONR_MASK;
+ return new DtbPageFault(req->vaddr, req->flags, flags);
}
}
}
diff --git a/arch/alpha/tlb.hh b/arch/alpha/tlb.hh
index 1c299e8b9..676345f01 100644
--- a/arch/alpha/tlb.hh
+++ b/arch/alpha/tlb.hh
@@ -88,9 +88,6 @@ class AlphaITB : public AlphaTLB
mutable Stats::Scalar<> acv;
mutable Stats::Formula accesses;
- protected:
- void fault(Addr pc, ExecContext *xc) const;
-
public:
AlphaITB(const std::string &name, int size);
virtual void regStats();
@@ -114,9 +111,6 @@ class AlphaDTB : public AlphaTLB
Stats::Formula acv;
Stats::Formula accesses;
- protected:
- void fault(MemReqPtr &req, uint64_t flags) const;
-
public:
AlphaDTB(const std::string &name, int size);
virtual void regStats();
diff --git a/arch/isa_parser.py b/arch/isa_parser.py
index 3f836ed7e..6fce783b1 100755
--- a/arch/isa_parser.py
+++ b/arch/isa_parser.py
@@ -1,5 +1,3 @@
-#! /usr/bin/env python
-
# Copyright (c) 2003-2005 The Regents of The University of Michigan
# All rights reserved.
#
@@ -162,13 +160,12 @@ def t_CPPDIRECTIVE(t):
def t_NEWFILE(t):
r'^\#\#newfile\s+"[\w/.-]*"'
- global fileNameStack
- fileNameStack.append((t.value[11:-1], t.lineno))
+ fileNameStack.push((t.value[11:-1], t.lineno))
t.lineno = 0
def t_ENDFILE(t):
r'^\#\#endfile'
- (filename, t.lineno) = fileNameStack.pop()
+ (old_filename, t.lineno) = fileNameStack.pop()
#
# The functions t_NEWLINE, t_ignore, and t_error are
@@ -698,7 +695,7 @@ def p_error(t):
if t:
error(t.lineno, "syntax error at '%s'" % t.value)
else:
- error_bt(0, "unknown syntax error")
+ error(0, "unknown syntax error", True)
# END OF GRAMMAR RULES
#
@@ -896,6 +893,12 @@ formatStack = Stack(NoFormat())
# The global default case stack.
defaultStack = Stack( None )
+# Global stack that tracks current file and line number.
+# Each element is a tuple (filename, lineno) that records the
+# *current* filename and the line number in the *previous* file where
+# it was included.
+fileNameStack = Stack()
+
###################
# Utility functions
@@ -932,25 +935,22 @@ def fixPythonIndentation(s):
return s
# Error handler. Just call exit. Output formatted to work under
-# Emacs compile-mode. This function should be called when errors due
-# to user input are detected (as opposed to parser bugs).
-def error(lineno, string):
+# Emacs compile-mode. Optional 'print_traceback' arg, if set to True,
+# prints a Python stack backtrace too (can be handy when trying to
+# debug the parser itself).
+def error(lineno, string, print_traceback = False):
spaces = ""
for (filename, line) in fileNameStack[0:-1]:
- print spaces + "In file included from " + filename
+ print spaces + "In file included from " + filename + ":"
spaces += " "
- # Uncomment the following line to get a Python stack backtrace for
- # these errors too. Can be handy when trying to debug the parser.
- # traceback.print_exc()
- sys.exit(spaces + "%s:%d: %s" % (fileNameStack[-1][0], lineno, string))
-
-# Like error(), but include a Python stack backtrace (for processing
-# Python exceptions). This function should be called for errors that
-# appear to be bugs in the parser itself.
-def error_bt(lineno, string):
- traceback.print_exc()
- print >> sys.stderr, "%s:%d: %s" % (input_filename, lineno, string)
- sys.exit(1)
+ # Print a Python stack backtrace if requested.
+ if (print_traceback):
+ traceback.print_exc()
+ if lineno != 0:
+ line_str = "%d:" % lineno
+ else:
+ line_str = ""
+ sys.exit(spaces + "%s:%s %s" % (fileNameStack[-1][0], line_str, string))
#####################################################################
@@ -1070,7 +1070,7 @@ def buildOperandTypeMap(userDict, lineno):
elif size == 64:
ctype = 'double'
if ctype == '':
- error(0, 'Unrecognized type description "%s" in userDict')
+ error(lineno, 'Unrecognized type description "%s" in userDict')
operandTypeMap[ext] = (size, ctype, is_signed)
#
@@ -1701,47 +1701,47 @@ def update_if_needed(file, contents):
f.write(contents)
f.close()
-# This regular expression matches include directives
+# This regular expression matches '##include' directives
includeRE = re.compile(r'^\s*##include\s+"(?P<filename>[\w/.-]*)".*$',
re.MULTILINE)
-def preprocess_isa_desc(isa_desc):
+# Function to replace a matched '##include' directive with the
+# contents of the specified file (with nested ##includes replaced
+# recursively). 'matchobj' is an re match object (from a match of
+# includeRE) and 'dirname' is the directory relative to which the file
+# path should be resolved.
+def replace_include(matchobj, dirname):
+ fname = matchobj.group('filename')
+ full_fname = os.path.normpath(os.path.join(dirname, fname))
+ contents = '##newfile "%s"\n%s\n##endfile\n' % \
+ (full_fname, read_and_flatten(full_fname))
+ return contents
+
+# Read a file and recursively flatten nested '##include' files.
+def read_and_flatten(filename):
+ current_dir = os.path.dirname(filename)
+ try:
+ contents = open(filename).read()
+ except IOError:
+ error(0, 'Error including file "%s"' % filename)
+ fileNameStack.push((filename, 0))
# Find any includes and include them
- pos = 0
- while 1:
- m = includeRE.search(isa_desc, pos)
- if not m:
- break
- filename = m.group('filename')
- print 'Including file "%s"' % filename
- try:
- isa_desc = isa_desc[:m.start()] + \
- '##newfile "' + filename + '"\n' + \
- open(filename).read() + \
- '##endfile\n' + \
- isa_desc[m.end():]
- except IOError:
- error(0, 'Error including file "%s"' % (filename))
- pos = m.start()
- return isa_desc
+ contents = includeRE.sub(lambda m: replace_include(m, current_dir),
+ contents)
+ fileNameStack.pop()
+ return contents
#
# Read in and parse the ISA description.
#
def parse_isa_desc(isa_desc_file, output_dir):
- # set a global var for the input filename... used in error messages
- global input_filename
- input_filename = isa_desc_file
- global fileNameStack
- fileNameStack = [(input_filename, 1)]
-
- # Suck the ISA description file in.
- input = open(isa_desc_file)
- isa_desc = input.read()
- input.close()
-
- # Perform Preprocessing
- isa_desc = preprocess_isa_desc(isa_desc)
+ # Read file and (recursively) all included files into a string.
+ # PLY requires that the input be in a single string so we have to
+ # do this up front.
+ isa_desc = read_and_flatten(isa_desc_file)
+
+ # Initialize filename stack with outer file.
+ fileNameStack.push((isa_desc_file, 0))
# Parse it.
(isa_name, namespace, global_code, namespace_code) = yacc.parse(isa_desc)
diff --git a/arch/mips/isa/formats.isa b/arch/mips/isa/formats.isa
deleted file mode 100644
index f7a9e4ce2..000000000
--- a/arch/mips/isa/formats.isa
+++ /dev/null
@@ -1,35 +0,0 @@
-// -*- mode:c++ -*-
-
-//Templates from this format are used later
-//Include the basic format
-##include "m5/arch/mips/isa/formats/basic.isa"
-
-//Include the basic format
-##include "m5/arch/mips/isa/formats/noop.isa"
-
-//Include utility formats/functions
-##include "m5/arch/mips/isa/formats/util.isa"
-
-//Include the cop0 formats
-##include "m5/arch/mips/isa/formats/cop0.isa"
-
-//Include the integer formats
-##include "m5/arch/mips/isa/formats/int.isa"
-
-//Include the floatOp format
-##include "m5/arch/mips/isa/formats/fp.isa"
-
-//Include the mem format
-##include "m5/arch/mips/isa/formats/mem.isa"
-
-//Include the trap format
-##include "m5/arch/mips/isa/formats/trap.isa"
-
-//Include the branch format
-##include "m5/arch/mips/isa/formats/branch.isa"
-
-//Include the noop format
-##include "m5/arch/mips/isa/formats/unimp.isa"
-
-//Include the noop format
-##include "m5/arch/mips/isa/formats/unknown.isa"
diff --git a/arch/mips/isa/formats/formats.isa b/arch/mips/isa/formats/formats.isa
new file mode 100644
index 000000000..7d493ffae
--- /dev/null
+++ b/arch/mips/isa/formats/formats.isa
@@ -0,0 +1,35 @@
+// -*- mode:c++ -*-
+
+//Templates from this format are used later
+//Include the basic format
+##include "basic.isa"
+
+//Include the basic format
+##include "noop.isa"
+
+//Include utility functions
+##include "util.isa"
+
+//Include the cop0 formats
+##include "cop0.isa"
+
+//Include the integer formats
+##include "int.isa"
+
+//Include the floatOp format
+##include "fp.isa"
+
+//Include the mem format
+##include "mem.isa"
+
+//Include the trap format
+##include "trap.isa"
+
+//Include the branch format
+##include "branch.isa"
+
+//Include the noop format
+##include "unimp.isa"
+
+//Include the noop format
+##include "unknown.isa"
diff --git a/arch/mips/isa/formats/mem.isa b/arch/mips/isa/formats/mem.isa
index 8a07e63d4..404aa1ee1 100644
--- a/arch/mips/isa/formats/mem.isa
+++ b/arch/mips/isa/formats/mem.isa
@@ -276,8 +276,7 @@ def template LoadCompleteAcc {{
Fault fault = NoFault;
%(fp_enable_check)s;
- %(op_src_decl)s;
- %(op_dest_decl)s;
+ %(op_decl)s;
memcpy(&Mem, data, sizeof(Mem));
@@ -375,8 +374,7 @@ def template StoreInitiateAcc {{
uint64_t write_result = 0;
%(fp_enable_check)s;
- %(op_src_decl)s;
- %(op_dest_decl)s;
+ %(op_decl)s;
%(op_rd)s;
%(ea_code)s;
diff --git a/arch/mips/isa/main.isa b/arch/mips/isa/main.isa
index 411e398b4..01d81323e 100644
--- a/arch/mips/isa/main.isa
+++ b/arch/mips/isa/main.isa
@@ -26,7 +26,7 @@
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-##include "m5/arch/mips/isa/includes.isa"
+##include "includes.isa"
////////////////////////////////////////////////////////////////////
//
@@ -37,16 +37,16 @@
namespace MipsISA;
//Include the bitfield definitions
-##include "m5/arch/mips/isa/bitfields.isa"
+##include "bitfields.isa"
//Include the operand_types and operand definitions
-##include "m5/arch/mips/isa/operands.isa"
+##include "operands.isa"
//Include the base class for mips instructions, and some support code
-##include "m5/arch/mips/isa/base.isa"
+##include "base.isa"
//Include the definitions for the instruction formats
-##include "m5/arch/mips/isa/formats.isa"
+##include "formats/formats.isa"
//Include the decoder definition
-##include "m5/arch/mips/isa/decoder.isa"
+##include "decoder.isa"
diff --git a/arch/sparc/isa/decoder.isa b/arch/sparc/isa/decoder.isa
index a1bbf8984..6c1356932 100644
--- a/arch/sparc/isa/decoder.isa
+++ b/arch/sparc/isa/decoder.isa
@@ -279,8 +279,8 @@ decode OP default Unknown::unknown()
0x5: rdpc({{Rd = xc->regs.pc;}}); //RDPC
0x6: rdfprs({{Rd = Fprs;}}); //RDFPRS
0xF: decode I {
- 0x0: Noop::membar({{//Membar isn't needed yet}});
- 0x1: Noop::stbar({{//Stbar isn't needed yet}});
+ 0x0: Noop::membar({{/*Membar isn't needed yet*/}});
+ 0x1: Noop::stbar({{/*Stbar isn't needed yet*/}});
}
}
0x2A: decode RS1 {
@@ -305,19 +305,19 @@ decode OP default Unknown::unknown()
0x8: rdprpil({{Rd = Pil;}});
0x9: rdprcwp({{Rd = Cwp;}});
0xA: rdprcansave({{Rd = Cansave;}});
- 0xB: rdprcanrestore({{Rd = CanRestore;}});
+ 0xB: rdprcanrestore({{Rd = Canrestore;}});
0xC: rdprcleanwin({{Rd = Cleanwin;}});
0xD: rdprotherwin({{Rd = Otherwin;}});
0xE: rdprwstate({{Rd = Wstate;}});
}
//The floating point queue isn't implemented right now.
- 0xF: Trap::rdprfq({{fault = IllegalInstruction;}});
+ 0xF: Trap::rdprfq({{fault = new IllegalInstruction;}});
0x1F: Priv::rdprver({{Rd = Ver;}});
}
- 0x2B: BasicOperate::flushw({{//window toilet}}); //FLUSHW
+ 0x2B: BasicOperate::flushw({{/*window toilet*/}});
0x2C: decode MOVCC3
{
- 0x0: Trap::movccfcc({{fault = new FpDisabled}});
+ 0x0: Trap::movccfcc({{fault = new FpDisabled;}});
0x1: decode CC
{
0x0: movcci({{
@@ -362,8 +362,8 @@ decode OP default Unknown::unknown()
0xF: Trap::sir({{fault = new SoftwareInitiatedReset;}});
}
0x31: decode FCN {
- 0x0: BasicOperate::saved({{//Boogy Boogy}}); //SAVED
- 0x1: BasicOperate::restored({{//Boogy Boogy}}); //RESTORED
+ 0x0: BasicOperate::saved({{/*Boogy Boogy*/}});
+ 0x1: BasicOperate::restored({{/*Boogy Boogy*/}});
}
0x32: decode RD {
format Priv
@@ -401,8 +401,8 @@ decode OP default Unknown::unknown()
0x34: Trap::fpop1({{fault = new FpDisabled;}});
0x35: Trap::fpop2({{fault = new FpDisabled;}});
- 0x38: Branch::jmpl({{//Stuff}}); //JMPL
- 0x39: Branch::return({{//Other Stuff}}); //RETURN
+ 0x38: Branch::jmpl({{/*Stuff*/}});
+ 0x39: Branch::return({{/*Other Stuff*/}});
0x3A: decode CC
{
0x0: Trap::tcci({{
@@ -428,12 +428,12 @@ decode OP default Unknown::unknown()
#endif
}});
}
- 0x3B: BasicOperate::flush({{//Lala}}); //FLUSH
- 0x3C: BasicOperate::save({{//leprechauns); //SAVE
- 0x3D: BasicOperate::restore({{//Eat my short int}}); //RESTORE
+ 0x3B: BasicOperate::flush({{/*Lala*/}});
+ 0x3C: BasicOperate::save({{/*leprechauns*/}});
+ 0x3D: BasicOperate::restore({{/*Eat my short int*/}});
0x3E: decode FCN {
- 0x1: BasicOperate::done({{//Done thing}}); //DONE
- 0x2: BasicOperate::retry({{//Retry thing}}); //RETRY
+ 0x1: BasicOperate::done({{/*Done thing*/}});
+ 0x2: BasicOperate::retry({{/*Retry thing*/}});
}
}
}
@@ -444,14 +444,14 @@ decode OP default Unknown::unknown()
0x02: lduh({{Rd.uhw = Mem.uhw;}}); //LDUH
0x03: ldd({{
uint64_t val = Mem.udw;
- setIntReg(RD & (~1), val<31:0>);
- setIntReg(RD | 1, val<63:32>);
+ RdLow = val<31:0>;
+ RdHigh = val<63:32>;
}});//LDD
0x04: stw({{Mem.sw = Rd.sw;}}); //STW
0x05: stb({{Mem.sb = Rd.sb;}}); //STB
0x06: sth({{Mem.shw = Rd.shw;}}); //STH
0x07: std({{
- Mem.udw = readIntReg(RD & (~1))<31:0> | (readIntReg(RD | 1)<31:0> << 32);
+ Mem.udw = RdLow<31:0> | RdHigh<31:0> << 32;
}});//STD
0x08: ldsw({{Rd.sw = Mem.sw;}}); //LDSW
0x09: ldsb({{Rd.sb = Mem.sb;}}); //LDSB
@@ -473,14 +473,14 @@ decode OP default Unknown::unknown()
0x12: lduha({{Rd.uhw = Mem.uhw;}}); //LDUHA
0x13: ldda({{
uint64_t val = Mem.udw;
- setIntReg(RD & (~1), val<31:0>);
- setIntReg(RD | 1, val<63:32>);
+ RdLow = val<31:0>;
+ RdHigh = val<63:32>;
}}); //LDDA
0x14: stwa({{Mem.uw = Rd.uw;}}); //STWA
0x15: stba({{Mem.ub = Rd.ub;}}); //STBA
0x16: stha({{Mem.uhw = Rd.uhw;}}); //STHA
0x17: stda({{
- Mem.udw = readIntReg(RD & (~1))<31:0> | (readIntReg(RD | 1)<31:0> << 32);
+ Mem.udw = RdLow<31:0> | RdHigh<31:0> << 32;
}}); //STDA
0x18: ldswa({{Rd.sw = Mem.sw;}}); //LDSWA
0x19: ldsba({{Rd.sb = Mem.sb;}}); //LDSBA
diff --git a/arch/sparc/isa/formats.isa b/arch/sparc/isa/formats.isa
index 9310ba3d3..8683f5e01 100644
--- a/arch/sparc/isa/formats.isa
+++ b/arch/sparc/isa/formats.isa
@@ -1,28 +1,28 @@
//Include the basic format
//Templates from this format are used later
-##include "m5/arch/sparc/isa/formats/basic.isa"
+##include "formats/basic.isa"
//Include the integerOp and integerOpCc format
-##include "m5/arch/sparc/isa/formats/integerop.isa"
+##include "formats/integerop.isa"
//Include the memory format
-##include "m5/arch/sparc/isa/formats/mem.isa"
+##include "formats/mem.isa"
//Include the compare and swap format
-##include "m5/arch/sparc/isa/formats/cas.isa"
+##include "formats/cas.isa"
//Include the trap format
-##include "m5/arch/sparc/isa/formats/trap.isa"
+##include "formats/trap.isa"
//Include the "unknown" format
-##include "m5/arch/sparc/isa/formats/unknown.isa"
+##include "formats/unknown.isa"
//Include the priveleged mode format
-##include "m5/arch/sparc/isa/formats/priv.isa"
+##include "formats/priv.isa"
//Include the branch format
-##include "m5/arch/sparc/isa/formats/branch.isa"
+##include "formats/branch.isa"
//Include the noop format
-##include "m5/arch/sparc/isa/formats/noop.isa"
+##include "formats/noop.isa"
diff --git a/arch/sparc/isa/formats/mem.isa b/arch/sparc/isa/formats/mem.isa
index 06725eae8..f1162e24b 100644
--- a/arch/sparc/isa/formats/mem.isa
+++ b/arch/sparc/isa/formats/mem.isa
@@ -34,9 +34,10 @@ def template MemExecute {{
Trace::InstRecord *traceData) const
{
Fault fault = NoFault;
+ Addr EA;
%(op_decl)s;
%(op_rd)s;
- ea_code
+ %(ea_code)s;
%(code)s;
if(fault == NoFault)
@@ -51,12 +52,17 @@ def template MemExecute {{
// Primary format for integer operate instructions:
def format Mem(code, *opt_flags) {{
- orig_code = code
- cblk = CodeBlock(code)
- iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
+ addrCalc = 'EA = I ? (Rs1 + SIMM13) : Rs1 + Rs2;'
+ composite = code + '\n' + addrCalc
+ origCodeBlk = CodeBlock(code)
+ compositeBlk = CodeBlock(composite)
+ addrCalcBlk = CodeBlock(addrCalc)
+ iop = InstObjParams(name, Name, 'SparcStaticInst', compositeBlk, opt_flags)
+ iop.code = origCodeBlk.code
+ iop.orig_code = origCodeBlk.orig_code
+ iop.ea_code = addrCalcBlk.code
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
exec_output = MemExecute.subst(iop)
- exec_output.replace('ea_code', 'EA = I ? (R1 + SIMM13) : R1 + R2;');
}};
diff --git a/arch/sparc/isa/formats/priv.isa b/arch/sparc/isa/formats/priv.isa
index c89e769b4..162ad5ee0 100644
--- a/arch/sparc/isa/formats/priv.isa
+++ b/arch/sparc/isa/formats/priv.isa
@@ -91,12 +91,18 @@ def template PrivExecute {{
%(op_decl)s;
%(op_rd)s;
+ //Since these are processed inside templates and not in codeblocks,
+ //They aren't translated by the isa_parser. Their names begin with
+ //underscores so they don't cause conflicts.
+ uint32_t _PstatePriv = xc->readMiscReg(MISCREG_PSTATE_PRIV);
+
//If the processor isn't in privileged mode, fault out right away
- if(!PstatePriv)
- return new PrivilegedOpcode
+ if(!_PstatePriv)
+ return new PrivilegedOpcode;
%(code)s;
%(op_wb)s;
+ return NoFault;
}
}};
@@ -107,12 +113,18 @@ def template PrivTickExecute {{
%(op_decl)s;
%(op_rd)s;
+ //Since these are processed inside templates and not in codeblocks,
+ //They aren't translated by the isa_parser. Their names begin with
+ //underscores so they don't cause conflicts.
+ uint32_t _PstatePriv = xc->readMiscReg(MISCREG_PSTATE_PRIV);
+ uint32_t _TickNpt = xc->readMiscReg(MISCREG_TICK_NPT);
//If the processor isn't in privileged mode, fault out right away
- if(!PstatePriv && TickNpt)
- return new PrivilegedAction
+ if(!_PstatePriv && _TickNpt)
+ return new PrivilegedAction;
%(code)s;
%(op_wb)s;
+ return NoFault;
}
}};
diff --git a/arch/sparc/isa/formats/trap.isa b/arch/sparc/isa/formats/trap.isa
index 935fbfe6b..db4494132 100644
--- a/arch/sparc/isa/formats/trap.isa
+++ b/arch/sparc/isa/formats/trap.isa
@@ -36,6 +36,8 @@ def template TrapExecute {{
Trace::InstRecord *traceData) const
{
Fault fault = NoFault;
+ %(op_decl)s;
+ %(op_rd)s;
%(code)s
return fault;
}
diff --git a/arch/sparc/isa/main.isa b/arch/sparc/isa/main.isa
index ab0290d58..35167d6b7 100644
--- a/arch/sparc/isa/main.isa
+++ b/arch/sparc/isa/main.isa
@@ -26,7 +26,7 @@
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-##include "m5/arch/sparc/isa/includes.isa"
+##include "includes.isa"
////////////////////////////////////////////////////////////////////
//
@@ -37,16 +37,16 @@
namespace SparcISA;
//Include the bitfield definitions
-##include "m5/arch/sparc/isa/bitfields.isa"
+##include "bitfields.isa"
//Include the operand_types and operand definitions
-##include "m5/arch/sparc/isa/operands.isa"
+##include "operands.isa"
//Include the base class for sparc instructions, and some support code
-##include "m5/arch/sparc/isa/base.isa"
+##include "base.isa"
//Include the definitions for the instruction formats
-##include "m5/arch/sparc/isa/formats.isa"
+##include "formats.isa"
//Include the decoder definition
-##include "m5/arch/sparc/isa/decoder.isa"
+##include "decoder.isa"
diff --git a/arch/sparc/isa/operands.isa b/arch/sparc/isa/operands.isa
index abfdf7bcd..0d521fae0 100644
--- a/arch/sparc/isa/operands.isa
+++ b/arch/sparc/isa/operands.isa
@@ -16,18 +16,20 @@ def operands {{
# Int regs default to unsigned, but code should not count on this.
# For clarity, descriptions that depend on unsigned behavior should
# explicitly specify '.uq'.
- 'Rd': ('IntReg', 'udw', 'RD', 'IsInteger', 1),
- 'Rs1': ('IntReg', 'udw', 'RS1', 'IsInteger', 2),
- 'Rs2': ('IntReg', 'udw', 'RS2', 'IsInteger', 3),
+ 'Rd': ('IntReg', 'udw', 'RD', 'IsInteger', 1),
+ 'RdLow': ('IntReg', 'udw', 'RD & (~1)', 'IsInteger', 2),
+ 'RdHigh': ('IntReg', 'udw', 'RD | 1', 'IsInteger', 3),
+ 'Rs1': ('IntReg', 'udw', 'RS1', 'IsInteger', 4),
+ 'Rs2': ('IntReg', 'udw', 'RS2', 'IsInteger', 5),
#'Fa': ('FloatReg', 'df', 'FA', 'IsFloating', 1),
#'Fb': ('FloatReg', 'df', 'FB', 'IsFloating', 2),
#'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3),
- 'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
+ 'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
#'NPC': ('NPC', 'uq', None, ( None, None, 'IsControl' ), 4),
#'Runiq': ('ControlReg', 'uq', 'Uniq', None, 1),
#'FPCR': ('ControlReg', 'uq', 'Fpcr', None, 1),
- 'R0': ('IntReg', 'udw', '0', None, 1),
- 'R16': ('IntReg', 'udw', '16', None, 1),
+ 'R0': ('IntReg', 'udw', '0', None, 1),
+ 'R16': ('IntReg', 'udw', '16', None, 1),
# Control registers
'Pstate': ('ControlReg', 'udw', 'MISCREG_PSTATE', None, 1),
'PstateAg': ('ControlReg', 'udw', 'MISCREG_PSTATE_AG', None, 2),
diff --git a/arch/sparc/isa_traits.hh b/arch/sparc/isa_traits.hh
index 4886da7cf..6cf77eb0e 100644
--- a/arch/sparc/isa_traits.hh
+++ b/arch/sparc/isa_traits.hh
@@ -90,6 +90,9 @@ namespace SparcISA
// 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag)
FP_Base_DepTag = 32,
Ctrl_Base_DepTag = 96,
+ //XXX These are here solely to get compilation and won't work
+ Fpcr_DepTag = 0,
+ Uniq_DepTag = 0
};
//This makes sure the big endian versions of certain functions are used.
@@ -98,11 +101,6 @@ namespace SparcISA
typedef uint32_t MachInst;
typedef uint64_t ExtMachInst;
- inline ExtMachInst
- makeExtMI(MachInst inst, const Addr &pc) {
- return ExtMachInst(inst);
- }
-
const int NumIntRegs = 32;
const int NumFloatRegs = 64;
const int NumMiscRegs = 32;
@@ -160,31 +158,6 @@ namespace SparcISA
// return a no-op instruction... used for instruction fetch faults
extern const MachInst NoopMachInst;
-
- // Instruction address compression hooks
- inline Addr realPCToFetchPC(const Addr &addr)
- {
- return addr;
- }
-
- inline Addr fetchPCToRealPC(const Addr &addr)
- {
- return addr;
- }
-
- // the size of "fetched" instructions (not necessarily the size
- // of real instructions for PISA)
- inline size_t fetchInstSize()
- {
- return sizeof(MachInst);
- }
-
- /**
- * Function to insure ISA semantics about 0 registers.
- * @param xc The execution context.
- */
- template <class XC>
- void zeroRegisters(XC *xc);
}
#include "arch/sparc/regfile.hh"
diff --git a/arch/sparc/regfile.hh b/arch/sparc/regfile.hh
index 944fdfe80..09b8e49d7 100644
--- a/arch/sparc/regfile.hh
+++ b/arch/sparc/regfile.hh
@@ -55,15 +55,15 @@ namespace SparcISA
class FloatRegFile
{
protected:
- //Since the floating point registers overlap each other,
- //A generic storage space is used. The float to be returned is
- //pulled from the appropriate section of this region.
- char regSpace[32 * 64];
-
static const int SingleWidth = 32;
static const int DoubleWidth = 64;
static const int QuadWidth = 128;
+ //Since the floating point registers overlap each other,
+ //A generic storage space is used. The float to be returned is
+ //pulled from the appropriate section of this region.
+ char regSpace[SingleWidth / 8 * NumFloatRegs];
+
public:
FloatReg readReg(int floatReg, int width)
diff --git a/arch/sparc/utility.hh b/arch/sparc/utility.hh
new file mode 100644
index 000000000..1e67b3370
--- /dev/null
+++ b/arch/sparc/utility.hh
@@ -0,0 +1,89 @@
+/*
+ * Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __ARCH_SPARC_UTILITY_HH__
+#define __ARCH_SPARC_UTILITY_HH__
+
+#include "arch/sparc/isa_traits.hh"
+#include "base/misc.hh"
+
+namespace SparcISA
+{
+ inline ExtMachInst
+ makeExtMI(MachInst inst, const Addr &pc) {
+ return ExtMachInst(inst);
+ }
+
+ inline bool isCallerSaveIntegerRegister(unsigned int reg) {
+ panic("register classification not implemented");
+ return false;
+ }
+
+ inline bool isCalleeSaveIntegerRegister(unsigned int reg) {
+ panic("register classification not implemented");
+ return false;
+ }
+
+ inline bool isCallerSaveFloatRegister(unsigned int reg) {
+ panic("register classification not implemented");
+ return false;
+ }
+
+ inline bool isCalleeSaveFloatRegister(unsigned int reg) {
+ panic("register classification not implemented");
+ return false;
+ }
+
+ // Instruction address compression hooks
+ inline Addr realPCToFetchPC(const Addr &addr)
+ {
+ return addr;
+ }
+
+ inline Addr fetchPCToRealPC(const Addr &addr)
+ {
+ return addr;
+ }
+
+ // the size of "fetched" instructions (not necessarily the size
+ // of real instructions for PISA)
+ inline size_t fetchInstSize()
+ {
+ return sizeof(MachInst);
+ }
+
+ /**
+ * Function to insure ISA semantics about 0 registers.
+ * @param xc The execution context.
+ */
+ template <class XC>
+ void zeroRegisters(XC *xc);
+
+} // namespace SparcISA
+
+#endif
diff --git a/base/timebuf.hh b/base/timebuf.hh
index 435803fae..f6b5b2781 100644
--- a/base/timebuf.hh
+++ b/base/timebuf.hh
@@ -31,8 +31,6 @@
#include <vector>
-using namespace std;
-
template <class T>
class TimeBuffer
{
@@ -42,7 +40,7 @@ class TimeBuffer
int size;
char *data;
- vector<char *> index;
+ std::vector<char *> index;
int base;
void valid(int idx)
diff --git a/build/SConstruct b/build/SConstruct
index 306d3a9dc..e1854b1d3 100644
--- a/build/SConstruct
+++ b/build/SConstruct
@@ -231,6 +231,11 @@ sticky_opts = Options(args=ARGUMENTS)
sticky_opts.AddOptions(
EnumOption('TARGET_ISA', 'Target ISA', 'alpha', env['ALL_ISA_LIST']),
BoolOption('FULL_SYSTEM', 'Full-system support', False),
+ # There's a bug in scons 0.96.1 that causes ListOptions with list
+ # values (more than one value) not to be able to be restored from
+ # a saved option file. If this causes trouble then upgrade to
+ # scons 0.96.90 or later.
+ ListOption('CPU_MODELS', 'CPU models', 'all', env['ALL_CPU_LIST']),
BoolOption('ALPHA_TLASER',
'Model Alpha TurboLaser platform (vs. Tsunami)', False),
BoolOption('NO_FAST_ALLOC', 'Disable fast object allocator', False),
@@ -254,12 +259,6 @@ sticky_opts.AddOptions(
# Non-sticky options only apply to the current build.
nonsticky_opts = Options(args=ARGUMENTS)
nonsticky_opts.AddOptions(
- # This really should be a sticky option, but there's a bug in
- # scons 0.96.1 that causes ListOptions not to be able to be
- # restored from a saved option file. It looks like this is fixed
- # in 0.96.9, but there's a different bug in that version that means we
- # can't just upgrade.
- ListOption('CPU_MODELS', 'CPU models', 'all', env['ALL_CPU_LIST']),
BoolOption('update_ref', 'Update test reference outputs', False)
)
diff --git a/kern/tru64/tru64.hh b/kern/tru64/tru64.hh
index 3f5ef3dea..b4f45e650 100644
--- a/kern/tru64/tru64.hh
+++ b/kern/tru64/tru64.hh
@@ -55,8 +55,6 @@ class Tru64 {};
#include "sim/root.hh"
#include "sim/syscall_emul.hh"
-using namespace std;
-
typedef struct stat global_stat;
typedef struct statfs global_statfs;
typedef struct dirent global_dirent;
@@ -751,6 +749,7 @@ class Tru64 {
tableFunc(SyscallDesc *desc, int callnum, Process *process,
ExecContext *xc)
{
+ using namespace std;
using namespace TheISA;
int id = xc->getSyscallArg(0); // table ID
@@ -824,6 +823,7 @@ class Tru64 {
nxm_task_initFunc(SyscallDesc *desc, int callnum, Process *process,
ExecContext *xc)
{
+ using namespace std;
using namespace TheISA;
TypedBufferArg<Tru64::nxm_task_attr> attrp(xc->getSyscallArg(0));
@@ -957,6 +957,7 @@ class Tru64 {
nxm_thread_createFunc(SyscallDesc *desc, int callnum, Process *process,
ExecContext *xc)
{
+ using namespace std;
using namespace TheISA;
TypedBufferArg<Tru64::nxm_thread_attr> attrp(xc->getSyscallArg(0));
@@ -1081,6 +1082,8 @@ class Tru64 {
nxm_thread_blockFunc(SyscallDesc *desc, int callnum, Process *process,
ExecContext *xc)
{
+ using namespace std;
+
uint64_t tid = xc->getSyscallArg(0);
uint64_t secs = xc->getSyscallArg(1);
uint64_t flags = xc->getSyscallArg(2);
@@ -1098,6 +1101,8 @@ class Tru64 {
nxm_blockFunc(SyscallDesc *desc, int callnum, Process *process,
ExecContext *xc)
{
+ using namespace std;
+
Addr uaddr = xc->getSyscallArg(0);
uint64_t val = xc->getSyscallArg(1);
uint64_t secs = xc->getSyscallArg(2);
@@ -1119,6 +1124,8 @@ class Tru64 {
nxm_unblockFunc(SyscallDesc *desc, int callnum, Process *process,
ExecContext *xc)
{
+ using namespace std;
+
Addr uaddr = xc->getSyscallArg(0);
cout << xc->getCpuPtr()->name() << ": nxm_unblock "
@@ -1149,6 +1156,8 @@ class Tru64 {
activate_waiting_context(Addr uaddr, Process *process,
bool activate_all = false)
{
+ using namespace std;
+
int num_activated = 0;
list<Process::WaitRec>::iterator i = process->waitList.begin();
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-27 19:38:40 +0000