diff options
| -rw-r--r-- | src/arch/arm/isa.cc | 7 | ||||
| -rw-r--r-- | src/arch/arm/miscregs.hh | 3 | ||||
| -rw-r--r-- | src/arch/arm/utility.cc | 24 | ||||
| -rw-r--r-- | src/sim/serialize.hh | 2 | ||||
| -rwxr-xr-x | util/cpt_upgrader.py | 14 |
5 files changed, 22 insertions, 28 deletions
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index 99acbb4fd..117873450 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -654,13 +654,6 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) tc->getITBPtr()->invalidateMiscReg(); tc->getDTBPtr()->invalidateMiscReg(); break; - case MISCREG_CPSR_MODE: - // This miscreg is used by copy*Regs to set the CPSR mode - // without updating other CPSR variables. It's used to - // make sure the register map is in such a state that we can - // see all of the registers for the copy. - updateRegMap(val); - return; case MISCREG_L2CTLR: warn("miscreg L2CTLR (%s) written with %#x. ignored...\n", miscRegName[misc_reg], uint32_t(val)); diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh index 2dceab70c..02c03a7fc 100644 --- a/src/arch/arm/miscregs.hh +++ b/src/arch/arm/miscregs.hh @@ -209,7 +209,6 @@ namespace ArmISA MISCREG_ID_ISAR3, MISCREG_ID_ISAR4, MISCREG_ID_ISAR5, - MISCREG_CPSR_MODE, MISCREG_LOCKFLAG, MISCREG_LOCKADDR, MISCREG_ID_PFR1, @@ -311,7 +310,7 @@ namespace ArmISA "pmceid1", "pmc_other", "pmxevcntr", "pmuserenr", "pmintenset", "pmintenclr", "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5", - "cpsr_mode", "lockflag", "lockaddr", "id_pfr1", + "lockflag", "lockaddr", "id_pfr1", "l2ctlr", // Unimplemented below "tcmtr", diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc index 71ad21e1e..776c1ae82 100644 --- a/src/arch/arm/utility.cc +++ b/src/arch/arm/utility.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2009-2010 ARM Limited + * Copyright (c) 2009-2012 ARM Limited * All rights reserved. * * The license below extends only to copyright in the software and shall @@ -127,25 +127,13 @@ skipFunction(ThreadContext *tc) void copyRegs(ThreadContext *src, ThreadContext *dest) { - int i; + for (int i = 0; i < TheISA::NumIntRegs; i++) + dest->setIntRegFlat(i, src->readIntRegFlat(i)); - int saved_mode = ((CPSR)src->readMiscReg(MISCREG_CPSR)).mode; + for (int i = 0; i < TheISA::NumFloatRegs; i++) + dest->setFloatRegFlat(i, src->readFloatRegFlat(i)); - // Make sure we're in user mode, so we can easily see all the registers - // in the copy loop - src->setMiscReg(MISCREG_CPSR_MODE, MODE_USER); - dest->setMiscReg(MISCREG_CPSR_MODE, MODE_USER); - - for(i = 0; i < TheISA::NumIntRegs; i++) - dest->setIntReg(i, src->readIntReg(i)); - - // Restore us back to the old mode - src->setMiscReg(MISCREG_CPSR_MODE, saved_mode); - dest->setMiscReg(MISCREG_CPSR_MODE, saved_mode); - - for(i = 0; i < TheISA::NumFloatRegs; i++) - dest->setFloatReg(i, src->readFloatReg(i)); - for(i = 0; i < TheISA::NumMiscRegs; i++) + for (int i = 0; i < TheISA::NumMiscRegs; i++) dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i)); // setMiscReg "with effect" will set the misc register mapping correctly. diff --git a/src/sim/serialize.hh b/src/sim/serialize.hh index c3c857115..dd33ae74f 100644 --- a/src/sim/serialize.hh +++ b/src/sim/serialize.hh @@ -57,7 +57,7 @@ class SimObject; * SimObject shouldn't cause the version number to increase, only changes to * existing objects such as serializing/unserializing more state, changing sizes * of serialized arrays, etc. */ -static const uint64_t gem5CheckpointVersion = 0x0000000000000004; +static const uint64_t gem5CheckpointVersion = 0x0000000000000005; template <class T> void paramOut(std::ostream &os, const std::string &name, const T ¶m); diff --git a/util/cpt_upgrader.py b/util/cpt_upgrader.py index 4dbca3fcb..e1f56b3ba 100755 --- a/util/cpt_upgrader.py +++ b/util/cpt_upgrader.py @@ -180,6 +180,19 @@ def from_3(cpt): for (key, value) in options: cpt.set(sec, key, value) +# Version 5 of the checkpoint format removes the MISCREG_CPSR_MODE +# register from the ARM register file. +def from_4(cpt): + if cpt.get('root','isa') == 'arm': + for sec in cpt.sections(): + import re + # Search for all ISA sections + if re.search('.*sys.*\.cpu.*\.isa', sec): + mr = cpt.get(sec, 'miscRegs').split() + # Remove MISCREG_CPSR_MODE + del mr[137] + cpt.set(sec, 'miscRegs', ' '.join(str(x) for x in mr)) + migrations = [] @@ -187,6 +200,7 @@ migrations.append(from_0) migrations.append(from_1) migrations.append(from_2) migrations.append(from_3) +migrations.append(from_4) verbose_print = False |