diff options
| -rw-r--r-- | src/arch/x86/isa/insts/system/msrs.py | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/src/arch/x86/isa/insts/system/msrs.py b/src/arch/x86/isa/insts/system/msrs.py index b79b6dbe9..04020ef67 100644 --- a/src/arch/x86/isa/insts/system/msrs.py +++ b/src/arch/x86/isa/insts/system/msrs.py @@ -63,8 +63,7 @@ def macroop RDTSC .serialize_before rdtsc t1 mov rax, rax, t1, dataSize=4 - srli t1, t1, 32, dataSize=8 - mov rdx, rdx, t1, dataSize=4 + srli rdx, t1, 32, dataSize=8 }; def macroop RDTSCP @@ -73,8 +72,7 @@ def macroop RDTSCP mfence rdtsc t1 mov rax, rax, t1, dataSize=4 - srli t1, t1, 32, dataSize=8 - mov rdx, rdx, t1, dataSize=4 + srli rdx, t1, 32, dataSize=8 rdval rcx, "InstRegIndex(MISCREG_TSC_AUX)", dataSize=4 }; ''' |