diff options
| -rw-r--r-- | src/cpu/BaseCPU.py | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py index c100f0ed5..3e82daf29 100644 --- a/src/cpu/BaseCPU.py +++ b/src/cpu/BaseCPU.py @@ -299,9 +299,10 @@ class BaseCPU(MemObject): self._cached_ports += ["checker.itb.walker.port", \ "checker.dtb.walker.port"] - def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None): + def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc=None, dwc=None, + xbar=None): self.addPrivateSplitL1Caches(ic, dc, iwc, dwc) - self.toL2Bus = L2XBar() + self.toL2Bus = xbar if xbar else L2XBar() self.connectCachedPorts(self.toL2Bus) self.l2cache = l2c self.toL2Bus.master = self.l2cache.cpu_side |