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-rw-r--r--src/arch/arm/isa.hh7
-rw-r--r--src/arch/arm/miscregs.hh9
2 files changed, 12 insertions, 4 deletions
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 1d8f14cab..f6ad56dd4 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -168,6 +168,10 @@ namespace ArmISA
case MISCREG_CLIDR:
warn("The clidr register always reports 0 caches.\n");
break;
+ case MISCREG_CCSIDR:
+ warn("The ccsidr register isn't implemented and "
+ "always reads as 0.\n");
+ break;
}
return readMiscRegNoEffect(misc_reg);
}
@@ -235,6 +239,9 @@ namespace ArmISA
panic("Disabling coprocessors isn't implemented.\n");
}
break;
+ case MISCREG_CSSELR:
+ warn("The csselr register isn't implemented.\n");
+ break;
}
return setMiscRegNoEffect(misc_reg, newVal);
}
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index d66ce0f78..49b015984 100644
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -94,6 +94,8 @@ namespace ArmISA
MISCREG_CP15DMB,
MISCREG_CPACR,
MISCREG_CLIDR,
+ MISCREG_CCSIDR,
+ MISCREG_CSSELR,
MISCREG_ICIALLUIS,
MISCREG_ICIALLU,
MISCREG_ICIMVAU,
@@ -118,9 +120,7 @@ namespace ArmISA
MISCREG_ID_ISAR3,
MISCREG_ID_ISAR4,
MISCREG_ID_ISAR5,
- MISCREG_CCSIDR,
MISCREG_AIDR,
- MISCREG_CSSELR,
MISCREG_ACTLR,
MISCREG_DFSR,
MISCREG_IFSR,
@@ -160,13 +160,14 @@ namespace ArmISA
"fpsr", "fpsid", "fpscr", "fpexc",
"sctlr", "dccisw", "dccimvac", "dccmvac",
"contextidr", "tpidrurw", "tpidruro", "tpidrprw",
- "cp15isb", "cp15dsb", "cp15dmb", "cpacr", "clidr",
+ "cp15isb", "cp15dsb", "cp15dmb", "cpacr",
+ "clidr", "ccsidr", "csselr",
"icialluis", "iciallu", "icimvau", "bpimva",
"ctr", "tcmtr", "mpuir", "mpidr", "midr",
"id_pfr0", "id_pfr1", "id_dfr0", "id_afr0",
"id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3",
"id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
- "ccsidr", "aidr", "csselr", "actlr",
+ "aidr", "actlr",
"dfsr", "ifsr", "adfsr", "aifsr", "dfar", "ifar",
"drbar", "irbar", "drsr", "irsr", "dracr", "iracr",
"rgnr", "bpiallis",