diff options
| -rw-r--r-- | arch/alpha/isa_traits.hh | 2 | ||||
| -rw-r--r-- | arch/mips/isa/decoder.isa | 12 | ||||
| -rw-r--r-- | arch/mips/isa_traits.hh | 103 | ||||
| -rw-r--r-- | arch/sparc/isa_traits.hh | 1 | ||||
| -rw-r--r-- | cpu/cpu_exec_context.hh | 11 | ||||
| -rw-r--r-- | cpu/simple/cpu.cc | 8 |
6 files changed, 105 insertions, 32 deletions
diff --git a/arch/alpha/isa_traits.hh b/arch/alpha/isa_traits.hh index 8e1f21a35..3cd6868b8 100644 --- a/arch/alpha/isa_traits.hh +++ b/arch/alpha/isa_traits.hh @@ -202,6 +202,8 @@ extern const int reg_redir[NumIntRegs]; MiscRegFile miscRegs; // control register file Addr pc; // program counter Addr npc; // next-cycle program counter + Addr nnpc; + #if FULL_SYSTEM int intrflag; // interrupt flag inline int instAsid() diff --git a/arch/mips/isa/decoder.isa b/arch/mips/isa/decoder.isa index 9994acd0b..3f054f6a5 100644 --- a/arch/mips/isa/decoder.isa +++ b/arch/mips/isa/decoder.isa @@ -30,7 +30,17 @@ decode OPCODE_HI default Unknown::unknown() { //Table A-3 Note: "1. Specific encodings of the rt, rd, and sa fields //are used to distinguish among the SLL, NOP, SSNOP and EHB functions." - 0x0: sll({{ Rd = Rt.uw << SA; }}); + 0x0: decode RS { + 0x0: decode RT default BasicOp::sll({{ Rd = Rt.uw << SA; }}) { + 0x0: decode RD{ + 0x0: decode HINT { + 0x0:nop({{}}); //really sll r0,r0,0 + 0x1:ssnop({{}});//really sll r0,r0,1 + 0x3:ehb({{}}); //really sll r0,r0,3 + } + } + } + } 0x2: decode SRL { 0: srl({{ Rd = Rt.uw >> SA; }}); diff --git a/arch/mips/isa_traits.hh b/arch/mips/isa_traits.hh index 408cc3463..1dfa0dc7a 100644 --- a/arch/mips/isa_traits.hh +++ b/arch/mips/isa_traits.hh @@ -65,7 +65,7 @@ namespace MipsISA NumIntRegs = 32, NumFloatRegs = 32, - NumMiscRegs = 256, + NumMiscRegs = 258, //account for hi,lo regs MaxRegsOfAnyType = 32, // Static instruction parameters @@ -127,8 +127,50 @@ namespace MipsISA // cop-0/cop-1 system control register file typedef uint64_t MiscReg; - typedef MiscReg MiscRegFile[NumMiscRegs]; +//typedef MiscReg MiscRegFile[NumMiscRegs]; + class MiscRegFile { + public: + MiscReg + protected: + uint64_t fpcr; // floating point condition codes + uint64_t uniq; // process-unique register + bool lock_flag; // lock flag for LL/SC + Addr lock_addr; // lock address for LL/SC + MiscReg miscRegFile[NumMiscRegs]; + + public: + //These functions should be removed once the simplescalar cpu model + //has been replaced. + int getInstAsid(); + int getDataAsid(); + + MiscReg readReg(int misc_reg) + { return miscRegFile[misc_reg]; } + + MiscReg readRegWithEffect(int misc_reg, Fault &fault, ExecContext *xc) + { return miscRegFile[misc_reg];} + + Fault setReg(int misc_reg, const MiscReg &val) + { miscRegFile[misc_reg] = val; return NoFault; } + + Fault setRegWithEffect(int misc_reg, const MiscReg &val, + ExecContext *xc) + { miscRegFile[misc_reg] = val; return NoFault; } + +#if FULL_SYSTEM + void clearIprs() { }; + + protected: + InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs + + private: + MiscReg readIpr(int idx, Fault &fault, ExecContext *xc) { } + + Fault setIpr(int idx, uint64_t val, ExecContext *xc) { } +#endif + friend class RegFile; + }; enum MiscRegTags { //Coprocessor 0 Registers @@ -207,10 +249,10 @@ namespace MipsISA EPC = 105,//105-112 //14-0 Program counter at last exception - PrId = 113//113-120, //15-0 Processor identification and revision + PRId = 113//113-120, //15-0 Processor identification and revision EBase = 114, //15-1 Exception vector base register - Config = 121,//121-128 + Config = 121,//Bank 16: 121-128 Config1 = 122, Config2 = 123, Config3 = 124, @@ -218,9 +260,9 @@ namespace MipsISA Config7 = 128, - LLAddr = 129,//129-136 + LLAddr = 129,//Bank 17: 129-136 - WatchLo0 = 137,//137-144 + WatchLo0 = 137,//Bank 18: 137-144 WatchLo1 = 138, WatchLo2 = 139, WatchLo3 = 140, @@ -229,7 +271,7 @@ namespace MipsISA WatchLo6 = 143, WatchLo7 = 144, - WatchHi0 = 145,//145-152 + WatchHi0 = 145,//Bank 19: 145-152 WatchHi1 = 146, WatchHi2 = 147, WatchHi3 = 148, @@ -238,21 +280,21 @@ namespace MipsISA WatchHi6 = 151, WatchHi7 = 152, - XCContext64 = 153,//153-160 + XCContext64 = 153,//Bank 20: 153-160 - //161-168 + //Bank 21: 161-168 - //169-176 + //Bank 22: 169-176 - Debug = 177, //177-184 + Debug = 177, //Bank 23: 177-184 TraceControl1 = 178, TraceControl2 = 179, UserTraceData = 180, TraceBPC = 181, - DEPC = 185,//185-192 + DEPC = 185,//Bank 24: 185-192 - PerfCnt0 = 193,//193 - 200 + PerfCnt0 = 193,//Bank 25: 193 - 200 PerfCnt1 = 194, PerfCnt2 = 195, PerfCnt3 = 196, @@ -261,48 +303,47 @@ namespace MipsISA PerfCnt6 = 199, PerfCnt7 = 200, - ErrCtl = 201, //201 - 208 + ErrCtl = 201, //Bank 26: 201 - 208 - CacheErr0 = 209, //209 - 216 + CacheErr0 = 209, //Bank 27: 209 - 216 CacheErr1 = 210, CacheErr2 = 211, CacheErr3 = 212, - TagLo0 = 217,//217 - 224 + TagLo0 = 217,//Bank 28: 217 - 224 + DataLo1 = 218, TagLo2 = 219, + DataLo3 = 220, TagLo4 = 221, + DataLo5 = 222, TagLo6 = 223, + DataLo7 = 234, - DataLo1 = 226,//225 - 232 - DataLo3 = 228, - DataLo5 = 220, - DataLo7 = 232, - - TagHi0 = 233,//233 - 240 + TagHi0 = 233,//Bank 29: 233 - 240 + DataHi1 = 234, TagHi2 = 235, + DataHi3 = 236, TagHi4 = 237, + DataHi5 = 238, TagHi6 = 239, + DataHi7 = 240, - DataHi0 = 241,//241 - 248 - DataHi2 = 243, - DataHi4 = 245, - DataHi6 = 247, - ErrorEPC = 249,//249 - 256 + ErrorEPC = 249,//Bank 30: 241 - 248 - DESAVE = 257, + DESAVE = 257,//Bank 31: 249-256 //More Misc. Regs Hi, Lo, FCSR, FPCR, - LockAddr, - LockFlag, //Alpha Regs, but here now, for //compiling sake - UNIQ + UNIQ, + LockAddr, + LockFlag }; extern const Addr PageShift; diff --git a/arch/sparc/isa_traits.hh b/arch/sparc/isa_traits.hh index c592a05ed..1752ed194 100644 --- a/arch/sparc/isa_traits.hh +++ b/arch/sparc/isa_traits.hh @@ -409,6 +409,7 @@ namespace SparcISA Addr pc; // Program Counter Addr npc; // Next Program Counter + Addr nnpc; void serialize(std::ostream &os); void unserialize(Checkpoint *cp, const std::string §ion); diff --git a/cpu/cpu_exec_context.hh b/cpu/cpu_exec_context.hh index e2fbb2368..a5153e618 100644 --- a/cpu/cpu_exec_context.hh +++ b/cpu/cpu_exec_context.hh @@ -445,6 +445,17 @@ class CPUExecContext regs.npc = val; } + uint64_t readNextNPC() + { + return regs.nnpc; + } + + void setNextNPC(uint64_t val) + { + regs.nnpc = val; + } + + MiscReg readMiscReg(int misc_reg) { return regs.miscRegs.readReg(misc_reg); diff --git a/cpu/simple/cpu.cc b/cpu/simple/cpu.cc index fd0163677..8db72b77e 100644 --- a/cpu/simple/cpu.cc +++ b/cpu/simple/cpu.cc @@ -823,9 +823,17 @@ SimpleCPU::tick() #endif // FULL_SYSTEM } else { +#if THE_ISA != MIPS_ISA // go to the next instruction cpuXC->setPC(cpuXC->readNextPC()); cpuXC->setNextPC(cpuXC->readNextPC() + sizeof(MachInst)); +#else + // go to the next instruction + cpuXC->setPC(cpuXC->readNextPC()); + cpuXC->setNextPC(cpuXC->readNextNPC()); + cpuXC->setNextNPC(cpuXC->readNextNPC() + sizeof(MachInst)); +#endif + } #if FULL_SYSTEM |