diff options
-rw-r--r-- | src/cpu/base_dyn_inst.hh | 42 | ||||
-rw-r--r-- | src/cpu/base_dyn_inst_impl.hh | 1 | ||||
-rw-r--r-- | src/cpu/o3/alpha/cpu_impl.hh | 2 | ||||
-rw-r--r-- | src/cpu/o3/fetch_impl.hh | 16 | ||||
-rw-r--r-- | src/cpu/o3/lsq_unit.hh | 9 | ||||
-rw-r--r-- | src/cpu/o3/lsq_unit_impl.hh | 40 | ||||
-rw-r--r-- | tests/long/00.gzip/test.py | 5 | ||||
-rw-r--r-- | tests/long/10.mcf/test.py | 5 | ||||
-rw-r--r-- | tests/long/20.parser/test.py | 6 | ||||
-rw-r--r-- | tests/long/30.eon/test.py | 8 | ||||
-rw-r--r-- | tests/long/40.perlbmk/test.py | 5 | ||||
-rw-r--r-- | tests/long/50.vortex/test.py | 5 | ||||
-rw-r--r-- | tests/long/60.bzip2/test.py | 5 | ||||
-rw-r--r-- | tests/long/70.twolf/test.py | 5 | ||||
-rw-r--r-- | tests/run.py | 7 |
15 files changed, 105 insertions, 56 deletions
diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh index c68810954..4a4555566 100644 --- a/src/cpu/base_dyn_inst.hh +++ b/src/cpu/base_dyn_inst.hh @@ -206,6 +206,9 @@ class BaseDynInst : public FastAlloc, public RefCounted */ Result instResult; + /** Records changes to result? */ + bool recordResult; + /** PC of this instruction. */ Addr PC; @@ -263,6 +266,9 @@ class BaseDynInst : public FastAlloc, public RefCounted /** Dumps out contents of this BaseDynInst into given string. */ void dump(std::string &outstring); + /** Read this CPU's ID. */ + int readCpuId() { return cpu->readCpuId(); } + /** Returns the fault type. */ Fault getFault() { return fault; } @@ -402,37 +408,42 @@ class BaseDynInst : public FastAlloc, public RefCounted /** Records an integer register being set to a value. */ void setIntReg(const StaticInst *si, int idx, uint64_t val) { - instResult.integer = val; + if (recordResult) + instResult.integer = val; } /** Records an fp register being set to a value. */ void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width) { - if (width == 32) - instResult.dbl = (double)val; - else if (width == 64) - instResult.dbl = val; - else - panic("Unsupported width!"); + if (recordResult) { + if (width == 32) + instResult.dbl = (double)val; + else if (width == 64) + instResult.dbl = val; + else + panic("Unsupported width!"); + } } /** Records an fp register being set to a value. */ void setFloatReg(const StaticInst *si, int idx, FloatReg val) { -// instResult.fp = val; - instResult.dbl = (double)val; + if (recordResult) + instResult.dbl = (double)val; } /** Records an fp register being set to an integer value. */ void setFloatRegBits(const StaticInst *si, int idx, uint64_t val, int width) { - instResult.integer = val; + if (recordResult) + instResult.integer = val; } /** Records an fp register being set to an integer value. */ void setFloatRegBits(const StaticInst *si, int idx, uint64_t val) { - instResult.integer = val; + if (recordResult) + instResult.integer = val; } /** Records that one of the source registers is ready. */ @@ -624,6 +635,15 @@ class BaseDynInst : public FastAlloc, public RefCounted /** Sets iterator for this instruction in the list of all insts. */ void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; } + + public: + /** Returns the number of consecutive store conditional failures. */ + unsigned readStCondFailures() + { return thread->storeCondFailures; } + + /** Sets the number of consecutive store conditional failures. */ + void setStCondFailures(unsigned sc_failures) + { thread->storeCondFailures = sc_failures; } }; template<class Impl> diff --git a/src/cpu/base_dyn_inst_impl.hh b/src/cpu/base_dyn_inst_impl.hh index d6cdff5c5..2f6859de2 100644 --- a/src/cpu/base_dyn_inst_impl.hh +++ b/src/cpu/base_dyn_inst_impl.hh @@ -97,6 +97,7 @@ BaseDynInst<Impl>::initVars() readyRegs = 0; instResult.integer = 0; + recordResult = true; status.reset(); diff --git a/src/cpu/o3/alpha/cpu_impl.hh b/src/cpu/o3/alpha/cpu_impl.hh index 04eadfa5a..618716fc6 100644 --- a/src/cpu/o3/alpha/cpu_impl.hh +++ b/src/cpu/o3/alpha/cpu_impl.hh @@ -231,7 +231,7 @@ Fault AlphaO3CPU<Impl>::hwrei(unsigned tid) { // Need to clear the lock flag upon returning from an interrupt. - this->lockFlag = false; + this->setMiscReg(TheISA::Lock_Flag_DepTag, false, tid); this->thread[tid]->kernelStats->hwrei(); diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh index 5ef6e27ea..350ecd52d 100644 --- a/src/cpu/o3/fetch_impl.hh +++ b/src/cpu/o3/fetch_impl.hh @@ -62,7 +62,8 @@ template<class Impl> void DefaultFetch<Impl>::IcachePort::recvFunctional(PacketPtr pkt) { - warn("Default fetch doesn't update it's state from a functional call."); + DPRINTF(Fetch, "DefaultFetch doesn't update its state from a " + "functional call."); } template<class Impl> @@ -79,6 +80,7 @@ template<class Impl> bool DefaultFetch<Impl>::IcachePort::recvTiming(PacketPtr pkt) { + DPRINTF(Fetch, "Received timing\n"); if (pkt->isResponse()) { fetch->processCacheCompletion(pkt); } @@ -1158,8 +1160,8 @@ DefaultFetch<Impl>::fetch(bool &status_change) fetch_PC = next_PC; if (instruction->isQuiesce()) { -// warn("%lli: Quiesce instruction encountered, halting fetch!", -// curTick); + DPRINTF(Fetch, "Quiesce instruction encountered, halting fetch!", + curTick); fetchStatus[tid] = QuiescePending; ++numInst; status_change = true; @@ -1273,11 +1275,13 @@ DefaultFetch<Impl>::fetch(bool &status_change) fetchStatus[tid] = TrapPending; status_change = true; - -// warn("%lli fault (%d) detected @ PC %08p", curTick, fault, PC[tid]); #else // !FULL_SYSTEM - warn("cycle %lli: fault (%s) detected @ PC %08p", curTick, fault->name(), PC[tid]); + fetchStatus[tid] = TrapPending; + status_change = true; + #endif // FULL_SYSTEM + DPRINTF(Fetch, "[tid:%i]: fault (%s) detected @ PC %08p", + tid, fault->name(), PC[tid]); } } diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh index 1b207fdbc..a2e11173e 100644 --- a/src/cpu/o3/lsq_unit.hh +++ b/src/cpu/o3/lsq_unit.hh @@ -37,6 +37,7 @@ #include <queue> #include "arch/faults.hh" +#include "arch/locked_mem.hh" #include "config/full_system.hh" #include "base/hashmap.hh" #include "cpu/inst_seq.hh" @@ -510,8 +511,12 @@ LSQUnit<Impl>::read(Request *req, T &data, int load_idx) #if FULL_SYSTEM if (req->isLocked()) { - cpu->lockAddr = req->getPaddr(); - cpu->lockFlag = true; + // Disable recording the result temporarily. Writing to misc + // regs normally updates the result, but this is not the + // desired behavior when handling store conditionals. + load_inst->recordResult = false; + TheISA::handleLockedRead(load_inst.get(), req); + load_inst->recordResult = true; } #endif diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh index 9a0e48819..4facea9f9 100644 --- a/src/cpu/o3/lsq_unit_impl.hh +++ b/src/cpu/o3/lsq_unit_impl.hh @@ -29,6 +29,7 @@ * Korey Sewell */ +#include "arch/locked_mem.hh" #include "config/use_checker.hh" #include "cpu/o3/lsq.hh" @@ -615,27 +616,24 @@ LSQUnit<Impl>::writebackStores() // @todo: Remove this SC hack once the memory system handles it. if (req->isLocked()) { - if (req->isUncacheable()) { - req->setScResult(2); - } else { - if (cpu->lockFlag) { - req->setScResult(1); - DPRINTF(LSQUnit, "Store conditional [sn:%lli] succeeded.", - inst->seqNum); - } else { - req->setScResult(0); - // Hack: Instantly complete this store. -// completeDataAccess(data_pkt); - DPRINTF(LSQUnit, "Store conditional [sn:%lli] failed. " - "Instantly completing it.\n", - inst->seqNum); - WritebackEvent *wb = new WritebackEvent(inst, data_pkt, this); - wb->schedule(curTick + 1); - delete state; - completeStore(storeWBIdx); - incrStIdx(storeWBIdx); - continue; - } + // Disable recording the result temporarily. Writing to + // misc regs normally updates the result, but this is not + // the desired behavior when handling store conditionals. + inst->recordResult = false; + bool success = TheISA::handleLockedWrite(inst.get(), req); + inst->recordResult = true; + + if (!success) { + // Instantly complete this store. + DPRINTF(LSQUnit, "Store conditional [sn:%lli] failed. " + "Instantly completing it.\n", + inst->seqNum); + WritebackEvent *wb = new WritebackEvent(inst, data_pkt, this); + wb->schedule(curTick + 1); + delete state; + completeStore(storeWBIdx); + incrStIdx(storeWBIdx); + continue; } } else { // Non-store conditionals do not need a writeback. diff --git a/tests/long/00.gzip/test.py b/tests/long/00.gzip/test.py index 7a74a0b0a..5c33376bd 100644 --- a/tests/long/00.gzip/test.py +++ b/tests/long/00.gzip/test.py @@ -26,5 +26,6 @@ # # Authors: Korey Sewell -root.system.cpu.workload = LiveProcess(cmd = 'gzip smred.log 1', - executable = binpath('gzip')) +process = LiveProcess(executable = binpath('gzip')) +process.cmd = 'gzip ' + inputpath('gzip', 'smred.log') + ' 1' +root.system.cpu.workload = process diff --git a/tests/long/10.mcf/test.py b/tests/long/10.mcf/test.py index af2536c7e..36d077c96 100644 --- a/tests/long/10.mcf/test.py +++ b/tests/long/10.mcf/test.py @@ -26,5 +26,6 @@ # # Authors: Korey Sewell -root.system.cpu.workload = LiveProcess(cmd = 'mcf lgred.in', - executable = binpath('mcf')) +process = LiveProcess(executable = binpath('mcf')) +process.cmd = 'mcf' + inputpath('mcf', 'lgred.in') +root.system.cpu.workload = process diff --git a/tests/long/20.parser/test.py b/tests/long/20.parser/test.py index 0b142db25..760908722 100644 --- a/tests/long/20.parser/test.py +++ b/tests/long/20.parser/test.py @@ -26,5 +26,7 @@ # # Authors: Korey Sewell -root.system.cpu.workload = LiveProcess(cmd = 'parser 2.1.dict -batch < lgred.in', - executable = binpath('parser')) +process = LiveProcess(executable = binpath('parser')) +process.cmd = 'parser 2.1.dict -batch' +process.input = inputpath('parser', 'lgred.in') +root.system.cpu.workload = process diff --git a/tests/long/30.eon/test.py b/tests/long/30.eon/test.py index b9f0c2b51..d6bf3bb76 100644 --- a/tests/long/30.eon/test.py +++ b/tests/long/30.eon/test.py @@ -26,4 +26,10 @@ # # Authors: Korey Sewell -root.system.cpu.workload = LiveProcess(cmd = 'eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook',executable = binpath('eon')) +process = LiveProcess(executable = binpath('eon')) +process.cmd = 'eon' + inputpath('eon', 'chair.control.cook') + \ + inputpath('eon', 'chair.camera') + \ + inputpath('eon', 'chair.surfaces') + \ + inputpath('eon', 'chair.cook.ppm') + 'ppm' \ + + 'pixels_out.cook' +root.system.cpu.workload = process diff --git a/tests/long/40.perlbmk/test.py b/tests/long/40.perlbmk/test.py index b5cd17251..81c36bab3 100644 --- a/tests/long/40.perlbmk/test.py +++ b/tests/long/40.perlbmk/test.py @@ -26,5 +26,6 @@ # # Authors: Korey Sewell -root.system.cpu.workload = LiveProcess(cmd = 'perlbmk -I./lib lgred.makerand.pl', - executable = binpath('perlbmk')) +process = LiveProcess(executable = binpath('perlbmk')) +process.cmd = 'perlbmk -I./lib' + inputpath('perlbmk', 'lgred.makerand.pl') +root.system.cpu.workload = process diff --git a/tests/long/50.vortex/test.py b/tests/long/50.vortex/test.py index f531b8ac8..f6d1e03df 100644 --- a/tests/long/50.vortex/test.py +++ b/tests/long/50.vortex/test.py @@ -26,5 +26,6 @@ # # Authors: Korey Sewell -root.system.cpu.workload = LiveProcess(cmd = 'vortex smred.raw', - executable = binpath('vortex')) +process = LiveProcess(executable = binpath('vortex')) +process.cmd = 'vortex' + inputpath('smred.raw') +root.system.cpu.workload = process diff --git a/tests/long/60.bzip2/test.py b/tests/long/60.bzip2/test.py index 3f16efa09..e96d64656 100644 --- a/tests/long/60.bzip2/test.py +++ b/tests/long/60.bzip2/test.py @@ -26,5 +26,6 @@ # # Authors: Korey Sewell -root.system.cpu.workload = LiveProcess(cmd = 'bzip2 lgred.source', - executable = binpath('bzip2')) +process = LiveProcess(executable = binpath('bzip2')) +process.cmd = cmd = 'bzip2' + inputpath('bzip2', 'lgred.source') +root.system.cpu.workload = process diff --git a/tests/long/70.twolf/test.py b/tests/long/70.twolf/test.py index 4ec7a3d03..be7a04f97 100644 --- a/tests/long/70.twolf/test.py +++ b/tests/long/70.twolf/test.py @@ -26,5 +26,6 @@ # # Authors: Korey Sewell -root.system.cpu.workload = LiveProcess(cmd = 'twolf smred/smred', - executable = binpath('twolf')) +process = LiveProcess(executable = binpath('twolf')) +process.cmd = 'twolf' + inputpath('twolf', 'smred/smred') +root.system.cpu.workload = process diff --git a/tests/run.py b/tests/run.py index a405b7f69..df34faca8 100644 --- a/tests/run.py +++ b/tests/run.py @@ -42,6 +42,13 @@ def binpath(app, file=None): file = app return os.path.join(test_progs, app, 'bin', isa, opsys, file) +# generate path to input file +def inputpath(app, file=None): + # input file has same name as app unless specified otherwise + if not file: + file = app + return os.path.join(test_progs, app, 'input', file) + # build configuration execfile(os.path.join(tests_root, 'configs', config + '.py')) |