diff options
39 files changed, 720 insertions, 601 deletions
diff --git a/src/arch/x86/emulenv.cc b/src/arch/x86/emulenv.cc index 28282dc7a..31b705d79 100644 --- a/src/arch/x86/emulenv.cc +++ b/src/arch/x86/emulenv.cc @@ -88,5 +88,18 @@ void EmulEnv::doModRM(const ExtMachInst & machInst) } } } + //Figure out what segment to use. This won't be entirely accurate since + //the presence of a displacement is supposed to make the instruction + //default to the data segment. + if (base != INTREG_RBP && base != INTREG_RSP || + 0/*Has an immediate offset*/) { + seg = SEGMENT_REG_DS; + //Handle any segment override that might have been in the instruction + int segFromInst = machInst.legacy.seg; + if (segFromInst) + seg = (SegmentRegIndex)(segFromInst - 1); + } else { + seg = SEGMENT_REG_SS; + } } diff --git a/src/arch/x86/emulenv.hh b/src/arch/x86/emulenv.hh index 66c56fb79..1044dbdf9 100644 --- a/src/arch/x86/emulenv.hh +++ b/src/arch/x86/emulenv.hh @@ -58,8 +58,9 @@ #ifndef __ARCH_X86_EMULENV_HH__ #define __ARCH_X86_EMULENV_HH__ -#include "arch/x86/types.hh" #include "arch/x86/intregs.hh" +#include "arch/x86/segmentregs.hh" +#include "arch/x86/types.hh" namespace X86ISA { @@ -67,6 +68,7 @@ namespace X86ISA { RegIndex reg; RegIndex regm; + SegmentRegIndex seg; uint8_t scale; RegIndex index; RegIndex base; @@ -76,7 +78,7 @@ namespace X86ISA EmulEnv(RegIndex _reg, RegIndex _regm, int _dataSize, int _addressSize, int _stackSize) : - reg(_reg), regm(_regm), + reg(_reg), regm(_regm), seg(SEGMENT_REG_DS), scale(0), index(NUM_INTREGS), base(NUM_INTREGS), dataSize(_dataSize), addressSize(_addressSize), diff --git a/src/arch/x86/insts/microldstop.hh b/src/arch/x86/insts/microldstop.hh index 8fef14121..fac1fa3aa 100644 --- a/src/arch/x86/insts/microldstop.hh +++ b/src/arch/x86/insts/microldstop.hh @@ -113,19 +113,22 @@ namespace X86ISA switch(size) { case 1: - fault = xc->read(alignedEA, (uint8_t&)Mem, flags); + fault = xc->read(alignedEA, (uint8_t&)(Mem.a), flags); break; case 2: - fault = xc->read(alignedEA, (uint16_t&)Mem, flags); + fault = xc->read(alignedEA, (uint16_t&)(Mem.a), flags); break; case 4: - fault = xc->read(alignedEA, (uint32_t&)Mem, flags); + fault = xc->read(alignedEA, (uint32_t&)(Mem.a), flags); break; case 8: - fault = xc->read(alignedEA, (uint64_t&)Mem, flags); + fault = xc->read(alignedEA, (uint64_t&)(Mem.a), flags); + break; + case 16: + fault = xc->read(alignedEA, Mem, flags); break; default: - panic("Bad operand size %d!\n", size); + panic("Bad operand size %d for read at %#x.\n", size, EA); } return fault; } @@ -141,19 +144,22 @@ namespace X86ISA switch(size) { case 1: - fault = xc->write((uint8_t&)Mem, alignedEA, flags, 0); + fault = xc->write((uint8_t&)(Mem.a), alignedEA, flags, 0); break; case 2: - fault = xc->write((uint16_t&)Mem, alignedEA, flags, 0); + fault = xc->write((uint16_t&)(Mem.a), alignedEA, flags, 0); break; case 4: - fault = xc->write((uint32_t&)Mem, alignedEA, flags, 0); + fault = xc->write((uint32_t&)(Mem.a), alignedEA, flags, 0); break; case 8: - fault = xc->write((uint64_t&)Mem, alignedEA, flags, 0); + fault = xc->write((uint64_t&)(Mem.a), alignedEA, flags, 0); + break; + case 16: + fault = xc->write(Mem, alignedEA, flags, 0); break; default: - panic("Bad operand size %d!\n", size); + panic("Bad operand size %d for write at %#x.\n", size, EA); } return fault; } diff --git a/src/arch/x86/isa/decoder/one_byte_opcodes.isa b/src/arch/x86/isa/decoder/one_byte_opcodes.isa index 7c627b0c2..cce07d6fe 100644 --- a/src/arch/x86/isa/decoder/one_byte_opcodes.isa +++ b/src/arch/x86/isa/decoder/one_byte_opcodes.isa @@ -529,13 +529,13 @@ } } 0x1F: decode OPCODE_OP_BOTTOM3 { - 0x0: clc(); - 0x1: stc(); - 0x2: cli(); - 0x3: sti(); - 0x4: cld(); - 0x5: std(); format Inst { + 0x0: CLC(); + 0x1: STC(); + 0x2: WarnUnimpl::cli(); + 0x3: WarnUnimpl::sti(); + 0x4: CLD(); + 0x5: STD(); //0x6: group4(); 0x6: decode MODRM_REG { 0x0: INC(Eb); diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa b/src/arch/x86/isa/decoder/two_byte_opcodes.isa index e8307c6e6..f2d8a972e 100644 --- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa +++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa @@ -329,8 +329,8 @@ 0x7: Inst::IMUL(Gv,Ev); } 0x16: decode OPCODE_OP_BOTTOM3 { - 0x0: cmpxchg_Eb_Gb(); - 0x1: cmpxchg_Ev_Gv(); + 0x0: Inst::CMPXCHG(Eb,Gb); + 0x1: Inst::CMPXCHG(Ev,Gv); 0x2: lss_Gz_Mp(); 0x3: btr_Ev_Gv(); 0x4: lfs_Gz_Mp(); diff --git a/src/arch/x86/isa/insts/arithmetic/add_and_subtract.py b/src/arch/x86/isa/insts/arithmetic/add_and_subtract.py index de4996f54..87fbb796c 100644 --- a/src/arch/x86/isa/insts/arithmetic/add_and_subtract.py +++ b/src/arch/x86/isa/insts/arithmetic/add_and_subtract.py @@ -68,45 +68,45 @@ def macroop ADD_R_I def macroop ADD_M_I { limm t2, imm - ld t1, ds, [scale, index, base], disp + ld t1, seg, sib, disp add t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF) - st t1, ds, [scale, index, base], disp + st t1, seg, sib, disp }; def macroop ADD_P_I { rdip t7 limm t2, imm - ld t1, ds, [0, t0, t7], disp + ld t1, seg, riprel, disp add t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF) - st t1, ds, [0, t0, t7], disp + st t1, seg, riprel, disp }; def macroop ADD_M_R { - ld t1, ds, [scale, index, base], disp + ld t1, seg, sib, disp add t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF) - st t1, ds, [scale, index, base], disp + st t1, seg, sib, disp }; def macroop ADD_P_R { rdip t7 - ld t1, ds, [0, t0, t7], disp + ld t1, seg, riprel, disp add t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF) - st t1, ds, [0, t0, t7], disp + st t1, seg, riprel, disp }; def macroop ADD_R_M { - ld t1, ds, [scale, index, base], disp + ld t1, seg, sib, disp add reg, reg, t1, flags=(OF,SF,ZF,AF,PF,CF) }; def macroop ADD_R_P { rdip t7 - ld t1, ds, [0, t0, t7], disp + ld t1, seg, riprel, disp add reg, reg, t1, flags=(OF,SF,ZF,AF,PF,CF) }; @@ -123,47 +123,47 @@ def macroop SUB_R_I def macroop SUB_R_M { - ld t1, ds, [scale, index, base], disp + ld t1, seg, sib, disp sub reg, reg, t1, flags=(OF,SF,ZF,AF,PF,CF) }; def macroop SUB_R_P { rdip t7 - ld t1, ds, [0, t0, t7], disp + ld t1, seg, riprel, disp sub reg, reg, t1, flags=(OF,SF,ZF,AF,PF,CF) }; def macroop SUB_M_I { limm t2, imm - ld t1, ds, [scale, index, base], disp + ld t1, seg, sib, disp sub t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF) - st t1, ds, [scale, index, base], disp + st t1, seg, sib, disp }; def macroop SUB_P_I { rdip t7 limm t2, imm - ld t1, ds, [0, t0, t7], disp + ld t1, seg, riprel, disp sub t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF) - st t1, ds, [0, t0, t7], disp + st t1, seg, riprel, disp }; def macroop SUB_M_R { - ld t1, ds, [scale, index, base], disp + ld t1, seg, sib, disp sub t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF) - st t1, ds, [scale, index, base], disp + st t1, seg, sib, disp }; def macroop SUB_P_R { rdip t7 - ld t1, ds, [0, t0, t7], disp + ld t1, seg, riprel, disp sub t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF) - st t1, ds, [0, t0, t7], disp + st t1, seg, riprel, disp }; def macroop ADC_R_R @@ -180,45 +180,45 @@ def macroop ADC_R_I def macroop ADC_M_I { limm t2, imm - ld t1, ds, [scale, index, base], disp + ld t1, seg, sib, disp adc t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF) - st t1, ds, [scale, index, base], disp + st t1, seg, sib, disp }; def macroop ADC_P_I { rdip t7 limm t2, imm - ld t1, ds, [0, t0, t7], disp + ld t1, seg, riprel, disp adc t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF) - st t1, ds, [0, t0, t7], disp + st t1, seg, riprel, disp }; def macroop ADC_M_R { - ld t1, ds, [scale, index, base], disp + ld t1, seg, sib, disp adc t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF) - st t1, ds, [scale, index, base], disp + st t1, seg, sib, disp }; def macroop ADC_P_R { rdip t7 - ld t1, ds, [0, t0, t7], disp + ld t1, seg, riprel, disp adc t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF) - st t1, ds, [0, t0, t7], disp + st t1, seg, riprel, disp }; def macroop ADC_R_M { - ld t1, ds, [scale, index, base], disp + ld t1, seg, sib, disp adc reg, reg, t1, flags=(OF,SF,ZF,AF,PF,CF) }; def macroop ADC_R_P { rdip t7 - ld t1, ds, [0, t0, t7], disp + ld t1, seg, riprel, disp adc reg, reg, t1, flags=(OF,SF,ZF,AF,PF,CF) }; @@ -235,47 +235,47 @@ def macroop SBB_R_I def macroop SBB_R_M { - ld t1, ds, [scale, index, base], disp + ld t1, seg, sib, disp sbb reg, reg, t1, flags=(OF,SF,ZF,AF,PF,CF) }; def macroop SBB_R_P { rdip t7 - ld t1, ds, [0, t0, t7], disp + ld t1, seg, riprel, disp sbb reg, reg, t1, flags=(OF,SF,ZF,AF,PF,CF) }; def macroop SBB_M_I { limm t2, imm - ld t1, ds, [scale, index, base], disp + ld t1, seg, sib, disp sbb t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF) - st t1, ds, [scale, index, base], disp + st t1, seg, sib, disp }; def macroop SBB_P_I { rdip t7 limm t2, imm - ld t1, ds, [0, t0, t7], disp + ld t1, seg, riprel, disp sbb t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF) - st t1, ds, [0, t0, t7], disp + st t1, seg, riprel, disp }; def macroop SBB_M_R { - ld t1, ds, [scale, index, base], disp + ld t1, seg, sib, disp sbb t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF) - st t1, ds, [scale, index, base], disp + st t1, seg, sib, disp }; def macroop SBB_P_R { rdip t7 - ld t1, ds, [0, t0, t7], disp + ld t1, seg, riprel, disp sbb t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF) - st t1, ds, [0, t0, t7], disp + st t1, seg, riprel, disp }; def macroop NEG_R @@ -285,16 +285,16 @@ def macroop NEG_R def macroop NEG_M { - ld t1, ds, [scale, index, base], disp + ld t1, seg, sib, disp sub t1, t0, t1, flags=(CF,OF,SF,ZF,AF,PF) - st t1, ds, [scale, index, base], disp + st t1, seg, sib, disp }; def macroop NEG_P { rdip t7 - ld t1, ds, [0, t0, t7], disp + ld t1, seg, riprel, disp sub t1, t0, t1, flags=(CF,OF,SF,ZF,AF,PF) - st t1, ds, [0, t0, t7], disp + st t1, seg, riprel, disp }; ''' diff --git a/src/arch/x86/isa/insts/arithmetic/increment_and_decrement.py b/src/arch/x86/isa/insts/arithmetic/increment_and_decrement.py index f53fa8f05..2a8024eee 100644 --- a/src/arch/x86/isa/insts/arithmetic/increment_and_decrement.py +++ b/src/arch/x86/isa/insts/arithmetic/increment_and_decrement.py @@ -61,17 +61,17 @@ def macroop INC_R def macroop INC_M { - ld t1, ds, [scale, index, base], disp + ld t1, seg, sib, disp addi t1, t1, 1, flags=(OF, SF, ZF, AF, PF) - st t1, ds, [scale, index, base], disp + st t1, seg, sib, disp }; def macroop INC_P { rdip t7 - ld t1, ds, [0, t0, t7], disp - addi reg, reg, 1, flags=(OF, SF, ZF, AF, PF) - st t1, ds, [0, t0, t7], disp + ld t1, seg, riprel, disp + addi t1, t1, 1, flags=(OF, SF, ZF, AF, PF) + st t1, seg, riprel, disp }; def macroop DEC_R @@ -81,16 +81,16 @@ def macroop DEC_R def macroop DEC_M { - ld t1, ds, [scale, index, base], disp + ld t1, seg, sib, disp subi t1, t1, 1, flags=(OF, SF, ZF, AF, PF) - st t1, ds, [scale, index, base], disp + st t1, seg, sib, disp }; def macroop DEC_P { rdip t7 - ld t1, ds, [0, t0, t7], disp - subi reg, reg, 1, flags=(OF, SF, ZF, AF, PF) - st t1, ds, [0, t0, t7], disp + ld t1, seg, riprel, disp + subi t1, t1, 1, flags=(OF, SF, ZF, AF, PF) + st t1, seg, riprel, disp }; ''' diff --git a/src/arch/x86/isa/insts/arithmetic/multiply_and_divide.py b/src/arch/x86/isa/insts/arithmetic/multiply_and_divide.py index 5355775eb..a865e163b 100644 --- a/src/arch/x86/isa/insts/arithmetic/multiply_and_divide.py +++ b/src/arch/x86/isa/insts/arithmetic/multiply_and_divide.py @@ -66,14 +66,14 @@ def macroop MUL_B_R def macroop MUL_B_M { - ld t1, ds, [scale, index, base], disp + ld t1, seg, sib, disp mul1u rax, rax, t1, dataSize="2" }; def macroop MUL_B_P { rdip t7 - ld t1, ds, [scale, index, base], disp + ld t1, seg, riprel, disp mul1u rax, rax, t1, dataSize="2" }; @@ -89,7 +89,7 @@ def macroop MUL_R def macroop MUL_M { - ld t1, ds, [scale, index, base], disp + ld t1, seg, sib, disp muleh rdx, rax, t1 mulel rax, rax, t1 }; @@ -97,7 +97,7 @@ def macroop MUL_M def macroop MUL_P { rdip t7 - ld t1, ds, [scale, index, base], disp + ld t1, seg, riprel, disp muleh rdx, rax, t1 mulel rax, rax, t1 }; @@ -113,14 +113,14 @@ def macroop IMUL_B_R def macroop IMUL_B_M { - ld t1, ds, [scale, index, base], disp + ld t1, seg, sib, disp mul1s rax, rax, t1, dataSize="2" }; def macroop IMUL_B_P { rdip t7 - ld t1, ds, [scale, index, base], disp + ld t1, seg, riprel, disp mul1s rax, rax, t1, dataSize="2" }; @@ -136,7 +136,7 @@ def macroop IMUL_R def macroop IMUL_M { - ld t1, ds, [scale, index, base], disp + ld t1, seg, sib, disp muleh rdx, rax, t1 mulel rax, rax, t1 }; @@ -144,7 +144,7 @@ def macroop IMUL_M def macroop IMUL_P { rdip t7 - ld t1, ds, [scale, index, base], disp + ld t1, seg, riprel, disp muleh rdx, rax, t1 mulel rax, rax, t1 }; @@ -161,14 +161,14 @@ def macroop IMUL_R_R def macroop IMUL_R_M { - ld t1, ds, [scale, index, base], disp + ld t1, seg, sib, disp mulel reg, reg, t1 }; def macroop IMUL_R_P { rdip t7 - ld t1, ds, [scale, index, base], disp + ld t1, seg, riprel, disp mulel reg, reg, t1 }; @@ -185,7 +185,7 @@ def macroop IMUL_R_R_I def macroop IMUL_R_M_I { limm t1, imm - ld t2, ds, [scale, index, base], disp + ld t2, seg, sib, disp mulel reg, t2, t1 }; @@ -193,7 +193,7 @@ def macroop IMUL_R_P_I { rdip t7 limm t1, imm - ld t2, ds, [0, t0, t7] + ld t2, seg, riprel mulel reg, t2, t1 }; @@ -208,14 +208,14 @@ def macroop DIV_B_R def macroop DIV_B_M { - ld t1, ds, [scale, index, base], disp + ld t1, seg, sib, disp div1 rax, rax, t1 }; def macroop DIV_B_P { rdip t7 - ld t1, ds, [0, t0, t7], disp + ld t1, seg, riprel, disp div1 rax, rax, t1 }; @@ -231,7 +231,7 @@ def macroop DIV_R def macroop DIV_M { - ld t1, ds, [scale, index, base], disp + ld t1, seg, sib, disp divr rdx, rax, t1 divq rax, rax, t1 }; @@ -239,18 +239,12 @@ def macroop DIV_M def macroop DIV_P { rdip t7 - ld t1, ds, [0, t0, t7], disp + ld t1, seg, riprel, disp divr rdx, rax, t1 divq rax, rax, t1 }; ''' #let {{ -# class MUL(Inst): -# "GenFault ${new UnimpInstFault}" -# class IMUL(Inst): -# "GenFault ${new UnimpInstFault}" -# class DIV(Inst): -# "GenFault ${new UnimpInstFault}" # class IDIV(Inst): # "GenFault ${new UnimpInstFault}" #}}; diff --git a/src/arch/x86/isa/insts/compare_and_test/compare.py b/src/arch/x86/isa/insts/compare_and_test/compare.py index 8f5890b23..76c75a442 100644 --- a/src/arch/x86/isa/insts/compare_and_test/compare.py +++ b/src/arch/x86/isa/insts/compare_and_test/compare.py @@ -56,21 +56,21 @@ microcode = ''' def macroop CMP_R_M { - ld t1, ds, [scale, index, base], disp + ld t1, seg, sib, disp sub t0, reg, t1, flags=(OF, SF, ZF, AF, PF, CF) }; def macroop CMP_R_P { rdip t7 - ld t1, ds, [0, t0, t7], disp + ld t1, seg, riprel, disp sub t0, reg, t1, flags=(OF, SF, ZF, AF, PF, CF) }; def macroop CMP_M_I { limm t2, imm - ld t1, ds, [scale, index, base], disp + ld t1, seg, sib, disp sub t0, t1, t2, flags=(OF, SF, ZF, AF, PF, CF) }; @@ -78,20 +78,20 @@ def macroop CMP_P_I { limm t2, imm rdip t7 - ld t1, ds, [0, t0, t7], disp + ld t1, seg, riprel, disp sub t0, t1, t2, flags=(OF, SF, ZF, AF, PF, CF) }; def macroop CMP_M_R { - ld t1, ds, [scale, index, base], disp + ld t1, seg, sib, disp sub t0, t1, reg, flags=(OF, SF, ZF, AF, PF, CF) }; def macroop CMP_P_R { rdip t7 - ld t1, ds, [0, t0, t7], disp + ld t1, seg, riprel, disp sub t0, t1, reg, flags=(OF, SF, ZF, AF, PF, CF) }; diff --git a/src/arch/x86/isa/insts/compare_and_test/set_byte_on_condition.py b/src/arch/x86/isa/insts/compare_and_test/set_byte_on_condition.py index 2008bf666..81091905c 100644 --- a/src/arch/x86/isa/insts/compare_and_test/set_byte_on_condition.py +++ b/src/arch/x86/isa/insts/compare_and_test/set_byte_on_condition.py @@ -64,7 +64,7 @@ def macroop SETZ_M { movi t1, t1, 1, flags=(CZF,) movi t1, t1, 0, flags=(nCZF,) - st t1, ds, [scale, index, base], disp + st t1, seg, sib, disp }; def macroop SETZ_P @@ -72,7 +72,7 @@ def macroop SETZ_P rdip t7 movi t1, t1, 1, flags=(CZF,) movi t1, t1, 0, flags=(nCZF,) - st t1, ds, [0, t0, t7], disp + st t1, seg, riprel, disp }; def macroop SETNZ_R @@ -85,7 +85,7 @@ def macroop SETNZ_M { movi t1, t1, 1, flags=(nCZF,) movi t1, t1, 0, flags=(CZF,) - st t1, ds, [scale, index, base], disp + st t1, seg, sib, disp }; def macroop SETNZ_P @@ -93,7 +93,7 @@ def macroop SETNZ_P rdip t7 movi t1, t1, 1, flags=(nCZF,) movi t1, t1, 0, flags=(CZF,) - st t1, ds, [0, t0, t7], disp + st t1, seg, riprel, disp }; def macroop SETB_R @@ -106,7 +106,7 @@ def macroop SETB_M { movi t1, t1, 1, flags=(CCF,) movi t1, t1, 0, flags=(nCCF,) - st t1, ds, [scale, index, base], disp + st t1, seg, sib, disp }; def macroop SETB_P @@ -114,7 +114,7 @@ def macroop SETB_P rdip t7 movi t1, t1, 1, flags=(CCF,) movi t1, t1, 0, flags=(nCCF,) - st t1, ds, [0, t0, t7], disp + st t1, seg, riprel, disp }; def macroop SETNB_R @@ -127,7 +127,7 @@ def macroop SETNB_M { movi t1, t1, 1, flags=(nCCF,) movi t1, t1, 0, flags=(CCF,) - st t1, ds, [scale, index, base], disp + st t1, seg, sib, disp }; def macroop SETNB_P @@ -135,7 +135,7 @@ def macroop SETNB_P rdip t7 movi t1, t1, 1, flags=(nCCF,) movi t1, t1, 0, flags=(CCF,) - st t1, ds, [0, t0, t7], disp + st t1, seg, riprel, disp }; def macroop SETBE_R @@ -148,7 +148,7 @@ def macroop SETBE_M { movi t1, t1, 1, flags=(CCvZF,) movi t1, t1, 0, flags=(nCCvZF,) - st t1, ds, [scale, index, base], disp + st t1, seg, sib, disp }; def macroop SETBE_P @@ -156,7 +156,7 @@ def macroop SETBE_P rdip t7 movi t1, t1, 1, flags=(CCvZF,) movi t1, t1, 0, flags=(nCCvZF,) - st t1, ds, [0, t0, t7], disp + st t1, seg, riprel, disp }; def macroop SETNBE_R @@ -169,7 +169,7 @@ def macroop SETNBE_M { movi t1, t1, 1, flags=(nCCvZF,) movi t1, t1, 0, flags=(CCvZF,) - st t1, ds, [scale, index, base], disp + st t1, seg, sib, disp }; def macroop SETNBE_P @@ -177,7 +177,7 @@ def macroop SETNBE_P rdip t7 movi t1, t1, 1, flags=(nCCvZF,) movi t1, t1, 0, flags=(CCvZF,) - st t1, ds, [0, t0, t7], disp + st t1, seg, riprel, disp }; def macroop SETS_R @@ -190,7 +190,7 @@ def macroop SETS_M { movi t1, t1, 1, flags=(CSF,) movi t1, t1, 0, flags=(nCSF,) - st t1, ds, [scale, index, base], disp + st t1, seg, sib, disp }; def macroop SETS_P @@ -198,7 +198,7 @@ def macroop SETS_P rdip t7 movi t1, t1, 1, flags=(CSF,) movi t1, t1, 0, flags=(nCSF,) - st t1, ds, [0, t0, t7], disp + st t1, seg, riprel, disp }; def macroop SETNS_R @@ -211,7 +211,7 @@ def macroop SETNS_M { movi t1, t1, 1, flags=(nCSF,) movi t1, t1, 0, flags=(CSF,) - st t1, ds, [scale, index, base], disp + st t1, seg, sib, disp }; def macroop SETNS_P @@ -219,7 +219,7 @@ def macroop SETNS_P rdip t7 movi t1, t1, 1, flags=(nCSF,) movi t1, t1, 0, flags=(CSF,) - st t1, ds, [0, t0, t7], disp + st t1, seg, riprel, disp }; def macroop SETP_R @@ -232,7 +232,7 @@ def macroop SETP_M { movi t1, t1, 1, flags=(CPF,) movi t1, t1, 0, flags=(nCPF,) - st t1, ds, [scale, index, base], disp + st t1, seg, sib, disp }; def macroop SETP_P @@ -240,7 +240,7 @@ def macroop SETP_P rdip t7 movi t1, t1, 1, flags=(CPF,) movi t1, t1, 0, flags=(nCPF,) - st t1, ds, [0, t0, t7], disp + st t1, seg, riprel, disp }; def macroop SETNP_R @@ -253,7 +253,7 @@ def macroop SETNP_M { movi t1, t1, 1, flags=(nCPF,) movi t1, t1, 0, flags=(CPF,) - st t1, ds, [scale, index, base], disp + st t1, seg, sib, disp }; def macroop SETNP_P @@ -261,7 +261,7 @@ def macroop SETNP_P rdip t7 movi t1, t1, 1, flags=(nCPF,) movi t1, t1, 0, flags=(CPF,) - st t1, ds, [0, t0, t7], disp + st t1, seg, riprel, disp }; def macroop SETL_R @@ -274,7 +274,7 @@ def macroop SETL_M { movi t1, t1, 1, flags=(CSxOF,) movi t1, t1, 0, flags=(nCSxOF,) - st t1, ds, [scale, index, base], disp + st t1, seg, sib, disp }; def macroop SETL_P @@ -282,7 +282,7 @@ def macroop SETL_P rdip t7 movi t1, t1, 1, flags=(CSxOF,) movi t1, t1, 0, flags=(nCSxOF,) - st t1, ds, [0, t0, t7], disp + st t1, seg, riprel, disp }; def macroop SETNL_R @@ -295,7 +295,7 @@ def macroop SETNL_M { movi t1, t1, 1, flags=(nCSxOF,) movi t1, t1, 0, flags=(CSxOF,) - st t1, ds, [scale, index, base], disp + st t1, seg, sib, disp }; def macroop SETNL_P @@ -303,7 +303,7 @@ def macroop SETNL_P rdip t7 movi t1, t1, 1, flags=(nCSxOF,) movi t1, t1, 0, flags=(CSxOF,) - st t1, ds, [0, t0, t7], disp + st t1, seg, riprel, disp }; def macroop SETLE_R @@ -316,7 +316,7 @@ def macroop SETLE_M { movi t1, t1, 1, flags=(CSxOvZF,) movi t1, t1, 0, flags=(nCSxOvZF,) - st t1, ds, [scale, index, base], disp + st t1, seg, sib, disp }; def macroop SETLE_P @@ -324,7 +324,7 @@ def macroop SETLE_P rdip t7 movi t1, t1, 1, flags=(CSxOvZF,) movi t1, t1, 0, flags=(nCSxOvZF,) - st t1, ds, [0, t0, t7], disp + st t1, seg, riprel, disp }; def macroop SETNLE_R @@ -337,7 +337,7 @@ def macroop SETNLE_M { movi t1, t1, 1, flags=(nCSxOvZF,) movi t1, t1, 0, flags=(CSxOvZF,) - st t1, ds, [scale, index, base], disp + st t1, seg, sib, disp }; def macroop SETNLE_P @@ -345,7 +345,7 @@ def macroop SETNLE_P rdip t7 movi t1, t1, 1, flags=(nCSxOvZF,) movi t1, t1, 0, flags=(CSxOvZF,) - st t1, ds, [0, t0, t7], disp + st t1, seg, riprel, disp }; def macroop SETO_R @@ -358,7 +358,7 @@ def macroop SETO_M { movi t1, t1, 1, flags=(COF,) movi t1, t1, 0, flags=(nCOF,) - st t1, ds, [scale, index, base], disp + st t1, seg, sib, disp }; def macroop SETO_P @@ -366,7 +366,7 @@ def macroop SETO_P rdip t7 movi t1, t1, 1, flags=(COF,) movi t1, t1, 0, flags=(nCOF,) - st t1, ds, [0, t0, t7], disp + st t1, seg, riprel, disp }; def macroop SETNO_R @@ -379,7 +379,7 @@ def macroop SETNO_M { movi t1, t1, 1, flags=(nCOF,) movi t1, t1, 0, flags=(COF,) - st t1, ds, [scale, index, base], disp + st t1, seg, sib, disp }; def macroop SETNO_P @@ -387,6 +387,6 @@ def macroop SETNO_P rdip t7 movi t1, t1, 1, flags=(nCOF,) movi t1, t1, 0, flags=(COF,) - st t1, ds, [0, t0, t7], disp + st t1, seg, riprel, disp }; ''' diff --git a/src/arch/x86/isa/insts/compare_and_test/test.py b/src/arch/x86/isa/insts/compare_and_test/test.py index 8da33899a..2b4bf7b9a 100644 --- a/src/arch/x86/isa/insts/compare_and_test/test.py +++ b/src/arch/x86/isa/insts/compare_and_test/test.py @@ -56,14 +56,14 @@ microcode = ''' def macroop TEST_M_R { - ld t1, ds, [scale, index, base], disp + ld t1, seg, sib, disp and t0, t1, reg, flags=(SF, ZF, PF) }; def macroop TEST_P_R { rdip t7 - ld t1, ds, [0, t0, t7], disp + ld t1, seg, riprel, disp and t0, t1, reg, flags=(SF, ZF, PF) }; @@ -74,7 +74,7 @@ def macroop TEST_R_R def macroop TEST_M_I { - ld t1, ds, [scale, index, base], disp + ld t1, seg, sib, disp limm t2, imm and t0, t1, t2, flags=(SF, ZF, PF) }; @@ -82,7 +82,7 @@ def macroop TEST_M_I def macroop TEST_P_I { rdip t7 - ld t1, ds, [0, t0, t7], disp + ld t1, seg, riprel, disp limm t2, imm and t0, t1, t2, flags=(SF, ZF, PF) }; diff --git a/src/arch/x86/isa/insts/control_transfer/call.py b/src/arch/x86/isa/insts/control_transfer/call.py index c5bb66e58..504e9ab0a 100644 --- a/src/arch/x86/isa/insts/control_transfer/call.py +++ b/src/arch/x86/isa/insts/control_transfer/call.py @@ -83,7 +83,7 @@ def macroop CALL_NEAR_M .adjust_env oszIn64Override rdip t7 - ld t1, ds, [scale, index, base], disp + ld t1, seg, sib, disp subi rsp, rsp, dsz st t7, ss, [0, t0, rsp] wripi t1, 0 @@ -95,7 +95,7 @@ def macroop CALL_NEAR_P .adjust_env oszIn64Override rdip t7 - ld t1, ds, [0, t0, t7], disp + ld t1, seg, riprel, disp subi rsp, rsp, dsz st t7, ss, [0, t0, rsp] wripi t1, 0 diff --git a/src/arch/x86/isa/insts/control_transfer/conditional_jump.py b/src/arch/x86/isa/insts/control_transfer/conditional_jump.py index 7ca426be6..b04ca97d6 100644 --- a/src/arch/x86/isa/insts/control_transfer/conditional_jump.py +++ b/src/arch/x86/isa/insts/control_transfer/conditional_jump.py @@ -53,8 +53,164 @@ # # Authors: Gabe Black -microcode = "" -#let {{ -# class JCC(Inst): -# "GenFault ${new UnimpInstFault}" -#}}; +microcode = ''' +def macroop JZ_I +{ + # Make the defualt data size of jumps 64 bits in 64 bit mode + .adjust_env oszIn64Override + + rdip t1 + limm t2, imm + wrip t1, t2, flags=(CZF,) +}; + +def macroop JNZ_I +{ + # Make the defualt data size of jumps 64 bits in 64 bit mode + .adjust_env oszIn64Override + + rdip t1 + limm t2, imm + wrip t1, t2, flags=(nCZF,) +}; + +def macroop JB_I +{ + # Make the default data size of jumps 64 bits in 64 bit mode + .adjust_env oszIn64Override + + rdip t1 + limm t2, imm + wrip t1, t2, flags=(CCF,) +}; + +def macroop JNB_I +{ + # Make the default data size of jumps 64 bits in 64 bit mode + .adjust_env oszIn64Override + + rdip t1 + limm t2, imm + wrip t1, t2, flags=(nCCF,) +}; + +def macroop JBE_I +{ + # Make the default data size of jumps 64 bits in 64 bit mode + .adjust_env oszIn64Override + + rdip t1 + limm t2, imm + wrip t1, t2, flags=(CCvZF,) +}; + +def macroop JNBE_I +{ + # Make the default data size of jumps 64 bits in 64 bit mode + .adjust_env oszIn64Override + + rdip t1 + limm t2, imm + wrip t1, t2, flags=(nCCvZF,) +}; + +def macroop JS_I +{ + # Make the default data size of jumps 64 bits in 64 bit mode + .adjust_env oszIn64Override + + rdip t1 + limm t2, imm + wrip t1, t2, flags=(CSF,) +}; + +def macroop JNS_I +{ + # Make the default data size of jumps 64 bits in 64 bit mode + .adjust_env oszIn64Override + + rdip t1 + limm t2, imm + wrip t1, t2, flags=(nCSF,) +}; + +def macroop JP_I +{ + # Make the default data size of jumps 64 bits in 64 bit mode + .adjust_env oszIn64Override + + rdip t1 + limm t2, imm + wrip t1, t2, flags=(CPF,) +}; + +def macroop JNP_I +{ + # Make the default data size of jumps 64 bits in 64 bit mode + .adjust_env oszIn64Override + + rdip t1 + limm t2, imm + wrip t1, t2, flags=(nCPF,) +}; + +def macroop JL_I +{ + # Make the default data size of jumps 64 bits in 64 bit mode + .adjust_env oszIn64Override + + rdip t1 + limm t2, imm + wrip t1, t2, flags=(CSxOF,) +}; + +def macroop JNL_I +{ + # Make the default data size of jumps 64 bits in 64 bit mode + .adjust_env oszIn64Override + + rdip t1 + limm t2, imm + wrip t1, t2, flags=(nCSxOF,) +}; + +def macroop JLE_I +{ + # Make the default data size of jumps 64 bits in 64 bit mode + .adjust_env oszIn64Override + + rdip t1 + limm t2, imm + wrip t1, t2, flags=(CSxOvZF,) +}; + +def macroop JNLE_I +{ + # Make the default data size of jumps 64 bits in 64 bit mode + .adjust_env oszIn64Override + + rdip t1 + limm t2, imm + wrip t1, t2, flags=(nCSxOvZF,) +}; + +def macroop JO_I +{ + # Make the default data size of jumps 64 bits in 64 bit mode + .adjust_env oszIn64Override + + rdip t1 + limm t2, imm + wrip t1, t2, flags=(COF,) +}; + +def macroop JNO_I +{ + # Make the default data size of jumps 64 bits in 64 bit mode + .adjust_env oszIn64Override + + rdip t1 + limm t2, imm + wrip t1, t2, flags=(nCOF,) +}; +''' diff --git a/src/arch/x86/isa/insts/control_transfer/jump.py b/src/arch/x86/isa/insts/control_transfer/jump.py index 0df84cbe8..bb3ae4213 100644 --- a/src/arch/x86/isa/insts/control_transfer/jump.py +++ b/src/arch/x86/isa/insts/control_transfer/jump.py @@ -54,166 +54,6 @@ # Authors: Gabe Black microcode = ''' -def macroop JZ_I -{ - # Make the defualt data size of jumps 64 bits in 64 bit mode - .adjust_env oszIn64Override - - rdip t1 - limm t2, imm - wrip t1, t2, flags=(CZF,) -}; - -def macroop JNZ_I -{ - # Make the defualt data size of jumps 64 bits in 64 bit mode - .adjust_env oszIn64Override - - rdip t1 - limm t2, imm - wrip t1, t2, flags=(nCZF,) -}; - -def macroop JB_I -{ - # Make the default data size of jumps 64 bits in 64 bit mode - .adjust_env oszIn64Override - - rdip t1 - limm t2, imm - wrip t1, t2, flags=(CCF,) -}; - -def macroop JNB_I -{ - # Make the default data size of jumps 64 bits in 64 bit mode - .adjust_env oszIn64Override - - rdip t1 - limm t2, imm - wrip t1, t2, flags=(nCCF,) -}; - -def macroop JBE_I -{ - # Make the default data size of jumps 64 bits in 64 bit mode - .adjust_env oszIn64Override - - rdip t1 - limm t2, imm - wrip t1, t2, flags=(CCvZF,) -}; - -def macroop JNBE_I -{ - # Make the default data size of jumps 64 bits in 64 bit mode - .adjust_env oszIn64Override - - rdip t1 - limm t2, imm - wrip t1, t2, flags=(nCCvZF,) -}; - -def macroop JS_I -{ - # Make the default data size of jumps 64 bits in 64 bit mode - .adjust_env oszIn64Override - - rdip t1 - limm t2, imm - wrip t1, t2, flags=(CSF,) -}; - -def macroop JNS_I -{ - # Make the default data size of jumps 64 bits in 64 bit mode - .adjust_env oszIn64Override - - rdip t1 - limm t2, imm - wrip t1, t2, flags=(nCSF,) -}; - -def macroop JP_I -{ - # Make the default data size of jumps 64 bits in 64 bit mode - .adjust_env oszIn64Override - - rdip t1 - limm t2, imm - wrip t1, t2, flags=(CPF,) -}; - -def macroop JNP_I -{ - # Make the default data size of jumps 64 bits in 64 bit mode - .adjust_env oszIn64Override - - rdip t1 - limm t2, imm - wrip t1, t2, flags=(nCPF,) -}; - -def macroop JL_I -{ - # Make the default data size of jumps 64 bits in 64 bit mode - .adjust_env oszIn64Override - - rdip t1 - limm t2, imm - wrip t1, t2, flags=(CSxOF,) -}; - -def macroop JNL_I -{ - # Make the default data size of jumps 64 bits in 64 bit mode - .adjust_env oszIn64Override - - rdip t1 - limm t2, imm - wrip t1, t2, flags=(nCSxOF,) -}; - -def macroop JLE_I -{ - # Make the default data size of jumps 64 bits in 64 bit mode - .adjust_env oszIn64Override - - rdip t1 - limm t2, imm - wrip t1, t2, flags=(CSxOvZF,) -}; - -def macroop JNLE_I -{ - # Make the default data size of jumps 64 bits in 64 bit mode - .adjust_env oszIn64Override - - rdip t1 - limm t2, imm - wrip t1, t2, flags=(nCSxOvZF,) -}; - -def macroop JO_I -{ - # Make the default data size of jumps 64 bits in 64 bit mode - .adjust_env oszIn64Override - - rdip t1 - limm t2, imm - wrip t1, t2, flags=(COF,) -}; - -def macroop JNO_I -{ - # Make the default data size of jumps 64 bits in 64 bit mode - .adjust_env oszIn64Override - - rdip t1 - limm t2, imm - wrip t1, t2, flags=(nCOF,) -}; - def macroop JMP_I { # Make the default data size of jumps 64 bits in 64 bit mode @@ -237,7 +77,7 @@ def macroop JMP_M # Make the default data size of jumps 64 bits in 64 bit mode .adjust_env oszIn64Override - ld t1, ds, [scale, index, base], disp + ld t1, seg, sib, disp wripi t1, 0 }; @@ -247,7 +87,7 @@ def macroop JMP_P .adjust_env oszIn64Override rdip t7 - ld t1, ds, [0, t0, t7], disp + ld t1, seg, riprel, disp wripi t1, 0 }; ''' diff --git a/src/arch/x86/isa/insts/control_transfer/xreturn.py b/src/arch/x86/isa/insts/control_transfer/xreturn.py index 0000cd3c1..1efddf1d2 100644 --- a/src/arch/x86/isa/insts/control_transfer/xreturn.py +++ b/src/arch/x86/isa/insts/control_transfer/xreturn.py @@ -59,7 +59,7 @@ def macroop RET_NEAR # Make the default data size of rets 64 bits in 64 bit mode .adjust_env oszIn64Override - ld t1, ss, [0, t0, rsp] + ld t1, ss, [1, t0, rsp] addi rsp, rsp, dsz wripi t1, 0 }; @@ -70,7 +70,7 @@ def macroop RET_NEAR_I .adjust_env oszIn64Override limm t2, imm - ld t1, ss, [0, t0, rsp] + ld t1, ss, [1, t0, rsp] addi rsp, rsp, dsz add rsp, rsp, t2 wripi t1, 0 diff --git a/src/arch/x86/isa/insts/data_conversion/sign_extension.py b/src/arch/x86/isa/insts/data_conversion/sign_extension.py index 6a2612c3c..0bdd4036c 100644 --- a/src/arch/x86/isa/insts/data_conversion/sign_extension.py +++ b/src/arch/x86/isa/insts/data_conversion/sign_extension.py @@ -65,17 +65,3 @@ def macroop CQO_R_R { sra regm, regm, "env.dataSize * 8 - 1" }; ''' -#let {{ -# class CBW(Inst): -# "GenFault ${new UnimpInstFault}" -# class CWDE(Inst): -# "GenFault ${new UnimpInstFault}" -# class CDQE(Inst): -# "GenFault ${new UnimpInstFault}" -# class CWD(Inst): -# "GenFault ${new UnimpInstFault}" -# class CDQ(Inst): -# "GenFault ${new UnimpInstFault}" -# class CQO(Inst): -# "GenFault ${new UnimpInstFault}" -#}}; diff --git a/src/arch/x86/isa/insts/data_transfer/conditional_move.py b/src/arch/x86/isa/insts/data_transfer/conditional_move.py index 17f8841f2..1a60c5b61 100644 --- a/src/arch/x86/isa/insts/data_transfer/conditional_move.py +++ b/src/arch/x86/isa/insts/data_transfer/conditional_move.py @@ -61,14 +61,14 @@ def macroop CMOVZ_R_R def macroop CMOVZ_R_M { - ld t1, ds, [scale, index, base], disp + ld t1, seg, sib, disp mov reg, reg, t1, flags=(CZF,) }; def macroop CMOVZ_R_P { rdip t7 - ld t1, ds, [0, t0, t7], disp + ld t1, seg, riprel, disp mov reg, reg, t1, flags=(CZF,) }; @@ -79,14 +79,14 @@ def macroop CMOVNZ_R_R def macroop CMOVNZ_R_M { - ld t1, ds, [scale, index, base], disp + ld t1, seg, sib, disp mov reg, reg, t1, flags=(nCZF,) }; def macroop CMOVNZ_R_P { rdip t7 - ld t1, ds, [0, t0, t7], disp + ld t1, seg, riprel, disp mov reg, reg, t1, flags=(nCZF,) }; @@ -97,14 +97,14 @@ def macroop CMOVB_R_R def macroop CMOVB_R_M { - ld t1, ds, [scale, index, base], disp + ld t1, seg, sib, disp mov reg, reg, t1, flags=(CCF,) }; def macroop CMOVB_R_P { rdip t7 - ld t1, ds, [0, t0, t7], disp + ld t1, seg, riprel, disp mov reg, reg, t1, flags=(CCF,) }; @@ -115,14 +115,14 @@ def macroop CMOVNB_R_R def macroop CMOVNB_R_M { - ld t1, ds, [scale, index, base], disp + ld t1, seg, sib, disp mov reg, reg, t1, flags=(nCCF,) }; def macroop CMOVNB_R_P { rdip t7 - ld t1, ds, [0, t0, t7], disp + ld t1, seg, riprel, disp mov reg, reg, t1, flags=(nCCF,) }; @@ -133,14 +133,14 @@ def macroop CMOVBE_R_R def macroop CMOVBE_R_M { - ld t1, ds, [scale, index, base], disp + ld t1, seg, sib, disp mov reg, reg, t1, flags=(CCvZF,) }; def macroop CMOVBE_R_P { rdip t7 - ld t1, ds, [0, t0, t7], disp + ld t1, seg, riprel, disp mov reg, reg, t1, flags=(CCvZF,) }; @@ -151,14 +151,14 @@ def macroop CMOVNBE_R_R def macroop CMOVNBE_R_M { - ld t1, ds, [scale, index, base], disp + ld t1, seg, sib, disp mov reg, reg, t1, flags=(nCCvZF,) }; def macroop CMOVNBE_R_P { rdip t7 - ld t1, ds, [0, t0, t7], disp + ld t1, seg, riprel, disp mov reg, reg, t1, flags=(nCCvZF,) }; @@ -169,14 +169,14 @@ def macroop CMOVS_R_R def macroop CMOVS_R_M { - ld t1, ds, [scale, index, base], disp + ld t1, seg, sib, disp mov reg, reg, t1, flags=(CSF,) }; def macroop CMOVS_R_P { rdip t7 - ld t1, ds, [0, t0, t7], disp + ld t1, seg, riprel, disp mov reg, reg, t1, flags=(CSF,) }; @@ -187,14 +187,14 @@ def macroop CMOVNS_R_R def macroop CMOVNS_R_M { - ld t1, ds, [scale, index, base], disp + ld t1, seg, sib, disp mov reg, reg, t1, flags=(nCSF,) }; def macroop CMOVNS_R_P { rdip t7 - ld t1, ds, [0, t0, t7], disp + ld t1, seg, riprel, disp mov reg, reg, t1, flags=(nCSF,) }; @@ -205,14 +205,14 @@ def macroop CMOVP_R_R def macroop CMOVP_R_M { - ld t1, ds, [scale, index, base], disp + ld t1, seg, sib, disp mov reg, reg, t1, flags=(CPF,) }; def macroop CMOVP_R_P { rdip t7 - ld t1, ds, [0, t0, t7], disp + ld t1, seg, riprel, disp mov reg, reg, t1, flags=(CPF,) }; @@ -223,14 +223,14 @@ def macroop CMOVNP_R_R def macroop CMOVNP_R_M { - ld t1, ds, [scale, index, base], disp + ld t1, seg, sib, disp mov reg, reg, regm, flags=(nCPF,) }; def macroop CMOVNP_R_P { rdip t7 - ld t1, ds, [0, t0, t7], disp + ld t1, seg, riprel, disp mov reg, reg, regm, flags=(nCPF,) }; @@ -241,14 +241,14 @@ def macroop CMOVL_R_R def macroop CMOVL_R_M { - ld t1, ds, [scale, index, base], disp + ld t1, seg, sib, disp mov reg, reg, t1, flags=(CSxOF,) }; def macroop CMOVL_R_P { rdip t7 - ld t1, ds, [0, t0, t7], disp + ld t1, seg, riprel, disp mov reg, reg, t1, flags=(CSxOF,) }; @@ -259,14 +259,14 @@ def macroop CMOVNL_R_R def macroop CMOVNL_R_M { - ld t1, ds, [scale, index, base], disp + ld t1, seg, sib, disp mov reg, reg, t1, flags=(nCSxOF,) }; def macroop CMOVNL_R_P { rdip t7 - ld t1, ds, [0, t0, t7], disp + ld t1, seg, riprel, disp mov reg, reg, t1, flags=(nCSxOF,) }; @@ -277,14 +277,14 @@ def macroop CMOVLE_R_R def macroop CMOVLE_R_M { - ld t1, ds, [scale, index, base], disp + ld t1, seg, sib, disp mov reg, reg, t1, flags=(CSxOvZF,) }; def macroop CMOVLE_R_P { rdip t7 - ld t1, ds, [0, t0, t7], disp + ld t1, seg, riprel, disp mov reg, reg, t1, flags=(CSxOvZF,) }; @@ -295,14 +295,14 @@ def macroop CMOVNLE_R_R def macroop CMOVNLE_R_M { - ld t1, ds, [scale, index, base], disp + ld t1, seg, sib, disp mov reg, reg, t1, flags=(nCSxOvZF,) }; def macroop CMOVNLE_R_P { rdip t7 - ld t1, ds, [0, t0, t7], disp + ld t1, seg, riprel, disp mov reg, reg, t1, flags=(nCSxOvZF,) }; @@ -313,14 +313,14 @@ def macroop CMOVO_R_R def macroop CMOVO_R_M { - ld t1, ds, [scale, index, base], disp + ld t1, seg, sib, disp mov reg, reg, t1, flags=(COF,) }; def macroop CMOVO_R_P { rdip t7 - ld t1, ds, [0, t0, t7], disp + ld t1, seg, riprel, disp mov reg, reg, t1, flags=(COF,) }; @@ -331,14 +331,14 @@ def macroop CMOVNO_R_R def macroop CMOVNO_R_M { - ld t1, ds, [scale, index, base], disp + ld t1, seg, sib, disp mov reg, reg, t1, flags=(nCOF,) }; def macroop CMOVNO_R_P { rdip t7 - ld t1, ds, [0, t0, t7], disp + ld t1, seg, riprel, disp mov reg, reg, t1, flags=(nCOF,) }; ''' diff --git a/src/arch/x86/isa/insts/data_transfer/move.py b/src/arch/x86/isa/insts/data_transfer/move.py index bbc55e47c..a248f5656 100644 --- a/src/arch/x86/isa/insts/data_transfer/move.py +++ b/src/arch/x86/isa/insts/data_transfer/move.py @@ -64,21 +64,21 @@ def macroop MOV_R_R { }; def macroop MOV_M_R { - st reg, ds, [scale, index, base], disp + st reg, seg, sib, disp }; def macroop MOV_P_R { rdip t7 - st reg, ds, [0, t0, t7], disp + st reg, seg, riprel, disp }; def macroop MOV_R_M { - ld reg, ds, [scale, index, base], disp + ld reg, seg, sib, disp }; def macroop MOV_R_P { rdip t7 - ld reg, ds, [0, t0, t7], disp + ld reg, seg, riprel, disp }; def macroop MOV_R_I { @@ -87,13 +87,13 @@ def macroop MOV_R_I { def macroop MOV_M_I { limm t1, imm - st t1, ds, [scale, index, base], disp + st t1, seg, sib, disp }; def macroop MOV_P_I { rdip t7 limm t1, imm - st t1, ds, [0, t0, t7], disp + st t1, seg, riprel, disp }; # @@ -105,13 +105,13 @@ def macroop MOVSXD_R_R { }; def macroop MOVSXD_R_M { - ld t1, ds, [scale, index, base], disp, dataSize=4 + ld t1, seg, sib, disp, dataSize=4 sext reg, t1, 32 }; def macroop MOVSXD_R_P { rdip t7 - ld t1, ds, [0, t0, t7], disp, dataSize=4 + ld t1, seg, riprel, disp, dataSize=4 sext reg, t1, 32 }; @@ -120,13 +120,13 @@ def macroop MOVSX_B_R_R { }; def macroop MOVSX_B_R_M { - ld reg, ds, [scale, index, base], disp, dataSize=1 + ld reg, seg, sib, disp, dataSize=1 sext reg, reg, 8 }; def macroop MOVSX_B_R_P { rdip t7 - ld reg, ds, [0, t0, t7], disp, dataSize=1 + ld reg, seg, riprel, disp, dataSize=1 sext reg, reg, 8 }; @@ -135,13 +135,13 @@ def macroop MOVSX_W_R_R { }; def macroop MOVSX_W_R_M { - ld reg, ds, [scale, index, base], disp, dataSize=2 + ld reg, seg, sib, disp, dataSize=2 sext reg, reg, 16 }; def macroop MOVSX_W_R_P { rdip t7 - ld reg, ds, [0, t0, t7], disp, dataSize=2 + ld reg, seg, riprel, disp, dataSize=2 sext reg, reg, 16 }; @@ -154,13 +154,13 @@ def macroop MOVZX_B_R_R { }; def macroop MOVZX_B_R_M { - ld t1, ds, [scale, index, base], disp, dataSize=1 + ld t1, seg, sib, disp, dataSize=1 zext reg, t1, 8 }; def macroop MOVZX_B_R_P { rdip t7 - ld t1, ds, [0, t0, t7], disp, dataSize=1 + ld t1, seg, riprel, disp, dataSize=1 zext reg, t1, 8 }; @@ -169,23 +169,17 @@ def macroop MOVZX_W_R_R { }; def macroop MOVZX_W_R_M { - ld t1, ds, [scale, index, base], disp, dataSize=2 + ld t1, seg, sib, disp, dataSize=2 zext reg, t1, 16 }; def macroop MOVZX_W_R_P { rdip t7 - ld t1, ds, [0, t0, t7], disp, dataSize=2 + ld t1, seg, riprel, disp, dataSize=2 zext reg, t1, 16 }; ''' #let {{ -# class MOV(Inst): -# "Mov ^0 ^0 ^1" -# class MOVSX(Inst): -# "GenFault ${new UnimpInstFault}" -# class MOVZX(Inst): -# "GenFault ${new UnimpInstFault}" # class MOVD(Inst): # "GenFault ${new UnimpInstFault}" # class MOVNTI(Inst): diff --git a/src/arch/x86/isa/insts/data_transfer/stack_operations.py b/src/arch/x86/isa/insts/data_transfer/stack_operations.py index 082e24485..9e6807039 100644 --- a/src/arch/x86/isa/insts/data_transfer/stack_operations.py +++ b/src/arch/x86/isa/insts/data_transfer/stack_operations.py @@ -58,7 +58,7 @@ def macroop POP_R { # Make the default data size of pops 64 bits in 64 bit mode .adjust_env oszIn64Override - ld reg, ss, [0, t0, rsp] + ld reg, ss, [1, t0, rsp] addi rsp, rsp, dsz }; @@ -66,9 +66,9 @@ def macroop POP_M { # Make the default data size of pops 64 bits in 64 bit mode .adjust_env oszIn64Override - ld t1, ss, [0, t0, rsp] + ld t1, ss, [1, t0, rsp] addi rsp, rsp, dsz - st t1, ds, [scale, index, base], disp + st t1, seg, sib, disp }; def macroop POP_P { @@ -76,9 +76,9 @@ def macroop POP_P { .adjust_env oszIn64Override rdip t7 - ld t1, ss, [0, t0, rsp] + ld t1, ss, [1, t0, rsp] addi rsp, rsp, dsz - st t1, ds, [0, t0, t7] + st t1, seg, riprel, disp }; def macroop PUSH_R { @@ -87,7 +87,7 @@ def macroop PUSH_R { # This needs to work slightly differently from the other versions of push # because the -original- version of the stack pointer is what gets pushed - st reg, ss, [0, t0, rsp], "-env.dataSize" + st reg, ss, [1, t0, rsp], "-env.dataSize" subi rsp, rsp, dsz }; @@ -97,16 +97,16 @@ def macroop PUSH_I { limm t1, imm subi rsp, rsp, dsz - st t1, ss, [0, t0, rsp] + st t1, ss, [1, t0, rsp] }; def macroop PUSH_M { # Make the default data size of pops 64 bits in 64 bit mode .adjust_env oszIn64Override - ld t1, ds, [scale, index, base], disp + ld t1, seg, sib, disp subi rsp, rsp, dsz - st t1, ss, [0, t0, rsp] + st t1, ss, [1, t0, rsp] }; def macroop PUSH_P { @@ -114,31 +114,31 @@ def macroop PUSH_P { .adjust_env oszIn64Override rdip t7 - ld t1, ds, [0, t0, t7], disp + ld t1, seg, riprel, disp subi rsp, rsp, dsz - st t1, ss, [0, t0, rsp] + st t1, ss, [1, t0, rsp] }; def macroop PUSHA { - st rax, ss, [0, t0, rsp], "-0 * env.dataSize" - st rcx, ss, [0, t0, rsp], "-1 * env.dataSize" - st rdx, ss, [0, t0, rsp], "-2 * env.dataSize" - st rbx, ss, [0, t0, rsp], "-3 * env.dataSize" - st rsp, ss, [0, t0, rsp], "-4 * env.dataSize" - st rbp, ss, [0, t0, rsp], "-5 * env.dataSize" - st rsi, ss, [0, t0, rsp], "-6 * env.dataSize" - st rdi, ss, [0, t0, rsp], "-7 * env.dataSize" + st rax, ss, [1, t0, rsp], "-0 * env.dataSize" + st rcx, ss, [1, t0, rsp], "-1 * env.dataSize" + st rdx, ss, [1, t0, rsp], "-2 * env.dataSize" + st rbx, ss, [1, t0, rsp], "-3 * env.dataSize" + st rsp, ss, [1, t0, rsp], "-4 * env.dataSize" + st rbp, ss, [1, t0, rsp], "-5 * env.dataSize" + st rsi, ss, [1, t0, rsp], "-6 * env.dataSize" + st rdi, ss, [1, t0, rsp], "-7 * env.dataSize" subi rsp, rsp, "8 * env.dataSize" }; def macroop POPA { - ld rdi, ss, [0, t0, rsp], "0 * env.dataSize" - ld rsi, ss, [0, t0, rsp], "1 * env.dataSize" - ld rbp, ss, [0, t0, rsp], "2 * env.dataSize" - ld rbx, ss, [0, t0, rsp], "4 * env.dataSize" - ld rdx, ss, [0, t0, rsp], "5 * env.dataSize" - ld rcx, ss, [0, t0, rsp], "6 * env.dataSize" - ld rax, ss, [0, t0, rsp], "7 * env.dataSize" + ld rdi, ss, [1, t0, rsp], "0 * env.dataSize" + ld rsi, ss, [1, t0, rsp], "1 * env.dataSize" + ld rbp, ss, [1, t0, rsp], "2 * env.dataSize" + ld rbx, ss, [1, t0, rsp], "4 * env.dataSize" + ld rdx, ss, [1, t0, rsp], "5 * env.dataSize" + ld rcx, ss, [1, t0, rsp], "6 * env.dataSize" + ld rax, ss, [1, t0, rsp], "7 * env.dataSize" addi rsp, rsp, "8 * env.dataSize" }; @@ -147,13 +147,11 @@ def macroop LEAVE { .adjust_env oszIn64Override mov rsp, rsp, rbp - ld rbp, ss, [0, t0, rsp] + ld rbp, ss, [1, t0, rsp] addi rsp, rsp, dsz }; ''' #let {{ # class ENTER(Inst): # "GenFault ${new UnimpInstFault}" -# class LEAVE(Inst): -# "GenFault ${new UnimpInstFault}" #}}; diff --git a/src/arch/x86/isa/insts/data_transfer/xchg.py b/src/arch/x86/isa/insts/data_transfer/xchg.py index 4f401deb7..9478c71fc 100644 --- a/src/arch/x86/isa/insts/data_transfer/xchg.py +++ b/src/arch/x86/isa/insts/data_transfer/xchg.py @@ -68,31 +68,31 @@ def macroop XCHG_R_R def macroop XCHG_R_M { - ld t1, ds, [scale, index, base], disp - st reg, ds, [scale, index, base], disp + ld t1, seg, sib, disp + st reg, seg, sib, disp mov reg, reg, t1 }; def macroop XCHG_R_P { rdip t7 - ld t1, ds, [0, t0, t7], disp - st reg, ds, [0, t0, t7], disp + ld t1, seg, riprel, disp + st reg, seg, riprel, disp mov reg, reg, t1 }; def macroop XCHG_M_R { - ld t1, ds, [scale, index, base], disp - st reg, ds, [scale, index, base], disp + ld t1, seg, sib, disp + st reg, seg, sib, disp mov reg, reg, t1 }; def macroop XCHG_P_R { rdip t7 - ld t1, ds, [0, t0, t7], disp - st reg, ds, [0, t0, t7], disp + ld t1, seg, riprel, disp + st reg, seg, riprel, disp mov reg, reg, t1 }; ''' diff --git a/src/arch/x86/isa/insts/flags/set_and_clear.py b/src/arch/x86/isa/insts/flags/set_and_clear.py index d70b95382..4c655e0b2 100644 --- a/src/arch/x86/isa/insts/flags/set_and_clear.py +++ b/src/arch/x86/isa/insts/flags/set_and_clear.py @@ -53,18 +53,39 @@ # # Authors: Gabe Black -microcode = "" +microcode = ''' +def macroop CLD { + ruflags t1 + limm t2, "~((uint64_t)DFBit)" + and t1, t1, t2 + wruflags t1, t0 +}; + +def macroop STD { + ruflags t1 + limm t2, "DFBit" + or t1, t1, t2 + wruflags t1, t0 +}; + +def macroop CLC { + ruflags t1 + andi t2, t1, "CFBit" + wruflags t1, t2 +}; + +def macroop STC { + ruflags t1 + ori t1, t1, "CFBit" + wruflags t1, t0 +}; + +def macroop CMC { + ruflags t1 + wruflagsi t1, "CFBit" +}; +''' #let {{ -# class CLC(Inst): -# "GenFault ${new UnimpInstFault}" -# class CMC(Inst): -# "GenFault ${new UnimpInstFault}" -# class STC(Inst): -# "GenFault ${new UnimpInstFault}" -# class CLD(Inst): -# "GenFault ${new UnimpInstFault}" -# class STD(Inst): -# "GenFault ${new UnimpInstFault}" # class CLI(Inst): # "GenFault ${new UnimpInstFault}" # class STI(Inst): diff --git a/src/arch/x86/isa/insts/load_effective_address.py b/src/arch/x86/isa/insts/load_effective_address.py index fc8b17629..0c4e0f7df 100644 --- a/src/arch/x86/isa/insts/load_effective_address.py +++ b/src/arch/x86/isa/insts/load_effective_address.py @@ -55,11 +55,11 @@ microcode = ''' def macroop LEA_R_M { - lea reg, ds, [scale, index, base], disp + lea reg, seg, sib, disp }; def macroop LEA_R_P { rdip t7 - lea reg, ds, [0, t0, t7], disp + lea reg, seg, riprel, disp }; ''' diff --git a/src/arch/x86/isa/insts/logical.py b/src/arch/x86/isa/insts/logical.py index 81a4730de..2137ae82f 100644 --- a/src/arch/x86/isa/insts/logical.py +++ b/src/arch/x86/isa/insts/logical.py @@ -62,45 +62,45 @@ def macroop OR_R_R def macroop OR_M_I { limm t2, imm - ld t1, ds, [scale, index, base], disp + ld t1, seg, sib, disp or t1, t1, t2, flags=(OF,SF,ZF,PF,CF) - st t1, ds, [scale, index, base], disp + st t1, seg, sib, disp }; def macroop OR_P_I { limm t2, imm rdip t7 - ld t1, ds, [0, t0, t7], disp + ld t1, seg, riprel, disp or t1, t1, t2, flags=(OF,SF,ZF,PF,CF) - st t1, ds, [0, t0, t7], disp + st t1, seg, riprel, disp }; def macroop OR_M_R { - ld t1, ds, [scale, index, base], disp + ld t1, seg, sib, disp or t1, t1, reg, flags=(OF,SF,ZF,PF,CF) - st t1, ds, [scale, index, base], disp + st t1, seg, sib, disp }; def macroop OR_P_R { rdip t7 - ld t1, ds, [0, t0, t7], disp + ld t1, seg, riprel, disp or t1, t1, reg, flags=(OF,SF,ZF,PF,CF) - st t1, ds, [0, t0, t7], disp + st t1, seg, riprel, disp }; def macroop OR_R_M { - ld t1, ds, [scale, index, base], disp + ld t1, seg, sib, disp or reg, reg, t1, flags=(OF,SF,ZF,PF,CF) }; def macroop OR_R_P { rdip t7 - ld t1, ds, [0, t0, t7], disp + ld t1, seg, riprel, disp or reg, reg, t1, flags=(OF,SF,ZF,PF,CF) }; @@ -124,45 +124,45 @@ def macroop XOR_R_I def macroop XOR_M_I { limm t2, imm - ld t1, ds, [scale, index, base], disp + ld t1, seg, sib, disp xor t1, t1, t2, flags=(OF,SF,ZF,PF,CF) - st t1, ds, [scale, index, base], disp + st t1, seg, sib, disp }; def macroop XOR_P_I { limm t2, imm rdip t7 - ld t1, ds, [scale, index, base], disp + ld t1, seg, riprel, disp xor t1, t1, t2, flags=(OF,SF,ZF,PF,CF) - st t1, ds, [scale, index, base], disp + st t1, seg, riprel, disp }; def macroop XOR_M_R { - ld t1, ds, [scale, index, base], disp + ld t1, seg, sib, disp xor t1, t1, reg, flags=(OF,SF,ZF,PF,CF) - st t1, ds, [scale, index, base], disp + st t1, seg, sib, disp }; def macroop XOR_P_R { rdip t7 - ld t1, ds, [scale, index, base], disp + ld t1, seg, riprel, disp xor t1, t1, reg, flags=(OF,SF,ZF,PF,CF) - st t1, ds, [scale, index, base], disp + st t1, seg, riprel, disp }; def macroop XOR_R_M { - ld t1, ds, [scale, index, base], disp + ld t1, seg, sib, disp xor reg, reg, t1, flags=(OF,SF,ZF,PF,CF) }; def macroop XOR_R_P { rdip t7 - ld t1, ds, [scale, index, base], disp + ld t1, seg, riprel, disp xor reg, reg, t1, flags=(OF,SF,ZF,PF,CF) }; @@ -173,14 +173,14 @@ def macroop AND_R_R def macroop AND_R_M { - ld t1, ds, [scale, index, base], disp + ld t1, seg, sib, disp and reg, reg, t1, flags=(OF,SF,ZF,PF,CF) }; def macroop AND_R_P { rdip t7 - ld t1, ds, [scale, index, base], disp + ld t1, seg, riprel, disp and reg, reg, t1, flags=(OF,SF,ZF,PF,CF) }; @@ -192,34 +192,34 @@ def macroop AND_R_I def macroop AND_M_I { - ld t2, ds, [scale, index, base], disp + ld t2, seg, sib, disp limm t1, imm and t2, t2, t1, flags=(OF,SF,ZF,PF,CF) - st t2, ds, [scale, index, base], disp + st t2, seg, sib, disp }; def macroop AND_P_I { rdip t7 - ld t2, ds, [scale, index, base], disp + ld t2, seg, riprel, disp limm t1, imm and t2, t2, t1, flags=(OF,SF,ZF,PF,CF) - st t2, ds, [scale, index, base], disp + st t2, seg, riprel, disp }; def macroop AND_M_R { - ld t1, ds, [scale, index, base], disp + ld t1, seg, sib, disp and t1, t1, reg, flags=(OF,SF,ZF,PF,CF) - st t1, ds, [scale, index, base], disp + st t1, seg, sib, disp }; def macroop AND_P_R { rdip t7 - ld t1, ds, [scale, index, base], disp + ld t1, seg, riprel, disp and t1, t1, reg, flags=(OF,SF,ZF,PF,CF) - st t1, ds, [scale, index, base], disp + st t1, seg, riprel, disp }; def macroop NOT_R @@ -231,17 +231,17 @@ def macroop NOT_R def macroop NOT_M { limm t1, -1 - ld t2, ds, [scale, index, base], disp + ld t2, seg, sib, disp xor t2, t2, t1 - st t2, ds, [scale, index, base], disp + st t2, seg, sib, disp }; def macroop NOT_P { limm t1, -1 rdip t7 - ld t2, ds, [0, t0, t7], disp + ld t2, seg, riprel, disp xor t2, t2, t1 - st t2, ds, [0, t0, t7], disp + st t2, seg, riprel, disp }; ''' diff --git a/src/arch/x86/isa/insts/processor_information.py b/src/arch/x86/isa/insts/processor_information.py index f7ef4db98..48891cd84 100644 --- a/src/arch/x86/isa/insts/processor_information.py +++ b/src/arch/x86/isa/insts/processor_information.py @@ -67,7 +67,3 @@ def macroop CPUID_R { limm rcx, 0x444d4163, dataSize=4 }; ''' -#let {{ -# class CPUID(Inst): -# "GenFault ${new UnimpInstFault}" -#}}; diff --git a/src/arch/x86/isa/insts/rotate_and_shift/rotate.py b/src/arch/x86/isa/insts/rotate_and_shift/rotate.py index 538e641ab..a13df3a64 100644 --- a/src/arch/x86/isa/insts/rotate_and_shift/rotate.py +++ b/src/arch/x86/isa/insts/rotate_and_shift/rotate.py @@ -61,17 +61,17 @@ def macroop ROL_R_I def macroop ROL_M_I { - ld t1, ds, [scale, index, base], disp + ld t1, seg, sib, disp roli t1, t1, imm - st t1, ds, [scale, index, base], disp + st t1, seg, sib, disp }; def macroop ROL_P_I { rdip t7 - ld t1, ds, [0, t0, t7], disp + ld t1, seg, riprel, disp roli t1, t1, imm - st t1, ds, [0, t0, t7], disp + st t1, seg, riprel, disp }; def macroop ROL_1_R @@ -81,17 +81,17 @@ def macroop ROL_1_R def macroop ROL_1_M { - ld t1, ds, [scale, index, base], disp + ld t1, seg, sib, disp roli t1, t1, 1 - st t1, ds, [scale, index, base], disp + st t1, seg, sib, disp }; def macroop ROL_1_P { rdip t7 - ld t1, ds, [0, t0, t7], disp + ld t1, seg, riprel, disp roli t1, t1, 1 - st t1, ds, [0, t0, t7], disp + st t1, seg, riprel, disp }; def macroop ROL_R_R @@ -101,17 +101,17 @@ def macroop ROL_R_R def macroop ROL_M_R { - ld t1, ds, [scale, index, base], disp + ld t1, seg, sib, disp rol t1, t1, reg - st t1, ds, [scale, index, base], disp + st t1, seg, sib, disp }; def macroop ROL_P_R { rdip t7 - ld t1, ds, [0, t0, t7], disp + ld t1, seg, riprel, disp rol t1, t1, reg - st t1, ds, [0, t0, t7], disp + st t1, seg, riprel, disp }; def macroop ROR_R_I @@ -121,17 +121,17 @@ def macroop ROR_R_I def macroop ROR_M_I { - ld t1, ds, [scale, index, base], disp + ld t1, seg, sib, disp rori t1, t1, imm - st t1, ds, [scale, index, base], disp + st t1, seg, sib, disp }; def macroop ROR_P_I { rdip t7 - ld t1, ds, [0, t0, t7], disp + ld t1, seg, riprel, disp rori t1, t1, imm - st t1, ds, [0, t0, t7], disp + st t1, seg, riprel, disp }; def macroop ROR_1_R @@ -141,17 +141,17 @@ def macroop ROR_1_R def macroop ROR_1_M { - ld t1, ds, [scale, index, base], disp + ld t1, seg, sib, disp rori t1, t1, 1 - st t1, ds, [scale, index, base], disp + st t1, seg, sib, disp }; def macroop ROR_1_P { rdip t7 - ld t1, ds, [0, t0, t7], disp + ld t1, seg, riprel, disp rori t1, t1, 1 - st t1, ds, [0, t0, t7], disp + st t1, seg, riprel, disp }; def macroop ROR_R_R @@ -161,17 +161,17 @@ def macroop ROR_R_R def macroop ROR_M_R { - ld t1, ds, [scale, index, base], disp + ld t1, seg, sib, disp ror t1, t1, reg - st t1, ds, [scale, index, base], disp + st t1, seg, sib, disp }; def macroop ROR_P_R { rdip t7 - ld t1, ds, [0, t0, t7], disp + ld t1, seg, riprel, disp ror t1, t1, reg - st t1, ds, [0, t0, t7], disp + st t1, seg, riprel, disp }; def macroop RCL_R_I @@ -181,17 +181,17 @@ def macroop RCL_R_I def macroop RCL_M_I { - ld t1, ds, [scale, index, base], disp + ld t1, seg, sib, disp rcli t1, t1, imm - st t1, ds, [scale, index, base], disp + st t1, seg, sib, disp }; def macroop RCL_P_I { rdip t7 - ld t1, ds, [0, t0, t7], disp + ld t1, seg, riprel, disp rcli t1, t1, imm - st t1, ds, [0, t0, t7], disp + st t1, seg, riprel, disp }; def macroop RCL_1_R @@ -201,17 +201,17 @@ def macroop RCL_1_R def macroop RCL_1_M { - ld t1, ds, [scale, index, base], disp + ld t1, seg, sib, disp rcli t1, t1, 1 - st t1, ds, [scale, index, base], disp + st t1, seg, sib, disp }; def macroop RCL_1_P { rdip t7 - ld t1, ds, [0, t0, t7], disp + ld t1, seg, riprel, disp rcli t1, t1, 1 - st t1, ds, [0, t0, t7], disp + st t1, seg, riprel, disp }; def macroop RCL_R_R @@ -221,17 +221,17 @@ def macroop RCL_R_R def macroop RCL_M_R { - ld t1, ds, [scale, index, base], disp + ld t1, seg, sib, disp rcl t1, t1, reg - st t1, ds, [scale, index, base], disp + st t1, seg, sib, disp }; def macroop RCL_P_R { rdip t7 - ld t1, ds, [0, t0, t7], disp + ld t1, seg, riprel, disp rcl t1, t1, reg - st t1, ds, [0, t0, t7], disp + st t1, seg, riprel, disp }; def macroop RCR_R_I @@ -241,17 +241,17 @@ def macroop RCR_R_I def macroop RCR_M_I { - ld t1, ds, [scale, index, base], disp + ld t1, seg, sib, disp rcri t1, t1, imm - st t1, ds, [scale, index, base], disp + st t1, seg, sib, disp }; def macroop RCR_P_I { rdip t7 - ld t1, ds, [0, t0, t7], disp + ld t1, seg, riprel, disp rcri t1, t1, imm - st t1, ds, [0, t0, t7], disp + st t1, seg, riprel, disp }; def macroop RCR_1_R @@ -261,17 +261,17 @@ def macroop RCR_1_R def macroop RCR_1_M { - ld t1, ds, [scale, index, base], disp + ld t1, seg, sib, disp rcri t1, t1, 1 - st t1, ds, [scale, index, base], disp + st t1, seg, sib, disp }; def macroop RCR_1_P { rdip t7 - ld t1, ds, [0, t0, t7], disp + ld t1, seg, riprel, disp rcri t1, t1, 1 - st t1, ds, [0, t0, t7], disp + st t1, seg, riprel, disp }; def macroop RCR_R_R @@ -281,16 +281,16 @@ def macroop RCR_R_R def macroop RCR_M_R { - ld t1, ds, [scale, index, base], disp + ld t1, seg, sib, disp rcr t1, t1, reg - st t1, ds, [scale, index, base], disp + st t1, seg, sib, disp }; def macroop RCR_P_R { rdip t7 - ld t1, ds, [0, t0, t7], disp + ld t1, seg, riprel, disp rcr t1, t1, reg - st t1, ds, [0, t0, t7], disp + st t1, seg, riprel, disp }; ''' diff --git a/src/arch/x86/isa/insts/rotate_and_shift/shift.py b/src/arch/x86/isa/insts/rotate_and_shift/shift.py index 64eab3edc..45758b489 100644 --- a/src/arch/x86/isa/insts/rotate_and_shift/shift.py +++ b/src/arch/x86/isa/insts/rotate_and_shift/shift.py @@ -61,17 +61,17 @@ def macroop SAL_R_I def macroop SAL_M_I { - ld t1, ds, [scale, index, base], disp + ld t1, seg, sib, disp slli t1, t1, imm - st t1, ds, [scale, index, base], disp + st t1, seg, sib, disp }; def macroop SAL_P_I { rdip t7 - ld t1, ds, [0, t0, t7], disp + ld t1, seg, riprel, disp slli t1, t1, imm - st t1, ds, [0, t0, t7], disp + st t1, seg, riprel, disp }; def macroop SAL_1_R @@ -81,17 +81,17 @@ def macroop SAL_1_R def macroop SAL_1_M { - ld t1, ds, [scale, index, base], disp + ld t1, seg, sib, disp slli t1, t1, 1 - st t1, ds, [scale, index, base], disp + st t1, seg, sib, disp }; def macroop SAL_1_P { rdip t7 - ld t1, ds, [0, t0, t7], disp + ld t1, seg, riprel, disp slli t1, t1, 1 - st t1, ds, [0, t0, t7], disp + st t1, seg, riprel, disp }; def macroop SAL_R_R @@ -101,17 +101,17 @@ def macroop SAL_R_R def macroop SAL_M_R { - ld t1, ds, [scale, index, base], disp + ld t1, seg, sib, disp sll t1, t1, reg - st t1, ds, [scale, index, base], disp + st t1, seg, sib, disp }; def macroop SAL_P_R { rdip t7 - ld t1, ds, [0, t0, t7], disp + ld t1, seg, riprel, disp sll t1, t1, reg - st t1, ds, [0, t0, t7], disp + st t1, seg, riprel, disp }; def macroop SHR_R_I @@ -121,17 +121,17 @@ def macroop SHR_R_I def macroop SHR_M_I { - ld t1, ds, [scale, index, base], disp + ld t1, seg, sib, disp srli t1, t1, imm - st t1, ds, [scale, index, base], disp + st t1, seg, sib, disp }; def macroop SHR_P_I { rdip t7 - ld t1, ds, [0, t0, t7], disp + ld t1, seg, riprel, disp srli t1, t1, imm - st t1, ds, [0, t0, t7], disp + st t1, seg, riprel, disp }; def macroop SHR_1_R @@ -141,17 +141,17 @@ def macroop SHR_1_R def macroop SHR_1_M { - ld t1, ds, [scale, index, base], disp + ld t1, seg, sib, disp srli t1, t1, 1 - st t1, ds, [scale, index, base], disp + st t1, seg, sib, disp }; def macroop SHR_1_P { rdip t7 - ld t1, ds, [0, t0, t7], disp + ld t1, seg, riprel, disp srli t1, t1, 1 - st t1, ds, [0, t0, t7], disp + st t1, seg, riprel, disp }; def macroop SHR_R_R @@ -161,17 +161,17 @@ def macroop SHR_R_R def macroop SHR_M_R { - ld t1, ds, [scale, index, base], disp + ld t1, seg, sib, disp srl t1, t1, reg - st t1, ds, [scale, index, base], disp + st t1, seg, sib, disp }; def macroop SHR_P_R { rdip t7 - ld t1, ds, [0, t0, t7], disp + ld t1, seg, riprel, disp srl t1, t1, reg - st t1, ds, [0, t0, t7], disp + st t1, seg, riprel, disp }; def macroop SAR_R_I @@ -181,17 +181,17 @@ def macroop SAR_R_I def macroop SAR_M_I { - ld t1, ds, [scale, index, base], disp + ld t1, seg, sib, disp srai t1, t1, imm - st t1, ds, [scale, index, base], disp + st t1, seg, sib, disp }; def macroop SAR_P_I { rdip t7 - ld t1, ds, [0, t0, t7], disp + ld t1, seg, riprel, disp srai t1, t1, imm - st t1, ds, [0, t0, t7], disp + st t1, seg, riprel, disp }; def macroop SAR_1_R @@ -201,17 +201,17 @@ def macroop SAR_1_R def macroop SAR_1_M { - ld t1, ds, [scale, index, base], disp + ld t1, seg, sib, disp srai t1, t1, 1 - st t1, ds, [scale, index, base], disp + st t1, seg, sib, disp }; def macroop SAR_1_P { rdip t7 - ld t1, ds, [0, t0, t7], disp + ld t1, seg, riprel, disp srai t1, t1, 1 - st t1, ds, [0, t0, t7], disp + st t1, seg, riprel, disp }; def macroop SAR_R_R @@ -221,16 +221,16 @@ def macroop SAR_R_R def macroop SAR_M_R { - ld t1, ds, [scale, index, base], disp + ld t1, seg, sib, disp sra t1, t1, reg - st t1, ds, [scale, index, base], disp + st t1, seg, sib, disp }; def macroop SAR_P_R { rdip t7 - ld t1, ds, [0, t0, t7], disp + ld t1, seg, riprel, disp sra t1, t1, reg - st t1, ds, [0, t0, t7], disp + st t1, seg, riprel, disp }; ''' diff --git a/src/arch/x86/isa/insts/semaphores.py b/src/arch/x86/isa/insts/semaphores.py index 32f28cf82..800f1b325 100644 --- a/src/arch/x86/isa/insts/semaphores.py +++ b/src/arch/x86/isa/insts/semaphores.py @@ -53,14 +53,33 @@ # # Authors: Gabe Black -microcode = "" +microcode = ''' +def macroop CMPXCHG_R_R { + sub t0, rax, reg, flags=(OF, SF, ZF, AF, PF, CF) + mov reg, reg, regm, flags=(CZF,) + mov rax, rax, reg, flags=(nCZF,) +}; + +def macroop CMPXCHG_M_R { + ld t1, seg, sib, disp + sub t0, rax, t1, flags=(OF, SF, ZF, AF, PF, CF) + + mov t1, t1, reg, flags=(CZF,) + st t1, seg, sib, disp + mov rax, rax, t1, flags=(nCZF,) +}; + +def macroop CMPXCHG_P_R { + rdip t7 + ld t1, seg, riprel, disp + sub t0, rax, t1, flags=(OF, SF, ZF, AF, PF, CF) + + mov t1, t1, reg, flags=(CZF,) + st t1, seg, riprel, disp + mov rax, rax, t1, flags=(nCZF,) +}; +''' #let {{ -# class CMPXCHG(Inst): -# "GenFault ${new UnimpInstFault}" -# class CMPXCHG8B(Inst): -# "GenFault ${new UnimpInstFault}" -# class CMPXCHG16B(Inst): -# "GenFault ${new UnimpInstFault}" # class XADD(Inst): # "GenFault ${new UnimpInstFault}" # class XCHG(Inst): diff --git a/src/arch/x86/isa/macroop.isa b/src/arch/x86/isa/macroop.isa index 4131246a4..4675b9d56 100644 --- a/src/arch/x86/isa/macroop.isa +++ b/src/arch/x86/isa/macroop.isa @@ -196,6 +196,7 @@ let {{ self.regUsed = False self.regm = "0" self.regmUsed = False + self.seg = "SEGMENT_REG_DS" self.size = None self.addressSize = "ADDRSIZE" self.dataSize = "OPSIZE" diff --git a/src/arch/x86/isa/microasm.isa b/src/arch/x86/isa/microasm.isa index 213468b0b..5c567a30c 100644 --- a/src/arch/x86/isa/microasm.isa +++ b/src/arch/x86/isa/microasm.isa @@ -84,6 +84,7 @@ let {{ "regm" : "env.regm", "imm" : "IMMEDIATE", "disp" : "DISPLACEMENT", + "seg" : "env.seg", "scale" : "env.scale", "index" : "env.index", "base" : "env.base", @@ -91,10 +92,16 @@ let {{ "osz" : "env.operandSize", "ssz" : "env.stackSize" } + assembler.symbols.update(symbols) + + # Short hand for common scale-index-base combinations. + assembler.symbols["sib"] = \ + [symbols["scale"], symbols["index"], symbols["base"]] + assembler.symbols["riprel"] = \ + ["1", assembler.symbols["t0"], assembler.symbols["t7"]] for reg in ('ax', 'bx', 'cx', 'dx', 'sp', 'bp', 'si', 'di'): assembler.symbols["r%s" % reg] = "INTREG_R%s" % reg.upper() - assembler.symbols.update(symbols) for flag in ('CF', 'PF', 'ECF', 'AF', 'EZF', 'ZF', 'SF', 'OF'): assembler.symbols[flag] = flag + "Bit" diff --git a/src/arch/x86/isa/microops/ldstop.isa b/src/arch/x86/isa/microops/ldstop.isa index b8cddb09b..403a1aacf 100644 --- a/src/arch/x86/isa/microops/ldstop.isa +++ b/src/arch/x86/isa/microops/ldstop.isa @@ -123,9 +123,19 @@ def template MicroLoadExecute {{ %(ea_code)s; DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA); - fault = read(xc, EA, Mem, 0); + Twin64_t alignedMem; + fault = read(xc, EA, alignedMem, 0); int offset = EA & (dataSize - 1); - Mem = bits(Mem, (offset + dataSize) * 8 - 1, offset * 8); + if(dataSize != 8 || !offset) + { + Mem = bits(alignedMem.a, + (offset + dataSize) * 8 - 1, offset * 8); + } + else + { + Mem = alignedMem.b << (dataSize - offset) * 8; + Mem |= bits(alignedMem.a, dataSize * 8 - 1, offset * 8); + } if(fault == NoFault) { @@ -153,7 +163,8 @@ def template MicroLoadInitiateAcc {{ DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA); int offset = EA & (dataSize - 1); - fault = read(xc, EA, Mem, offset); + Twin64_t alignedMem; + fault = read(xc, EA, alignedMem, offset); return fault; } @@ -169,9 +180,18 @@ def template MicroLoadCompleteAcc {{ %(op_decl)s; %(op_rd)s; - Mem = pkt->get<typeof(Mem)>(); + Twin64_t alignedMem = pkt->get<Twin64_t>(); int offset = pkt->req->getFlags(); - Mem = bits(Mem, (offset + dataSize) * 8 - 1, offset * 8); + if(dataSize != 8 || !offset) + { + Mem = bits(alignedMem.a, + (offset + dataSize) * 8 - 1, offset * 8); + } + else + { + Mem = alignedMem.b << (dataSize - offset) * 8; + Mem |= bits(alignedMem.a, dataSize * 8 - 1, offset * 8); + } %(code)s; if(fault == NoFault) @@ -201,8 +221,14 @@ def template MicroStoreExecute {{ if(fault == NoFault) { - Mem = Mem << ((EA & (dataSize - 1)) * 8); - fault = write(xc, Mem, EA, 0); + int offset = EA & (dataSize - 1); + + Twin64_t alignedMem; + alignedMem.a = Mem << (offset * 8); + alignedMem.b = + bits(Mem, dataSize * 8 - 1, (dataSize - offset) * 8); + + fault = write(xc, alignedMem, EA, 0); if(fault == NoFault) { %(op_wb)s; @@ -229,8 +255,14 @@ def template MicroStoreInitiateAcc {{ if(fault == NoFault) { - Mem = Mem << ((EA & (dataSize - 1)) * 8); - fault = write(xc, Mem, EA, 0); + int offset = EA & (dataSize - 1); + + Twin64_t alignedMem; + alignedMem.a = Mem << (offset * 8); + alignedMem.b = + bits(Mem, dataSize * 8 - 1, (dataSize - offset) * 8); + + fault = write(xc, alignedMem, EA, 0); if(fault == NoFault) { %(op_wb)s; @@ -362,7 +394,7 @@ let {{ decoder_output = "" exec_output = "" - calculateEA = "EA = scale * Index + Base + disp;" + calculateEA = "EA = SegBase + scale * Index + Base + disp;" def defineMicroLoadOp(mnemonic, code): global header_output diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa index 3c562efc0..ac88be657 100644 --- a/src/arch/x86/isa/microops/regop.isa +++ b/src/arch/x86/isa/microops/regop.isa @@ -615,8 +615,12 @@ let {{ ''') defineMicroRegOpWr('Wrip', 'RIP = psrc1 + op2', elseCode="RIP = RIP;") + defineMicroRegOpWr('Wruflags', 'ccFlagBits = psrc1 ^ op2') defineMicroRegOpRd('Rdip', 'DestReg = RIP') + defineMicroRegOpRd('Ruflags', 'DestReg = ccFlagBits') + defineMicroRegOpImm('Ruflag', 'DestReg = bits(ccFlagBits, imm8);', \ + flagCode = genCCFlagBitsLogic) defineMicroRegOpImm('Sext', ''' IntReg val = psrc1; diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa index eaedbdf17..64179ca98 100644 --- a/src/arch/x86/isa/operands.isa +++ b/src/arch/x86/isa/operands.isa @@ -105,5 +105,6 @@ def operands {{ 'rax': ('IntReg', 'uqw', '(INTREG_RAX)', 'IsInteger', 7), 'RIP': ('NPC', 'uqw', None, (None, None, 'IsControl'), 10), 'ccFlagBits': ('IntReg', 'uqw', 'NUM_INTREGS + NumMicroIntRegs', None, 20), + 'SegBase': ('ControlReg', 'uqw', 'MISCREG_SEG_BASE_BASE + segment', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 50), 'Mem': ('Mem', 'uqw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100) }}; diff --git a/src/arch/x86/isa/specialize.isa b/src/arch/x86/isa/specialize.isa index b5f51ab58..59e9577d9 100644 --- a/src/arch/x86/isa/specialize.isa +++ b/src/arch/x86/isa/specialize.isa @@ -138,9 +138,9 @@ let {{ #Figure out what to do with fixed register operands #This is the index to use, so we should stick it some place. if opType.reg in ("A", "B", "C", "D"): - env.addReg("INTREG_R%sX | (REX_B << 3)" % opType.reg) + env.addReg("INTREG_R%sX" % opType.reg) else: - env.addReg("INTREG_R%s | (REX_B << 3)" % opType.reg) + env.addReg("INTREG_R%s" % opType.reg) Name += "_R" elif opType.tag == "B": # This refers to registers whose index is encoded as part of the opcode @@ -176,6 +176,10 @@ let {{ # Non register modrm settings should cause an error env.addReg(ModRMRMIndex) Name += "_R" + elif opType.tag in ("X", "Y"): + # This type of memory addressing is for string instructions. + # They'll use the right index and segment internally. + Name += "_M" else: raise Exception, "Unrecognized tag %s." % opType.tag diff --git a/src/arch/x86/linux/linux.hh b/src/arch/x86/linux/linux.hh index bde7925a9..8a78d5320 100644 --- a/src/arch/x86/linux/linux.hh +++ b/src/arch/x86/linux/linux.hh @@ -87,16 +87,16 @@ class X86Linux64 : public Linux static OpenFlagTransTable openFlagTable[]; - static const int TGT_O_RDONLY = 0x00000000; //!< O_RDONLY - static const int TGT_O_WRONLY = 0x00000001; //!< O_WRONLY - static const int TGT_O_RDWR = 0x00000002; //!< O_RDWR - static const int TGT_O_NONBLOCK = 0x00004000; //!< O_NONBLOCK - static const int TGT_O_APPEND = 0x00000008; //!< O_APPEND - static const int TGT_O_CREAT = 0x00000200; //!< O_CREAT - static const int TGT_O_TRUNC = 0x00000400; //!< O_TRUNC - static const int TGT_O_EXCL = 0x00000800; //!< O_EXCL - static const int TGT_O_NOCTTY = 0x00008000; //!< O_NOCTTY - static const int TGT_O_SYNC = 0x00002000; //!< O_SYNC + static const int TGT_O_RDONLY = 00000000; //!< O_RDONLY + static const int TGT_O_WRONLY = 00000001; //!< O_WRONLY + static const int TGT_O_RDWR = 00000002; //!< O_RDWR + static const int TGT_O_NONBLOCK = 00004000; //!< O_NONBLOCK + static const int TGT_O_APPEND = 00002000; //!< O_APPEND + static const int TGT_O_CREAT = 00000100; //!< O_CREAT + static const int TGT_O_TRUNC = 00001000; //!< O_TRUNC + static const int TGT_O_EXCL = 00000200; //!< O_EXCL + static const int TGT_O_NOCTTY = 00000400; //!< O_NOCTTY + static const int TGT_O_SYNC = 00010000; //!< O_SYNC // static const int TGT_O_DRD = 0x00010000; //!< O_DRD // static const int TGT_O_DIRECTIO = 0x00020000; //!< O_DIRECTIO // static const int TGT_O_CACHE = 0x00002000; //!< O_CACHE diff --git a/src/arch/x86/linux/syscalls.cc b/src/arch/x86/linux/syscalls.cc index efbe33dfa..1146af708 100644 --- a/src/arch/x86/linux/syscalls.cc +++ b/src/arch/x86/linux/syscalls.cc @@ -57,6 +57,7 @@ #include "arch/x86/linux/process.hh" #include "arch/x86/linux/linux.hh" +#include "arch/x86/miscregs.hh" #include "kern/linux/linux.hh" #include "sim/syscall_emul.hh" @@ -80,6 +81,45 @@ unameFunc(SyscallDesc *desc, int callnum, LiveProcess *process, return 0; } +static SyscallReturn +archPrctlFunc(SyscallDesc *desc, int callnum, LiveProcess *process, + ThreadContext *tc) +{ + enum ArchPrctlCodes + { + SetFS = 0x1002, + GetFS = 0x1003, + SetGS = 0x1001, + GetGS = 0x1004 + }; + + //First argument is the code, second is the address + int code = tc->getSyscallArg(0); + uint64_t addr = tc->getSyscallArg(1); + uint64_t fsBase, gsBase; + TranslatingPort *p = tc->getMemPort(); + switch(code) + { + //Each of these valid options should actually check addr. + case SetFS: + tc->setMiscRegNoEffect(MISCREG_FS_BASE, addr); + return 0; + case GetFS: + fsBase = tc->readMiscRegNoEffect(MISCREG_FS_BASE); + p->write(addr, fsBase); + return 0; + case SetGS: + tc->setMiscRegNoEffect(MISCREG_GS_BASE, addr); + return 0; + case GetGS: + gsBase = tc->readMiscRegNoEffect(MISCREG_GS_BASE); + p->write(addr, gsBase); + return 0; + default: + return -EINVAL; + } +} + SyscallDesc X86LinuxProcess::syscallDescs[] = { /* 0 */ SyscallDesc("read", readFunc), /* 1 */ SyscallDesc("write", writeFunc), @@ -239,7 +279,7 @@ SyscallDesc X86LinuxProcess::syscallDescs[] = { /* 155 */ SyscallDesc("pivot_root", unimplementedFunc), /* 156 */ SyscallDesc("_sysctl", unimplementedFunc), /* 157 */ SyscallDesc("prctl", unimplementedFunc), - /* 158 */ SyscallDesc("arch_prctl", unimplementedFunc), + /* 158 */ SyscallDesc("arch_prctl", archPrctlFunc), /* 159 */ SyscallDesc("adjtimex", unimplementedFunc), /* 160 */ SyscallDesc("setrlimit", unimplementedFunc), /* 161 */ SyscallDesc("chroot", unimplementedFunc), diff --git a/src/arch/x86/miscregfile.cc b/src/arch/x86/miscregfile.cc index 9d8e94061..e2c39c7cd 100644 --- a/src/arch/x86/miscregfile.cc +++ b/src/arch/x86/miscregfile.cc @@ -127,7 +127,6 @@ MiscReg MiscRegFile::readRegNoEffect(int miscReg) MiscReg MiscRegFile::readReg(int miscReg, ThreadContext * tc) { - warn("No miscreg effects implemented yet!\n"); return readRegNoEffect(miscReg); } @@ -155,7 +154,6 @@ void MiscRegFile::setRegNoEffect(int miscReg, const MiscReg &val) void MiscRegFile::setReg(int miscReg, const MiscReg &val, ThreadContext * tc) { - warn("No miscreg effects implemented yet!\n"); setRegNoEffect(miscReg, val); } diff --git a/src/arch/x86/miscregs.hh b/src/arch/x86/miscregs.hh index 39425fc9d..8792bf6dd 100644 --- a/src/arch/x86/miscregs.hh +++ b/src/arch/x86/miscregs.hh @@ -70,6 +70,7 @@ namespace X86ISA EZFBit = 1 << 5, ZFBit = 1 << 6, SFBit = 1 << 7, + DFBit = 1 << 10, OFBit = 1 << 11 }; @@ -77,7 +78,8 @@ namespace X86ISA { // Control registers // Most of these are invalid. - MISCREG_CR0, + MISCREG_CR_BASE, + MISCREG_CR0 = MISCREG_CR_BASE, MISCREG_CR1, MISCREG_CR2, MISCREG_CR3, @@ -95,7 +97,8 @@ namespace X86ISA MISCREG_CR15, // Debug registers - MISCREG_DR0, + MISCREG_DR_BASE, + MISCREG_DR0 = MISCREG_DR_BASE, MISCREG_DR1, MISCREG_DR2, MISCREG_DR3, @@ -108,7 +111,8 @@ namespace X86ISA MISCREG_RFLAGS, // Segment selectors - MISCREG_ES, + MISCREG_SEG_SEL_BASE, + MISCREG_ES = MISCREG_SEG_SEL_BASE, MISCREG_CS, MISCREG_SS, MISCREG_DS, @@ -116,7 +120,8 @@ namespace X86ISA MISCREG_GS, // Hidden segment base field - MISCREG_ES_BASE, + MISCREG_SEG_BASE_BASE, + MISCREG_ES_BASE = MISCREG_SEG_BASE_BASE, MISCREG_CS_BASE, MISCREG_SS_BASE, MISCREG_DS_BASE, @@ -124,7 +129,8 @@ namespace X86ISA MISCREG_GS_BASE, // Hidden segment limit field - MISCREG_ES_LIMIT, + MISCREG_SEG_LIMIT_BASE, + MISCREG_ES_LIMIT = MISCREG_SEG_LIMIT_BASE, MISCREG_CS_LIMIT, MISCREG_SS_LIMIT, MISCREG_DS_LIMIT, @@ -132,7 +138,8 @@ namespace X86ISA MISCREG_GS_LIMIT, // Hidden segment limit attributes - MISCREG_ES_ATTR, + MISCREG_SEG_ATTR_BASE, + MISCREG_ES_ATTR = MISCREG_SEG_ATTR_BASE, MISCREG_CS_ATTR, MISCREG_SS_ATTR, MISCREG_DS_ATTR, @@ -140,23 +147,27 @@ namespace X86ISA MISCREG_GS_ATTR, // System segment selectors - MISCREG_LDTR, + MISCREG_SYSSEG_SEL_BASE, + MISCREG_LDTR = MISCREG_SYSSEG_SEL_BASE, MISCREG_TR, // Hidden system segment base field - MISCREG_LDTR_BASE, + MISCREG_SYSSEG_BASE_BASE, + MISCREG_LDTR_BASE = MISCREG_SYSSEG_BASE_BASE, MISCREG_TR_BASE, MISCREG_GDTR_BASE, MISCREG_IDTR_BASE, // Hidden system segment limit field - MISCREG_LDTR_LIMIT, + MISCREG_SYSSEG_LIMIT_BASE, + MISCREG_LDTR_LIMIT = MISCREG_SYSSEG_LIMIT_BASE, MISCREG_TR_LIMIT, MISCREG_GDTR_LIMIT, MISCREG_IDTR_LIMIT, // Hidden system segment attribute field - MISCREG_LDTR_ATTR, + MISCREG_SYSSEG_ATTR_BASE, + MISCREG_LDTR_ATTR = MISCREG_SYSSEG_ATTR_BASE, MISCREG_TR_ATTR, //XXX Add "Model-Specific Registers" diff --git a/src/arch/x86/process.cc b/src/arch/x86/process.cc index 3cb027d41..364050994 100644 --- a/src/arch/x86/process.cc +++ b/src/arch/x86/process.cc @@ -88,6 +88,7 @@ #include "arch/x86/isa_traits.hh" #include "arch/x86/process.hh" +#include "arch/x86/segmentregs.hh" #include "arch/x86/types.hh" #include "base/loader/object_file.hh" #include "base/loader/elf_object.hh" @@ -145,13 +146,8 @@ void X86LiveProcess::startup() { argsInit(sizeof(IntReg), VMPageSize); - - //The AMD64 abi says that only rsp and rdx are defined at process - //startup. rsp will be set by argsInit, and I don't understand what - //rdx should be set to. The other floating point and integer registers - //will be zeroed by the register file constructors, but control registers - //should be initialized here. Since none of those are implemented, there - //isn't anything here. + for(int i = 0; i < NUM_SEGMENTREGS; i++) + threadContexts[0]->setMiscRegNoEffect(MISCREG_ES_BASE + i, 0); } void diff --git a/src/arch/x86/types.hh b/src/arch/x86/types.hh index f8a5dbe34..c2c60e7cc 100644 --- a/src/arch/x86/types.hh +++ b/src/arch/x86/types.hh @@ -71,12 +71,12 @@ namespace X86ISA enum Prefixes { NoOverride, + ESOverride, CSOverride, + SSOverride, DSOverride, - ESOverride, FSOverride, GSOverride, - SSOverride, RexPrefix, OperandSizeOverride, AddressSizeOverride, |