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-rw-r--r--src/cpu/base_dyn_inst.hh42
-rw-r--r--src/cpu/base_dyn_inst_impl.hh1
-rw-r--r--src/cpu/o3/alpha/cpu_impl.hh2
-rw-r--r--src/cpu/o3/fetch_impl.hh9
-rw-r--r--src/cpu/o3/lsq_unit.hh9
-rw-r--r--src/cpu/o3/lsq_unit_impl.hh40
6 files changed, 64 insertions, 39 deletions
diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index c68810954..4a4555566 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -206,6 +206,9 @@ class BaseDynInst : public FastAlloc, public RefCounted
*/
Result instResult;
+ /** Records changes to result? */
+ bool recordResult;
+
/** PC of this instruction. */
Addr PC;
@@ -263,6 +266,9 @@ class BaseDynInst : public FastAlloc, public RefCounted
/** Dumps out contents of this BaseDynInst into given string. */
void dump(std::string &outstring);
+ /** Read this CPU's ID. */
+ int readCpuId() { return cpu->readCpuId(); }
+
/** Returns the fault type. */
Fault getFault() { return fault; }
@@ -402,37 +408,42 @@ class BaseDynInst : public FastAlloc, public RefCounted
/** Records an integer register being set to a value. */
void setIntReg(const StaticInst *si, int idx, uint64_t val)
{
- instResult.integer = val;
+ if (recordResult)
+ instResult.integer = val;
}
/** Records an fp register being set to a value. */
void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
{
- if (width == 32)
- instResult.dbl = (double)val;
- else if (width == 64)
- instResult.dbl = val;
- else
- panic("Unsupported width!");
+ if (recordResult) {
+ if (width == 32)
+ instResult.dbl = (double)val;
+ else if (width == 64)
+ instResult.dbl = val;
+ else
+ panic("Unsupported width!");
+ }
}
/** Records an fp register being set to a value. */
void setFloatReg(const StaticInst *si, int idx, FloatReg val)
{
-// instResult.fp = val;
- instResult.dbl = (double)val;
+ if (recordResult)
+ instResult.dbl = (double)val;
}
/** Records an fp register being set to an integer value. */
void setFloatRegBits(const StaticInst *si, int idx, uint64_t val, int width)
{
- instResult.integer = val;
+ if (recordResult)
+ instResult.integer = val;
}
/** Records an fp register being set to an integer value. */
void setFloatRegBits(const StaticInst *si, int idx, uint64_t val)
{
- instResult.integer = val;
+ if (recordResult)
+ instResult.integer = val;
}
/** Records that one of the source registers is ready. */
@@ -624,6 +635,15 @@ class BaseDynInst : public FastAlloc, public RefCounted
/** Sets iterator for this instruction in the list of all insts. */
void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }
+
+ public:
+ /** Returns the number of consecutive store conditional failures. */
+ unsigned readStCondFailures()
+ { return thread->storeCondFailures; }
+
+ /** Sets the number of consecutive store conditional failures. */
+ void setStCondFailures(unsigned sc_failures)
+ { thread->storeCondFailures = sc_failures; }
};
template<class Impl>
diff --git a/src/cpu/base_dyn_inst_impl.hh b/src/cpu/base_dyn_inst_impl.hh
index d6cdff5c5..2f6859de2 100644
--- a/src/cpu/base_dyn_inst_impl.hh
+++ b/src/cpu/base_dyn_inst_impl.hh
@@ -97,6 +97,7 @@ BaseDynInst<Impl>::initVars()
readyRegs = 0;
instResult.integer = 0;
+ recordResult = true;
status.reset();
diff --git a/src/cpu/o3/alpha/cpu_impl.hh b/src/cpu/o3/alpha/cpu_impl.hh
index b7362fad9..8c3d7ee32 100644
--- a/src/cpu/o3/alpha/cpu_impl.hh
+++ b/src/cpu/o3/alpha/cpu_impl.hh
@@ -260,7 +260,7 @@ Fault
AlphaO3CPU<Impl>::hwrei(unsigned tid)
{
// Need to clear the lock flag upon returning from an interrupt.
- this->lockFlag = false;
+ this->setMiscReg(TheISA::Lock_Flag_DepTag, false, tid);
this->thread[tid]->kernelStats->hwrei();
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index e7bf83b20..2f7a75129 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -63,7 +63,7 @@ template<class Impl>
void
DefaultFetch<Impl>::IcachePort::recvFunctional(PacketPtr pkt)
{
- warn("Default fetch doesn't update it's state from a functional call.");
+ warn("DefaultFetch doesn't update its state from a functional call.");
}
template<class Impl>
@@ -1276,11 +1276,12 @@ DefaultFetch<Impl>::fetch(bool &status_change)
fetchStatus[tid] = TrapPending;
status_change = true;
-
-// warn("%lli fault (%d) detected @ PC %08p", curTick, fault, PC[tid]);
#else // !FULL_SYSTEM
- warn("cycle %lli: fault (%s) detected @ PC %08p", curTick, fault->name(), PC[tid]);
+ fetchStatus[tid] = TrapPending;
+ status_change = true;
+
#endif // FULL_SYSTEM
+ DPRINTF(Fetch, "[tid:%i]: fault (%d) detected @ PC %08p", tid, fault, PC[tid]);
}
}
diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh
index 1b207fdbc..a2e11173e 100644
--- a/src/cpu/o3/lsq_unit.hh
+++ b/src/cpu/o3/lsq_unit.hh
@@ -37,6 +37,7 @@
#include <queue>
#include "arch/faults.hh"
+#include "arch/locked_mem.hh"
#include "config/full_system.hh"
#include "base/hashmap.hh"
#include "cpu/inst_seq.hh"
@@ -510,8 +511,12 @@ LSQUnit<Impl>::read(Request *req, T &data, int load_idx)
#if FULL_SYSTEM
if (req->isLocked()) {
- cpu->lockAddr = req->getPaddr();
- cpu->lockFlag = true;
+ // Disable recording the result temporarily. Writing to misc
+ // regs normally updates the result, but this is not the
+ // desired behavior when handling store conditionals.
+ load_inst->recordResult = false;
+ TheISA::handleLockedRead(load_inst.get(), req);
+ load_inst->recordResult = true;
}
#endif
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index d940d7cb3..8a63ff011 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -29,6 +29,7 @@
* Korey Sewell
*/
+#include "arch/locked_mem.hh"
#include "config/use_checker.hh"
#include "cpu/o3/lsq.hh"
@@ -614,27 +615,24 @@ LSQUnit<Impl>::writebackStores()
// @todo: Remove this SC hack once the memory system handles it.
if (req->isLocked()) {
- if (req->isUncacheable()) {
- req->setScResult(2);
- } else {
- if (cpu->lockFlag) {
- req->setScResult(1);
- DPRINTF(LSQUnit, "Store conditional [sn:%lli] succeeded.",
- inst->seqNum);
- } else {
- req->setScResult(0);
- // Hack: Instantly complete this store.
-// completeDataAccess(data_pkt);
- DPRINTF(LSQUnit, "Store conditional [sn:%lli] failed. "
- "Instantly completing it.\n",
- inst->seqNum);
- WritebackEvent *wb = new WritebackEvent(inst, data_pkt, this);
- wb->schedule(curTick + 1);
- delete state;
- completeStore(storeWBIdx);
- incrStIdx(storeWBIdx);
- continue;
- }
+ // Disable recording the result temporarily. Writing to
+ // misc regs normally updates the result, but this is not
+ // the desired behavior when handling store conditionals.
+ inst->recordResult = false;
+ bool success = TheISA::handleLockedWrite(inst.get(), req);
+ inst->recordResult = true;
+
+ if (!success) {
+ // Instantly complete this store.
+ DPRINTF(LSQUnit, "Store conditional [sn:%lli] failed. "
+ "Instantly completing it.\n",
+ inst->seqNum);
+ WritebackEvent *wb = new WritebackEvent(inst, data_pkt, this);
+ wb->schedule(curTick + 1);
+ delete state;
+ completeStore(storeWBIdx);
+ incrStIdx(storeWBIdx);
+ continue;
}
} else {
// Non-store conditionals do not need a writeback.
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-06 14:13:51 +0000