diff options
182 files changed, 6021 insertions, 912 deletions
diff --git a/SConstruct b/SConstruct index a6659fe9b..fa2366963 100644 --- a/SConstruct +++ b/SConstruct @@ -182,7 +182,6 @@ for t in abs_targets: env = Environment(ENV = os.environ, # inherit user's environment vars ROOT = ROOT, SRCDIR = SRCDIR) -Export('env') #Parse CC/CXX early so that we use the correct compiler for # to test for dependencies/versions/libraries/includes @@ -192,6 +191,8 @@ if ARGUMENTS.get('CC', None): if ARGUMENTS.get('CXX', None): env['CXX'] = ARGUMENTS.get('CXX') +Export('env') + env.SConsignFile(joinpath(build_root,"sconsign")) # Default duplicate option is to use hard links, but this messes up @@ -269,16 +270,29 @@ if compare_versions(swig_version[2], min_swig_version) < 0: Exit(1) # Set up SWIG flags & scanner -env.Append(SWIGFLAGS=Split('-c++ -python -modern $_CPPINCFLAGS')) +swig_flags=Split('-c++ -python -modern -templatereduce $_CPPINCFLAGS') +env.Append(SWIGFLAGS=swig_flags) + +# filter out all existing swig scanners, they mess up the dependency +# stuff for some reason +scanners = [] +for scanner in env['SCANNERS']: + skeys = scanner.skeys + if skeys == '.i': + continue + + if isinstance(skeys, (list, tuple)) and '.i' in skeys: + continue -import SCons.Scanner + scanners.append(scanner) +# add the new swig scanner that we like better +from SCons.Scanner import ClassicCPP as CPPScanner swig_inc_re = '^[ \t]*[%,#][ \t]*(?:include|import)[ \t]*(<|")([^>"]+)(>|")' +scanners.append(CPPScanner("SwigScan", [ ".i" ], "CPPPATH", swig_inc_re)) -swig_scanner = SCons.Scanner.ClassicCPP("SwigScan", ".i", "CPPPATH", - swig_inc_re) - -env.Append(SCANNERS = swig_scanner) +# replace the scanners list that has what we want +env['SCANNERS'] = scanners # Platform-specific configuration. Note again that we assume that all # builds under a given build root run on the same host platform. diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py index 8a87c3a6b..6bcdafb14 100644 --- a/configs/common/FSConfig.py +++ b/configs/common/FSConfig.py @@ -38,14 +38,14 @@ class CowIdeDisk(IdeDisk): def childImage(self, ci): self.image.child.image_file = ci -class BaseTsunami(Tsunami): - ethernet = NSGigE(configdata=NSGigEPciData(), - pci_bus=0, pci_dev=1, pci_func=0) - etherint = NSGigEInt(device=Parent.ethernet) - ide = IdeController(disks=[Parent.disk0, Parent.disk2], - pci_func=0, pci_dev=0, pci_bus=0) - def makeLinuxAlphaSystem(mem_mode, mdesc = None): + class BaseTsunami(Tsunami): + ethernet = NSGigE(configdata=NSGigEPciData(), + pci_bus=0, pci_dev=1, pci_func=0) + etherint = NSGigEInt(device=Parent.ethernet) + ide = IdeController(disks=[Parent.disk0, Parent.disk2], + pci_func=0, pci_dev=0, pci_bus=0) + self = LinuxAlphaSystem() if not mdesc: # generic system diff --git a/configs/common/cpu2000.py b/configs/common/cpu2000.py index 18f6aedea..2f5844dc6 100644 --- a/configs/common/cpu2000.py +++ b/configs/common/cpu2000.py @@ -131,7 +131,7 @@ class Benchmark(object): def makeLiveProcessArgs(self, **kwargs): # set up default args for LiveProcess object process_args = {} - process_args['cmd'] = self.name + ' ' + ' '.join(self.args) + process_args['cmd'] = [ self.name ] + self.args process_args['executable'] = self.executable if self.stdin: process_args['input'] = self.stdin diff --git a/ext/libelf/SConscript b/ext/libelf/SConscript index 2fae8c25f..31e570396 100644 --- a/ext/libelf/SConscript +++ b/ext/libelf/SConscript @@ -28,7 +28,7 @@ # # Authors: Nathan Binkert -import os +import os, subprocess Import('env') @@ -88,6 +88,22 @@ ElfFile('libelf_fsize.c') ElfFile('libelf_msize.c') m4env = Environment(ENV=os.environ) +if env.get('CC'): + m4env['CC'] = env['CC'] +if env.get('CXX'): + m4env['CXX'] = env['CXX'] + +# If we have gm4 use it +if m4env.Detect('gm4'): + m4env['M4'] = 'gm4' + +# Check that m4 is available +import SCons.Tool.m4 +if not SCons.Tool.m4.exists(m4env): + print "Error: Can't find version of M4 macro processor. " + \ + "Please install M4 and try again." + Exit(1) + m4env.Append(M4FLAGS='-DSRCDIR=%s' % Dir('.').path) m4env['M4COM'] = '$M4 $M4FLAGS $SOURCES > $TARGET' m4env.M4(target=File('libelf_convert.c'), @@ -101,3 +117,4 @@ m4env.Library('elf', elf_files) env.Append(CPPPATH=Dir('.')) env.Append(LIBS=['elf']) env.Append(LIBPATH=[Dir('.')]) + diff --git a/ext/libelf/elf_begin.c b/ext/libelf/elf_begin.c index 1ffd26651..1b37aa061 100644 --- a/ext/libelf/elf_begin.c +++ b/ext/libelf/elf_begin.c @@ -26,7 +26,7 @@ #include <sys/types.h> -#include <sys/errno.h> +#include <errno.h> #include <sys/mman.h> #include <sys/stat.h> diff --git a/ext/libelf/elf_common.h b/ext/libelf/elf_common.h index 0a48d5cb2..c169e7e40 100644 --- a/ext/libelf/elf_common.h +++ b/ext/libelf/elf_common.h @@ -45,9 +45,9 @@ */ typedef struct { - u_int32_t n_namesz; /* Length of name. */ - u_int32_t n_descsz; /* Length of descriptor. */ - u_int32_t n_type; /* Type of this note. */ + uint32_t n_namesz; /* Length of name. */ + uint32_t n_descsz; /* Length of descriptor. */ + uint32_t n_type; /* Type of this note. */ } Elf_Note; /* Indexes into the e_ident array. Keep synced with diff --git a/ext/libelf/elf_strptr.c b/ext/libelf/elf_strptr.c index b89b0eac7..6a05fa1d4 100644 --- a/ext/libelf/elf_strptr.c +++ b/ext/libelf/elf_strptr.c @@ -26,6 +26,9 @@ #include <sys/param.h> +#ifdef __sun +#include <sys/sysmacros.h> +#endif #include <assert.h> #include "gelf.h" diff --git a/ext/libelf/elf_update.c b/ext/libelf/elf_update.c index 513789563..6959d3c3e 100644 --- a/ext/libelf/elf_update.c +++ b/ext/libelf/elf_update.c @@ -27,6 +27,9 @@ #include <sys/mman.h> #include <sys/param.h> +#ifdef __sun +#include <sys/sysmacros.h> +#endif #include <assert.h> #include <errno.h> diff --git a/ext/libelf/libelf_allocate.c b/ext/libelf/libelf_allocate.c index c4c1b6ac5..9e1280c47 100644 --- a/ext/libelf/libelf_allocate.c +++ b/ext/libelf/libelf_allocate.c @@ -28,7 +28,7 @@ * Internal APIs */ -#include <sys/errno.h> +#include <errno.h> #include <assert.h> #include "libelf.h" diff --git a/src/arch/alpha/predecoder.hh b/src/arch/alpha/predecoder.hh index 650f2bfa2..0407ce99b 100644 --- a/src/arch/alpha/predecoder.hh +++ b/src/arch/alpha/predecoder.hh @@ -69,9 +69,9 @@ namespace AlphaISA //Use this to give data to the predecoder. This should be used //when there is control flow. - void moreBytes(Addr pc, Addr off, MachInst inst) + void moreBytes(Addr pc, Addr _fetchPC, Addr off, MachInst inst) { - fetchPC = pc; + fetchPC = _fetchPC; assert(off == 0); ext_inst = inst; #if FULL_SYSTEM @@ -80,13 +80,6 @@ namespace AlphaISA #endif } - //Use this to give data to the predecoder. This should be used - //when instructions are executed in order. - void moreBytes(MachInst machInst) - { - moreBytes(fetchPC + sizeof(machInst), 0, machInst); - } - bool needMoreBytes() { return true; diff --git a/src/arch/alpha/remote_gdb.cc b/src/arch/alpha/remote_gdb.cc index a68e5218e..ea5db36f4 100644 --- a/src/arch/alpha/remote_gdb.cc +++ b/src/arch/alpha/remote_gdb.cc @@ -284,7 +284,7 @@ RemoteGDB::setSingleStep() // User was stopped at pc, e.g. the instruction at pc was not // executed. MachInst inst = read<MachInst>(pc); - StaticInstPtr si(inst); + StaticInstPtr si(inst, pc); if (si->hasBranchTarget(pc, context, bpc)) { // Don't bother setting a breakpoint on the taken branch if it // is the same as the next pc diff --git a/src/arch/alpha/tlb.cc b/src/arch/alpha/tlb.cc index 2dfff8c5f..714bca22a 100644 --- a/src/arch/alpha/tlb.cc +++ b/src/arch/alpha/tlb.cc @@ -292,6 +292,10 @@ ITB::regStats() Fault ITB::translate(RequestPtr &req, ThreadContext *tc) const { + //If this is a pal pc, then set PHYSICAL + if(FULL_SYSTEM && PcPAL(req->getPC())) + req->setFlags(req->getFlags() | PHYSICAL); + if (PcPAL(req->getPC())) { // strip off PAL PC marker (lsb is 1) req->setPaddr((req->getVaddr() & ~3) & PAddrImplMask); diff --git a/src/arch/isa_parser.py b/src/arch/isa_parser.py index 6c8201f77..7edb9f3d7 100755 --- a/src/arch/isa_parser.py +++ b/src/arch/isa_parser.py @@ -194,7 +194,7 @@ def t_error(t): t.skip(1) # Build the lexer -lex.lex() +lexer = lex.lex() ##################################################################### # @@ -729,7 +729,7 @@ def p_error(t): # END OF GRAMMAR RULES # # Now build the parser. -yacc.yacc() +parser = yacc.yacc() ##################################################################### @@ -1881,7 +1881,8 @@ def parse_isa_desc(isa_desc_file, output_dir): fileNameStack.push((isa_desc_file, 0)) # Parse it. - (isa_name, namespace, global_code, namespace_code) = yacc.parse(isa_desc) + (isa_name, namespace, global_code, namespace_code) = \ + parser.parse(isa_desc, lexer=lexer) # grab the last three path components of isa_desc_file to put in # the output diff --git a/src/arch/micro_asm.py b/src/arch/micro_asm.py new file mode 100644 index 000000000..a8a63e1f8 --- /dev/null +++ b/src/arch/micro_asm.py @@ -0,0 +1,491 @@ +# Copyright (c) 2003-2005 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +import os +import sys +import re +import string +import traceback +# get type names +from types import * + +# Prepend the directory where the PLY lex & yacc modules are found +# to the search path. +sys.path[0:0] = [os.environ['M5_PLY']] + +from ply import lex +from ply import yacc + +########################################################################## +# +# Base classes for use outside of the assembler +# +########################################################################## + +class Micro_Container(object): + def __init__(self, name): + self.microops = [] + self.name = name + self.directives = {} + self.micro_classes = {} + self.labels = {} + + def add_microop(self, microop): + self.microops.append(microop) + + def __str__(self): + string = "%s:\n" % self.name + for microop in self.microops: + string += " %s\n" % microop + return string + +class Combinational_Macroop(Micro_Container): + pass + +class Rom_Macroop(object): + def __init__(self, name, target): + self.name = name + self.target = target + + def __str__(self): + return "%s: %s\n" % (self.name, self.target) + +class Rom(Micro_Container): + def __init__(self, name): + super(Rom, self).__init__(name) + self.externs = {} + +########################################################################## +# +# Support classes +# +########################################################################## + +class Label(object): + def __init__(self): + self.extern = False + self.name = "" + +class Block(object): + def __init__(self): + self.statements = [] + +class Statement(object): + def __init__(self): + self.is_microop = False + self.is_directive = False + self.params = "" + +class Microop(Statement): + def __init__(self): + super(Microop, self).__init__() + self.mnemonic = "" + self.labels = [] + self.is_microop = True + +class Directive(Statement): + def __init__(self): + super(Directive, self).__init__() + self.name = "" + self.is_directive = True + +########################################################################## +# +# Functions that handle common tasks +# +########################################################################## + +def print_error(message): + print + print "*** %s" % message + print + +def handle_statement(parser, container, statement): + if statement.is_microop: + try: + microop = eval('parser.microops[statement.mnemonic](%s)' % + statement.params) + except: + print_error("Error creating microop object.") + raise + try: + for label in statement.labels: + container.labels[label.name] = microop + if label.extern: + container.externs[label.name] = microop + container.add_microop(microop) + except: + print_error("Error adding microop.") + raise + elif statement.is_directive: + try: + eval('container.directives[statement.name](%s)' % statement.params) + except: + print_error("Error executing directive.") + print container.directives + raise + else: + raise Exception, "Didn't recognize the type of statement", statement + +########################################################################## +# +# Lexer specification +# +########################################################################## + +# Error handler. Just call exit. Output formatted to work under +# Emacs compile-mode. Optional 'print_traceback' arg, if set to True, +# prints a Python stack backtrace too (can be handy when trying to +# debug the parser itself). +def error(lineno, string, print_traceback = False): + # Print a Python stack backtrace if requested. + if (print_traceback): + traceback.print_exc() + if lineno != 0: + line_str = "%d:" % lineno + else: + line_str = "" + sys.exit("%s %s" % (line_str, string)) + +reserved = ('DEF', 'MACROOP', 'ROM', 'EXTERN') + +tokens = reserved + ( + # identifier + 'ID', + # arguments for microops and directives + 'PARAMS', + + 'LPAREN', 'RPAREN', + 'LBRACE', 'RBRACE', + 'COLON', 'SEMI', 'DOT', + 'NEWLINE' + ) + +# New lines are ignored at the top level, but they end statements in the +# assembler +states = ( + ('asm', 'exclusive'), + ('params', 'exclusive'), +) + +reserved_map = { } +for r in reserved: + reserved_map[r.lower()] = r + +# Ignore comments +def t_ANY_COMMENT(t): + r'\#[^\n]*(?=\n)' + +def t_ANY_MULTILINECOMMENT(t): + r'/\*([^/]|((?<!\*)/))*\*/' + +# A colon marks the end of a label. It should follow an ID which will +# put the lexer in the "params" state. Seeing the colon will put it back +# in the "asm" state since it knows it saw a label and not a mnemonic. +def t_params_COLON(t): + r':' + t.lexer.begin('asm') + return t + +# An "ID" in the micro assembler is either a label, directive, or mnemonic +# If it's either a directive or a mnemonic, it will be optionally followed by +# parameters. If it's a label, the following colon will make the lexer stop +# looking for parameters. +def t_asm_ID(t): + r'[A-Za-z_]\w*' + t.type = reserved_map.get(t.value, 'ID') + t.lexer.begin('params') + return t + +# If there is a label and you're -not- in the assember (which would be caught +# above), don't start looking for parameters. +def t_ANY_ID(t): + r'[A-Za-z_]\w*' + t.type = reserved_map.get(t.value, 'ID') + return t + +# Parameters are a string of text which don't contain an unescaped statement +# statement terminator, ie a newline or semi colon. +def t_params_PARAMS(t): + r'([^\n;\\]|(\\[\n;\\]))+' + t.lineno += t.value.count('\n') + unescapeParamsRE = re.compile(r'(\\[\n;\\])') + def unescapeParams(mo): + val = mo.group(0) + print "About to sub %s for %s" % (val[1], val) + return val[1] + print "Looking for matches in %s" % t.value + t.value = unescapeParamsRE.sub(unescapeParams, t.value) + t.lexer.begin('asm') + return t + +# Braces enter and exit micro assembly +def t_INITIAL_LBRACE(t): + r'\{' + t.lexer.begin('asm') + return t + +def t_asm_RBRACE(t): + r'\}' + t.lexer.begin('INITIAL') + return t + +# At the top level, keep track of newlines only for line counting. +def t_INITIAL_NEWLINE(t): + r'\n+' + t.lineno += t.value.count('\n') + +# In the micro assembler, do line counting but also return a token. The +# token is needed by the parser to detect the end of a statement. +def t_asm_NEWLINE(t): + r'\n+' + t.lineno += t.value.count('\n') + return t + +# A newline or semi colon when looking for params signals that the statement +# is over and the lexer should go back to looking for regular assembly. +def t_params_NEWLINE(t): + r'\n+' + t.lineno += t.value.count('\n') + t.lexer.begin('asm') + return t + +def t_params_SEMI(t): + r';' + t.lexer.begin('asm') + return t + +# Basic regular expressions to pick out simple tokens +t_ANY_LPAREN = r'\(' +t_ANY_RPAREN = r'\)' +t_ANY_SEMI = r';' +t_ANY_DOT = r'\.' + +t_ANY_ignore = ' \t\x0c' + +def t_ANY_error(t): + error(t.lineno, "illegal character '%s'" % t.value[0]) + t.skip(1) + +########################################################################## +# +# Parser specification +# +########################################################################## + +# Start symbol for a file which may have more than one macroop or rom +# specification. +def p_file(t): + 'file : opt_rom_or_macros' + +def p_opt_rom_or_macros_0(t): + 'opt_rom_or_macros : ' + +def p_opt_rom_or_macros_1(t): + 'opt_rom_or_macros : rom_or_macros' + +def p_rom_or_macros_0(t): + 'rom_or_macros : rom_or_macro' + +def p_rom_or_macros_1(t): + 'rom_or_macros : rom_or_macros rom_or_macro' + +def p_rom_or_macro_0(t): + '''rom_or_macro : rom_block + | macroop_def''' + +# Defines a section of microcode that should go in the current ROM +def p_rom_block(t): + 'rom_block : DEF ROM block SEMI' + if not t.parser.rom: + print_error("Rom block found, but no Rom object specified.") + raise TypeError, "Rom block found, but no Rom object was specified." + for statement in t[3].statements: + handle_statement(t.parser, t.parser.rom, statement) + t[0] = t.parser.rom + +# Defines a macroop that jumps to an external label in the ROM +def p_macroop_def_0(t): + 'macroop_def : DEF MACROOP ID LPAREN ID RPAREN SEMI' + if not t.parser.rom_macroop_type: + print_error("ROM based macroop found, but no ROM macroop class was specified.") + raise TypeError, "ROM based macroop found, but no ROM macroop class was specified." + macroop = t.parser.rom_macroop_type(t[3], t[5]) + t.parser.macroops[t[3]] = macroop + + +# Defines a macroop that is combinationally generated +def p_macroop_def_1(t): + 'macroop_def : DEF MACROOP ID block SEMI' + try: + curop = t.parser.macro_type(t[3]) + except TypeError: + print_error("Error creating macroop object.") + raise + for statement in t[4].statements: + handle_statement(t.parser, curop, statement) + t.parser.macroops[t[3]] = curop + +# A block of statements +def p_block(t): + 'block : LBRACE statements RBRACE' + block = Block() + block.statements = t[2] + t[0] = block + +def p_statements_0(t): + 'statements : statement' + if t[1]: + t[0] = [t[1]] + else: + t[0] = [] + +def p_statements_1(t): + 'statements : statements statement' + if t[2]: + t[1].append(t[2]) + t[0] = t[1] + +def p_statement(t): + 'statement : content_of_statement end_of_statement' + t[0] = t[1] + +# A statement can be a microop or an assembler directive +def p_content_of_statement_0(t): + '''content_of_statement : microop + | directive''' + t[0] = t[1] + +# Ignore empty statements +def p_content_of_statement_1(t): + 'content_of_statement : ' + pass + +# Statements are ended by newlines or a semi colon +def p_end_of_statement(t): + '''end_of_statement : NEWLINE + | SEMI''' + pass + +# Different flavors of microop to avoid shift/reduce errors +def p_microop_0(t): + 'microop : labels ID' + microop = Microop() + microop.labels = t[1] + microop.mnemonic = t[2] + t[0] = microop + +def p_microop_1(t): + 'microop : ID' + microop = Microop() + microop.mnemonic = t[1] + t[0] = microop + +def p_microop_2(t): + 'microop : labels ID PARAMS' + microop = Microop() + microop.labels = t[1] + microop.mnemonic = t[2] + microop.params = t[3] + t[0] = microop + +def p_microop_3(t): + 'microop : ID PARAMS' + microop = Microop() + microop.mnemonic = t[1] + microop.params = t[2] + t[0] = microop + +# Labels in the microcode +def p_labels_0(t): + 'labels : label' + t[0] = [t[1]] + +def p_labels_1(t): + 'labels : labels label' + t[1].append(t[2]) + t[0] = t[1] + +def p_label_0(t): + 'label : ID COLON' + label = Label() + label.is_extern = False + label.text = t[1] + t[0] = label + +def p_label_1(t): + 'label : EXTERN ID COLON' + label = Label() + label.is_extern = True + label.text = t[2] + t[0] = label + +# Directives for the macroop +def p_directive_0(t): + 'directive : DOT ID' + directive = Directive() + directive.name = t[2] + t[0] = directive + +def p_directive_1(t): + 'directive : DOT ID PARAMS' + directive = Directive() + directive.name = t[2] + directive.params = t[3] + t[0] = directive + +# Parse error handler. Note that the argument here is the offending +# *token*, not a grammar symbol (hence the need to use t.value) +def p_error(t): + if t: + error(t.lineno, "syntax error at '%s'" % t.value) + else: + error(0, "unknown syntax error", True) + +class MicroAssembler(object): + + def __init__(self, macro_type, microops, + rom = None, rom_macroop_type = None): + self.lexer = lex.lex() + self.parser = yacc.yacc() + self.parser.macro_type = macro_type + self.parser.macroops = {} + self.parser.microops = microops + self.parser.rom = rom + self.parser.rom_macroop_type = rom_macroop_type + + def assemble(self, asm): + self.parser.parse(asm, lexer=self.lexer) + # Begin debug printing + for macroop in self.parser.macroops.values(): + print macroop + print self.parser.rom + # End debug printing + macroops = self.parser.macroops + self.parser.macroops = {} + return macroops diff --git a/src/arch/micro_asm_test.py b/src/arch/micro_asm_test.py new file mode 100755 index 000000000..b074ecb58 --- /dev/null +++ b/src/arch/micro_asm_test.py @@ -0,0 +1,107 @@ +# Copyright (c) 2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +from micro_asm import MicroAssembler, Combinational_Macroop, Rom_Macroop, Rom + +class Bah(object): + def __init__(self): + self.mnemonic = "bah" + +class Bah_Tweaked(object): + def __init__(self): + self.mnemonic = "bah_tweaked" + +class Hoop(object): + def __init__(self, first_param, second_param): + self.mnemonic = "hoop_%s_%s" % (first_param, second_param) + def __str__(self): + return "%s" % self.mnemonic + +class Dah(object): + def __init__(self): + self.mnemonic = "dah" + +microops = { + "bah": Bah, + "hoop": Hoop, + "dah": Dah +} + +class TestMacroop(Combinational_Macroop): + def tweak(self): + microops["bah"] = Bah_Tweaked + def untweak(self): + microops["bah"] = Bah + def print_debug(self, message): + print message + + def __init__(self, name): + super(TestMacroop, self).__init__(name) + self.directives = { + "tweak": self.tweak, + "untweak": self.untweak, + "print": self.print_debug + } + +assembler = MicroAssembler(TestMacroop, microops, Rom('main ROM'), Rom_Macroop) + +testAssembly = ''' +# Single line comment + +def rom { + goo: bah + extern la: hoop 4*8, "a" +}; /* multiline comment on one line */ + +/* multi line comment across lines + to make sure they work */ + +def macroop squishy { + .tweak + bah + .untweak + .print "In the midst" + bah + dah # single line comment after something + .tweak +}; + +#Extending the rom... +def rom +{ + #Here's more stuff for the rom + bah +}; + +def macroop squashy { + bah +}; + +def macroop jumper (bar); +''' +assembler.assemble(testAssembly) diff --git a/src/arch/mips/predecoder.hh b/src/arch/mips/predecoder.hh index a25cce8a7..90f768d73 100644 --- a/src/arch/mips/predecoder.hh +++ b/src/arch/mips/predecoder.hh @@ -66,19 +66,12 @@ namespace MipsISA //Use this to give data to the predecoder. This should be used //when there is control flow. - void moreBytes(Addr currPC, Addr off, MachInst inst) + void moreBytes(Addr pc, Addr fetchPC, Addr off, MachInst inst) { assert(off == 0); emi = inst; } - //Use this to give data to the predecoder. This should be used - //when instructions are executed in order. - void moreBytes(MachInst machInst) - { - moreBytes(0, 0, machInst); - } - bool needMoreBytes() { return true; diff --git a/src/arch/sparc/isa/formats/mem/blockmem.isa b/src/arch/sparc/isa/formats/mem/blockmem.isa index e19016bd0..caf5bb8ce 100644 --- a/src/arch/sparc/isa/formats/mem/blockmem.isa +++ b/src/arch/sparc/isa/formats/mem/blockmem.isa @@ -248,14 +248,14 @@ def template BlockMemConstructor {{ : %(base_class)s("%(mnemonic)s", machInst) { %(constructor)s; - microOps[0] = new %(class_name)s_0(machInst); - microOps[1] = new %(class_name)s_1(machInst); - microOps[2] = new %(class_name)s_2(machInst); - microOps[3] = new %(class_name)s_3(machInst); - microOps[4] = new %(class_name)s_4(machInst); - microOps[5] = new %(class_name)s_5(machInst); - microOps[6] = new %(class_name)s_6(machInst); - microOps[7] = new %(class_name)s_7(machInst); + microops[0] = new %(class_name)s_0(machInst); + microops[1] = new %(class_name)s_1(machInst); + microops[2] = new %(class_name)s_2(machInst); + microops[3] = new %(class_name)s_3(machInst); + microops[4] = new %(class_name)s_4(machInst); + microops[5] = new %(class_name)s_5(machInst); + microops[6] = new %(class_name)s_6(machInst); + microops[7] = new %(class_name)s_7(machInst); } }}; @@ -289,9 +289,9 @@ let {{ for microPc in range(8): flag_code = '' if (microPc == 7): - flag_code = "flags[IsLastMicroOp] = true;" + flag_code = "flags[IsLastMicroop] = true;" elif (microPc == 0): - flag_code = "flags[IsDelayedCommit] = true; flags[IsFirstMicroOp] = true;" + flag_code = "flags[IsDelayedCommit] = true; flags[IsFirstMicroop] = true;" else: flag_code = "flags[IsDelayedCommit] = true;" pcedCode = matcher.sub("Frd_%d" % microPc, code) diff --git a/src/arch/sparc/isa/formats/micro.isa b/src/arch/sparc/isa/formats/micro.isa index da0f97d1b..c1d0c4f36 100644 --- a/src/arch/sparc/isa/formats/micro.isa +++ b/src/arch/sparc/isa/formats/micro.isa @@ -58,33 +58,33 @@ output header {{ class SparcMacroInst : public SparcStaticInst { protected: - const uint32_t numMicroOps; + const uint32_t numMicroops; //Constructor. SparcMacroInst(const char *mnem, ExtMachInst _machInst, - OpClass __opClass, uint32_t _numMicroOps) + OpClass __opClass, uint32_t _numMicroops) : SparcStaticInst(mnem, _machInst, __opClass), - numMicroOps(_numMicroOps) + numMicroops(_numMicroops) { - assert(numMicroOps); - microOps = new StaticInstPtr[numMicroOps]; - flags[IsMacroOp] = true; + assert(numMicroops); + microops = new StaticInstPtr[numMicroops]; + flags[IsMacroop] = true; } ~SparcMacroInst() { - delete [] microOps; + delete [] microops; } std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; - StaticInstPtr * microOps; + StaticInstPtr * microops; - StaticInstPtr fetchMicroOp(MicroPC microPC) + StaticInstPtr fetchMicroop(MicroPC microPC) { - assert(microPC < numMicroOps); - return microOps[microPC]; + assert(microPC < numMicroops); + return microops[microPC]; } %(MacroExecute)s @@ -100,7 +100,7 @@ output header {{ ExtMachInst _machInst, OpClass __opClass) : SparcStaticInst(mnem, _machInst, __opClass) { - flags[IsMicroOp] = true; + flags[IsMicroop] = true; } }; diff --git a/src/arch/sparc/miscregfile.cc b/src/arch/sparc/miscregfile.cc index f511ef454..0300694cc 100644 --- a/src/arch/sparc/miscregfile.cc +++ b/src/arch/sparc/miscregfile.cc @@ -142,27 +142,38 @@ void MiscRegFile::clear() MiscReg MiscRegFile::readRegNoEffect(int miscReg) { - switch (miscReg) { - case MISCREG_TLB_DATA: - /* Package up all the data for the tlb: - * 6666555555555544444444443333333333222222222211111111110000000000 - * 3210987654321098765432109876543210987654321098765432109876543210 - * secContext | priContext | |tl|partid| |||||^hpriv - * ||||^red - * |||^priv - * ||^am - * |^lsuim - * ^lsudm - */ - return bits((uint64_t)hpstate,2,2) | - bits((uint64_t)hpstate,5,5) << 1 | - bits((uint64_t)pstate,3,2) << 2 | - bits((uint64_t)lsuCtrlReg,3,2) << 4 | - bits((uint64_t)partId,7,0) << 8 | - bits((uint64_t)tl,2,0) << 16 | - (uint64_t)priContext << 32 | - (uint64_t)secContext << 48; + // The three miscRegs are moved up from the switch statement + // due to more frequent calls. + + if (miscReg == MISCREG_GL) + return gl; + if (miscReg == MISCREG_CWP) + return cwp; + if (miscReg == MISCREG_TLB_DATA) { + /* Package up all the data for the tlb: + * 6666555555555544444444443333333333222222222211111111110000000000 + * 3210987654321098765432109876543210987654321098765432109876543210 + * secContext | priContext | |tl|partid| |||||^hpriv + * ||||^red + * |||^priv + * ||^am + * |^lsuim + * ^lsudm + */ + return bits((uint64_t)hpstate,2,2) | + bits((uint64_t)hpstate,5,5) << 1 | + bits((uint64_t)pstate,3,2) << 2 | + bits((uint64_t)lsuCtrlReg,3,2) << 4 | + bits((uint64_t)partId,7,0) << 8 | + bits((uint64_t)tl,2,0) << 16 | + (uint64_t)priContext << 32 | + (uint64_t)secContext << 48; + } + + switch (miscReg) { + //case MISCREG_TLB_DATA: + // [original contents see above] //case MISCREG_Y: // return y; //case MISCREG_CCR: @@ -207,8 +218,9 @@ MiscReg MiscRegFile::readRegNoEffect(int miscReg) return tl; case MISCREG_PIL: return pil; - case MISCREG_CWP: - return cwp; + //CWP, GL moved + //case MISCREG_CWP: + // return cwp; //case MISCREG_CANSAVE: // return cansave; //case MISCREG_CANRESTORE: @@ -219,8 +231,8 @@ MiscReg MiscRegFile::readRegNoEffect(int miscReg) // return otherwin; //case MISCREG_WSTATE: // return wstate; - case MISCREG_GL: - return gl; + //case MISCREG_GL: + // return gl; /** Hyper privileged registers */ case MISCREG_HPSTATE: diff --git a/src/arch/sparc/predecoder.hh b/src/arch/sparc/predecoder.hh index 4a8c9dc4a..38d8fd1a2 100644 --- a/src/arch/sparc/predecoder.hh +++ b/src/arch/sparc/predecoder.hh @@ -67,7 +67,7 @@ namespace SparcISA //Use this to give data to the predecoder. This should be used //when there is control flow. - void moreBytes(Addr currPC, Addr off, MachInst inst) + void moreBytes(Addr pc, Addr fetchPC, Addr off, MachInst inst) { assert(off == 0); @@ -85,13 +85,6 @@ namespace SparcISA << (sizeof(MachInst) * 8)); } - //Use this to give data to the predecoder. This should be used - //when instructions are executed in order. - void moreBytes(MachInst machInst) - { - moreBytes(0, 0, machInst); - } - bool needMoreBytes() { return true; diff --git a/src/arch/x86/intregfile.cc b/src/arch/x86/intregfile.cc index 15e86d88b..9c9ea134e 100644 --- a/src/arch/x86/intregfile.cc +++ b/src/arch/x86/intregfile.cc @@ -87,6 +87,7 @@ #include "arch/x86/intregfile.hh" #include "base/misc.hh" +#include "base/trace.hh" #include "sim/serialize.hh" #include <string.h> @@ -119,11 +120,13 @@ void IntRegFile::clear() IntReg IntRegFile::readReg(int intReg) { + DPRINTF(X86, "Read int reg %d and got value %#x\n", intReg, regs[intReg]); return regs[intReg]; } void IntRegFile::setReg(int intReg, const IntReg &val) { + DPRINTF(X86, "Setting int reg %d to value %#x\n", intReg, val); regs[intReg] = val; } diff --git a/src/arch/x86/intregs.hh b/src/arch/x86/intregs.hh index 562539de9..fc2098716 100644 --- a/src/arch/x86/intregs.hh +++ b/src/arch/x86/intregs.hh @@ -66,45 +66,45 @@ namespace X86ISA INTREG_EAX = INTREG_RAX, INTREG_AX = INTREG_RAX, INTREG_AL = INTREG_RAX, - INTREG_AH = INTREG_RAX, INTREG_RCX, INTREG_ECX = INTREG_RCX, INTREG_CX = INTREG_RCX, INTREG_CL = INTREG_RCX, - INTREG_CH = INTREG_RCX, INTREG_RDX, INTREG_EDX = INTREG_RDX, INTREG_DX = INTREG_RDX, INTREG_DL = INTREG_RDX, - INTREG_DH = INTREG_RDX, INTREG_RBX, INTREG_EBX = INTREG_RBX, INTREG_BX = INTREG_RBX, INTREG_BL = INTREG_RBX, - INTREG_BH = INTREG_RBX, INTREG_RSP, INTREG_ESP = INTREG_RSP, INTREG_SP = INTREG_RSP, INTREG_SPL = INTREG_RSP, + INTREG_AH = INTREG_RSP, INTREG_RBP, INTREG_EBP = INTREG_RBP, INTREG_BP = INTREG_RBP, INTREG_BPL = INTREG_RBP, + INTREG_CH = INTREG_RBP, INTREG_RSI, INTREG_ESI = INTREG_RSI, INTREG_SI = INTREG_RSI, INTREG_SIL = INTREG_RSI, + INTREG_DH = INTREG_RSI, INTREG_RDI, INTREG_EDI = INTREG_RDI, INTREG_DI = INTREG_RDI, INTREG_DIL = INTREG_RDI, + INTREG_BH = INTREG_RDI, INTREG_R8, INTREG_R8D = INTREG_R8, diff --git a/src/arch/x86/isa/bitfields.isa b/src/arch/x86/isa/bitfields.isa index fff324caa..82fa4f25b 100644 --- a/src/arch/x86/isa/bitfields.isa +++ b/src/arch/x86/isa/bitfields.isa @@ -58,9 +58,21 @@ // Bitfield definitions. // -//Prefixes +//REX prefix def bitfield REX rex; +def bitfield REX_W rex.w; +def bitfield REX_R rex.r; +def bitfield REX_X rex.x; +def bitfield REX_B rex.b; + +//Legacy prefixes def bitfield LEGACY legacy; +def bitfield LEGACY_REPNE legacy.repne; +def bitfield LEGACY_REP legacy.rep; +def bitfield LEGACY_LOCK legacy.lock; +def bitfield LEGACY_ADDR legacy.addr; +def bitfield LEGACY_OP legacy.op; +def bitfield LEGACY_SEG legacy.seg; // Pieces of the opcode def bitfield OPCODE_NUM opcode.num; @@ -85,3 +97,6 @@ def bitfield SIB sib; def bitfield SIB_SCALE sib.scale; def bitfield SIB_INDEX sib.index; def bitfield SIB_BASE sib.base; + +def bitfield OPSIZE opSize; +def bitfield ADDRSIZE addrSize; diff --git a/src/arch/x86/isa/decoder/one_byte_opcodes.isa b/src/arch/x86/isa/decoder/one_byte_opcodes.isa index 4e044363b..b72b2b16a 100644 --- a/src/arch/x86/isa/decoder/one_byte_opcodes.isa +++ b/src/arch/x86/isa/decoder/one_byte_opcodes.isa @@ -61,12 +61,11 @@ 0x1: decode OPCODE_OP_TOP5 { format WarnUnimpl { 0x00: decode OPCODE_OP_BOTTOM3 { - 0x4: Inst::ADD(rAl,Ib); - 0x5: Inst::ADD(rAx,Iz); + 0x4: ADD(); + 0x5: ADD(); 0x6: push_ES(); 0x7: pop_ES(); - default: MultiInst::ADD(OPCODE_OP_BOTTOM3, - [Eb,Gb],[Ev,Gv],[Gb,Eb],[Gv,Ev]); + default: ADD(); } 0x01: decode OPCODE_OP_BOTTOM3 { 0x0: or_Eb_Gb(); @@ -129,7 +128,8 @@ {{"Tried to execute the SS segment override prefix!"}}); 0x7: aaa(); default: MultiInst::XOR(OPCODE_OP_BOTTOM3, - [Eb,Gb],[Ev,Gv],[Gb,Eb],[Gv,Ev]); + [Eb,Gb], [Ev,Gv], + [Gb,Eb], [Gv,Ev]); } 0x07: decode OPCODE_OP_BOTTOM3 { 0x0: cmp_Eb_Gb(); @@ -163,11 +163,11 @@ 0x7: dec_eDI(); } 0x0A: decode OPCODE_OP_BOTTOM3 { - 0x0: push_rAX(); + 0x0: Inst::PUSH(rAx); 0x1: push_rCX(); 0x2: push_rDX(); 0x3: push_rBX(); - 0x4: push_rSP(); + 0x4: Inst::PUSH(rSP); 0x5: push_rBP(); 0x6: push_rSI(); 0x7: push_rDI(); @@ -179,7 +179,7 @@ 0x3: pop_rBX(); 0x4: pop_rSP(); 0x5: pop_rBP(); - 0x6: pop_rSI(); + 0x6: Inst::POP(rSI); 0x7: pop_rDI(); } 0x0C: decode OPCODE_OP_BOTTOM3 { @@ -230,18 +230,28 @@ 0x0: group1_Eb_Ib(); 0x1: group1_Ev_Iz(); 0x2: group1_Eb_Ib(); - 0x3: group1_Ev_Ib(); + //0x3: group1_Ev_Ib(); + 0x3: decode MODRM_REG { + 0x0: add_Eb_Ib(); + 0x1: or_Eb_Ib(); + 0x2: adc_Eb_Ib(); + 0x3: sbb_Eb_Ib(); + 0x4: Inst::AND(Eb,Ib); + 0x5: sub_Eb_Ib(); + 0x6: xor_Eb_Ib(); + 0x7: cmp_Eb_Ib(); + } 0x4: test_Eb_Gb(); 0x5: test_Ev_Gv(); 0x6: xchg_Eb_Gb(); 0x7: xchg_Ev_Gv(); } 0x11: decode OPCODE_OP_BOTTOM3 { - 0x0: Inst::MOV(); //mov_Eb_Gb(); - 0x1: Inst::MOV(); //mov_Ev_Gv(); - 0x2: Inst::MOV(); //mov_Gb_Eb(); - 0x3: Inst::MOV(); //mov_Gv_Ev(); - 0x4: Inst::MOV(); //mov_MwRv_Sw(); + 0x0: Inst::MOV(Eb,Gb); + 0x1: Inst::MOV(Ev,Gv); + 0x2: Inst::MOV(Gb,Eb); + 0x3: Inst::MOV(Gv,Eb); + 0x4: mov_MwRv_Sw(); //What to do with this one? 0x5: lea_Gv_M(); 0x6: mov_Sw_MwRv(); 0x7: group10_Ev(); //Make sure this is Ev @@ -313,8 +323,14 @@ 0x3: ret_near(); 0x4: les_Gz_Mp(); 0x5: lds_Gz_Mp(); - 0x6: group12_Eb_Ib(); - 0x7: group12_Ev_Iz(); + //0x6: group12_Eb_Ib(); + 0x6: decode MODRM_REG { + 0x0: Inst::MOV(Eb,Ib); + } + //0x7: group12_Ev_Iz(); + 0x7: decode MODRM_REG { + 0x0: Inst::MOV(Ev,Iz); + } } 0x19: decode OPCODE_OP_BOTTOM3 { 0x0: enter_Iw_Ib(); diff --git a/src/arch/x86/isa/formats/multi.isa b/src/arch/x86/isa/formats/multi.isa index 8f91c249c..37b28fe64 100644 --- a/src/arch/x86/isa/formats/multi.isa +++ b/src/arch/x86/isa/formats/multi.isa @@ -55,32 +55,23 @@ // // Authors: Gabe Black -//////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////////// // -// Instructions that do the same thing to multiple sets of arguments. +// Instructions operate on one or multiple types of sets of arguments. // - -let {{ - def doInst(name, Name, opTypeSet): - if not instDict.has_key(Name): - raise Exception, "Unrecognized instruction: %s" % Name - inst = instDict[Name]() - return inst.emit(opTypeSet) -}}; +////////////////////////////////////////////////////////////////////////// def format Inst(*opTypeSet) {{ - (header_output, - decoder_output, - decode_block, - exce_output) = doInst(name, Name, list(opTypeSet)).makeList() + blocks = specializeInst(Name, list(opTypeSet), EmulEnv()) + (header_output, decoder_output, + decode_block, exec_output) = blocks.makeList() }}; def format MultiInst(switchVal, *opTypeSets) {{ switcher = {} for (count, opTypeSet) in zip(xrange(len(opTypeSets)), opTypeSets): - switcher[count] = (opTypeSet,) - (header_output, - decoder_output, - decode_block, - exec_output) = doSplitDecode(name, Name, doInst, switchVal, switcher).makeList() + switcher[count] = (Name, opTypeSet, EmulEnv()) + blocks = doSplitDecode(specializeInst, switchVal, switcher) + (header_output, decoder_output, + decode_block, exec_output) = blocks.makeList() }}; diff --git a/src/arch/x86/isa/includes.isa b/src/arch/x86/isa/includes.isa index 3440ec5da..8bb282150 100644 --- a/src/arch/x86/isa/includes.isa +++ b/src/arch/x86/isa/includes.isa @@ -99,6 +99,7 @@ output header {{ #include "arch/x86/faults.hh" #include "arch/x86/isa_traits.hh" #include "arch/x86/regfile.hh" +#include "arch/x86/types.hh" #include "base/misc.hh" #include "cpu/static_inst.hh" #include "mem/packet.hh" @@ -106,6 +107,7 @@ output header {{ }}; output decoder {{ + #include "base/cprintf.hh" #include "base/loader/symtab.hh" #include "cpu/thread_context.hh" // for Jump::branchTarget() diff --git a/src/arch/x86/isa/insts/__init__.py b/src/arch/x86/isa/insts/__init__.py new file mode 100644 index 000000000..717690926 --- /dev/null +++ b/src/arch/x86/isa/insts/__init__.py @@ -0,0 +1,79 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +categories = ["arithmetic", + "cache_and_memory_management", + "compare_and_test", + "control_transfer", + "data_conversion", + "data_transfer", + "flags", + "input_output", + "load_effective_address", + "load_segment_registers", + "logical", + "no_operation", + "processor_information", + "rotate_and_shift", + "semaphores", + "string", + "system_calls"] + +microcode = ''' +# X86 microcode +''' +for category in categories: + exec "import %s as cat" % category + microcode += cat.microcode diff --git a/src/arch/x86/isa/insts/arithmetic/__init__.py b/src/arch/x86/isa/insts/arithmetic/__init__.py new file mode 100644 index 000000000..c7e6b8c5f --- /dev/null +++ b/src/arch/x86/isa/insts/arithmetic/__init__.py @@ -0,0 +1,64 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +categories = ["add_and_subtract", + "increment_and_decrement", + "multiply_and_divide"] + +microcode = "" +for category in categories: + exec "import %s as cat" % category + microcode += cat.microcode + diff --git a/src/arch/x86/isa/insts/arithmetic/add_and_subtract.py b/src/arch/x86/isa/insts/arithmetic/add_and_subtract.py new file mode 100644 index 000000000..283152f30 --- /dev/null +++ b/src/arch/x86/isa/insts/arithmetic/add_and_subtract.py @@ -0,0 +1,68 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class ADC(Inst): +# "Adc ^0 ^0 ^1" +# class ADD(Inst): +# "Add ^0 ^0 ^1" +# class SBB(Inst): +# "Sbb ^0 ^0 ^1" +# class SUB(Inst): +# "Sub ^0 ^0 ^1" +# class NEG(Inst): +# "Sub ^0 $0 ^0" +#}}; diff --git a/src/arch/x86/isa/insts/arithmetic/increment_and_decrement.py b/src/arch/x86/isa/insts/arithmetic/increment_and_decrement.py new file mode 100644 index 000000000..c504d47ce --- /dev/null +++ b/src/arch/x86/isa/insts/arithmetic/increment_and_decrement.py @@ -0,0 +1,62 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class DEC(Inst): +# "GenFault ${new UnimpInstFault}" +# class INC(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/arithmetic/multiply_and_divide.py b/src/arch/x86/isa/insts/arithmetic/multiply_and_divide.py new file mode 100644 index 000000000..662022e6a --- /dev/null +++ b/src/arch/x86/isa/insts/arithmetic/multiply_and_divide.py @@ -0,0 +1,66 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class MUL(Inst): +# "GenFault ${new UnimpInstFault}" +# class IMUL(Inst): +# "GenFault ${new UnimpInstFault}" +# class DIV(Inst): +# "GenFault ${new UnimpInstFault}" +# class IDIV(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/cache_and_memory_management.py b/src/arch/x86/isa/insts/cache_and_memory_management.py new file mode 100644 index 000000000..b5fc43fcd --- /dev/null +++ b/src/arch/x86/isa/insts/cache_and_memory_management.py @@ -0,0 +1,72 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class LFENCE(Inst): +# "GenFault ${new UnimpInstFault}" +# class SFENCE(Inst): +# "GenFault ${new UnimpInstFault}" +# class MFENCE(Inst): +# "GenFault ${new UnimpInstFault}" +# class PREFETCHlevel(Inst): +# "GenFault ${new UnimpInstFault}" +# class PREFETCH(Inst): +# "GenFault ${new UnimpInstFault}" +# class PREFETCHW(Inst): +# "GenFault ${new UnimpInstFault}" +# class CLFLUSH(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/compare_and_test/__init__.py b/src/arch/x86/isa/insts/compare_and_test/__init__.py new file mode 100644 index 000000000..56f33585a --- /dev/null +++ b/src/arch/x86/isa/insts/compare_and_test/__init__.py @@ -0,0 +1,66 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +categories = ["bit_scan", + "bit_test", + "bounds", + "compare", + "set_byte_on_condition", + "test"] + +microcode = "" +for category in categories: + exec "import %s as cat" % category + microcode += cat.microcode diff --git a/src/arch/x86/isa/insts/compare_and_test/bit_scan.py b/src/arch/x86/isa/insts/compare_and_test/bit_scan.py new file mode 100644 index 000000000..f04520296 --- /dev/null +++ b/src/arch/x86/isa/insts/compare_and_test/bit_scan.py @@ -0,0 +1,62 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class BSF(Inst): +# "GenFault ${new UnimpInstFault}" +# class BSR(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/compare_and_test/bit_test.py b/src/arch/x86/isa/insts/compare_and_test/bit_test.py new file mode 100644 index 000000000..e950f008a --- /dev/null +++ b/src/arch/x86/isa/insts/compare_and_test/bit_test.py @@ -0,0 +1,66 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class BT(Inst): +# "GenFault ${new UnimpInstFault}" +# class BTC(Inst): +# "GenFault ${new UnimpInstFault}" +# class BTR(Inst): +# "GenFault ${new UnimpInstFault}" +# class BTS(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/compare_and_test/bounds.py b/src/arch/x86/isa/insts/compare_and_test/bounds.py new file mode 100644 index 000000000..4b6cc8f71 --- /dev/null +++ b/src/arch/x86/isa/insts/compare_and_test/bounds.py @@ -0,0 +1,60 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class BOUND(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/compare_and_test/compare.py b/src/arch/x86/isa/insts/compare_and_test/compare.py new file mode 100644 index 000000000..12b5b859f --- /dev/null +++ b/src/arch/x86/isa/insts/compare_and_test/compare.py @@ -0,0 +1,60 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class CMP(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/compare_and_test/set_byte_on_condition.py b/src/arch/x86/isa/insts/compare_and_test/set_byte_on_condition.py new file mode 100644 index 000000000..3d9250c2d --- /dev/null +++ b/src/arch/x86/isa/insts/compare_and_test/set_byte_on_condition.py @@ -0,0 +1,60 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class SETcc(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/compare_and_test/test.py b/src/arch/x86/isa/insts/compare_and_test/test.py new file mode 100644 index 000000000..b4d1cf9b8 --- /dev/null +++ b/src/arch/x86/isa/insts/compare_and_test/test.py @@ -0,0 +1,60 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class TEST(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/control_transfer/__init__.py b/src/arch/x86/isa/insts/control_transfer/__init__.py new file mode 100644 index 000000000..6694b857c --- /dev/null +++ b/src/arch/x86/isa/insts/control_transfer/__init__.py @@ -0,0 +1,66 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +categories = ["call", + "conditional_jump", + "interrupts_and_exceptions", + "jump", + "loop", + "xreturn"] + +microcode = "" +for category in categories: + exec "import %s as cat" % category + microcode += cat.microcode diff --git a/src/arch/x86/isa/insts/control_transfer/call.py b/src/arch/x86/isa/insts/control_transfer/call.py new file mode 100644 index 000000000..231db6e40 --- /dev/null +++ b/src/arch/x86/isa/insts/control_transfer/call.py @@ -0,0 +1,60 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class CALL(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/control_transfer/conditional_jump.py b/src/arch/x86/isa/insts/control_transfer/conditional_jump.py new file mode 100644 index 000000000..7ca426be6 --- /dev/null +++ b/src/arch/x86/isa/insts/control_transfer/conditional_jump.py @@ -0,0 +1,60 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class JCC(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/control_transfer/interrupts_and_exceptions.py b/src/arch/x86/isa/insts/control_transfer/interrupts_and_exceptions.py new file mode 100644 index 000000000..7039b4b5c --- /dev/null +++ b/src/arch/x86/isa/insts/control_transfer/interrupts_and_exceptions.py @@ -0,0 +1,68 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class INT(Inst): +# "GenFault ${new UnimpInstFault}" +# class INTO(Inst): +# "GenFault ${new UnimpInstFault}" +# class IRET(Inst): +# "GenFault ${new UnimpInstFault}" +# class IRETD(Inst): +# "GenFault ${new UnimpInstFault}" +# class IRETQ(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/control_transfer/jump.py b/src/arch/x86/isa/insts/control_transfer/jump.py new file mode 100644 index 000000000..e90e5b12b --- /dev/null +++ b/src/arch/x86/isa/insts/control_transfer/jump.py @@ -0,0 +1,60 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class JMP(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/control_transfer/loop.py b/src/arch/x86/isa/insts/control_transfer/loop.py new file mode 100644 index 000000000..d742f217f --- /dev/null +++ b/src/arch/x86/isa/insts/control_transfer/loop.py @@ -0,0 +1,60 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class LOOPcc(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/control_transfer/xreturn.py b/src/arch/x86/isa/insts/control_transfer/xreturn.py new file mode 100644 index 000000000..aaffa2b92 --- /dev/null +++ b/src/arch/x86/isa/insts/control_transfer/xreturn.py @@ -0,0 +1,60 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class RET(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/data_conversion/__init__.py b/src/arch/x86/isa/insts/data_conversion/__init__.py new file mode 100644 index 000000000..b3a40b8a0 --- /dev/null +++ b/src/arch/x86/isa/insts/data_conversion/__init__.py @@ -0,0 +1,66 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +categories = ["ascii_adjust", + "bcd_adjust", + "endian_conversion", + "extract_sign_mask", + "sign_extension", + "translate"] + +microcode = "" +for category in categories: + exec "import %s as cat" % category + microcode += cat.microcode diff --git a/src/arch/x86/isa/insts/data_conversion/ascii_adjust.py b/src/arch/x86/isa/insts/data_conversion/ascii_adjust.py new file mode 100644 index 000000000..a1e322e56 --- /dev/null +++ b/src/arch/x86/isa/insts/data_conversion/ascii_adjust.py @@ -0,0 +1,66 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class AAA(Inst): +# "GenFault ${new UnimpInstFault}" +# class AAD(Inst): +# "GenFault ${new UnimpInstFault}" +# class AAM(Inst): +# "GenFault ${new UnimpInstFault}" +# class AAS(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/data_conversion/bcd_adjust.py b/src/arch/x86/isa/insts/data_conversion/bcd_adjust.py new file mode 100644 index 000000000..213724768 --- /dev/null +++ b/src/arch/x86/isa/insts/data_conversion/bcd_adjust.py @@ -0,0 +1,62 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class DAA(Inst): +# "GenFault ${new UnimpInstFault}" +# class DAS(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/data_conversion/endian_conversion.py b/src/arch/x86/isa/insts/data_conversion/endian_conversion.py new file mode 100644 index 000000000..b98d09816 --- /dev/null +++ b/src/arch/x86/isa/insts/data_conversion/endian_conversion.py @@ -0,0 +1,60 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class BSWAP(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/data_conversion/extract_sign_mask.py b/src/arch/x86/isa/insts/data_conversion/extract_sign_mask.py new file mode 100644 index 000000000..1e0810594 --- /dev/null +++ b/src/arch/x86/isa/insts/data_conversion/extract_sign_mask.py @@ -0,0 +1,62 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class MOVMSKPS(Inst): +# "GenFault ${new UnimpInstFault}" +# class MOVMSKPD(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/data_conversion/sign_extension.py b/src/arch/x86/isa/insts/data_conversion/sign_extension.py new file mode 100644 index 000000000..e96eee694 --- /dev/null +++ b/src/arch/x86/isa/insts/data_conversion/sign_extension.py @@ -0,0 +1,70 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class CBW(Inst): +# "GenFault ${new UnimpInstFault}" +# class CWDE(Inst): +# "GenFault ${new UnimpInstFault}" +# class CDQE(Inst): +# "GenFault ${new UnimpInstFault}" +# class CWD(Inst): +# "GenFault ${new UnimpInstFault}" +# class CDQ(Inst): +# "GenFault ${new UnimpInstFault}" +# class CQO(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/data_conversion/translate.py b/src/arch/x86/isa/insts/data_conversion/translate.py new file mode 100644 index 000000000..bb286b976 --- /dev/null +++ b/src/arch/x86/isa/insts/data_conversion/translate.py @@ -0,0 +1,60 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class XLAT(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/data_transfer/__init__.py b/src/arch/x86/isa/insts/data_transfer/__init__.py new file mode 100644 index 000000000..eda173b34 --- /dev/null +++ b/src/arch/x86/isa/insts/data_transfer/__init__.py @@ -0,0 +1,63 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +categories = ["conditional_move", + "move", + "stack_operations"] + +microcode = "" +for category in categories: + exec "import %s as cat" % category + microcode += cat.microcode diff --git a/src/arch/x86/isa/insts/data_transfer/conditional_move.py b/src/arch/x86/isa/insts/data_transfer/conditional_move.py new file mode 100644 index 000000000..513e90c4e --- /dev/null +++ b/src/arch/x86/isa/insts/data_transfer/conditional_move.py @@ -0,0 +1,60 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class CMOVcc(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/data_transfer/move.py b/src/arch/x86/isa/insts/data_transfer/move.py new file mode 100644 index 000000000..9d23b24e8 --- /dev/null +++ b/src/arch/x86/isa/insts/data_transfer/move.py @@ -0,0 +1,89 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +def macroop MOV_R_R { + mov "env.reg", "env.reg", "env.regm" +}; + +def macroop MOV_M_R { + #Do a store to put the register operand into memory +}; + +def macroop MOV_R_M { + #Do a load to fill the register operand from memory +}; + +def macroop MOV_R_I { + limm "env.reg", "env.immediate" +}; + +def macroop MOV_M_I { + limm "env.reg", "env.immediate" + #Do a store to put the register operand into memory +}; +''' +#let {{ +# class MOV(Inst): +# "Mov ^0 ^0 ^1" +# class MOVSX(Inst): +# "GenFault ${new UnimpInstFault}" +# class MOVZX(Inst): +# "GenFault ${new UnimpInstFault}" +# class MOVD(Inst): +# "GenFault ${new UnimpInstFault}" +# class MOVNTI(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/data_transfer/stack_operations.py b/src/arch/x86/isa/insts/data_transfer/stack_operations.py new file mode 100644 index 000000000..b7ec0ec66 --- /dev/null +++ b/src/arch/x86/isa/insts/data_transfer/stack_operations.py @@ -0,0 +1,88 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +def macroop POP_R { + .adjust_env "if(machInst.mode.submode == SixtyFourBitMode && env.dataSize == 4) env.dataSize = 8\;" + # There needs to be a load here to actually "pop" the data + addi "INTREG_RSP", "INTREG_RSP", "env.dataSize" +}; + +def macroop PUSH_R { + .adjust_env "if(machInst.mode.submode == SixtyFourBitMode && env.dataSize == 4) env.dataSize = 8\;" + subi "INTREG_RSP", "INTREG_RSP", "env.dataSize" + # There needs to be a store here to actually "push" the data +}; +''' +#let {{ +# class POP(Inst): +# "GenFault ${new UnimpInstFault}" +# class POPA(Inst): +# "GenFault ${new UnimpInstFault}" +# class POPA(Inst): +# "GenFault ${new UnimpInstFault}" +# class POPAD(Inst): +# "GenFault ${new UnimpInstFault}" +# class PUSH(Inst): +# "GenFault ${new UnimpInstFault}" +# class PUSHA(Inst): +# "GenFault ${new UnimpInstFault}" +# class PUSHAD(Inst): +# "GenFault ${new UnimpInstFault}" +# class ENTER(Inst): +# "GenFault ${new UnimpInstFault}" +# class LEAVE(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/flags/__init__.py b/src/arch/x86/isa/insts/flags/__init__.py new file mode 100644 index 000000000..92a8e6a2d --- /dev/null +++ b/src/arch/x86/isa/insts/flags/__init__.py @@ -0,0 +1,63 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +categories = ["load_and_store", + "push_and_pop", + "set_and_clear"] + +microcode = "" +for category in categories: + exec "import %s as cat" % category + microcode += cat.microcode diff --git a/src/arch/x86/isa/insts/flags/load_and_store.py b/src/arch/x86/isa/insts/flags/load_and_store.py new file mode 100644 index 000000000..c6f279a25 --- /dev/null +++ b/src/arch/x86/isa/insts/flags/load_and_store.py @@ -0,0 +1,62 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class LAHF(Inst): +# "GenFault ${new UnimpInstFault}" +# class SAHF(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/flags/push_and_pop.py b/src/arch/x86/isa/insts/flags/push_and_pop.py new file mode 100644 index 000000000..dbb6c34c4 --- /dev/null +++ b/src/arch/x86/isa/insts/flags/push_and_pop.py @@ -0,0 +1,70 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class POPF(Inst): +# "GenFault ${new UnimpInstFault}" +# class POPFD(Inst): +# "GenFault ${new UnimpInstFault}" +# class POPFQ(Inst): +# "GenFault ${new UnimpInstFault}" +# class PUSHF(Inst): +# "GenFault ${new UnimpInstFault}" +# class PUSHFD(Inst): +# "GenFault ${new UnimpInstFault}" +# class pushfq(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/flags/set_and_clear.py b/src/arch/x86/isa/insts/flags/set_and_clear.py new file mode 100644 index 000000000..d70b95382 --- /dev/null +++ b/src/arch/x86/isa/insts/flags/set_and_clear.py @@ -0,0 +1,72 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class CLC(Inst): +# "GenFault ${new UnimpInstFault}" +# class CMC(Inst): +# "GenFault ${new UnimpInstFault}" +# class STC(Inst): +# "GenFault ${new UnimpInstFault}" +# class CLD(Inst): +# "GenFault ${new UnimpInstFault}" +# class STD(Inst): +# "GenFault ${new UnimpInstFault}" +# class CLI(Inst): +# "GenFault ${new UnimpInstFault}" +# class STI(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/input_output/__init__.py b/src/arch/x86/isa/insts/input_output/__init__.py new file mode 100644 index 000000000..54fb3d9b0 --- /dev/null +++ b/src/arch/x86/isa/insts/input_output/__init__.py @@ -0,0 +1,62 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +categories = ["general_io", + "string_io"] + +microcode = "" +for category in categories: + exec "import %s as cat" % category + microcode += cat.microcode diff --git a/src/arch/x86/isa/insts/input_output/general_io.py b/src/arch/x86/isa/insts/input_output/general_io.py new file mode 100644 index 000000000..f9aa9d6e4 --- /dev/null +++ b/src/arch/x86/isa/insts/input_output/general_io.py @@ -0,0 +1,62 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class IN(Inst): +# "GenFault ${new UnimpInstFault}" +# class OUT(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/input_output/string_io.py b/src/arch/x86/isa/insts/input_output/string_io.py new file mode 100644 index 000000000..a35ba772f --- /dev/null +++ b/src/arch/x86/isa/insts/input_output/string_io.py @@ -0,0 +1,78 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class INS(Inst): +# "GenFault ${new UnimpInstFault}" +# class INSB(Inst): +# "GenFault ${new UnimpInstFault}" +# class INSW(Inst): +# "GenFault ${new UnimpInstFault}" +# class INSD(Inst): +# "GenFault ${new UnimpInstFault}" +# class INSQ(Inst): +# "GenFault ${new UnimpInstFault}" +# class OUTS(Inst): +# "GenFault ${new UnimpInstFault}" +# class OUTSB(Inst): +# "GenFault ${new UnimpInstFault}" +# class OUTSW(Inst): +# "GenFault ${new UnimpInstFault}" +# class OUTSD(Inst): +# "GenFault ${new UnimpInstFault}" +# class OUTSQ(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/load_effective_address.py b/src/arch/x86/isa/insts/load_effective_address.py new file mode 100644 index 000000000..dab6960b1 --- /dev/null +++ b/src/arch/x86/isa/insts/load_effective_address.py @@ -0,0 +1,60 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class LEA(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/load_segment_registers.py b/src/arch/x86/isa/insts/load_segment_registers.py new file mode 100644 index 000000000..8aec4b99e --- /dev/null +++ b/src/arch/x86/isa/insts/load_segment_registers.py @@ -0,0 +1,72 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class LDS(Inst): +# "GenFault ${new UnimpInstFault}" +# class LES(Inst): +# "GenFault ${new UnimpInstFault}" +# class LFS(Inst): +# "GenFault ${new UnimpInstFault}" +# class LGS(Inst): +# "GenFault ${new UnimpInstFault}" +# class LSS(Inst): +# "GenFault ${new UnimpInstFault}" +# class MOV_SEG(Inst): +# "GenFault ${new UnimpInstFault}" +# class POP(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/logical.py b/src/arch/x86/isa/insts/logical.py new file mode 100644 index 000000000..ec0ed97b2 --- /dev/null +++ b/src/arch/x86/isa/insts/logical.py @@ -0,0 +1,114 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +def macroop XOR_R_R +{ + xor "env.reg", "env.reg", "env.regm" +}; + +def macroop XOR_R_I +{ + limm "NUM_INTREGS", "env.immediate" + xor "env.reg", "env.reg", "NUM_INTREGS" +}; + +def macroop XOR_M_R +{ + #Do a load to get one of the sources + xor "NUM_INTREGS", "NUM_INTREGS", "env.reg" + #Do a store to write the destination +}; + +def macroop XOR_R_M +{ + #Do a load to get one of the sources + xor "env.reg", "env.reg", "NUM_INTREGS" +}; + +def macroop AND_R_I +{ + limm "NUM_INTREGS", "env.immediate" + and "env.reg", "env.reg", "NUM_INTREGS" +}; + +def macroop AND_M_I +{ + #Do a load to get one of the sources + limm "NUM_INTREGS", "env.immediate" + and "NUM_INTREGS", "NUM_INTREGS", "NUM_INTREGS+1" + #Do a store to write the destination +}; +''' +#let {{ +#microcodeString = ''' +# def macroop AND +# { +# And reg reg regm +# }; +# def macroop OR +# { +# Or reg reg regm +# }; +# def macroop XOR +# { +# Xor reg reg regm +# }; +# def macroop NOT +# { +# Xor reg reg "0xFFFFFFFFFFFFFFFFULL" +# }; +#''' +#}}; diff --git a/src/arch/x86/isa/insts/no_operation.py b/src/arch/x86/isa/insts/no_operation.py new file mode 100644 index 000000000..1a287aea7 --- /dev/null +++ b/src/arch/x86/isa/insts/no_operation.py @@ -0,0 +1,60 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class NOP(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/processor_information.py b/src/arch/x86/isa/insts/processor_information.py new file mode 100644 index 000000000..b9c8a407e --- /dev/null +++ b/src/arch/x86/isa/insts/processor_information.py @@ -0,0 +1,60 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class CPUID(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/rotate_and_shift/__init__.py b/src/arch/x86/isa/insts/rotate_and_shift/__init__.py new file mode 100644 index 000000000..c6c019f0d --- /dev/null +++ b/src/arch/x86/isa/insts/rotate_and_shift/__init__.py @@ -0,0 +1,62 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +categories = ["rotate", + "shift"] + +microcode = "" +for category in categories: + exec "import %s as cat" % category + microcode += cat.microcode diff --git a/src/arch/x86/isa/insts/rotate_and_shift/rotate.py b/src/arch/x86/isa/insts/rotate_and_shift/rotate.py new file mode 100644 index 000000000..e3aaf0043 --- /dev/null +++ b/src/arch/x86/isa/insts/rotate_and_shift/rotate.py @@ -0,0 +1,66 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class RCL(Inst): +# "GenFault ${new UnimpInstFault}" +# class RCR(Inst): +# "GenFault ${new UnimpInstFault}" +# class ROL(Inst): +# "GenFault ${new UnimpInstFault}" +# class ROR(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/rotate_and_shift/shift.py b/src/arch/x86/isa/insts/rotate_and_shift/shift.py new file mode 100644 index 000000000..f72794657 --- /dev/null +++ b/src/arch/x86/isa/insts/rotate_and_shift/shift.py @@ -0,0 +1,70 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class SAL(Inst): +# "GenFault ${new UnimpInstFault}" +# class SAR(Inst): +# "GenFault ${new UnimpInstFault}" +# class SHL(Inst): +# "GenFault ${new UnimpInstFault}" +# class SHR(Inst): +# "GenFault ${new UnimpInstFault}" +# class SHLD(Inst): +# "GenFault ${new UnimpInstFault}" +# class SHRD(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/semaphores.py b/src/arch/x86/isa/insts/semaphores.py new file mode 100644 index 000000000..32f28cf82 --- /dev/null +++ b/src/arch/x86/isa/insts/semaphores.py @@ -0,0 +1,68 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class CMPXCHG(Inst): +# "GenFault ${new UnimpInstFault}" +# class CMPXCHG8B(Inst): +# "GenFault ${new UnimpInstFault}" +# class CMPXCHG16B(Inst): +# "GenFault ${new UnimpInstFault}" +# class XADD(Inst): +# "GenFault ${new UnimpInstFault}" +# class XCHG(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/string/__init__.py b/src/arch/x86/isa/insts/string/__init__.py new file mode 100644 index 000000000..f43a8d3e5 --- /dev/null +++ b/src/arch/x86/isa/insts/string/__init__.py @@ -0,0 +1,65 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +categories = ["compare_strings", + "load_string", + "move_string", + "scan_string", + "store_string"] + +microcode = "" +for category in categories: + exec "import %s as cat" % category + microcode += cat.microcode diff --git a/src/arch/x86/isa/insts/string/compare_strings.py b/src/arch/x86/isa/insts/string/compare_strings.py new file mode 100644 index 000000000..1484c4706 --- /dev/null +++ b/src/arch/x86/isa/insts/string/compare_strings.py @@ -0,0 +1,68 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class CMPS(Inst): +# "GenFault ${new UnimpInstFault}" +# class CMPSB(Inst): +# "GenFault ${new UnimpInstFault}" +# class CMPSW(Inst): +# "GenFault ${new UnimpInstFault}" +# class CMPSD(Inst): +# "GenFault ${new UnimpInstFault}" +# class CMPSQ(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/string/load_string.py b/src/arch/x86/isa/insts/string/load_string.py new file mode 100644 index 000000000..0f749a273 --- /dev/null +++ b/src/arch/x86/isa/insts/string/load_string.py @@ -0,0 +1,68 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class LODS(Inst): +# "GenFault ${new UnimpInstFault}" +# class LODSB(Inst): +# "GenFault ${new UnimpInstFault}" +# class LODSW(Inst): +# "GenFault ${new UnimpInstFault}" +# class LODSD(Inst): +# "GenFault ${new UnimpInstFault}" +# class LODSQ(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/string/move_string.py b/src/arch/x86/isa/insts/string/move_string.py new file mode 100644 index 000000000..0a855b384 --- /dev/null +++ b/src/arch/x86/isa/insts/string/move_string.py @@ -0,0 +1,68 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class MOVS(Inst): +# "GenFault ${new UnimpInstFault}" +# class MOVSB(Inst): +# "GenFault ${new UnimpInstFault}" +# class MOVSW(Inst): +# "GenFault ${new UnimpInstFault}" +# class MOVSD(Inst): +# "GenFault ${new UnimpInstFault}" +# class MOVSQ(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/string/scan_string.py b/src/arch/x86/isa/insts/string/scan_string.py new file mode 100644 index 000000000..cd3d5b549 --- /dev/null +++ b/src/arch/x86/isa/insts/string/scan_string.py @@ -0,0 +1,68 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class SCAS(Inst): +# "GenFault ${new UnimpInstFault}" +# class SCASB(Inst): +# "GenFault ${new UnimpInstFault}" +# class SCASW(Inst): +# "GenFault ${new UnimpInstFault}" +# class SCASD(Inst): +# "GenFault ${new UnimpInstFault}" +# class SCASQ(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/string/store_string.py b/src/arch/x86/isa/insts/string/store_string.py new file mode 100644 index 000000000..08a126c1f --- /dev/null +++ b/src/arch/x86/isa/insts/string/store_string.py @@ -0,0 +1,68 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class STOS(Inst): +# "Add 0 0 0" +# class STOSB(Inst): +# "Add 0 0 0" +# class STOSW(Inst): +# "Add 0 0 0" +# class STOSD(Inst): +# "Add 0 0 0" +# class STOSQ(Inst): +# "Add 0 0 0" +#}}; diff --git a/src/arch/x86/isa/insts/system_calls.py b/src/arch/x86/isa/insts/system_calls.py new file mode 100644 index 000000000..e056bea84 --- /dev/null +++ b/src/arch/x86/isa/insts/system_calls.py @@ -0,0 +1,66 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class SYSENTER(Inst): +# "GenFault ${new UnimpInstFault}" +# class SYSEXIT(Inst): +# "GenFault ${new UnimpInstFault}" +# class SYSCALL(Inst): +# "GenFault ${new UnimpInstFault}" +# class SYSRET(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/macroop.isa b/src/arch/x86/isa/macroop.isa index 663ec7aee..2d928d7c9 100644 --- a/src/arch/x86/isa/macroop.isa +++ b/src/arch/x86/isa/macroop.isa @@ -71,34 +71,34 @@ def template MacroExecPanic {{ output header {{ - // Base class for macroops - class MacroOp : public StaticInst + // Base class for combinationally generated macroops + class Macroop : public StaticInst { protected: - const uint32_t numMicroOps; + const uint32_t numMicroops; //Constructor. - MacroOp(const char *mnem, ExtMachInst _machInst, - uint32_t _numMicroOps) + Macroop(const char *mnem, ExtMachInst _machInst, + uint32_t _numMicroops) : StaticInst(mnem, _machInst, No_OpClass), - numMicroOps(_numMicroOps) + numMicroops(_numMicroops) { - assert(numMicroOps); - microOps = new StaticInstPtr[numMicroOps]; - flags[IsMacroOp] = true; + assert(numMicroops); + microops = new StaticInstPtr[numMicroops]; + flags[IsMacroop] = true; } - ~MacroOp() + ~Macroop() { - delete [] microOps; + delete [] microops; } - StaticInstPtr * microOps; + StaticInstPtr * microops; - StaticInstPtr fetchMicroOp(MicroPC microPC) + StaticInstPtr fetchMicroop(MicroPC microPC) { - assert(microPC < numMicroOps); - return microOps[microPC]; + assert(microPC < numMicroops); + return microops[microPC]; } std::string generateDisassembly(Addr pc, @@ -113,26 +113,30 @@ output header {{ // Basic instruction class declaration template. def template MacroDeclare {{ - /** - * Static instruction class for "%(mnemonic)s". - */ - class %(class_name)s : public %(base_class)s + namespace X86Macroop { - public: - // Constructor. - %(class_name)s(ExtMachInst machInst); + /** + * Static instruction class for "%(mnemonic)s". + */ + class %(class_name)s : public %(base_class)s + { + public: + // Constructor. + %(class_name)s(ExtMachInst machInst, EmulEnv env); + }; }; }}; // Basic instruction class constructor template. def template MacroConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst) - : %(base_class)s("%(mnemonic)s", machInst, %(num_micro_ops)s) + inline X86Macroop::%(class_name)s::%(class_name)s(ExtMachInst machInst, EmulEnv env) + : %(base_class)s("%(mnemonic)s", machInst, %(num_microops)s) { - %(constructor)s; - //alloc_micro_ops is the code that sets up the microOps - //array in the parent class. - %(alloc_micro_ops)s; + %(adjust_env)s; + %(constructor)s; + //alloc_microops is the code that sets up the microops + //array in the parent class. + %(alloc_microops)s; } }}; @@ -142,23 +146,104 @@ def template MacroConstructor {{ // let {{ - def genMacroOp(name, Name, opSeq): - numMicroOps = len(opSeq) - allocMicroOps = '' - micropc = 0 - for op in opSeq: - allocMicroOps += \ - "microOps[%d] = %s;\n" % \ - (micropc, op.getAllocator('"' + name + '"', True, False, #op.delayed, - micropc == 0, - micropc == numMicroOps - 1)) - micropc += 1 - iop = InstObjParams(name, Name, 'MacroOp', - {'code' : '', 'num_micro_ops' : numMicroOps, - 'alloc_micro_ops' : allocMicroOps}) - header_output = MacroDeclare.subst(iop) - decoder_output = MacroConstructor.subst(iop) - decode_block = BasicDecode.subst(iop) - exec_output = '' - return (header_output, decoder_output, decode_block, exec_output) + from micro_asm import Combinational_Macroop, Rom_Macroop + class X86Macroop(Combinational_Macroop): + def setAdjustEnv(self, val): + self.adjust_env = val + def __init__(self, name): + super(X86Macroop, self).__init__(name) + self.directives = { + "adjust_env" : self.setAdjustEnv + } + self.declared = False + self.adjust_env = "" + def getAllocator(self, env): + return "new X86Macroop::%s(machInst, %s)" % (self.name, env.getAllocator()) + def getDeclaration(self): + #FIXME This first parameter should be the mnemonic. I need to + #write some code which pulls that out + iop = InstObjParams(self.name, self.name, "Macroop", {"code" : ""}) + return MacroDeclare.subst(iop); + def getDefinition(self): + #FIXME This first parameter should be the mnemonic. I need to + #write some code which pulls that out + numMicroops = len(self.microops) + allocMicroops = '' + micropc = 0 + for op in self.microops: + allocMicroops += \ + "microops[%d] = %s;\n" % \ + (micropc, op.getAllocator(True, False, + micropc == 0, + micropc == numMicroops - 1)) + micropc += 1 + iop = InstObjParams(self.name, self.name, "Macroop", + {"code" : "", "num_microops" : numMicroops, + "alloc_microops" : allocMicroops, + "adjust_env" : self.adjust_env}) + return MacroConstructor.subst(iop); +}}; + +output header {{ + struct EmulEnv + { + X86ISA::RegIndex reg; + X86ISA::RegIndex regm; + uint64_t immediate; + uint64_t displacement; + int addressSize; + int dataSize; + + EmulEnv(X86ISA::RegIndex _reg, X86ISA::RegIndex _regm, + uint64_t _immediate, uint64_t _displacement, + int _addressSize, int _dataSize) : + reg(_reg), regm(_regm), + immediate(_immediate), displacement(_displacement), + addressSize(_addressSize), dataSize(_dataSize) + {;} + }; +}}; + +let {{ + class EmulEnv(object): + def __init__(self): + self.reg = "0" + self.regUsed = False + self.regm = "0" + self.regmUsed = False + self.immediate = "IMMEDIATE" + self.displacement = "DISPLACEMENT" + self.addressSize = "ADDRSIZE" + self.dataSize = "OPSIZE" + def getAllocator(self): + return '''EmulEnv(%(reg)s, + %(regm)s, + %(immediate)s, + %(displacement)s, + %(addressSize)s, + %(dataSize)s)''' % \ + self.__dict__ + def addReg(self, reg): + if not self.regUsed: + self.reg = reg + self.regUsed = True + elif not self.regmUsed: + self.regm = reg + self.regmUsed = True + else: + raise Exception, "EmulEnv is out of register specialization spots." +}}; + +let {{ + def genMacroop(Name, env): + blocks = OutputBlocks() + if not macroopDict.has_key(Name): + raise Exception, "Unrecognized instruction: %s" % Name + macroop = macroopDict[Name] + if not macroop.declared: + blocks.header_output = macroop.getDeclaration() + blocks.decoder_output = macroop.getDefinition() + macroop.declared = True + blocks.decode_block = "return %s;\n" % macroop.getAllocator(env) + return blocks }}; diff --git a/src/arch/x86/isa/main.isa b/src/arch/x86/isa/main.isa index 063d7125d..fed8903c0 100644 --- a/src/arch/x86/isa/main.isa +++ b/src/arch/x86/isa/main.isa @@ -67,60 +67,32 @@ //////////////////////////////////////////////////////////////////// // // Namespace statement. Everything below this line will be in the -// SparcISAInst namespace. +// X86ISAInst namespace. // namespace X86ISA; -//////////////////////////////////////////////////////////////////// -// -// General infrastructure code. These files provide infrastructure -// which was developed to support x86 but isn't specific to it. -// - -//Include code to build macroops. -##include "macroop.isa" - -//Include the simple microcode assembler. This will hopefully stay -//unspecialized for x86 and can later be made available to other ISAs. -##include "microasm.isa" +//Include the operand_types and operand definitions. These are needed by +//the microop definitions. +##include "operands.isa" -//////////////////////////////////////////////////////////////////// -// -// X86 only infrastructure code. -// +//Include the bitfield definitions +##include "bitfields.isa" //Include the base class for x86 instructions, and some support code. ##include "base.isa" -//Include code to specialize an instruction template to operate on -//a particular set of operands. This is specific to x86 and the x86 -//microcode ISA. -##include "specialize.isa" - -//////////////////////////////////////////////////////////////////// -// -// Code which directly specifies isa components like instructions -// microops, and the decoder. -// - //Include the definitions for the instruction formats ##include "formats/formats.isa" -//Include the operand_types and operand definitions. These are needed by -//the microop definitions. -##include "operands.isa" - -//Include the definitions of the micro ops. -//These are StaticInst classes which stand on their own and make up an -//internal instruction set. -##include "microops/microops.isa" - -//Include the instruction definitions which are microop assembler programs. -##include "insts/insts.isa" +//This file brings in the microcode, microop classes, macroop classes, +//and supporting components and assembles everything into macroops. +##include "microasm.isa" -//Include the bitfield definitions -##include "bitfields.isa" +//Include code to specialize an instruction template to operate on +//a particular set of operands. This is specific to x86 and the x86 +//microcode ISA. +##include "specialize.isa" //Include the decoder definition ##include "decoder/decoder.isa" diff --git a/src/arch/x86/isa/microasm.isa b/src/arch/x86/isa/microasm.isa index 9d21b6bcc..fde430691 100644 --- a/src/arch/x86/isa/microasm.isa +++ b/src/arch/x86/isa/microasm.isa @@ -55,177 +55,22 @@ // // Authors: Gabe Black -//////////////////////////////////////////////////////////////////// -// -// The microcode assembler -// +//Include the definitions of the micro ops. +//These are StaticInst classes which stand on their own and make up an +//internal instruction set, and also python representations which are passed +//into the microcode assembler. +##include "microops/microops.isa" -let {{ - # These are used when setting up microops so that they can specialize their - # base class template properly. - RegOpType = "RegisterOperand" - ImmOpType = "ImmediateOperand" -}}; +//Include code to build macroops in both C++ and python. +##include "macroop.isa" let {{ - class MicroOpStatement(object): - def __init__(self): - self.className = '' - self.label = '' - self.args = [] - - # This converts a list of python bools into - # a comma seperated list of C++ bools. - def microFlagsText(self, vals): - text = "" - for val in vals: - if val: - text += ", true" - else: - text += ", false" - return text - - def getAllocator(self, mnemonic, *microFlags): - args = '' - signature = "<" - emptySig = True - for arg in self.args: - if not emptySig: - signature += ", " - emptySig = False - if arg.has_key("operandImm"): - args += ", %s" % arg["operandImm"] - signature += ImmOpType - elif arg.has_key("operandReg"): - args += ", %s" % arg["operandReg"] - signature += RegOpType - elif arg.has_key("operandLabel"): - raise Exception, "Found a label while creating allocator string." - else: - raise Exception, "Unrecognized operand type." - signature += ">" - return 'new %s%s(machInst, %s%s%s)' % (self.className, signature, mnemonic, self.microFlagsText(microFlags), args) -}}; - -let{{ - def assembleMicro(name, Name, code): - - # This function takes in a block of microcode assembly and returns - # a python list of objects which describe it. - - # Keep this around in case we need it later - orig_code = code - # A list of the statements we've found thus far - statements = [] - - # Regular expressions to pull each piece of the statement out at a - # time. Each expression expects the thing it's looking for to be at - # the beginning of the line, so the previous component is stripped - # before continuing. - labelRe = re.compile(r'^[ \t]*(?P<label>\w\w*)[ \t]:') - lineRe = re.compile(r'^(?P<line>..*)(\n|$)') - classRe = re.compile(r'^[ \t]*(?P<className>[a-zA-Z_]\w*)') - # This recognizes three different flavors of operands: - # 1. Raw decimal numbers composed of digits between 0 and 9 - # 2. Code beginning with "{" and continuing until the first "}" - # ^ This one might need revising - # 3. A label, which starts with a capital or small letter, or - # underscore, which is optionally followed by a sequence of - # capital or small letters, underscores, or digts between 0 and 9 - opRe = re.compile( \ - r'^[ \t]*((\@(?P<operandLabel0>\w\w*))|' + - r'(\@\{(?P<operandLabel1>[^}]*)\})|' + - r'(\%(?P<operandReg0>\w\w*))|' + - r'(\%\{(?P<operandReg1>[^}]*)\})|' + - r'(\$(?P<operandImm0>\w\w*))|' + - r'(\$\{(?P<operandImm1>[^}]*)\}))') - lineMatch = lineRe.search(code) - while lineMatch != None: - statement = MicroOpStatement() - # Get a line and seperate it from the rest of the code - line = lineMatch.group("line") - orig_line = line - #print "Parsing line %s" % line - code = lineRe.sub('', code, 1) - - # Find the label, if any - labelMatch = labelRe.search(line) - if labelMatch != None: - statement.label = labelMatch.group("label") - #print "Found label %s." % statement.label - # Clear the label from the statement - line = labelRe.sub('', line, 1) - - # Find the class name which is roughly equivalent to the op name - classMatch = classRe.search(line) - if classMatch == None: - raise Exception, "Couldn't find class name in statement: %s" \ - % orig_line - else: - statement.className = classMatch.group("className") - #print "Found class name %s." % statement.className - - # Clear the class name from the statement - line = classRe.sub('', line, 1) - - #Find as many arguments as you can - statement.args = [] - opMatch = opRe.search(line) - while opMatch is not None: - statement.args.append({}) - # args is a list of dicts which collect different - # representations of operand values. Different forms might be - # needed in different places, for instance to replace a label - # with an offset. - for opType in ("operandLabel0", "operandReg0", "operandImm0", - "operandLabel1", "operandReg1", "operandImm1"): - if opMatch.group(opType): - statement.args[-1][opType[:-1]] = opMatch.group(opType) - if len(statement.args[-1]) == 0: - print "Problem parsing operand in statement: %s" \ - % orig_line - line = opRe.sub('', line, 1) - #print "Found operand %s." % statement.args[-1] - opMatch = opRe.search(line) - #print "Found operands", statement.args - - # Add this statement to our collection - statements.append(statement) - - # Get the next line - lineMatch = lineRe.search(code) - - # Decode the labels into displacements - - labels = {} - micropc = 0 - for statement in statements: - if statement.label: - labels[statement.label] = count - micropc += 1 - micropc = 0 - for statement in statements: - for arg in statement.args: - if arg.has_key("operandLabel"): - if not labels.has_key(arg["operandLabel"]): - raise Exception, "Unrecognized label: %s." % arg["operandLabel"] - # This is assuming that intra microcode branches go to - # the next micropc + displacement, or - # micropc + 1 + displacement. - arg["operandImm"] = labels[arg["operandLabel"]] - micropc - 1 - micropc += 1 - - if len(statements) == 0: - raise Exception, "Didn't find any microops in microcode: \n%s" % orig_code - - # If we can implement this instruction with exactly one microop, just - # use that directly. - if len(statements) == 1: - decode_block = "return %s;" % \ - statements[0].getAllocator('"' + name + '"') - return ('', '', decode_block, '') - else: - # Build a macroop to contain the sequence of microops we've - # been given. - return genMacroOp(name, Name, statements) + import sys + sys.path[0:0] = ["src/arch/x86/isa/"] + from insts import microcode + print microcode + from micro_asm import MicroAssembler, Rom_Macroop, Rom + mainRom = Rom('main ROM') + assembler = MicroAssembler(X86Macroop, microopClasses, mainRom, Rom_Macroop) + macroopDict = assembler.assemble(microcode) }}; diff --git a/src/arch/x86/isa/microops/base.isa b/src/arch/x86/isa/microops/base.isa index f0aab7872..79ac4493a 100644 --- a/src/arch/x86/isa/microops/base.isa +++ b/src/arch/x86/isa/microops/base.isa @@ -55,25 +55,23 @@ // // Authors: Gabe Black -//The operand types a microop template can be specialized with -output header {{ - enum OperandType { - RegisterOperand, - ImmediateOperand - }; +let {{ + # This will be populated with mappings between microop mnemonics and + # the classes that represent them. + microopClasses = {} }}; //A class which is the base of all x86 micro ops. It provides a function to //set necessary flags appropriately. output header {{ - class X86MicroOpBase : public X86StaticInst + class X86MicroopBase : public X86StaticInst { protected: const char * instMnem; uint8_t opSize; uint8_t addrSize; - X86MicroOpBase(ExtMachInst _machInst, + X86MicroopBase(ExtMachInst _machInst, const char *mnem, const char *_instMnem, bool isMicro, bool isDelayed, bool isFirst, bool isLast, @@ -81,10 +79,10 @@ output header {{ X86StaticInst(mnem, _machInst, __opClass), instMnem(_instMnem) { - flags[IsMicroOp] = isMicro; + flags[IsMicroop] = isMicro; flags[IsDelayedCommit] = isDelayed; - flags[IsFirstMicroOp] = isFirst; - flags[IsLastMicroOp] = isLast; + flags[IsFirstMicroop] = isFirst; + flags[IsLastMicroop] = isLast; } std::string generateDisassembly(Addr pc, @@ -99,96 +97,40 @@ output header {{ }; }}; -// This sets up a class which is templated on the type of -// arguments a particular flavor of a microcode instruction -// can accept. It's parameters are specialized to create polymorphic -// behavior in microops. -def template BaseMicroOpTemplateDeclare {{ - template%(signature)s - class %(class_name)s; -}}; - -let {{ - def buildBaseMicroOpTemplate(Name, numParams): - assert(numParams > 0) - signature = "<" - signature += "int SignatureOperandTypeSpecifier0" - for count in xrange(1,numParams): - signature += \ - ", int SingatureOperandTypeSpecifier%d" % count - signature += ">" - subs = {"signature" : signature, "class_name" : Name} - return BaseMicroOpTemplateDeclare.subst(subs) -}}; +////////////////////////////////////////////////////////////////////////// +// +// Base class for the python representation of x86 microops +// +////////////////////////////////////////////////////////////////////////// let {{ - def buildMicroOpTemplateDict(*params): - signature = "<" - if len(params): - signature += params[0] - if len(params) > 1: - for param in params[1:]: - signature += ", %s" % param - signature += ">" - subs = {"param_dec" : "", "param_arg_dec" : "", - "param_init" : "", "signature" : signature} - for count in xrange(len(params)): - subs["param_dec"] += "uint64_t param%d;\n" % count - subs["param_arg_dec"] += ", uint64_t _param%d" % count - subs["param_init"] += ", param%d(_param%d)" % (count, count) - return subs -}}; - -// A tmeplate for building a specialized version of the microcode -// instruction which specifies which arguments it wants -def template MicroOpDeclare {{ - template<> - class %(class_name)s%(signature)s : public X86MicroOpBase - { - protected: - %(param_dec)s - void buildMe(); - - public: - %(class_name)s(ExtMachInst _machInst, - const char * instMnem, - bool isMicro, bool isDelayed, - bool isFirst, bool isLast - %(param_arg_dec)s); - - %(class_name)s(ExtMachInst _machInst, - const char * instMnem - %(param_arg_dec)s); - - %(BasicExecDeclare)s - }; + class X86Microop(object): + def __init__(self, name): + self.name = name + + # This converts a python bool into a C++ bool + def cppBool(self, val): + if val: + return "true" + else: + return "false" + + # This converts a list of python bools into + # a comma seperated list of C++ bools. + def microFlagsText(self, vals): + text = "" + for val in vals: + text += ", %s" % self.cppBool(val) + return text + + def getAllocator(self, mnemonic, *microFlags): + return 'new %s(machInst, %s)' % (self.className, mnemonic, self.microFlagsText(microFlags)) }}; -def template MicroOpConstructor {{ - - inline void %(class_name)s%(signature)s::buildMe() - { - %(constructor)s; - } - - inline %(class_name)s%(signature)s::%(class_name)s( - ExtMachInst machInst, const char * instMnem - %(param_arg_dec)s) : - %(base_class)s(machInst, "%(mnemonic)s", instMnem, - false, false, false, false, %(op_class)s) - %(param_init)s - { - buildMe(); - } +////////////////////////////////////////////////////////////////////////// +// +// FpOp Microop templates +// +////////////////////////////////////////////////////////////////////////// - inline %(class_name)s%(signature)s::%(class_name)s( - ExtMachInst machInst, const char * instMnem, - bool isMicro, bool isDelayed, bool isFirst, bool isLast - %(param_arg_dec)s) - : %(base_class)s(machInst, "%(mnemonic)s", instMnem, - isMicro, isDelayed, isFirst, isLast, %(op_class)s) - %(param_init)s - { - buildMe(); - } -}}; +//TODO Actually write an fp microop base class. diff --git a/src/arch/x86/isa/microops/ldstop.isa b/src/arch/x86/isa/microops/ldstop.isa new file mode 100644 index 000000000..7e164fa82 --- /dev/null +++ b/src/arch/x86/isa/microops/ldstop.isa @@ -0,0 +1,136 @@ +// Copyright (c) 2007 The Hewlett-Packard Development Company +// All rights reserved. +// +// Redistribution and use of this software in source and binary forms, +// with or without modification, are permitted provided that the +// following conditions are met: +// +// The software must be used only for Non-Commercial Use which means any +// use which is NOT directed to receiving any direct monetary +// compensation for, or commercial advantage from such use. Illustrative +// examples of non-commercial use are academic research, personal study, +// teaching, education and corporate research & development. +// Illustrative examples of commercial use are distributing products for +// commercial advantage and providing services using the software for +// commercial advantage. +// +// If you wish to use this software or functionality therein that may be +// covered by patents for commercial use, please contact: +// Director of Intellectual Property Licensing +// Office of Strategy and Technology +// Hewlett-Packard Company +// 1501 Page Mill Road +// Palo Alto, California 94304 +// +// Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. Redistributions +// in binary form must reproduce the above copyright notice, this list of +// conditions and the following disclaimer in the documentation and/or +// other materials provided with the distribution. Neither the name of +// the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. No right of +// sublicense is granted herewith. Derivatives of the software and +// output created using the software may be prepared, but only for +// Non-Commercial Uses. Derivatives of the software may be shared with +// others provided: (i) the others agree to abide by the list of +// conditions herein which includes the Non-Commercial Use restrictions; +// and (ii) such Derivatives of the software include the above copyright +// notice to acknowledge the contribution from this software where +// applicable, this list of conditions and the disclaimer below. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// Authors: Gabe Black + +////////////////////////////////////////////////////////////////////////// +// +// LdStOp Microop templates +// +////////////////////////////////////////////////////////////////////////// + +def template MicroLdStOpDeclare {{ + class %(class_name)s : public X86MicroopBase + { + protected: + const uint8_t scale; + const RegIndex index; + const RegIndex base; + const uint64_t disp; + const uint8_t segment; + const RegIndex data; + const uint8_t dataSize; + const uint8_t addressSize; + void buildMe(); + + public: + %(class_name)s(ExtMachInst _machInst, + const char * instMnem, + bool isMicro, bool isDelayed, bool isFirst, bool isLast, + uint8_t _scale, RegIndex _index, RegIndex _base, + uint64_t _disp, uint8_t _segment, + RegIndex _data, + uint8_t _dataSize, uint8_t _addressSize); + + %(class_name)s(ExtMachInst _machInst, + const char * instMnem, + uint8_t _scale, RegIndex _index, RegIndex _base, + uint64_t _disp, uint8_t _segment, + RegIndex _data, + uint8_t _dataSize, uint8_t _addressSize); + + %(BasicExecDeclare)s + }; +}}; + +def template MicroLdStOpConstructor {{ + + inline void %(class_name)s::buildMe() + { + %(constructor)s; + } + + inline %(class_name)s::%(class_name)s( + ExtMachInst machInst, const char * instMnem, + uint8_t _scale, RegIndex _index, RegIndex _base, + uint64_t _disp, uint8_t _segment, + RegIndex _data, + uint8_t _dataSize, uint8_t _addressSize) : + %(base_class)s(machInst, "%(mnemonic)s", instMnem, + false, false, false, false, %(op_class)s), + scale(_scale), index(_index), base(_base), + disp(_disp), segment(_segment), + data(_data), + dataSize(_dataSize), addressSize(_addressSize) + { + buildMe(); + } + + inline %(class_name)s::%(class_name)s( + ExtMachInst machInst, const char * instMnem, + bool isMicro, bool isDelayed, bool isFirst, bool isLast, + uint8_t _scale, RegIndex _index, RegIndex _base, + uint64_t _disp, uint8_t segment, + RegIndex data, + uint8_t dataSize, uint8_t addressSize) : + %(base_class)s(machInst, "%(mnemonic)s", instMnem, + isMicro, isDelayed, isFirst, isLast, %(op_class)s), + scale(_scale), index(_index), base(_base), + disp(_disp), segment(_segment), + data(_data), + dataSize(_dataSize), addressSize(_addressSize) + { + buildMe(); + } +}}; + diff --git a/src/arch/x86/isa/microops/limmop.isa b/src/arch/x86/isa/microops/limmop.isa new file mode 100644 index 000000000..c76c074b1 --- /dev/null +++ b/src/arch/x86/isa/microops/limmop.isa @@ -0,0 +1,152 @@ +// Copyright (c) 2007 The Hewlett-Packard Development Company +// All rights reserved. +// +// Redistribution and use of this software in source and binary forms, +// with or without modification, are permitted provided that the +// following conditions are met: +// +// The software must be used only for Non-Commercial Use which means any +// use which is NOT directed to receiving any direct monetary +// compensation for, or commercial advantage from such use. Illustrative +// examples of non-commercial use are academic research, personal study, +// teaching, education and corporate research & development. +// Illustrative examples of commercial use are distributing products for +// commercial advantage and providing services using the software for +// commercial advantage. +// +// If you wish to use this software or functionality therein that may be +// covered by patents for commercial use, please contact: +// Director of Intellectual Property Licensing +// Office of Strategy and Technology +// Hewlett-Packard Company +// 1501 Page Mill Road +// Palo Alto, California 94304 +// +// Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. Redistributions +// in binary form must reproduce the above copyright notice, this list of +// conditions and the following disclaimer in the documentation and/or +// other materials provided with the distribution. Neither the name of +// the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. No right of +// sublicense is granted herewith. Derivatives of the software and +// output created using the software may be prepared, but only for +// Non-Commercial Uses. Derivatives of the software may be shared with +// others provided: (i) the others agree to abide by the list of +// conditions herein which includes the Non-Commercial Use restrictions; +// and (ii) such Derivatives of the software include the above copyright +// notice to acknowledge the contribution from this software where +// applicable, this list of conditions and the disclaimer below. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// Authors: Gabe Black + +////////////////////////////////////////////////////////////////////////// +// +// LIMMOp Microop templates +// +////////////////////////////////////////////////////////////////////////// + +def template MicroLimmOpExecute {{ + Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, + Trace::InstRecord *traceData) const + { + %(op_decl)s; + %(op_rd)s; + %(code)s; + %(op_wb)s; + return NoFault; + } +}}; + +def template MicroLimmOpDeclare {{ + class %(class_name)s : public X86MicroopBase + { + protected: + const RegIndex dest; + const uint64_t imm; + void buildMe(); + + public: + %(class_name)s(ExtMachInst _machInst, + const char * instMnem, + bool isMicro, bool isDelayed, bool isFirst, bool isLast, + RegIndex _dest, uint64_t _imm); + + %(class_name)s(ExtMachInst _machInst, + const char * instMnem, + RegIndex _dest, uint64_t _imm); + + %(BasicExecDeclare)s + }; +}}; + +def template MicroLimmOpConstructor {{ + + inline void %(class_name)s::buildMe() + { + %(constructor)s; + } + + inline %(class_name)s::%(class_name)s( + ExtMachInst machInst, const char * instMnem, + RegIndex _dest, uint64_t _imm) : + %(base_class)s(machInst, "%(mnemonic)s", instMnem, + false, false, false, false, %(op_class)s), + dest(_dest), imm(_imm) + { + buildMe(); + } + + inline %(class_name)s::%(class_name)s( + ExtMachInst machInst, const char * instMnem, + bool isMicro, bool isDelayed, bool isFirst, bool isLast, + RegIndex _dest, uint64_t _imm) : + %(base_class)s(machInst, "%(mnemonic)s", instMnem, + isMicro, isDelayed, isFirst, isLast, %(op_class)s), + dest(_dest), imm(_imm) + { + buildMe(); + } +}}; + +let {{ + class LimmOp(X86Microop): + def __init__(self, dest, imm): + self.className = "Limm" + self.mnemonic = "limm" + self.dest = dest + self.imm = imm + + def getAllocator(self, *microFlags): + allocator = '''new %(class_name)s(machInst, mnemonic + %(flags)s, %(dest)s, %(imm)s)''' % { + "class_name" : self.className, + "mnemonic" : self.mnemonic, + "flags" : self.microFlagsText(microFlags), + "dest" : self.dest, "imm" : self.imm } + return allocator + + microopClasses["limm"] = LimmOp +}}; + +let {{ + # Build up the all register version of this micro op + iop = InstObjParams("limm", "Limm", 'X86MicroopBase', + {"code" : "DestReg = imm;"}) + header_output += MicroLimmOpDeclare.subst(iop) + decoder_output += MicroLimmOpConstructor.subst(iop) + exec_output += MicroLimmOpExecute.subst(iop) +}}; diff --git a/src/arch/x86/isa/microops/microops.isa b/src/arch/x86/isa/microops/microops.isa index d877152eb..50c9ac498 100644 --- a/src/arch/x86/isa/microops/microops.isa +++ b/src/arch/x86/isa/microops/microops.isa @@ -56,8 +56,14 @@ //Common microop stuff ##include "base.isa" -//A microop that generates a specified fault -##include "fault.isa" +//Register microop definitions +##include "regop.isa" -//Integer microop definitions -##include "int.isa" +//Load immediate microop definition +##include "limmop.isa" + +//Load/store microop definitions +##include "ldstop.isa" + +//Miscellaneous microop definitions +##include "specop.isa" diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa new file mode 100644 index 000000000..a99194c5e --- /dev/null +++ b/src/arch/x86/isa/microops/regop.isa @@ -0,0 +1,331 @@ +// Copyright (c) 2007 The Hewlett-Packard Development Company +// All rights reserved. +// +// Redistribution and use of this software in source and binary forms, +// with or without modification, are permitted provided that the +// following conditions are met: +// +// The software must be used only for Non-Commercial Use which means any +// use which is NOT directed to receiving any direct monetary +// compensation for, or commercial advantage from such use. Illustrative +// examples of non-commercial use are academic research, personal study, +// teaching, education and corporate research & development. +// Illustrative examples of commercial use are distributing products for +// commercial advantage and providing services using the software for +// commercial advantage. +// +// If you wish to use this software or functionality therein that may be +// covered by patents for commercial use, please contact: +// Director of Intellectual Property Licensing +// Office of Strategy and Technology +// Hewlett-Packard Company +// 1501 Page Mill Road +// Palo Alto, California 94304 +// +// Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. Redistributions +// in binary form must reproduce the above copyright notice, this list of +// conditions and the following disclaimer in the documentation and/or +// other materials provided with the distribution. Neither the name of +// the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. No right of +// sublicense is granted herewith. Derivatives of the software and +// output created using the software may be prepared, but only for +// Non-Commercial Uses. Derivatives of the software may be shared with +// others provided: (i) the others agree to abide by the list of +// conditions herein which includes the Non-Commercial Use restrictions; +// and (ii) such Derivatives of the software include the above copyright +// notice to acknowledge the contribution from this software where +// applicable, this list of conditions and the disclaimer below. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// Authors: Gabe Black + +////////////////////////////////////////////////////////////////////////// +// +// RegOp Microop templates +// +////////////////////////////////////////////////////////////////////////// + +def template MicroRegOpExecute {{ + Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, + Trace::InstRecord *traceData) const + { + Fault fault = NoFault; + + %(op_decl)s; + %(op_rd)s; + %(code)s; + + //Write the resulting state to the execution context + if(fault == NoFault) + { + %(op_wb)s; + } + return fault; + } +}}; + +def template MicroRegOpImmExecute {{ + Fault %(class_name)sImm::execute(%(CPU_exec_context)s *xc, + Trace::InstRecord *traceData) const + { + Fault fault = NoFault; + + %(op_decl)s; + %(op_rd)s; + %(code)s; + + //Write the resulting state to the execution context + if(fault == NoFault) + { + %(op_wb)s; + } + return fault; + } +}}; + +def template MicroRegOpDeclare {{ + class %(class_name)s : public %(base_class)s + { + protected: + const RegIndex src1; + const RegIndex src2; + const RegIndex dest; + const bool setStatus; + const uint8_t dataSize; + const uint8_t ext; + void buildMe(); + + public: + %(class_name)s(ExtMachInst _machInst, + const char * instMnem, + bool isMicro, bool isDelayed, bool isFirst, bool isLast, + RegIndex _src1, RegIndex _src2, RegIndex _dest, + bool _setStatus, uint8_t _dataSize, uint8_t _ext); + + %(class_name)s(ExtMachInst _machInst, + const char * instMnem, + RegIndex _src1, RegIndex _src2, RegIndex _dest, + bool _setStatus, uint8_t _dataSize, uint8_t _ext); + + %(BasicExecDeclare)s + }; +}}; + +def template MicroRegOpImmDeclare {{ + + class %(class_name)sImm : public %(base_class)s + { + protected: + const RegIndex src1; + const uint8_t imm8; + const RegIndex dest; + const bool setStatus; + const uint8_t dataSize; + const uint8_t ext; + void buildMe(); + + public: + %(class_name)sImm(ExtMachInst _machInst, + const char * instMnem, + bool isMicro, bool isDelayed, bool isFirst, bool isLast, + RegIndex _src1, uint8_t _imm8, RegIndex _dest, + bool _setStatus, uint8_t _dataSize, uint8_t _ext); + + %(class_name)sImm(ExtMachInst _machInst, + const char * instMnem, + RegIndex _src1, uint8_t _imm8, RegIndex _dest, + bool _setStatus, uint8_t _dataSize, uint8_t _ext); + + %(BasicExecDeclare)s + }; +}}; + +def template MicroRegOpConstructor {{ + + inline void %(class_name)s::buildMe() + { + %(constructor)s; + } + + inline %(class_name)s::%(class_name)s( + ExtMachInst machInst, const char * instMnem, + RegIndex _src1, RegIndex _src2, RegIndex _dest, + bool _setStatus, uint8_t _dataSize, uint8_t _ext) : + %(base_class)s(machInst, "%(mnemonic)s", instMnem, + false, false, false, false, %(op_class)s), + src1(_src1), src2(_src2), dest(_dest), + setStatus(_setStatus), dataSize(_dataSize), ext(_ext) + { + buildMe(); + } + + inline %(class_name)s::%(class_name)s( + ExtMachInst machInst, const char * instMnem, + bool isMicro, bool isDelayed, bool isFirst, bool isLast, + RegIndex _src1, RegIndex _src2, RegIndex _dest, + bool _setStatus, uint8_t _dataSize, uint8_t _ext) : + %(base_class)s(machInst, "%(mnemonic)s", instMnem, + isMicro, isDelayed, isFirst, isLast, %(op_class)s), + src1(_src1), src2(_src2), dest(_dest), + setStatus(_setStatus), dataSize(_dataSize), ext(_ext) + { + buildMe(); + } +}}; + +def template MicroRegOpImmConstructor {{ + + inline void %(class_name)sImm::buildMe() + { + %(constructor)s; + } + + inline %(class_name)sImm::%(class_name)sImm( + ExtMachInst machInst, const char * instMnem, + RegIndex _src1, uint8_t _imm8, RegIndex _dest, + bool _setStatus, uint8_t _dataSize, uint8_t _ext) : + %(base_class)s(machInst, "%(mnemonic)s", instMnem, + false, false, false, false, %(op_class)s), + src1(_src1), imm8(_imm8), dest(_dest), + setStatus(_setStatus), dataSize(_dataSize), ext(_ext) + { + buildMe(); + } + + inline %(class_name)sImm::%(class_name)sImm( + ExtMachInst machInst, const char * instMnem, + bool isMicro, bool isDelayed, bool isFirst, bool isLast, + RegIndex _src1, uint8_t _imm8, RegIndex _dest, + bool _setStatus, uint8_t _dataSize, uint8_t _ext) : + %(base_class)s(machInst, "%(mnemonic)s", instMnem, + isMicro, isDelayed, isFirst, isLast, %(op_class)s), + src1(_src1), imm8(_imm8), dest(_dest), + setStatus(_setStatus), dataSize(_dataSize), ext(_ext) + { + buildMe(); + } +}}; + +let {{ + class RegOp(X86Microop): + def __init__(self, dest, src1, src2): + self.dest = dest + self.src1 = src1 + self.src2 = src2 + self.setStatus = False + self.dataSize = 1 + self.ext = 0 + + def getAllocator(self, *microFlags): + allocator = '''new %(class_name)s(machInst, mnemonic + %(flags)s, %(src1)s, %(src2)s, %(dest)s, + %(setStatus)s, %(dataSize)s, %(ext)s)''' % { + "class_name" : self.className, + "flags" : self.microFlagsText(microFlags), + "src1" : self.src1, "src2" : self.src2, + "dest" : self.dest, + "setStatus" : self.cppBool(self.setStatus), + "dataSize" : self.dataSize, + "ext" : self.ext} + return allocator + + class RegOpImm(X86Microop): + def __init__(self, dest, src1, imm8): + self.dest = dest + self.src1 = src1 + self.imm8 = imm8 + self.setStatus = False + self.dataSize = 1 + self.ext = 0 + + def getAllocator(self, *microFlags): + allocator = '''new %(class_name)s(machInst, mnemonic + %(flags)s, %(src1)s, %(imm8)s, %(dest)s, + %(setStatus)s, %(dataSize)s, %(ext)s)''' % { + "class_name" : self.className, + "flags" : self.microFlagsText(microFlags), + "src1" : self.src1, "imm8" : self.imm8, + "dest" : self.dest, + "setStatus" : self.cppBool(self.setStatus), + "dataSize" : self.dataSize, + "ext" : self.ext} + return allocator +}}; + +let {{ + + # Make these empty strings so that concatenating onto + # them will always work. + header_output = "" + decoder_output = "" + exec_output = "" + + def defineMicroRegOp(mnemonic, code): + global header_output + global decoder_output + global exec_output + global microopClasses + Name = mnemonic + name = mnemonic.lower() + + # Find op2 in each of the instruction definitions. Create two versions + # of the code, one with an integer operand, and one with an immediate + # operand. + matcher = re.compile("op2(?P<typeQual>\\.\\w+)?") + regCode = matcher.sub("SrcReg2", code) + immCode = matcher.sub("imm8", code) + + # Build up the all register version of this micro op + iop = InstObjParams(name, Name, 'X86MicroopBase', {"code" : regCode}) + header_output += MicroRegOpDeclare.subst(iop) + decoder_output += MicroRegOpConstructor.subst(iop) + exec_output += MicroRegOpExecute.subst(iop) + + class RegOpChild(RegOp): + def __init__(self, dest, src1, src2): + super(RegOpChild, self).__init__(dest, src1, src2) + self.className = Name + self.mnemonic = name + + microopClasses[name] = RegOpChild + + # Build up the immediate version of this micro op + iop = InstObjParams(name + "i", Name, + 'X86MicroopBase', {"code" : immCode}) + header_output += MicroRegOpImmDeclare.subst(iop) + decoder_output += MicroRegOpImmConstructor.subst(iop) + exec_output += MicroRegOpImmExecute.subst(iop) + + class RegOpImmChild(RegOpImm): + def __init__(self, dest, src1, imm): + super(RegOpImmChild, self).__init__(dest, src1, imm) + self.className = Name + "Imm" + self.mnemonic = name + "i" + + microopClasses[name + "i"] = RegOpImmChild + + defineMicroRegOp('Add', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)') #Needs to set OF,CF,SF + defineMicroRegOp('Or', 'DestReg = merge(DestReg, SrcReg1 | op2, dataSize)') + defineMicroRegOp('Adc', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)') #Needs to add in CF, set OF,CF,SF + defineMicroRegOp('Sbb', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)') #Needs to subtract CF, set OF,CF,SF + defineMicroRegOp('And', 'DestReg = merge(DestReg, SrcReg1 & op2, dataSize)') + defineMicroRegOp('Sub', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)') #Needs to set OF,CF,SF + defineMicroRegOp('Xor', 'DestReg = merge(DestReg, SrcReg1 ^ op2, dataSize)') + defineMicroRegOp('Cmp', 'DestReg = merge(DestReg, DestReg - op2, dataSize)') #Needs to set OF,CF,SF and not DestReg + defineMicroRegOp('Mov', 'DestReg = merge(SrcReg1, op2, dataSize)') + +}}; diff --git a/src/arch/x86/isa/microops/specop.isa b/src/arch/x86/isa/microops/specop.isa new file mode 100644 index 000000000..96fdf1c5e --- /dev/null +++ b/src/arch/x86/isa/microops/specop.isa @@ -0,0 +1,125 @@ +// Copyright (c) 2007 The Hewlett-Packard Development Company +// All rights reserved. +// +// Redistribution and use of this software in source and binary forms, +// with or without modification, are permitted provided that the +// following conditions are met: +// +// The software must be used only for Non-Commercial Use which means any +// use which is NOT directed to receiving any direct monetary +// compensation for, or commercial advantage from such use. Illustrative +// examples of non-commercial use are academic research, personal study, +// teaching, education and corporate research & development. +// Illustrative examples of commercial use are distributing products for +// commercial advantage and providing services using the software for +// commercial advantage. +// +// If you wish to use this software or functionality therein that may be +// covered by patents for commercial use, please contact: +// Director of Intellectual Property Licensing +// Office of Strategy and Technology +// Hewlett-Packard Company +// 1501 Page Mill Road +// Palo Alto, California 94304 +// +// Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. Redistributions +// in binary form must reproduce the above copyright notice, this list of +// conditions and the following disclaimer in the documentation and/or +// other materials provided with the distribution. Neither the name of +// the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. No right of +// sublicense is granted herewith. Derivatives of the software and +// output created using the software may be prepared, but only for +// Non-Commercial Uses. Derivatives of the software may be shared with +// others provided: (i) the others agree to abide by the list of +// conditions herein which includes the Non-Commercial Use restrictions; +// and (ii) such Derivatives of the software include the above copyright +// notice to acknowledge the contribution from this software where +// applicable, this list of conditions and the disclaimer below. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// Authors: Gabe Black + +////////////////////////////////////////////////////////////////////////// +// +// Fault Microop +// +////////////////////////////////////////////////////////////////////////// + +def template MicroFaultExecute {{ + Fault %(class_name)s ::execute(%(CPU_exec_context)s *xc, + Trace::InstRecord *traceData) const + { + //Return the fault we were constructed with + return fault; + } +}}; + +def template MicroFaultDeclare {{ + class %(class_name)s : public X86MicroopBase + { + protected: + Fault fault; + void buildMe(); + + public: + %(class_name)s(ExtMachInst _machInst, + const char * instMnem, + bool isMicro, bool isDelayed, bool isFirst, bool isLast, + Fault _fault); + + %(class_name)s(ExtMachInst _machInst, + const char * instMnem, + Fault _fault); + + %(BasicExecDeclare)s + }; +}}; + +def template MicroFaultConstructor {{ + + inline void %(class_name)s::buildMe() + { + %(constructor)s; + } + + inline %(class_name)s::%(class_name)s( + ExtMachInst machInst, const char * instMnem, Fault _fault) : + %(base_class)s(machInst, "%(mnemonic)s", instMnem, + false, false, false, false, %(op_class)s), fault(_fault) + { + buildMe(); + } + + inline %(class_name)s::%(class_name)s( + ExtMachInst machInst, const char * instMnem, + bool isMicro, bool isDelayed, bool isFirst, bool isLast, + Fault _fault) : + %(base_class)s(machInst, "%(mnemonic)s", instMnem, + isMicro, isDelayed, isFirst, isLast, %(op_class)s), + fault(_fault) + { + buildMe(); + } +}}; + +let {{ + # This microop takes in a single parameter, a fault to return. + iop = InstObjParams("fault", "GenFault", 'X86MicroopBase', {"code" : ""}) + header_output += MicroFaultDeclare.subst(iop) + decoder_output += MicroFaultConstructor.subst(iop) + exec_output += MicroFaultExecute.subst(iop) +}}; diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa index af469ab3d..1564c23e9 100644 --- a/src/arch/x86/isa/operands.isa +++ b/src/arch/x86/isa/operands.isa @@ -96,6 +96,9 @@ def operand_types {{ }}; def operands {{ + 'DestReg': ('IntReg', 'uqw', 'dest', 'IsInteger', 1), + 'SrcReg1': ('IntReg', 'uqw', 'src1', 'IsInteger', 2), + 'SrcReg2': ('IntReg', 'uqw', 'src2', 'IsInteger', 3), 'IntRegOp0': ('IntReg', 'udw', 'param0', 'IsInteger', 1), 'IntRegOp1': ('IntReg', 'udw', 'param1', 'IsInteger', 2), 'IntRegOp2': ('IntReg', 'udw', 'param2', 'IsInteger', 2), diff --git a/src/arch/x86/isa/specialize.isa b/src/arch/x86/isa/specialize.isa index ff92c3551..faf863351 100644 --- a/src/arch/x86/isa/specialize.isa +++ b/src/arch/x86/isa/specialize.isa @@ -66,24 +66,26 @@ let {{ # vals is a dict which matches case values with what should be decoded to. # builder is called on the exploded contents of "vals" values to generate # whatever code should be used. - def doSplitDecode(name, Name, builder, switchVal, vals, default = None): + def doSplitDecode(builder, switchVal, vals, default = None): blocks = OutputBlocks() - blocks.decode_block += 'switch(%s) {\n' % switchVal + blocks.decode_block = 'switch(%s) {\n' % switchVal for (val, todo) in vals.items(): - built = builder(name, Name, *todo) - built.decode_block = '\tcase %s: %s\n' % (val, built.decode_block) - blocks.append(built) + new_blocks = builder(*todo) + new_blocks.decode_block = \ + '\tcase %s: %s\n' % (val, new_blocks.decode_block) + blocks.append(new_blocks) if default: - built = builder(name, Name, *default) - built.decode_block = '\tdefault: %s\n' % built.decode_block - blocks.append(built) + new_blocks = builder(*default) + new_blocks.decode_block = \ + '\tdefault: %s\n' % new_blocks.decode_block + blocks.append(new_blocks) blocks.decode_block += '}\n' return blocks }}; let {{ class OpType(object): - parser = re.compile(r"(?P<tag>[A-Z][A-Z]*)(?P<size>[a-z][a-z]*)|(r(?P<reg>[A-Za-z0-9][A-Za-z0-9]*))") + parser = re.compile(r"(?P<tag>[A-Z][A-Z]*)(?P<size>[a-z][a-z]*)|(r(?P<reg>[A-Z0-9]*)(?P<rsize>[a-z]*))") def __init__(self, opTypeString): match = OpType.parser.search(opTypeString) if match == None: @@ -91,74 +93,79 @@ let {{ self.reg = match.group("reg") self.tag = match.group("tag") self.size = match.group("size") + self.rsize = match.group("rsize") + + ModRMRegIndex = "(MODRM_REG | (REX_R << 3))" + ModRMRMIndex = "(MODRM_RM | (REX_B << 3))" # This function specializes the given piece of code to use a particular - # set of argument types described by "opTypes". These are "implemented" - # in reverse order. - def specializeInst(name, Name, code, opTypes): - opNum = len(opTypes) - 1 + # set of argument types described by "opTypes". + def specializeInst(Name, opTypes, env): + # print "Specializing %s with opTypes %s" % (Name, opTypes) while len(opTypes): - # print "Building a composite op with tags", opTypes - # print "And code", code - opNum = len(opTypes) - 1 - # A regular expression to find the operand placeholders we're - # interested in. - opRe = re.compile("\\^(?P<operandNum>%d)(?=[^0-9]|$)" % opNum) - - # Parse the operand type strign we're working with - opType = OpType(opTypes[opNum]) + # Parse the operand type string we're working with + opType = OpType(opTypes[0]) if opType.reg: #Figure out what to do with fixed register operands - if opType.reg in ("Ax", "Bx", "Cx", "Dx"): - code = opRe.sub("%%{INTREG_R%s}" % opType.reg.upper(), code) - elif opType.reg == "Al": - # We need a way to specify register width - code = opRe.sub("%{INTREG_RAX}", code) + #This is the index to use, so we should stick it some place. + if opType.reg in ("A", "B", "C", "D"): + env.addReg("INTREG_R%sX" % opType.reg) else: - print "Didn't know how to encode fixed register %s!" % opType.reg + env.addReg("INTREG_R%s" % opType.reg) + if opType.size: + if opType.rsize in ("l", "h", "b"): + print "byte" + elif opType.rsize == "x": + print "word" + else: + print "Didn't recognize fixed register size %s!" % opType.rsize + Name += "_R" elif opType.tag == None or opType.size == None: raise Exception, "Problem parsing operand tag: %s" % opType.tag elif opType.tag in ("C", "D", "G", "P", "S", "T", "V"): # Use the "reg" field of the ModRM byte to select the register - code = opRe.sub("%{(uint8_t)MODRM_REG}", code) + env.addReg(ModRMRegIndex) + Name += "_R" elif opType.tag in ("E", "Q", "W"): # This might refer to memory or to a register. We need to # divide it up farther. - regCode = opRe.sub("%{(uint8_t)MODRM_RM}", code) regTypes = copy.copy(opTypes) - regTypes.pop(-1) + regTypes.pop(0) + regEnv = copy.copy(env) + regEnv.addReg(ModRMRMIndex) + regName = Name + "_R" # This needs to refer to memory, but we'll fill in the details # later. It needs to take into account unaligned memory # addresses. - code = "GenFault ${new UnimpInstFault}\n" + code - memCode = opRe.sub("%0", code) memTypes = copy.copy(opTypes) - memTypes.pop(-1) - return doSplitDecode(name, Name, specializeInst, "MODRM_MOD", - {"3" : (regCode, regTypes)}, (memCode, memTypes)) + memTypes.pop(0) + memEnv = copy.copy(env) + memName = Name + "_M" + print "%0" + return doSplitDecode(specializeInst, "MODRM_MOD", + {"3" : (regName, regTypes, regEnv)}, + (memName, memTypes, memEnv)) elif opType.tag in ("I", "J"): - # Immediates are already in the instruction, so don't leave in - # those parameters - code = opRe.sub("${IMMEDIATE}", code) + # Immediates + print "IMMEDIATE" + Name += "_I" elif opType.tag == "M": # This needs to refer to memory, but we'll fill in the details # later. It needs to take into account unaligned memory # addresses. - code = "GenFault ${new UnimpInstFault}\n" + code - code = opRe.sub("%0", code) + print "%0" + Name += "_M" elif opType.tag in ("PR", "R", "VR"): # There should probably be a check here to verify that mod # is equal to 11b - code = opRe.sub("%{(uint8_t)MODRM_RM}", code) + env.addReg(ModRMRMIndex) + Name += "_R" else: raise Exception, "Unrecognized tag %s." % opType.tag - opTypes.pop(-1) + opTypes.pop(0) - # At this point, we've built up "code" to have all the necessary extra - # instructions needed to implement whatever types of operands were - # specified. Now we'll assemble it it into a StaticInst. - blocks = OutputBlocks() - blocks.append(assembleMicro(name, Name, code)) - return blocks + # Generate code to return a macroop of the given name which will + # operate in the "emulation environment" env + return genMacroop(Name, env) }}; diff --git a/src/arch/x86/predecoder.cc b/src/arch/x86/predecoder.cc index 573012ee6..3ed18aeb2 100644 --- a/src/arch/x86/predecoder.cc +++ b/src/arch/x86/predecoder.cc @@ -62,6 +62,24 @@ namespace X86ISA { + void Predecoder::reset() + { + origPC = basePC + offset; + DPRINTF(Predecoder, "Setting origPC to %#x\n", origPC); + emi.rex = 0; + emi.legacy = 0; + emi.opcode.num = 0; + + immediateCollected = 0; + emi.immediate = 0; + displacementCollected = 0; + emi.displacement = 0; + + emi.modRM = 0; + emi.sib = 0; + emi.mode = 0; + } + void Predecoder::process() { //This function drives the predecoder state machine. @@ -78,6 +96,9 @@ namespace X86ISA uint8_t nextByte = getNextByte(); switch(state) { + case ResetState: + reset(); + state = PrefixState; case PrefixState: state = doPrefixState(nextByte); break; @@ -150,7 +171,6 @@ namespace X86ISA emi.rex = nextByte; break; case 0: - emi.opcode.num = 0; nextState = OpcodeState; break; default: @@ -188,55 +208,50 @@ namespace X86ISA DPRINTF(Predecoder, "Found opcode %#x.\n", nextByte); emi.opcode.op = nextByte; - //Prepare for any immediate/displacement we might need - immediateCollected = 0; - emi.immediate = 0; - displacementCollected = 0; - emi.displacement = 0; - //Figure out the effective operand size. This can be overriden to //a fixed value at the decoder level. + int logOpSize; if(/*FIXME long mode*/1) { - if(emi.rex && emi.rex.w) - emi.opSize = 3; // 64 bit operand size + if(emi.rex.w) + logOpSize = 3; // 64 bit operand size else if(emi.legacy.op) - emi.opSize = 1; // 16 bit operand size + logOpSize = 1; // 16 bit operand size else - emi.opSize = 2; // 32 bit operand size + logOpSize = 2; // 32 bit operand size } else if(/*FIXME default 32*/1) { if(emi.legacy.op) - emi.opSize = 1; // 16 bit operand size + logOpSize = 1; // 16 bit operand size else - emi.opSize = 2; // 32 bit operand size + logOpSize = 2; // 32 bit operand size } else // 16 bit default operand size { if(emi.legacy.op) - emi.opSize = 2; // 32 bit operand size + logOpSize = 2; // 32 bit operand size else - emi.opSize = 1; // 16 bit operand size + logOpSize = 1; // 16 bit operand size } //Figure out how big of an immediate we'll retreive based //on the opcode. int immType = ImmediateType[emi.opcode.num - 1][nextByte]; - immediateSize = SizeTypeToSize[emi.opSize - 1][immType]; + immediateSize = SizeTypeToSize[logOpSize - 1][immType]; + + //Set the actual op size + emi.opSize = 1 << logOpSize; //Determine what to expect next if (UsesModRM[emi.opcode.num - 1][nextByte]) { nextState = ModRMState; } else { - //If there's no modRM byte, set it to 0 so we can detect - //that later. - emi.modRM = 0; if(immediateSize) { nextState = ImmediateState; } else { emiIsReady = true; - nextState = PrefixState; + nextState = ResetState; } } } @@ -282,7 +297,7 @@ namespace X86ISA nextState = ImmediateState; } else { emiIsReady = true; - nextState = PrefixState; + nextState = ResetState; } //The ModRM byte is consumed no matter what consumeByte(); @@ -304,7 +319,7 @@ namespace X86ISA nextState = ImmediateState; } else { emiIsReady = true; - nextState = PrefixState; + nextState = ResetState; } return nextState; } @@ -344,7 +359,7 @@ namespace X86ISA nextState = ImmediateState; } else { emiIsReady = true; - nextState = PrefixState; + nextState = ResetState; } } else @@ -375,12 +390,19 @@ namespace X86ISA //Instructions which use true 64 bit immediates won't be //affected, and instructions that use true 32 bit immediates //won't notice. - if(immediateSize == 4) + switch(immediateSize) + { + case 4: emi.immediate = sext<32>(emi.immediate); + break; + case 1: + emi.immediate = sext<8>(emi.immediate); + } + DPRINTF(Predecoder, "Collected immediate %#x.\n", emi.immediate); emiIsReady = true; - nextState = PrefixState; + nextState = ResetState; } else nextState = ImmediateState; diff --git a/src/arch/x86/predecoder.hh b/src/arch/x86/predecoder.hh index 6562ab9f5..3c858f061 100644 --- a/src/arch/x86/predecoder.hh +++ b/src/arch/x86/predecoder.hh @@ -60,6 +60,8 @@ #include "arch/x86/types.hh" #include "base/bitfield.hh" +#include "base/misc.hh" +#include "base/trace.hh" #include "sim/host.hh" class ThreadContext; @@ -81,6 +83,8 @@ namespace X86ISA MachInst fetchChunk; //The pc of the start of fetchChunk Addr basePC; + //The pc the current instruction started at + Addr origPC; //The offset into fetchChunk of current processing int offset; //The extended machine instruction being generated @@ -130,6 +134,8 @@ namespace X86ISA outOfBytes = true; } + void reset(); + //State machine state protected: //Whether or not we're out of bytes @@ -144,6 +150,7 @@ namespace X86ISA int immediateCollected; enum State { + ResetState, PrefixState, OpcodeState, ModRMState, @@ -166,10 +173,13 @@ namespace X86ISA public: Predecoder(ThreadContext * _tc) : - tc(_tc), basePC(0), offset(0), + tc(_tc), basePC(0), origPC(0), offset(0), outOfBytes(true), emiIsReady(false), - state(PrefixState) - {} + state(ResetState) + { + emi.mode.mode = LongMode; + emi.mode.submode = SixtyFourBitMode; + } ThreadContext * getTC() { @@ -185,9 +195,9 @@ namespace X86ISA //Use this to give data to the predecoder. This should be used //when there is control flow. - void moreBytes(Addr currPC, Addr off, MachInst data) + void moreBytes(Addr pc, Addr fetchPC, Addr off, MachInst data) { - basePC = currPC; + basePC = fetchPC; offset = off; fetchChunk = data; assert(off < sizeof(MachInst)); @@ -195,13 +205,6 @@ namespace X86ISA process(); } - //Use this to give data to the predecoder. This should be used - //when instructions are executed in order. - void moreBytes(MachInst machInst) - { - moreBytes(basePC + sizeof(machInst), 0, machInst); - } - bool needMoreBytes() { return outOfBytes; @@ -219,6 +222,15 @@ namespace X86ISA emiIsReady = false; return emi; } + + int getInstSize() + { + DPRINTF(Predecoder, + "Calculating the instruction size: " + "basePC: %#x offset: %#x origPC: %#x\n", + basePC, offset, origPC); + return basePC + offset - origPC; + } }; }; diff --git a/src/arch/x86/predecoder_tables.cc b/src/arch/x86/predecoder_tables.cc index 38b9c57a3..6fe54b719 100644 --- a/src/arch/x86/predecoder_tables.cc +++ b/src/arch/x86/predecoder_tables.cc @@ -170,7 +170,7 @@ namespace X86ISA // noimm byte word dword qword oword vword zword enter pointer {0, 1, 2, 4, 8, 16, 2, 2, 3, 4 }, //16 bit {0, 1, 2, 4, 8, 16, 4, 4, 3, 6 }, //32 bit - {0, 1, 2, 4, 8, 16, 4, 8, 3, 0 } //64 bit + {0, 1, 2, 4, 8, 16, 8, 4, 3, 0 } //64 bit }; //This table determines the immediate type. The first index is the diff --git a/src/arch/x86/regfile.cc b/src/arch/x86/regfile.cc index 568eb1d94..f54f531e2 100644 --- a/src/arch/x86/regfile.cc +++ b/src/arch/x86/regfile.cc @@ -117,7 +117,8 @@ void RegFile::setNextPC(Addr val) Addr RegFile::readNextNPC() { - return nextRip + sizeof(MachInst); + //There's no way to know how big the -next- instruction will be. + return nextRip + 1; } void RegFile::setNextNPC(Addr val) diff --git a/src/arch/x86/types.hh b/src/arch/x86/types.hh index 022f20ee5..fc9f1d82b 100644 --- a/src/arch/x86/types.hh +++ b/src/arch/x86/types.hh @@ -120,6 +120,24 @@ namespace X86ISA Bitfield<2,0> bottom3; EndBitUnion(Opcode) + BitUnion8(OperatingMode) + Bitfield<3> mode; + Bitfield<2,0> submode; + EndBitUnion(OperatingMode) + + enum X86Mode { + LongMode, + LegacyMode + }; + + enum X86SubMode { + SixtyFourBitMode, + CompatabilityMode, + ProtectedMode, + Virtual8086Mode, + RealMode + }; + //The intermediate structure the x86 predecoder returns. struct ExtMachInst { @@ -149,7 +167,11 @@ namespace X86ISA //The effective operand size. uint8_t opSize; - //The + //The effective address size. + uint8_t addrSize; + + //Mode information + OperatingMode mode; }; inline static std::ostream & @@ -171,6 +193,8 @@ namespace X86ISA inline static bool operator == (const ExtMachInst &emi1, const ExtMachInst &emi2) { + if(emi1.mode != emi2.mode) + return false; if(emi1.legacy != emi2.legacy) return false; if(emi1.rex != emi2.rex) diff --git a/src/arch/x86/utility.hh b/src/arch/x86/utility.hh index 1c98e7fbc..ed401a519 100644 --- a/src/arch/x86/utility.hh +++ b/src/arch/x86/utility.hh @@ -79,7 +79,7 @@ namespace __hash_namespace { ((uint64_t)emi.opcode.prefixB << 8) | ((uint64_t)emi.opcode.op)) ^ emi.immediate ^ emi.displacement ^ - emi.opSize; + emi.mode ^ emi.opSize; }; }; } diff --git a/src/arch/x86/x86_traits.hh b/src/arch/x86/x86_traits.hh index fa54c24e9..e45d62f8f 100644 --- a/src/arch/x86/x86_traits.hh +++ b/src/arch/x86/x86_traits.hh @@ -60,8 +60,7 @@ namespace X86ISA { - //XXX This will definitely need to be something larger in the future. - const int NumMicroIntRegs = 0; + const int NumMicroIntRegs = 16; const int NumMMXRegs = 8; const int NumXMMRegs = 16; diff --git a/src/base/SConscript b/src/base/SConscript index cc9d06a0e..ca68bfb60 100644 --- a/src/base/SConscript +++ b/src/base/SConscript @@ -57,7 +57,8 @@ Source('circlebuf.cc') Source('cprintf.cc') Source('crc.cc') Source('fast_alloc.cc') -Source('fenv.c') +if env['USE_FENV']: + Source('fenv.c') Source('fifo_buffer.cc') Source('hostinfo.cc') Source('hybrid_pred.cc') diff --git a/src/base/fenv.c b/src/base/fenv.c index 269913a60..2ec2f796f 100644 --- a/src/base/fenv.c +++ b/src/base/fenv.c @@ -39,7 +39,7 @@ static const int m5_round_ops[] = {FE_DOWNWARD, FE_TONEAREST, FE_TOWARDZERO, FE void m5_fesetround(int rm) { - assert(rm > 0 && rm < 4); + assert(rm >= 0 && rm < 4); fesetround(m5_round_ops[rm]); } diff --git a/src/cpu/FuncUnit.py b/src/cpu/FuncUnit.py index 541bdbd83..ad2d1b87b 100644 --- a/src/cpu/FuncUnit.py +++ b/src/cpu/FuncUnit.py @@ -29,15 +29,15 @@ from m5.SimObject import SimObject from m5.params import * -class OpType(Enum): - vals = ['(null)', 'IntAlu', 'IntMult', 'IntDiv', 'FloatAdd', +class OpClass(Enum): + vals = ['No_OpClass', 'IntAlu', 'IntMult', 'IntDiv', 'FloatAdd', 'FloatCmp', 'FloatCvt', 'FloatMult', 'FloatDiv', 'FloatSqrt', 'MemRead', 'MemWrite', 'IprAccess', 'InstPrefetch'] class OpDesc(SimObject): type = 'OpDesc' issueLat = Param.Int(1, "cycles until another can be issued") - opClass = Param.OpType("type of operation") + opClass = Param.OpClass("type of operation") opLat = Param.Int(1, "cycles until result is available") class FUDesc(SimObject): diff --git a/src/cpu/base_dyn_inst_impl.hh b/src/cpu/base_dyn_inst_impl.hh index a1c866336..216cc08ea 100644 --- a/src/cpu/base_dyn_inst_impl.hh +++ b/src/cpu/base_dyn_inst_impl.hh @@ -66,7 +66,7 @@ BaseDynInst<Impl>::BaseDynInst(TheISA::ExtMachInst machInst, Addr inst_PC, Addr inst_NPC, Addr pred_PC, Addr pred_NPC, InstSeqNum seq_num, ImplCPU *cpu) - : staticInst(machInst), traceData(NULL), cpu(cpu) + : staticInst(machInst, inst_PC), traceData(NULL), cpu(cpu) { seqNum = seq_num; diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc index 3e2b0f03e..9b87f2e8a 100644 --- a/src/cpu/exetrace.cc +++ b/src/cpu/exetrace.cc @@ -162,7 +162,7 @@ Trace::InstRecord::dump() static int fd = 0; //Don't print what happens for each micro-op, just print out //once at the last op, and for regular instructions. - if(!staticInst->isMicroOp() || staticInst->isLastMicroOp()) + if(!staticInst->isMicroop() || staticInst->isLastMicroop()) { if(!cosim_listener) { @@ -245,7 +245,7 @@ Trace::InstRecord::dump() #if 0 //THE_ISA == SPARC_ISA //Don't print what happens for each micro-op, just print out //once at the last op, and for regular instructions. - if(!staticInst->isMicroOp() || staticInst->isLastMicroOp()) + if(!staticInst->isMicroop() || staticInst->isLastMicroop()) { static uint64_t regs[32] = { 0, 0, 0, 0, 0, 0, 0, 0, @@ -432,7 +432,7 @@ Trace::InstRecord::dump() setupSharedData(); // We took a trap on a micro-op... - if (wasMicro && !staticInst->isMicroOp()) + if (wasMicro && !staticInst->isMicroop()) { // let's skip comparing this tick while (!compared) @@ -444,13 +444,13 @@ Trace::InstRecord::dump() wasMicro = false; } - if (staticInst->isLastMicroOp()) + if (staticInst->isLastMicroop()) wasMicro = false; - else if (staticInst->isMicroOp()) + else if (staticInst->isMicroop()) wasMicro = true; - if(!staticInst->isMicroOp() || staticInst->isLastMicroOp()) { + if(!staticInst->isMicroop() || staticInst->isLastMicroop()) { while (!compared) { if (shared_data->flags == OWN_M5) { m5Pc = PC & TheISA::PAddrImplMask; @@ -650,12 +650,13 @@ Trace::InstRecord::dump() << endl; predecoder.setTC(thread); - predecoder.moreBytes(m5Pc, 0, shared_data->instruction); + predecoder.moreBytes(m5Pc, m5Pc, 0, + shared_data->instruction); assert(predecoder.extMachInstReady()); StaticInstPtr legionInst = - StaticInst::decode(predecoder.getExtMachInst()); + StaticInst::decode(predecoder.getExtMachInst(), lgnPc); outs << setfill(' ') << setw(15) << " Legion Inst: " << "0x" << setw(8) << setfill('0') << hex diff --git a/src/cpu/o3/SConscript b/src/cpu/o3/SConscript index a1af620be..ad61ad228 100755 --- a/src/cpu/o3/SConscript +++ b/src/cpu/o3/SConscript @@ -75,7 +75,7 @@ if 'O3CPU' in env['CPU_MODELS']: sys.exit('O3 CPU does not support the \'%s\' ISA' % env['TARGET_ISA']) if env['USE_CHECKER']: - SimObject('m5/objects/O3Checker.py') + SimObject('O3Checker.py') Source('checker_builder.cc') if 'O3CPU' in env['CPU_MODELS'] or 'OzoneCPU' in env['CPU_MODELS']: diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh index e16f97558..ab55ec744 100644 --- a/src/cpu/o3/fetch_impl.hh +++ b/src/cpu/o3/fetch_impl.hh @@ -29,6 +29,9 @@ * Korey Sewell */ +#include <algorithm> +#include <cstring> + #include "config/use_checker.hh" #include "arch/isa_traits.hh" @@ -48,8 +51,6 @@ #include "sim/system.hh" #endif // FULL_SYSTEM -#include <algorithm> - template<class Impl> void DefaultFetch<Impl>::IcachePort::setPeer(Port *port) @@ -374,7 +375,7 @@ DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt) return; } - memcpy(cacheData[tid], pkt->getPtr<uint8_t *>(), cacheBlkSize); + memcpy(cacheData[tid], pkt->getPtr<uint8_t>(), cacheBlkSize); cacheDataValid[tid] = true; if (!drainPending) { @@ -1127,7 +1128,7 @@ DefaultFetch<Impl>::fetch(bool &status_change) (&cacheData[tid][offset])); predecoder.setTC(cpu->thread[tid]->getTC()); - predecoder.moreBytes(fetch_PC, 0, inst); + predecoder.moreBytes(fetch_PC, fetch_PC, 0, inst); ext_inst = predecoder.getExtMachInst(); @@ -1151,10 +1152,14 @@ DefaultFetch<Impl>::fetch(bool &status_change) DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n", tid, instruction->staticInst->disassemble(fetch_PC)); +#if TRACING_ON instruction->traceData = Trace::getInstRecord(curTick, cpu->tcBase(tid), instruction->staticInst, instruction->readPC()); +#else + instruction->traceData = NULL; +#endif ///FIXME This needs to be more robust in dealing with delay slots #if !ISA_HAS_DELAY_SLOT diff --git a/src/cpu/op_class.cc b/src/cpu/op_class.cc index f7ef49c0f..02cb4a08a 100644 --- a/src/cpu/op_class.cc +++ b/src/cpu/op_class.cc @@ -34,7 +34,7 @@ const char * opClassStrings[Num_OpClasses] = { - "(null)", + "No_OpClass", "IntAlu", "IntMult", "IntDiv", diff --git a/src/cpu/ozone/SConscript b/src/cpu/ozone/SConscript index 601e80a72..cb2006456 100644 --- a/src/cpu/ozone/SConscript +++ b/src/cpu/ozone/SConscript @@ -45,5 +45,5 @@ if 'OzoneCPU' in env['CPU_MODELS']: Source('lw_lsq.cc') Source('rename_table.cc') if env['USE_CHECKER']: - SimObject('m5/objects/OzoneChecker.py') + SimObject('OzoneChecker.py') Source('checker_builder.cc') diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index b0a01c3a3..ea1c7d87f 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -540,8 +540,8 @@ AtomicSimpleCPU::tick() } // @todo remove me after debugging with legion done - if (curStaticInst && (!curStaticInst->isMicroOp() || - curStaticInst->isFirstMicroOp())) + if (curStaticInst && (!curStaticInst->isMicroop() || + curStaticInst->isFirstMicroop())) instCnt++; if (simulate_stalls) { @@ -557,7 +557,7 @@ AtomicSimpleCPU::tick() } } - if(predecoder.needMoreBytes() || fault != NoFault) + if(fault != NoFault || !stayAtPC) advancePC(fault); } diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc index 4fed2059b..b7f60522f 100644 --- a/src/cpu/simple/base.cc +++ b/src/cpu/simple/base.cc @@ -70,7 +70,7 @@ using namespace std; using namespace TheISA; BaseSimpleCPU::BaseSimpleCPU(Params *p) - : BaseCPU(p), thread(NULL), predecoder(NULL) + : BaseCPU(p), traceData(NULL), thread(NULL), predecoder(NULL) { #if FULL_SYSTEM thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb); @@ -91,6 +91,9 @@ BaseSimpleCPU::BaseSimpleCPU(Params *p) lastDcacheStall = 0; threadContexts.push_back(tc); + + fetchOffset = 0; + stayAtPC = false; } BaseSimpleCPU::~BaseSimpleCPU() @@ -326,18 +329,19 @@ BaseSimpleCPU::checkForInterrupts() Fault BaseSimpleCPU::setupFetchRequest(Request *req) { + Addr threadPC = thread->readPC(); + // set up memory request for instruction fetch #if ISA_HAS_DELAY_SLOT - DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p NNPC:%08p\n",thread->readPC(), + DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p NNPC:%08p\n",threadPC, thread->readNextPC(),thread->readNextNPC()); #else - DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p",thread->readPC(), + DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p\n",threadPC, thread->readNextPC()); #endif - req->setVirt(0, thread->readPC() & ~3, sizeof(MachInst), - (FULL_SYSTEM && (thread->readPC() & 1)) ? PHYSICAL : 0, - thread->readPC()); + Addr fetchPC = (threadPC & PCMask) + fetchOffset; + req->setVirt(0, fetchPC, sizeof(MachInst), 0, threadPC); Fault fault = thread->translateInstReq(req); @@ -365,8 +369,10 @@ BaseSimpleCPU::preExecute() // decode the instruction inst = gtoh(inst); + //If we're not in the middle of a macro instruction if (!curMacroStaticInst) { + StaticInstPtr instPtr = NULL; //Predecode, ie bundle up an ExtMachInst @@ -374,36 +380,50 @@ BaseSimpleCPU::preExecute() predecoder.setTC(thread->getTC()); //If more fetch data is needed, pass it in. if(predecoder.needMoreBytes()) - predecoder.moreBytes(thread->readPC(), 0, inst); + predecoder.moreBytes(thread->readPC(), + (thread->readPC() & PCMask) + fetchOffset, 0, inst); else predecoder.process(); - //If an instruction is ready, decode it - if (predecoder.extMachInstReady()) - instPtr = StaticInst::decode(predecoder.getExtMachInst()); + + //If an instruction is ready, decode it. Otherwise, we'll have to + //fetch beyond the MachInst at the current pc. + if (predecoder.extMachInstReady()) { +#if THE_ISA == X86_ISA + thread->setNextPC(thread->readPC() + predecoder.getInstSize()); +#endif // X86_ISA + stayAtPC = false; + instPtr = StaticInst::decode(predecoder.getExtMachInst(), + thread->readPC()); + } else { + stayAtPC = true; + fetchOffset += sizeof(MachInst); + } //If we decoded an instruction and it's microcoded, start pulling //out micro ops - if (instPtr && instPtr->isMacroOp()) { + if (instPtr && instPtr->isMacroop()) { curMacroStaticInst = instPtr; curStaticInst = curMacroStaticInst-> - fetchMicroOp(thread->readMicroPC()); + fetchMicroop(thread->readMicroPC()); } else { curStaticInst = instPtr; } } else { //Read the next micro op from the macro op curStaticInst = curMacroStaticInst-> - fetchMicroOp(thread->readMicroPC()); + fetchMicroop(thread->readMicroPC()); } //If we decoded an instruction this "tick", record information about it. if(curStaticInst) { +#if TRACING_ON traceData = Trace::getInstRecord(curTick, tc, curStaticInst, thread->readPC()); DPRINTF(Decode,"Decode: Decoded %s instruction: 0x%x\n", curStaticInst->getName(), curStaticInst->machInst); +#endif // TRACING_ON #if FULL_SYSTEM thread->setInst(inst); @@ -418,7 +438,7 @@ BaseSimpleCPU::postExecute() if (thread->profile) { bool usermode = TheISA::inUserMode(tc); thread->profilePC = usermode ? 1 : thread->readPC(); - StaticInstPtr si(inst); + StaticInstPtr si(inst, thread->readPC()); ProfileNode *node = thread->profile->consume(tc, si); if (node) thread->profileNode = node; @@ -447,14 +467,16 @@ BaseSimpleCPU::postExecute() void BaseSimpleCPU::advancePC(Fault fault) { + //Since we're moving to a new pc, zero out the offset + fetchOffset = 0; if (fault != NoFault) { curMacroStaticInst = StaticInst::nullStaticInstPtr; fault->invoke(tc); thread->setMicroPC(0); thread->setNextMicroPC(1); - } else if (predecoder.needMoreBytes()) { + } else { //If we're at the last micro op for this instruction - if (curStaticInst && curStaticInst->isLastMicroOp()) { + if (curStaticInst && curStaticInst->isLastMicroop()) { //We should be working with a macro op assert(curMacroStaticInst); //Close out this macro op, and clean up the diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh index 787259c96..d221baca8 100644 --- a/src/cpu/simple/base.hh +++ b/src/cpu/simple/base.hh @@ -137,6 +137,12 @@ class BaseSimpleCPU : public BaseCPU StaticInstPtr curStaticInst; StaticInstPtr curMacroStaticInst; + //This is the offset from the current pc that fetch should be performed at + Addr fetchOffset; + //This flag says to stay at the current pc. This is useful for + //instructions which go beyond MachInst boundaries. + bool stayAtPC; + void checkForInterrupts(); Fault setupFetchRequest(Request *req); void preExecute(); @@ -160,6 +166,9 @@ class BaseSimpleCPU : public BaseCPU return numInst - startNumInst; } + // Mask to align PCs to MachInst sized boundaries + static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1); + // number of simulated memory references Stats::Scalar<> numMemRefs; diff --git a/src/cpu/static_inst.cc b/src/cpu/static_inst.cc index 64fcc0580..52a7ede03 100644 --- a/src/cpu/static_inst.cc +++ b/src/cpu/static_inst.cc @@ -37,6 +37,8 @@ StaticInstPtr StaticInst::nullStaticInstPtr; // Define the decode cache hash map. StaticInst::DecodeCache StaticInst::decodeCache; +StaticInst::AddrDecodeCache StaticInst::addrDecodeCache; +StaticInst::cacheElement StaticInst::recentDecodes[2]; void StaticInst::dumpDecodeCacheStats() @@ -76,9 +78,9 @@ StaticInst::hasBranchTarget(Addr pc, ThreadContext *tc, Addr &tgt) const } StaticInstPtr -StaticInst::fetchMicroOp(MicroPC micropc) +StaticInst::fetchMicroop(MicroPC micropc) { - panic("StaticInst::fetchMicroOp() called on instruction " + panic("StaticInst::fetchMicroop() called on instruction " "that is not microcoded."); } diff --git a/src/cpu/static_inst.hh b/src/cpu/static_inst.hh index a58ac85d6..b0a19c151 100644 --- a/src/cpu/static_inst.hh +++ b/src/cpu/static_inst.hh @@ -63,6 +63,7 @@ class AtomicSimpleCPU; class TimingSimpleCPU; class InorderCPU; class SymbolTable; +class AddrDecodePage; namespace Trace { class InstRecord; @@ -143,11 +144,11 @@ class StaticInstBase : public RefCounted IsUnverifiable, ///< Can't be verified by a checker //Flags for microcode - IsMacroOp, ///< Is a macroop containing microops - IsMicroOp, ///< Is a microop + IsMacroop, ///< Is a macroop containing microops + IsMicroop, ///< Is a microop IsDelayedCommit, ///< This microop doesn't commit right away - IsLastMicroOp, ///< This microop ends a microop sequence - IsFirstMicroOp, ///< This microop begins a microop sequence + IsLastMicroop, ///< This microop ends a microop sequence + IsFirstMicroop, ///< This microop begins a microop sequence //This flag doesn't do anything yet IsMicroBranch, ///< This microop branches within the microcode for a macroop @@ -242,11 +243,11 @@ class StaticInstBase : public RefCounted bool isQuiesce() const { return flags[IsQuiesce]; } bool isIprAccess() const { return flags[IsIprAccess]; } bool isUnverifiable() const { return flags[IsUnverifiable]; } - bool isMacroOp() const { return flags[IsMacroOp]; } - bool isMicroOp() const { return flags[IsMicroOp]; } + bool isMacroop() const { return flags[IsMacroop]; } + bool isMicroop() const { return flags[IsMicroop]; } bool isDelayedCommit() const { return flags[IsDelayedCommit]; } - bool isLastMicroOp() const { return flags[IsLastMicroOp]; } - bool isFirstMicroOp() const { return flags[IsFirstMicroOp]; } + bool isLastMicroop() const { return flags[IsLastMicroop]; } + bool isFirstMicroop() const { return flags[IsFirstMicroop]; } //This flag doesn't do anything yet bool isMicroBranch() const { return flags[IsMicroBranch]; } //@} @@ -349,6 +350,7 @@ class StaticInst : public StaticInstBase : StaticInstBase(__opClass), machInst(_machInst), mnemonic(_mnemonic), cachedDisassembly(0) { + memset(&recentDecodes, 0, 2 * sizeof(cacheElement)); } public: @@ -369,7 +371,7 @@ class StaticInst : public StaticInstBase * Return the microop that goes with a particular micropc. This should * only be defined/used in macroops which will contain microops */ - virtual StaticInstPtr fetchMicroOp(MicroPC micropc); + virtual StaticInstPtr fetchMicroop(MicroPC micropc); /** * Return the target address for a PC-relative branch. @@ -437,11 +439,52 @@ class StaticInst : public StaticInstBase /// Decode a machine instruction. /// @param mach_inst The binary instruction to decode. /// @retval A pointer to the corresponding StaticInst object. - //This is defined as inline below. - static StaticInstPtr decode(ExtMachInst mach_inst); + //This is defined as inlined below. + static StaticInstPtr decode(ExtMachInst mach_inst, Addr addr); /// Return name of machine instruction std::string getName() { return mnemonic; } + + /// Decoded instruction cache type, for address decoding. + /// A generic hash_map is used. + typedef m5::hash_map<Addr, AddrDecodePage *> AddrDecodeCache; + + /// A cache of decoded instruction objects from addresses. + static AddrDecodeCache addrDecodeCache; + + struct cacheElement { + Addr page_addr; + AddrDecodePage *decodePage; + } ; + + /// An array of recently decoded instructions. + // might not use an array if there is only two elements + static struct cacheElement recentDecodes[2]; + + /// Updates the recently decoded instructions entries + /// @param page_addr The page address recently used. + /// @param decodePage Pointer to decoding page containing the decoded + /// instruction. + static inline void + updateCache(Addr page_addr, AddrDecodePage *decodePage) + { + recentDecodes[1].page_addr = recentDecodes[0].page_addr; + recentDecodes[1].decodePage = recentDecodes[0].decodePage; + recentDecodes[0].page_addr = page_addr; + recentDecodes[0].decodePage = decodePage; + } + + /// Searches the decoded instruction cache for instruction decoding. + /// If it is not found, then we decode the instruction. + /// Otherwise, we get the instruction from the cache and move it into + /// the address-to-instruction decoding page. + /// @param mach_inst The binary instruction to decode. + /// @param addr The address that contained the binary instruction. + /// @param decodePage Pointer to decoding page containing the instruction. + /// @retval A pointer to the corresponding StaticInst object. + //This is defined as inlined below. + static StaticInstPtr searchCache(ExtMachInst mach_inst, Addr addr, + AddrDecodePage * decodePage); }; typedef RefCountingPtr<StaticInstBase> StaticInstBasePtr; @@ -472,8 +515,8 @@ class StaticInstPtr : public RefCountingPtr<StaticInst> /// Construct directly from machine instruction. /// Calls StaticInst::decode(). - explicit StaticInstPtr(TheISA::ExtMachInst mach_inst) - : RefCountingPtr<StaticInst>(StaticInst::decode(mach_inst)) + explicit StaticInstPtr(TheISA::ExtMachInst mach_inst, Addr addr) + : RefCountingPtr<StaticInst>(StaticInst::decode(mach_inst, addr)) { } @@ -484,8 +527,55 @@ class StaticInstPtr : public RefCountingPtr<StaticInst> } }; +/// A page of a list of decoded instructions from an address. +class AddrDecodePage +{ + typedef TheISA::ExtMachInst ExtMachInst; + protected: + StaticInstPtr instructions[TheISA::PageBytes]; + bool valid[TheISA::PageBytes]; + Addr lowerMask; + + public: + /// Constructor + AddrDecodePage() { + lowerMask = TheISA::PageBytes - 1; + memset(valid, 0, TheISA::PageBytes); + } + + /// Checks if the instruction is already decoded and the machine + /// instruction in the cache matches the current machine instruction + /// related to the address + /// @param mach_inst The binary instruction to check + /// @param addr The address containing the instruction + inline bool decoded(ExtMachInst mach_inst, Addr addr) + { + return (valid[addr & lowerMask] && + (instructions[addr & lowerMask]->machInst == mach_inst)); + } + + /// Returns the instruction object. decoded should be called first + /// to check if the instruction is valid. + /// @param addr The address of the instruction. + /// @retval A pointer to the corresponding StaticInst object. + inline StaticInstPtr getInst(Addr addr) + { return instructions[addr & lowerMask]; } + + /// Inserts a pointer to a StaticInst object into the list of decoded + /// instructions on the page. + /// @param addr The address of the instruction. + /// @param si A pointer to the corresponding StaticInst object. + inline void insert(Addr addr, StaticInstPtr &si) + { + instructions[addr & lowerMask] = si; + valid[addr & lowerMask] = true; + } + +}; + + inline StaticInstPtr -StaticInst::decode(StaticInst::ExtMachInst mach_inst) +StaticInst::decode(StaticInst::ExtMachInst mach_inst, Addr addr) { #ifdef DECODE_CACHE_HASH_STATS // Simple stats on decode hash_map. Turns out the default @@ -499,12 +589,54 @@ StaticInst::decode(StaticInst::ExtMachInst mach_inst) } #endif + Addr page_addr = addr & ~(TheISA::PageBytes - 1); + + // checks recently decoded addresses + if (recentDecodes[0].decodePage && + page_addr == recentDecodes[0].page_addr) { + if (recentDecodes[0].decodePage->decoded(mach_inst, addr)) + return recentDecodes[0].decodePage->getInst(addr); + + return searchCache(mach_inst, addr, recentDecodes[0].decodePage); + } + + if (recentDecodes[1].decodePage && + page_addr == recentDecodes[1].page_addr) { + if (recentDecodes[1].decodePage->decoded(mach_inst, addr)) + return recentDecodes[1].decodePage->getInst(addr); + + return searchCache(mach_inst, addr, recentDecodes[1].decodePage); + } + + // searches the page containing the address to decode + AddrDecodeCache::iterator iter = addrDecodeCache.find(page_addr); + if (iter != addrDecodeCache.end()) { + updateCache(page_addr, iter->second); + if (iter->second->decoded(mach_inst, addr)) + return iter->second->getInst(addr); + + return searchCache(mach_inst, addr, iter->second); + } + + // creates a new object for a page of decoded instructions + AddrDecodePage * decodePage = new AddrDecodePage; + addrDecodeCache[page_addr] = decodePage; + updateCache(page_addr, decodePage); + return searchCache(mach_inst, addr, decodePage); +} + +inline StaticInstPtr +StaticInst::searchCache(ExtMachInst mach_inst, Addr addr, + AddrDecodePage * decodePage) +{ DecodeCache::iterator iter = decodeCache.find(mach_inst); if (iter != decodeCache.end()) { + decodePage->insert(addr, iter->second); return iter->second; } StaticInstPtr si = TheISA::decodeInst(mach_inst); + decodePage->insert(addr, si); decodeCache[mach_inst] = si; return si; } diff --git a/src/mem/bus.cc b/src/mem/bus.cc index bde90c83f..0c1f384b1 100644 --- a/src/mem/bus.cc +++ b/src/mem/bus.cc @@ -607,6 +607,13 @@ Bus::drain(Event * de) } } +void +Bus::startup() +{ + if (tickNextIdle < curTick) + tickNextIdle = (curTick / clock) * clock + clock; +} + BEGIN_DECLARE_SIM_OBJECT_PARAMS(Bus) Param<int> bus_id; diff --git a/src/mem/bus.hh b/src/mem/bus.hh index 33619bf45..bd51337ed 100644 --- a/src/mem/bus.hh +++ b/src/mem/bus.hh @@ -264,6 +264,7 @@ class Bus : public MemObject virtual void deletePortRefs(Port *p); virtual void init(); + virtual void startup(); unsigned int drain(Event *de); diff --git a/src/mem/cache/BaseCache.py b/src/mem/cache/BaseCache.py index 4b98f6b30..32f3f0174 100644 --- a/src/mem/cache/BaseCache.py +++ b/src/mem/cache/BaseCache.py @@ -27,6 +27,7 @@ # Authors: Nathan Binkert from m5.params import * +from m5.proxy import Self from MemObject import MemObject class Prefetch(Enum): vals = ['none', 'tagged', 'stride', 'ghb'] @@ -77,7 +78,7 @@ class BaseCache(MemObject): "Squash prefetches with a later time on a subsequent miss") prefetch_degree = Param.Int(1, "Degree of the prefetch depth") - prefetch_latency = Param.Tick(10, + prefetch_latency = Param.Latency(10 * Self.latency, "Latency of the prefetcher") prefetch_policy = Param.Prefetch('none', "Type of prefetcher to use") diff --git a/src/mem/page_table.cc b/src/mem/page_table.cc index 96bc23793..b29a07078 100644 --- a/src/mem/page_table.cc +++ b/src/mem/page_table.cc @@ -90,8 +90,6 @@ PageTable::page_check(Addr addr, int64_t size) const } - - void PageTable::allocate(Addr vaddr, int64_t size) { @@ -109,12 +107,7 @@ PageTable::allocate(Addr vaddr, int64_t size) } pTable[vaddr] = system->new_page(); - pTableCache[2].paddr = pTableCache[1].paddr; - pTableCache[2].vaddr = pTableCache[1].vaddr; - pTableCache[1].paddr = pTableCache[0].paddr; - pTableCache[1].vaddr = pTableCache[0].vaddr; - pTableCache[0].paddr = pTable[vaddr]; - pTableCache[0].vaddr = vaddr; + updateCache(vaddr, pTable[vaddr]); } } @@ -126,16 +119,16 @@ PageTable::translate(Addr vaddr, Addr &paddr) Addr page_addr = pageAlign(vaddr); paddr = 0; - if (pTableCache[0].vaddr == vaddr) { - paddr = pTableCache[0].paddr; + if (pTableCache[0].vaddr == page_addr) { + paddr = pTableCache[0].paddr + pageOffset(vaddr); return true; } - if (pTableCache[1].vaddr == vaddr) { - paddr = pTableCache[1].paddr; + if (pTableCache[1].vaddr == page_addr) { + paddr = pTableCache[1].paddr + pageOffset(vaddr); return true; } - if (pTableCache[2].vaddr == vaddr) { - paddr = pTableCache[2].paddr; + if (pTableCache[2].vaddr == page_addr) { + paddr = pTableCache[2].paddr + pageOffset(vaddr); return true; } @@ -145,6 +138,7 @@ PageTable::translate(Addr vaddr, Addr &paddr) return false; } + updateCache(page_addr, iter->second); paddr = iter->second + pageOffset(vaddr); return true; } diff --git a/src/mem/page_table.hh b/src/mem/page_table.hh index 0e2b1f58c..64c824238 100644 --- a/src/mem/page_table.hh +++ b/src/mem/page_table.hh @@ -95,6 +95,22 @@ class PageTable */ Fault translate(RequestPtr &req); + /** + * Update the page table cache. + * @param vaddr virtual address (page aligned) to check + * @param paddr physical address (page aligned) to return + */ + inline void updateCache(Addr vaddr, Addr paddr) + { + pTableCache[2].paddr = pTableCache[1].paddr; + pTableCache[2].vaddr = pTableCache[1].vaddr; + pTableCache[1].paddr = pTableCache[0].paddr; + pTableCache[1].vaddr = pTableCache[0].vaddr; + pTableCache[0].paddr = paddr; + pTableCache[0].vaddr = vaddr; + } + + void serialize(std::ostream &os); void unserialize(Checkpoint *cp, const std::string §ion); }; diff --git a/src/python/m5/SimObject.py b/src/python/m5/SimObject.py index 42266a80e..f87e13732 100644 --- a/src/python/m5/SimObject.py +++ b/src/python/m5/SimObject.py @@ -722,6 +722,13 @@ class SimObject(object): for child in self._children.itervalues(): child.resume() + def getMemoryMode(self): + if not isinstance(self, m5.objects.System): + return None + + system_ptr = internal.sim_object.convertToSystemPtr(self._ccObject) + return system_ptr.getMemoryMode() + def changeTiming(self, mode): if isinstance(self, m5.objects.System): # i don't know if there's a better way to do this - calling diff --git a/src/python/m5/__init__.py b/src/python/m5/__init__.py index 06dc92bc6..a9206a474 100644 --- a/src/python/m5/__init__.py +++ b/src/python/m5/__init__.py @@ -190,17 +190,20 @@ def changeToAtomic(system): if not isinstance(system, (objects.Root, objects.System)): raise TypeError, "Parameter of type '%s'. Must be type %s or %s." % \ (type(system), objects.Root, objects.System) - doDrain(system) - print "Changing memory mode to atomic" - system.changeTiming(internal.sim_object.SimObject.Atomic) + if system.getMemoryMode() != internal.sim_object.SimObject.Atomic: + doDrain(system) + print "Changing memory mode to atomic" + system.changeTiming(internal.sim_object.SimObject.Atomic) def changeToTiming(system): if not isinstance(system, (objects.Root, objects.System)): raise TypeError, "Parameter of type '%s'. Must be type %s or %s." % \ (type(system), objects.Root, objects.System) - doDrain(system) - print "Changing memory mode to timing" - system.changeTiming(internal.sim_object.SimObject.Timing) + + if system.getMemoryMode() != internal.sim_object.SimObject.Timing: + doDrain(system) + print "Changing memory mode to timing" + system.changeTiming(internal.sim_object.SimObject.Timing) def switchCpus(cpuList): print "switching cpus" diff --git a/src/python/swig/sim_object.i b/src/python/swig/sim_object.i index b2af72c61..a1737c438 100644 --- a/src/python/swig/sim_object.i +++ b/src/python/swig/sim_object.i @@ -66,6 +66,7 @@ class System { private: System(); public: + SimObject::MemoryMode getMemoryMode(); void setMemoryMode(SimObject::MemoryMode mode); }; diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini index 882c78529..f2617931a 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini @@ -99,7 +99,7 @@ prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=10000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -274,7 +274,7 @@ prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=10000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -312,7 +312,7 @@ prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=10000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -366,7 +366,7 @@ bus_id=0 clock=1000 responder_set=false width=64 -port=system.physmem.port system.cpu.l2cache.mem_side +port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out index 701034053..7cb2e7d7d 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out @@ -275,7 +275,7 @@ prefetch_access=false prefetcher_size=100 prefetch_past_page=false prefetch_serial_squash=false -prefetch_latency=10 +prefetch_latency=10000 prefetch_degree=1 prefetch_policy=none prefetch_cache_check_push=true @@ -312,7 +312,7 @@ prefetch_access=false prefetcher_size=100 prefetch_past_page=false prefetch_serial_squash=false -prefetch_latency=10 +prefetch_latency=10000 prefetch_degree=1 prefetch_policy=none prefetch_cache_check_push=true @@ -349,7 +349,7 @@ prefetch_access=false prefetcher_size=100 prefetch_past_page=false prefetch_serial_squash=false -prefetch_latency=10 +prefetch_latency=10000 prefetch_degree=1 prefetch_policy=none prefetch_cache_check_push=true diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt index c07021f5a..e1bed0c51 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt @@ -8,10 +8,9 @@ global.BPredUnit.condIncorrect 422 # Nu global.BPredUnit.condPredicted 1093 # Number of conditional branches predicted global.BPredUnit.lookups 1843 # Number of BP lookups global.BPredUnit.usedRAS 241 # Number of times the RAS was used to get a target. -host_inst_rate 54565 # Simulator instruction rate (inst/s) -host_mem_usage 154084 # Number of bytes of host memory used -host_seconds 0.10 # Real time elapsed on the host -host_tick_rate 44392410 # Simulator tick rate (ticks/s) +host_inst_rate 7145 # Simulator instruction rate (inst/s) +host_seconds 0.79 # Real time elapsed on the host +host_tick_rate 5828052 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 17 # Number of conflicting loads. memdepunit.memDep.conflictingStores 127 # Number of conflicting stores. memdepunit.memDep.insertedLoads 1876 # Number of loads inserted to the mem dependence unit. @@ -269,7 +268,7 @@ system.cpu.ipc 0.611395 # IP system.cpu.ipc_total 0.611395 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0 7981 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist - (null) 2 0.03% # Type of FU issued + No_OpClass 2 0.03% # Type of FU issued IntAlu 5322 66.68% # Type of FU issued IntMult 1 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued @@ -287,7 +286,7 @@ system.cpu.iq.ISSUE:FU_type_0.end_dist system.cpu.iq.ISSUE:fu_busy_cnt 106 # FU busy when requested system.cpu.iq.ISSUE:fu_busy_rate 0.013282 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist - (null) 0 0.00% # attempts to use FU when none available + No_OpClass 0 0.00% # attempts to use FU when none available IntAlu 0 0.00% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout index 3ab3ef422..d935401d2 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout @@ -6,9 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled May 14 2007 16:35:50 -M5 started Tue May 15 12:18:39 2007 -M5 executing on zizzer.eecs.umich.edu -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing +M5 compiled Jun 10 2007 14:06:20 +M5 started Sun Jun 10 14:22:32 2007 +M5 executing on iceaxe +command line: /Users/nate/build/outgoing/build/ALPHA_SE/m5.debug -d /Users/nate/build/outgoing/build/ALPHA_SE/tests/debug/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second Exiting @ tick 4588000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini index bf00075ce..e4dfe86d3 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini @@ -53,7 +53,7 @@ bus_id=0 clock=1000 responder_set=false width=64 -port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port +port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=PhysicalMemory diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt index 4e1bd9447..f1c7bd968 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt @@ -1,9 +1,8 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 576538 # Simulator instruction rate (inst/s) -host_mem_usage 148208 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -host_tick_rate 276546720 # Simulator tick rate (ticks/s) +host_inst_rate 93019 # Simulator instruction rate (inst/s) +host_seconds 0.06 # Real time elapsed on the host +host_tick_rate 46199079 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5642 # Number of instructions simulated sim_seconds 0.000003 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout index 6848303a8..58fc0e374 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout @@ -6,9 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled May 14 2007 16:35:50 -M5 started Tue May 15 12:18:40 2007 -M5 executing on zizzer.eecs.umich.edu -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic tests/run.py quick/00.hello/alpha/linux/simple-atomic +M5 compiled Jun 10 2007 14:06:20 +M5 started Sun Jun 10 14:22:34 2007 +M5 executing on iceaxe +command line: /Users/nate/build/outgoing/build/ALPHA_SE/m5.debug -d /Users/nate/build/outgoing/build/ALPHA_SE/tests/debug/quick/00.hello/alpha/linux/simple-atomic tests/run.py quick/00.hello/alpha/linux/simple-atomic Global frequency set at 1000000000000 ticks per second Exiting @ tick 2820500 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini index 6daf0bd85..47315cc1d 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini @@ -44,7 +44,7 @@ prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=10000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -82,7 +82,7 @@ prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=10000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -120,7 +120,7 @@ prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=100000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -174,7 +174,7 @@ bus_id=0 clock=1000 responder_set=false width=64 -port=system.physmem.port system.cpu.l2cache.mem_side +port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out index 7041702bf..f7852a616 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out @@ -94,7 +94,7 @@ prefetch_access=false prefetcher_size=100 prefetch_past_page=false prefetch_serial_squash=false -prefetch_latency=10 +prefetch_latency=10000 prefetch_degree=1 prefetch_policy=none prefetch_cache_check_push=true @@ -131,7 +131,7 @@ prefetch_access=false prefetcher_size=100 prefetch_past_page=false prefetch_serial_squash=false -prefetch_latency=10 +prefetch_latency=10000 prefetch_degree=1 prefetch_policy=none prefetch_cache_check_push=true @@ -168,7 +168,7 @@ prefetch_access=false prefetcher_size=100 prefetch_past_page=false prefetch_serial_squash=false -prefetch_latency=10 +prefetch_latency=100000 prefetch_degree=1 prefetch_policy=none prefetch_cache_check_push=true diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt index ad908bf47..1b70f10b3 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt @@ -1,9 +1,8 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 280990 # Simulator instruction rate (inst/s) -host_mem_usage 153668 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -host_tick_rate 642654954 # Simulator tick rate (ticks/s) +host_inst_rate 54390 # Simulator instruction rate (inst/s) +host_seconds 0.10 # Real time elapsed on the host +host_tick_rate 126525357 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5642 # Number of instructions simulated sim_seconds 0.000013 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout index 3fc11f801..501ba5063 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout @@ -6,9 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled May 14 2007 16:35:50 -M5 started Tue May 15 12:18:40 2007 -M5 executing on zizzer.eecs.umich.edu -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing tests/run.py quick/00.hello/alpha/linux/simple-timing +M5 compiled Jun 10 2007 14:06:20 +M5 started Sun Jun 10 14:22:35 2007 +M5 executing on iceaxe +command line: /Users/nate/build/outgoing/build/ALPHA_SE/m5.debug -d /Users/nate/build/outgoing/build/ALPHA_SE/tests/debug/quick/00.hello/alpha/linux/simple-timing tests/run.py quick/00.hello/alpha/linux/simple-timing Global frequency set at 1000000000000 ticks per second Exiting @ tick 13168000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini index 40a8f1a84..e3080f9e5 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini @@ -99,7 +99,7 @@ prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=10000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -274,7 +274,7 @@ prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=10000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -312,7 +312,7 @@ prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=10000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -366,7 +366,7 @@ bus_id=0 clock=1000 responder_set=false width=64 -port=system.physmem.port system.cpu.l2cache.mem_side +port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out index 46dc2c36a..0cb6591c8 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out @@ -275,7 +275,7 @@ prefetch_access=false prefetcher_size=100 prefetch_past_page=false prefetch_serial_squash=false -prefetch_latency=10 +prefetch_latency=10000 prefetch_degree=1 prefetch_policy=none prefetch_cache_check_push=true @@ -312,7 +312,7 @@ prefetch_access=false prefetcher_size=100 prefetch_past_page=false prefetch_serial_squash=false -prefetch_latency=10 +prefetch_latency=10000 prefetch_degree=1 prefetch_policy=none prefetch_cache_check_push=true @@ -349,7 +349,7 @@ prefetch_access=false prefetcher_size=100 prefetch_past_page=false prefetch_serial_squash=false -prefetch_latency=10 +prefetch_latency=10000 prefetch_degree=1 prefetch_policy=none prefetch_cache_check_push=true diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt index c1b1b7625..6dd4c291d 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt @@ -8,10 +8,9 @@ global.BPredUnit.condIncorrect 208 # Nu global.BPredUnit.condPredicted 376 # Number of conditional branches predicted global.BPredUnit.lookups 738 # Number of BP lookups global.BPredUnit.usedRAS 140 # Number of times the RAS was used to get a target. -host_inst_rate 54176 # Simulator instruction rate (inst/s) -host_mem_usage 153592 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host -host_tick_rate 46286693 # Simulator tick rate (ticks/s) +host_inst_rate 8881 # Simulator instruction rate (inst/s) +host_seconds 0.27 # Real time elapsed on the host +host_tick_rate 7632084 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 8 # Number of conflicting loads. memdepunit.memDep.conflictingStores 7 # Number of conflicting stores. memdepunit.memDep.insertedLoads 608 # Number of loads inserted to the mem dependence unit. @@ -268,7 +267,7 @@ system.cpu.ipc 0.580920 # IP system.cpu.ipc_total 0.580920 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0 3075 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist - (null) 0 0.00% # Type of FU issued + No_OpClass 0 0.00% # Type of FU issued IntAlu 2178 70.83% # Type of FU issued IntMult 1 0.03% # Type of FU issued IntDiv 0 0.00% # Type of FU issued @@ -286,7 +285,7 @@ system.cpu.iq.ISSUE:FU_type_0.end_dist system.cpu.iq.ISSUE:fu_busy_cnt 35 # FU busy when requested system.cpu.iq.ISSUE:fu_busy_rate 0.011382 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist - (null) 0 0.00% # attempts to use FU when none available + No_OpClass 0 0.00% # attempts to use FU when none available IntAlu 2 5.71% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout index 587034bb2..60520dc0c 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout @@ -6,9 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled May 14 2007 16:35:50 -M5 started Tue May 15 12:18:41 2007 -M5 executing on zizzer.eecs.umich.edu -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing tests/run.py quick/00.hello/alpha/tru64/o3-timing +M5 compiled Jun 10 2007 14:06:20 +M5 started Sun Jun 10 14:22:36 2007 +M5 executing on iceaxe +command line: /Users/nate/build/outgoing/build/ALPHA_SE/m5.debug -d /Users/nate/build/outgoing/build/ALPHA_SE/tests/debug/quick/00.hello/alpha/tru64/o3-timing tests/run.py quick/00.hello/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second Exiting @ tick 2053000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini index 20dfddd0a..61db8446a 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini @@ -53,7 +53,7 @@ bus_id=0 clock=1000 responder_set=false width=64 -port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port +port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=PhysicalMemory diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt index e82d837af..29351d427 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt @@ -1,9 +1,8 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 484860 # Simulator instruction rate (inst/s) -host_mem_usage 147796 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -host_tick_rate 225459318 # Simulator tick rate (ticks/s) +host_inst_rate 111994 # Simulator instruction rate (inst/s) +host_seconds 0.02 # Real time elapsed on the host +host_tick_rate 55017079 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2578 # Number of instructions simulated sim_seconds 0.000001 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout index 3b5348194..f76500526 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout @@ -6,9 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled May 14 2007 16:35:50 -M5 started Tue May 15 12:18:42 2007 -M5 executing on zizzer.eecs.umich.edu -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic tests/run.py quick/00.hello/alpha/tru64/simple-atomic +M5 compiled Jun 10 2007 14:06:20 +M5 started Sun Jun 10 14:22:37 2007 +M5 executing on iceaxe +command line: /Users/nate/build/outgoing/build/ALPHA_SE/m5.debug -d /Users/nate/build/outgoing/build/ALPHA_SE/tests/debug/quick/00.hello/alpha/tru64/simple-atomic tests/run.py quick/00.hello/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second Exiting @ tick 1288500 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini index 1c1daa355..5a336ab13 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini @@ -44,7 +44,7 @@ prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=10000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -82,7 +82,7 @@ prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=10000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -120,7 +120,7 @@ prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=100000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -174,7 +174,7 @@ bus_id=0 clock=1000 responder_set=false width=64 -port=system.physmem.port system.cpu.l2cache.mem_side +port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out index 45a8521ac..241630ead 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out @@ -94,7 +94,7 @@ prefetch_access=false prefetcher_size=100 prefetch_past_page=false prefetch_serial_squash=false -prefetch_latency=10 +prefetch_latency=10000 prefetch_degree=1 prefetch_policy=none prefetch_cache_check_push=true @@ -131,7 +131,7 @@ prefetch_access=false prefetcher_size=100 prefetch_past_page=false prefetch_serial_squash=false -prefetch_latency=10 +prefetch_latency=10000 prefetch_degree=1 prefetch_policy=none prefetch_cache_check_push=true @@ -168,7 +168,7 @@ prefetch_access=false prefetcher_size=100 prefetch_past_page=false prefetch_serial_squash=false -prefetch_latency=10 +prefetch_latency=100000 prefetch_degree=1 prefetch_policy=none prefetch_cache_check_push=true diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt index 756244d02..621520fa3 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,9 +1,8 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 228404 # Simulator instruction rate (inst/s) -host_mem_usage 153176 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -host_tick_rate 552831639 # Simulator tick rate (ticks/s) +host_inst_rate 51133 # Simulator instruction rate (inst/s) +host_seconds 0.05 # Real time elapsed on the host +host_tick_rate 127514531 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2578 # Number of instructions simulated sim_seconds 0.000006 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout index f5e3a6008..1c6780cf0 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout @@ -6,9 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled May 14 2007 16:35:50 -M5 started Tue May 15 12:18:42 2007 -M5 executing on zizzer.eecs.umich.edu -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing tests/run.py quick/00.hello/alpha/tru64/simple-timing +M5 compiled Jun 10 2007 14:06:20 +M5 started Sun Jun 10 14:22:37 2007 +M5 executing on iceaxe +command line: /Users/nate/build/outgoing/build/ALPHA_SE/m5.debug -d /Users/nate/build/outgoing/build/ALPHA_SE/tests/debug/quick/00.hello/alpha/tru64/simple-timing tests/run.py quick/00.hello/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second Exiting @ tick 6472000 because target called exit() diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini index 5380fc831..e9dddb505 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini @@ -99,7 +99,7 @@ prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=10000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -274,7 +274,7 @@ prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=10000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -312,7 +312,7 @@ prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=10000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -382,7 +382,7 @@ bus_id=0 clock=1000 responder_set=false width=64 -port=system.physmem.port system.cpu.l2cache.mem_side +port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out index c8129d10d..45b063eb3 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out @@ -291,7 +291,7 @@ prefetch_access=false prefetcher_size=100 prefetch_past_page=false prefetch_serial_squash=false -prefetch_latency=10 +prefetch_latency=10000 prefetch_degree=1 prefetch_policy=none prefetch_cache_check_push=true @@ -328,7 +328,7 @@ prefetch_access=false prefetcher_size=100 prefetch_past_page=false prefetch_serial_squash=false -prefetch_latency=10 +prefetch_latency=10000 prefetch_degree=1 prefetch_policy=none prefetch_cache_check_push=true @@ -365,7 +365,7 @@ prefetch_access=false prefetcher_size=100 prefetch_past_page=false prefetch_serial_squash=false -prefetch_latency=10 +prefetch_latency=10000 prefetch_degree=1 prefetch_policy=none prefetch_cache_check_push=true diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt index 484bdcca9..dc1fcc248 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt @@ -8,10 +8,9 @@ global.BPredUnit.condIncorrect 1115 # Nu global.BPredUnit.condPredicted 2318 # Number of conditional branches predicted global.BPredUnit.lookups 3964 # Number of BP lookups global.BPredUnit.usedRAS 532 # Number of times the RAS was used to get a target. -host_inst_rate 56668 # Simulator instruction rate (inst/s) -host_mem_usage 154692 # Number of bytes of host memory used -host_seconds 0.20 # Real time elapsed on the host -host_tick_rate 27618195 # Simulator tick rate (ticks/s) +host_inst_rate 8215 # Simulator instruction rate (inst/s) +host_seconds 1.37 # Real time elapsed on the host +host_tick_rate 4009351 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 19 # Number of conflicting loads. memdepunit.memDep.conflictingLoads 18 # Number of conflicting loads. memdepunit.memDep.conflictingStores 54 # Number of conflicting stores. @@ -465,7 +464,7 @@ system.cpu.ipc_1 0.512251 # IP system.cpu.ipc_total 1.024410 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0 8232 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist - (null) 2 0.02% # Type of FU issued + No_OpClass 2 0.02% # Type of FU issued IntAlu 5551 67.43% # Type of FU issued IntMult 1 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued @@ -482,7 +481,7 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist system.cpu.iq.ISSUE:FU_type_0.end_dist system.cpu.iq.ISSUE:FU_type_1 8180 # Type of FU issued system.cpu.iq.ISSUE:FU_type_1.start_dist - (null) 2 0.02% # Type of FU issued + No_OpClass 2 0.02% # Type of FU issued IntAlu 5536 67.68% # Type of FU issued IntMult 1 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued @@ -499,7 +498,7 @@ system.cpu.iq.ISSUE:FU_type_1.start_dist system.cpu.iq.ISSUE:FU_type_1.end_dist system.cpu.iq.ISSUE:FU_type 16412 # Type of FU issued system.cpu.iq.ISSUE:FU_type.start_dist - (null) 4 0.02% # Type of FU issued + No_OpClass 4 0.02% # Type of FU issued IntAlu 11087 67.55% # Type of FU issued IntMult 2 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued @@ -521,7 +520,7 @@ system.cpu.iq.ISSUE:fu_busy_rate 0.010968 # FU system.cpu.iq.ISSUE:fu_busy_rate_0 0.005606 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_busy_rate_1 0.005362 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist - (null) 0 0.00% # attempts to use FU when none available + No_OpClass 0 0.00% # attempts to use FU when none available IntAlu 16 8.89% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout index ef617d5ef..6f3d2a7c5 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout @@ -7,9 +7,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled May 14 2007 16:35:50 -M5 started Tue May 15 12:18:42 2007 -M5 executing on zizzer.eecs.umich.edu -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing tests/run.py quick/01.hello-2T-smt/alpha/linux/o3-timing +M5 compiled Jun 10 2007 14:06:20 +M5 started Sun Jun 10 14:22:38 2007 +M5 executing on iceaxe +command line: /Users/nate/build/outgoing/build/ALPHA_SE/m5.debug -d /Users/nate/build/outgoing/build/ALPHA_SE/tests/debug/quick/01.hello-2T-smt/alpha/linux/o3-timing tests/run.py quick/01.hello-2T-smt/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second Exiting @ tick 5490000 because target called exit() diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini index 6e38281a1..2d3b1a754 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini @@ -76,7 +76,7 @@ prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=10000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -124,7 +124,7 @@ prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=10000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -198,7 +198,7 @@ prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=10000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -246,7 +246,7 @@ prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=10000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -345,7 +345,7 @@ prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=100000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -376,7 +376,7 @@ clock=1000 responder_set=false width=64 default=system.membus.responder.pio -port=system.bridge.side_b system.physmem.port system.l2c.mem_side +port=system.bridge.side_b system.physmem.port[0] system.l2c.mem_side [system.membus.responder] type=IsaFake diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out index 324ede6b4..1461f2550 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out @@ -86,7 +86,7 @@ prefetch_access=false prefetcher_size=100 prefetch_past_page=false prefetch_serial_squash=false -prefetch_latency=10 +prefetch_latency=100000 prefetch_degree=1 prefetch_policy=none prefetch_cache_check_push=true @@ -207,7 +207,7 @@ prefetch_access=false prefetcher_size=100 prefetch_past_page=false prefetch_serial_squash=false -prefetch_latency=10 +prefetch_latency=10000 prefetch_degree=1 prefetch_policy=none prefetch_cache_check_push=true @@ -249,7 +249,7 @@ prefetch_access=false prefetcher_size=100 prefetch_past_page=false prefetch_serial_squash=false -prefetch_latency=10 +prefetch_latency=10000 prefetch_degree=1 prefetch_policy=none prefetch_cache_check_push=true @@ -322,7 +322,7 @@ prefetch_access=false prefetcher_size=100 prefetch_past_page=false prefetch_serial_squash=false -prefetch_latency=10 +prefetch_latency=10000 prefetch_degree=1 prefetch_policy=none prefetch_cache_check_push=true @@ -364,7 +364,7 @@ prefetch_access=false prefetcher_size=100 prefetch_past_page=false prefetch_serial_squash=false -prefetch_latency=10 +prefetch_latency=10000 prefetch_degree=1 prefetch_policy=none prefetch_cache_check_push=true diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt index 7765c2852..033bc257f 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt @@ -1,9 +1,8 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 607412 # Simulator instruction rate (inst/s) -host_mem_usage 245896 # Number of bytes of host memory used -host_seconds 103.93 # Real time elapsed on the host -host_tick_rate 17996726251 # Simulator tick rate (ticks/s) +host_inst_rate 110028 # Simulator instruction rate (inst/s) +host_seconds 573.73 # Real time elapsed on the host +host_tick_rate 3259967057 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 63125943 # Number of instructions simulated sim_seconds 1.870335 # Number of seconds simulated diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr index 563ca3160..3e1cbc554 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr @@ -1,5 +1,5 @@ -Listening for system connection on port 3457 -0: system.remote_gdb.listener: listening for remote gdb on port 7001 -0: system.remote_gdb.listener: listening for remote gdb on port 7002 +Listening for system connection on port 3456 +0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000 +0: system.remote_gdb.listener: listening for remote gdb #1 on port 7001 warn: Entering event queue @ 0. Starting simulation... warn: 97861500: Trying to launch CPU number 1! diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout index 6afe2cfa0..e4b69d1d0 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout @@ -5,9 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled May 15 2007 19:06:05 -M5 started Tue May 15 19:06:07 2007 -M5 executing on zizzer.eecs.umich.edu -command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual +M5 compiled Jun 10 2007 14:10:03 +M5 started Mon Jun 11 01:04:58 2007 +M5 executing on iceaxe +command line: /Users/nate/build/outgoing/build/ALPHA_FS/m5.debug -d /Users/nate/build/outgoing/build/ALPHA_FS/tests/debug/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual Global frequency set at 1000000000000 ticks per second + 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 Exiting @ tick 1870335097000 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini index 791200f9a..0347fbde9 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini @@ -76,7 +76,7 @@ prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=10000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -124,7 +124,7 @@ prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=10000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -223,7 +223,7 @@ prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=100000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -254,7 +254,7 @@ clock=1000 responder_set=false width=64 default=system.membus.responder.pio -port=system.bridge.side_b system.physmem.port system.l2c.mem_side +port=system.bridge.side_b system.physmem.port[0] system.l2c.mem_side [system.membus.responder] type=IsaFake diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out index 94cc53f32..a196b7dc6 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out @@ -86,7 +86,7 @@ prefetch_access=false prefetcher_size=100 prefetch_past_page=false prefetch_serial_squash=false -prefetch_latency=10 +prefetch_latency=100000 prefetch_degree=1 prefetch_policy=none prefetch_cache_check_push=true @@ -722,7 +722,7 @@ prefetch_access=false prefetcher_size=100 prefetch_past_page=false prefetch_serial_squash=false -prefetch_latency=10 +prefetch_latency=10000 prefetch_degree=1 prefetch_policy=none prefetch_cache_check_push=true @@ -764,7 +764,7 @@ prefetch_access=false prefetcher_size=100 prefetch_past_page=false prefetch_serial_squash=false -prefetch_latency=10 +prefetch_latency=10000 prefetch_degree=1 prefetch_policy=none prefetch_cache_check_push=true diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt index aaa6c0c86..a2ea188c7 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt @@ -1,9 +1,8 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 577751 # Simulator instruction rate (inst/s) -host_mem_usage 244724 # Number of bytes of host memory used -host_seconds 103.86 # Real time elapsed on the host -host_tick_rate 17603359253 # Simulator tick rate (ticks/s) +host_inst_rate 109117 # Simulator instruction rate (inst/s) +host_seconds 549.94 # Real time elapsed on the host +host_tick_rate 3324672454 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 60007317 # Number of instructions simulated sim_seconds 1.828355 # Number of seconds simulated diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr index 072cb6c8c..f34493a86 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr @@ -1,3 +1,3 @@ Listening for system connection on port 3456 -0: system.remote_gdb.listener: listening for remote gdb on port 7000 +0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000 warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout index e47b6f226..6a6b8d735 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout @@ -5,9 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled May 15 2007 19:06:05 -M5 started Tue May 15 19:06:07 2007 -M5 executing on zizzer.eecs.umich.edu -command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic +M5 compiled Jun 10 2007 14:10:03 +M5 started Mon Jun 11 00:55:45 2007 +M5 executing on iceaxe +command line: /Users/nate/build/outgoing/build/ALPHA_FS/m5.debug -d /Users/nate/build/outgoing/build/ALPHA_FS/tests/debug/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic Global frequency set at 1000000000000 ticks per second + 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 Exiting @ tick 1828355481500 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini index 7bcdbdb71..552344dcb 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini @@ -74,7 +74,7 @@ prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=10000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -122,7 +122,7 @@ prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=10000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -194,7 +194,7 @@ prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=10000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -242,7 +242,7 @@ prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=10000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -341,7 +341,7 @@ prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=100000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -372,7 +372,7 @@ clock=1000 responder_set=false width=64 default=system.membus.responder.pio -port=system.bridge.side_b system.physmem.port system.l2c.mem_side +port=system.bridge.side_b system.physmem.port[0] system.l2c.mem_side [system.membus.responder] type=IsaFake diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out index 68698cf83..bb98fee3e 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out @@ -86,7 +86,7 @@ prefetch_access=false prefetcher_size=100 prefetch_past_page=false prefetch_serial_squash=false -prefetch_latency=10 +prefetch_latency=100000 prefetch_degree=1 prefetch_policy=none prefetch_cache_check_push=true @@ -207,7 +207,7 @@ prefetch_access=false prefetcher_size=100 prefetch_past_page=false prefetch_serial_squash=false -prefetch_latency=10 +prefetch_latency=10000 prefetch_degree=1 prefetch_policy=none prefetch_cache_check_push=true @@ -249,7 +249,7 @@ prefetch_access=false prefetcher_size=100 prefetch_past_page=false prefetch_serial_squash=false -prefetch_latency=10 +prefetch_latency=10000 prefetch_degree=1 prefetch_policy=none prefetch_cache_check_push=true @@ -322,7 +322,7 @@ prefetch_access=false prefetcher_size=100 prefetch_past_page=false prefetch_serial_squash=false -prefetch_latency=10 +prefetch_latency=10000 prefetch_degree=1 prefetch_policy=none prefetch_cache_check_push=true @@ -364,7 +364,7 @@ prefetch_access=false prefetcher_size=100 prefetch_past_page=false prefetch_serial_squash=false -prefetch_latency=10 +prefetch_latency=10000 prefetch_degree=1 prefetch_policy=none prefetch_cache_check_push=true diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt index 83bb77f93..0e86983a6 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt @@ -1,9 +1,8 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 213082 # Simulator instruction rate (inst/s) -host_mem_usage 203724 # Number of bytes of host memory used -host_seconds 296.83 # Real time elapsed on the host -host_tick_rate 6573231278 # Simulator tick rate (ticks/s) +host_inst_rate 62524 # Simulator instruction rate (inst/s) +host_seconds 1011.60 # Real time elapsed on the host +host_tick_rate 1928760125 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 63248814 # Number of instructions simulated sim_seconds 1.951129 # Number of seconds simulated diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr index dc84ff88b..af0df3710 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr @@ -1,5 +1,5 @@ -Listening for system connection on port 3457 -0: system.remote_gdb.listener: listening for remote gdb on port 7001 -0: system.remote_gdb.listener: listening for remote gdb on port 7002 +Listening for system connection on port 3456 +0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000 +0: system.remote_gdb.listener: listening for remote gdb #1 on port 7001 warn: Entering event queue @ 0. Starting simulation... warn: 423901000: Trying to launch CPU number 1! diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout index a3bd937f6..68b58c461 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout @@ -5,9 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled May 15 2007 19:06:05 -M5 started Tue May 15 19:07:53 2007 -M5 executing on zizzer.eecs.umich.edu -command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual +M5 compiled Jun 10 2007 14:10:03 +M5 started Mon Jun 11 01:30:38 2007 +M5 executing on iceaxe +command line: /Users/nate/build/outgoing/build/ALPHA_FS/m5.debug -d /Users/nate/build/outgoing/build/ALPHA_FS/tests/debug/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual Global frequency set at 1000000000000 ticks per second + 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 Exiting @ tick 1951129131000 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini index ded525737..c726f11fe 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini @@ -74,7 +74,7 @@ prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=10000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -122,7 +122,7 @@ prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=10000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -221,7 +221,7 @@ prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=100000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -252,7 +252,7 @@ clock=1000 responder_set=false width=64 default=system.membus.responder.pio -port=system.bridge.side_b system.physmem.port system.l2c.mem_side +port=system.bridge.side_b system.physmem.port[0] system.l2c.mem_side [system.membus.responder] type=IsaFake diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out index b51eb234e..e0e32bce4 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out @@ -86,7 +86,7 @@ prefetch_access=false prefetcher_size=100 prefetch_past_page=false prefetch_serial_squash=false -prefetch_latency=10 +prefetch_latency=100000 prefetch_degree=1 prefetch_policy=none prefetch_cache_check_push=true @@ -722,7 +722,7 @@ prefetch_access=false prefetcher_size=100 prefetch_past_page=false prefetch_serial_squash=false -prefetch_latency=10 +prefetch_latency=10000 prefetch_degree=1 prefetch_policy=none prefetch_cache_check_push=true @@ -764,7 +764,7 @@ prefetch_access=false prefetcher_size=100 prefetch_past_page=false prefetch_serial_squash=false -prefetch_latency=10 +prefetch_latency=10000 prefetch_degree=1 prefetch_policy=none prefetch_cache_check_push=true diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt index d9f42b16b..f72789e4b 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt @@ -1,9 +1,8 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 212380 # Simulator instruction rate (inst/s) -host_mem_usage 201984 # Number of bytes of host memory used -host_seconds 282.69 # Real time elapsed on the host -host_tick_rate 6746442466 # Simulator tick rate (ticks/s) +host_inst_rate 62427 # Simulator instruction rate (inst/s) +host_seconds 961.73 # Real time elapsed on the host +host_tick_rate 1983042717 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 60037406 # Number of instructions simulated sim_seconds 1.907146 # Number of seconds simulated diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr index 072cb6c8c..f34493a86 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr @@ -1,3 +1,3 @@ Listening for system connection on port 3456 -0: system.remote_gdb.listener: listening for remote gdb on port 7000 +0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000 warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout index b8196fe27..db9ad862d 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout @@ -5,9 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled May 15 2007 19:06:05 -M5 started Tue May 15 19:07:53 2007 -M5 executing on zizzer.eecs.umich.edu -command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing +M5 compiled Jun 10 2007 14:10:03 +M5 started Mon Jun 11 01:14:34 2007 +M5 executing on iceaxe +command line: /Users/nate/build/outgoing/build/ALPHA_FS/m5.debug -d /Users/nate/build/outgoing/build/ALPHA_FS/tests/debug/quick/10.linux-boot/alpha/linux/tsunami-simple-timing tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing Global frequency set at 1000000000000 ticks per second + 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 Exiting @ tick 1907146437000 because m5_exit instruction encountered diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini index 0431dd3db..a89c6ef26 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini @@ -44,7 +44,7 @@ bus_id=0 clock=1000 responder_set=false width=64 -port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port +port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=PhysicalMemory diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt index 7380e419f..5747db5c2 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt @@ -1,9 +1,8 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 819297 # Simulator instruction rate (inst/s) -host_mem_usage 147636 # Number of bytes of host memory used -host_seconds 0.61 # Real time elapsed on the host -host_tick_rate 409362131 # Simulator tick rate (ticks/s) +host_inst_rate 188118 # Simulator instruction rate (inst/s) +host_seconds 2.66 # Real time elapsed on the host +host_tick_rate 94046824 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 500000 # Number of instructions simulated sim_seconds 0.000250 # Number of seconds simulated diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout index c8bcb5723..01450bbce 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout @@ -7,9 +7,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled May 14 2007 16:35:50 -M5 started Tue May 15 12:18:43 2007 -M5 executing on zizzer.eecs.umich.edu -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic tests/run.py quick/20.eio-short/alpha/eio/simple-atomic +M5 compiled Jun 10 2007 14:06:20 +M5 started Sun Jun 10 14:22:41 2007 +M5 executing on iceaxe +command line: /Users/nate/build/outgoing/build/ALPHA_SE/m5.debug -d /Users/nate/build/outgoing/build/ALPHA_SE/tests/debug/quick/20.eio-short/alpha/eio/simple-atomic tests/run.py quick/20.eio-short/alpha/eio/simple-atomic Global frequency set at 1000000000000 ticks per second Exiting @ tick 249999500 because a thread reached the max instruction count diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini index c05a66f9d..e20143b89 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini @@ -44,7 +44,7 @@ prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=10000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -82,7 +82,7 @@ prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=10000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -120,7 +120,7 @@ prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=100000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -165,7 +165,7 @@ bus_id=0 clock=1000 responder_set=false width=64 -port=system.physmem.port system.cpu.l2cache.mem_side +port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out index 570ef7de8..e85a0bee1 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out @@ -85,7 +85,7 @@ prefetch_access=false prefetcher_size=100 prefetch_past_page=false prefetch_serial_squash=false -prefetch_latency=10 +prefetch_latency=10000 prefetch_degree=1 prefetch_policy=none prefetch_cache_check_push=true @@ -122,7 +122,7 @@ prefetch_access=false prefetcher_size=100 prefetch_past_page=false prefetch_serial_squash=false -prefetch_latency=10 +prefetch_latency=10000 prefetch_degree=1 prefetch_policy=none prefetch_cache_check_push=true @@ -159,7 +159,7 @@ prefetch_access=false prefetcher_size=100 prefetch_past_page=false prefetch_serial_squash=false -prefetch_latency=10 +prefetch_latency=100000 prefetch_degree=1 prefetch_policy=none prefetch_cache_check_push=true diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt index be87d3617..2ec710e81 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt @@ -1,9 +1,8 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 392036 # Simulator instruction rate (inst/s) -host_mem_usage 153128 # Number of bytes of host memory used -host_seconds 1.28 # Real time elapsed on the host -host_tick_rate 542334315 # Simulator tick rate (ticks/s) +host_inst_rate 83773 # Simulator instruction rate (inst/s) +host_seconds 5.97 # Real time elapsed on the host +host_tick_rate 115920990 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 500000 # Number of instructions simulated sim_seconds 0.000692 # Number of seconds simulated diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout index 83f216de6..a580fa457 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout @@ -7,9 +7,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled May 14 2007 16:35:50 -M5 started Tue May 15 12:18:44 2007 -M5 executing on zizzer.eecs.umich.edu -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing tests/run.py quick/20.eio-short/alpha/eio/simple-timing +M5 compiled Jun 10 2007 14:06:20 +M5 started Sun Jun 10 14:22:44 2007 +M5 executing on iceaxe +command line: /Users/nate/build/outgoing/build/ALPHA_SE/m5.debug -d /Users/nate/build/outgoing/build/ALPHA_SE/tests/debug/quick/20.eio-short/alpha/eio/simple-timing tests/run.py quick/20.eio-short/alpha/eio/simple-timing Global frequency set at 1000000000000 ticks per second Exiting @ tick 691915000 because a thread reached the max instruction count diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini index a6e3a8480..e30600052 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini @@ -42,7 +42,7 @@ prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=10000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -102,7 +102,7 @@ prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=10000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -162,7 +162,7 @@ prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=10000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -222,7 +222,7 @@ prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=10000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -282,7 +282,7 @@ prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=10000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -342,7 +342,7 @@ prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=10000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -402,7 +402,7 @@ prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=10000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -462,7 +462,7 @@ prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=10000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -513,7 +513,7 @@ prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=100000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.out b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.out index 53f718c0d..6bf1f2712 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.out +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.out @@ -52,7 +52,7 @@ prefetch_access=false prefetcher_size=100 prefetch_past_page=false prefetch_serial_squash=false -prefetch_latency=10 +prefetch_latency=100000 prefetch_degree=1 prefetch_policy=none prefetch_cache_check_push=true @@ -107,7 +107,7 @@ prefetch_access=false prefetcher_size=100 prefetch_past_page=false prefetch_serial_squash=false -prefetch_latency=10 +prefetch_latency=10000 prefetch_degree=1 prefetch_policy=none prefetch_cache_check_push=true @@ -162,7 +162,7 @@ prefetch_access=false prefetcher_size=100 prefetch_past_page=false prefetch_serial_squash=false -prefetch_latency=10 +prefetch_latency=10000 prefetch_degree=1 prefetch_policy=none prefetch_cache_check_push=true @@ -217,7 +217,7 @@ prefetch_access=false prefetcher_size=100 prefetch_past_page=false prefetch_serial_squash=false -prefetch_latency=10 +prefetch_latency=10000 prefetch_degree=1 prefetch_policy=none prefetch_cache_check_push=true @@ -272,7 +272,7 @@ prefetch_access=false prefetcher_size=100 prefetch_past_page=false prefetch_serial_squash=false -prefetch_latency=10 +prefetch_latency=10000 prefetch_degree=1 prefetch_policy=none prefetch_cache_check_push=true @@ -327,7 +327,7 @@ prefetch_access=false prefetcher_size=100 prefetch_past_page=false prefetch_serial_squash=false -prefetch_latency=10 +prefetch_latency=10000 prefetch_degree=1 prefetch_policy=none prefetch_cache_check_push=true @@ -382,7 +382,7 @@ prefetch_access=false prefetcher_size=100 prefetch_past_page=false prefetch_serial_squash=false -prefetch_latency=10 +prefetch_latency=10000 prefetch_degree=1 prefetch_policy=none prefetch_cache_check_push=true @@ -437,7 +437,7 @@ prefetch_access=false prefetcher_size=100 prefetch_past_page=false prefetch_serial_squash=false -prefetch_latency=10 +prefetch_latency=10000 prefetch_degree=1 prefetch_policy=none prefetch_cache_check_push=true @@ -499,7 +499,7 @@ prefetch_access=false prefetcher_size=100 prefetch_past_page=false prefetch_serial_squash=false -prefetch_latency=10 +prefetch_latency=10000 prefetch_degree=1 prefetch_policy=none prefetch_cache_check_push=true diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt b/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt index 2617dd49e..752268088 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt @@ -1,8 +1,7 @@ ---------- Begin Simulation Statistics ---------- -host_mem_usage 1265676 # Number of bytes of host memory used -host_seconds 390.60 # Real time elapsed on the host -host_tick_rate 215953 # Simulator tick rate (ticks/s) +host_seconds 37943.64 # Real time elapsed on the host +host_tick_rate 2223 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_seconds 0.000084 # Number of seconds simulated sim_ticks 84350509 # Number of ticks simulated diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout b/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout index 661781580..a77db6fb9 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled May 18 2007 23:44:20 -M5 started Fri May 18 23:46:19 2007 -M5 executing on zizzer.eecs.umich.edu -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest tests/run.py quick/50.memtest/alpha/linux/memtest +M5 compiled Jun 10 2007 14:06:20 +M5 started Sun Jun 10 14:22:51 2007 +M5 executing on iceaxe +command line: /Users/nate/build/outgoing/build/ALPHA_SE/m5.debug -d /Users/nate/build/outgoing/build/ALPHA_SE/tests/debug/quick/50.memtest/alpha/linux/memtest tests/run.py quick/50.memtest/alpha/linux/memtest Global frequency set at 1000000000000 ticks per second Exiting @ tick 84350509 because Maximum number of loads reached! diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini index 57b643510..c16d67687 100644 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini @@ -14,7 +14,7 @@ kernel=/dist/m5/system/binaries/vmlinux mem_mode=atomic pal=/dist/m5/system/binaries/ts_osfpal physmem=drivesys.physmem -readfile=/tmp/newmem/configs/boot/netperf-server.rcS +readfile=/Users/nate/work/m5/outgoing/configs/boot/netperf-server.rcS symbolfile= system_rev=1024 system_type=34 @@ -128,7 +128,7 @@ clock=1000 responder_set=false width=64 default=drivesys.membus.responder.pio -port=drivesys.bridge.side_b drivesys.physmem.port drivesys.cpu.icache_port drivesys.cpu.dcache_port +port=drivesys.bridge.side_b drivesys.physmem.port[0] drivesys.cpu.icache_port drivesys.cpu.dcache_port [drivesys.membus.responder] type=IsaFake @@ -704,7 +704,7 @@ kernel=/dist/m5/system/binaries/vmlinux mem_mode=atomic pal=/dist/m5/system/binaries/ts_osfpal physmem=testsys.physmem -readfile=/tmp/newmem/configs/boot/netperf-stream-client.rcS +readfile=/Users/nate/work/m5/outgoing/configs/boot/netperf-stream-client.rcS symbolfile= system_rev=1024 system_type=34 @@ -818,7 +818,7 @@ clock=1000 responder_set=false width=64 default=testsys.membus.responder.pio -port=testsys.bridge.side_b testsys.physmem.port testsys.cpu.icache_port testsys.cpu.dcache_port +port=testsys.bridge.side_b testsys.physmem.port[0] testsys.cpu.icache_port testsys.cpu.dcache_port [testsys.membus.responder] type=IsaFake diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out index 613664aec..1ed581be9 100644 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out @@ -18,7 +18,7 @@ kernel=/dist/m5/system/binaries/vmlinux console=/dist/m5/system/binaries/console pal=/dist/m5/system/binaries/ts_osfpal boot_osflags=root=/dev/hda1 console=ttyS0 -readfile=/tmp/newmem/configs/boot/netperf-stream-client.rcS +readfile=/Users/nate/work/m5/outgoing/configs/boot/netperf-stream-client.rcS symbolfile= init_param=0 system_type=34 @@ -643,7 +643,7 @@ kernel=/dist/m5/system/binaries/vmlinux console=/dist/m5/system/binaries/console pal=/dist/m5/system/binaries/ts_osfpal boot_osflags=root=/dev/hda1 console=ttyS0 -readfile=/tmp/newmem/configs/boot/netperf-server.rcS +readfile=/Users/nate/work/m5/outgoing/configs/boot/netperf-server.rcS symbolfile= init_param=0 system_type=34 diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt index 1a834ab03..e6bc6fb19 100644 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt @@ -139,10 +139,9 @@ drivesys.tsunami.ethernet.txPPS 25 # Pa drivesys.tsunami.ethernet.txPackets 5 # Number of Packets Transmitted drivesys.tsunami.ethernet.txTcpChecksums 2 # Number of tx TCP Checksums done by device drivesys.tsunami.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device -host_inst_rate 36401739 # Simulator instruction rate (inst/s) -host_mem_usage 388436 # Number of bytes of host memory used -host_seconds 7.51 # Real time elapsed on the host -host_tick_rate 26633033203 # Simulator tick rate (ticks/s) +host_inst_rate 6618724 # Simulator instruction rate (inst/s) +host_seconds 41.30 # Real time elapsed on the host +host_tick_rate 4842704130 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 273348482 # Number of instructions simulated sim_seconds 0.200001 # Number of seconds simulated @@ -381,10 +380,9 @@ drivesys.tsunami.ethernet.totalSwi 0 # to drivesys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR drivesys.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR drivesys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR -host_inst_rate 79025291125 # Simulator instruction rate (inst/s) -host_mem_usage 388436 # Number of bytes of host memory used +host_inst_rate 65191624612 # Simulator instruction rate (inst/s) host_seconds 0.00 # Real time elapsed on the host -host_tick_rate 211511841 # Simulator tick rate (ticks/s) +host_tick_rate 183725573 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 273348482 # Number of instructions simulated sim_seconds 0.000001 # Number of seconds simulated diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr index 045c1ddf7..8fb9590c3 100644 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr @@ -1,6 +1,6 @@ Listening for testsys connection on port 3456 -Listening for drivesys connection on port 3458 -0: testsys.remote_gdb.listener: listening for remote gdb on port 7000 -0: drivesys.remote_gdb.listener: listening for remote gdb on port 7003 +Listening for drivesys connection on port 3457 +0: testsys.remote_gdb.listener: listening for remote gdb #0 on port 7000 +0: drivesys.remote_gdb.listener: listening for remote gdb #1 on port 7001 warn: Entering event queue @ 0. Starting simulation... warn: Obsolete M5 instruction ivlb encountered. diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout index 4f93fd528..08d7271d7 100644 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout @@ -5,9 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled May 15 2007 19:06:05 -M5 started Tue May 15 19:12:37 2007 -M5 executing on zizzer.eecs.umich.edu -command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic tests/run.py quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic +M5 compiled Jun 10 2007 14:10:03 +M5 started Mon Jun 11 01:47:32 2007 +M5 executing on iceaxe +command line: /Users/nate/build/outgoing/build/ALPHA_FS/m5.debug -d /Users/nate/build/outgoing/build/ALPHA_FS/tests/debug/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic tests/run.py quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic Global frequency set at 1000000000000 ticks per second + 0: testsys.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 + 0: drivesys.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 Exiting @ tick 4300235844056 because checkpoint |