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-rw-r--r--SConstruct41
-rw-r--r--src/SConscript43
-rw-r--r--src/arch/SConscript35
-rw-r--r--src/arch/alpha/SConscript3
-rw-r--r--src/arch/alpha/arguments.cc6
-rw-r--r--src/arch/alpha/arguments.hh30
-rw-r--r--src/arch/alpha/ev5.cc10
-rw-r--r--src/arch/alpha/faults.cc2
-rw-r--r--src/arch/alpha/idle_event.cc45
-rw-r--r--src/arch/alpha/idle_event.hh47
-rw-r--r--src/arch/alpha/interrupts.hh166
-rw-r--r--src/arch/alpha/isa/decoder.isa6
-rw-r--r--src/arch/alpha/kernel_stats.cc211
-rw-r--r--src/arch/alpha/kernel_stats.hh96
-rw-r--r--src/arch/alpha/kgdb.h (renamed from src/base/kgdb.h)11
-rw-r--r--src/arch/alpha/linux/system.cc1
-rw-r--r--src/arch/alpha/linux/system.hh1
-rw-r--r--src/arch/alpha/remote_gdb.cc309
-rw-r--r--src/arch/alpha/remote_gdb.hh74
-rw-r--r--src/arch/alpha/stacktrace.cc518
-rw-r--r--src/arch/alpha/stacktrace.hh130
-rw-r--r--src/arch/alpha/system.cc6
-rw-r--r--src/arch/alpha/utility.hh6
-rw-r--r--src/arch/mips/stacktrace.hh5
-rw-r--r--src/arch/sparc/SConscript6
-rw-r--r--src/arch/sparc/arguments.cc73
-rw-r--r--src/arch/sparc/arguments.hh149
-rw-r--r--src/arch/sparc/asi.hh2
-rw-r--r--src/arch/sparc/faults.cc676
-rw-r--r--src/arch/sparc/faults.hh633
-rw-r--r--src/arch/sparc/interrupts.hh92
-rw-r--r--src/arch/sparc/kernel_stats.hh57
-rw-r--r--src/arch/sparc/miscregfile.cc147
-rw-r--r--src/arch/sparc/miscregfile.hh6
-rw-r--r--src/arch/sparc/remote_gdb.cc203
-rw-r--r--src/arch/sparc/remote_gdb.hh78
-rw-r--r--src/arch/sparc/stacktrace.cc372
-rw-r--r--src/arch/sparc/stacktrace.hh131
-rw-r--r--src/arch/sparc/system.cc13
-rw-r--r--src/arch/sparc/system.hh9
-rw-r--r--src/arch/sparc/tlb.cc79
-rw-r--r--src/arch/sparc/tlb.hh16
-rw-r--r--src/arch/sparc/utility.hh15
-rw-r--r--src/arch/sparc/vtophys.cc132
-rw-r--r--src/base/remote_gdb.cc476
-rw-r--r--src/base/remote_gdb.hh126
-rw-r--r--src/cpu/base.cc43
-rw-r--r--src/cpu/base.hh20
-rw-r--r--src/cpu/checker/cpu.cc2
-rw-r--r--src/cpu/checker/cpu.hh1
-rw-r--r--src/cpu/checker/thread_context.hh12
-rw-r--r--src/cpu/cpuevent.hh2
-rw-r--r--src/cpu/o3/alpha/cpu.hh3
-rw-r--r--src/cpu/o3/alpha/cpu_impl.hh51
-rw-r--r--src/cpu/o3/alpha/dyn_inst.hh2
-rw-r--r--src/cpu/o3/alpha/dyn_inst_impl.hh9
-rw-r--r--src/cpu/o3/alpha/thread_context.hh5
-rw-r--r--src/cpu/o3/commit_impl.hh7
-rw-r--r--src/cpu/o3/fetch_impl.hh14
-rw-r--r--src/cpu/o3/regfile.hh3
-rwxr-xr-xsrc/cpu/o3/thread_context.hh2
-rwxr-xr-xsrc/cpu/o3/thread_context_impl.hh2
-rw-r--r--src/cpu/ozone/cpu.hh14
-rw-r--r--src/cpu/ozone/cpu_impl.hh8
-rw-r--r--src/cpu/ozone/dyn_inst.hh1
-rw-r--r--src/cpu/ozone/dyn_inst_impl.hh12
-rw-r--r--src/cpu/ozone/front_end_impl.hh9
-rw-r--r--src/cpu/ozone/inorder_back_end_impl.hh6
-rw-r--r--src/cpu/ozone/lw_back_end_impl.hh3
-rw-r--r--src/cpu/pc_event.hh1
-rw-r--r--src/cpu/profile.hh4
-rw-r--r--src/cpu/simple/base.cc54
-rw-r--r--src/cpu/simple/base.hh1
-rw-r--r--src/cpu/simple_thread.cc8
-rw-r--r--src/cpu/simple_thread.hh10
-rw-r--r--src/cpu/thread_context.hh18
-rw-r--r--src/cpu/thread_state.cc2
-rw-r--r--src/cpu/thread_state.hh10
-rw-r--r--src/dev/SConscript79
-rw-r--r--src/dev/alpha/SConscript68
-rw-r--r--src/dev/alpha/access.h (renamed from src/dev/alpha_access.h)0
-rw-r--r--src/dev/alpha/console.cc (renamed from src/dev/alpha_console.cc)2
-rw-r--r--src/dev/alpha/console.hh (renamed from src/dev/alpha_console.hh)2
-rw-r--r--src/dev/alpha/tsunami.cc (renamed from src/dev/tsunami.cc)8
-rw-r--r--src/dev/alpha/tsunami.hh (renamed from src/dev/tsunami.hh)0
-rw-r--r--src/dev/alpha/tsunami_cchip.cc (renamed from src/dev/tsunami_cchip.cc)6
-rw-r--r--src/dev/alpha/tsunami_cchip.hh (renamed from src/dev/tsunami_cchip.hh)2
-rw-r--r--src/dev/alpha/tsunami_io.cc (renamed from src/dev/tsunami_io.cc)8
-rw-r--r--src/dev/alpha/tsunami_io.hh (renamed from src/dev/tsunami_io.hh)2
-rw-r--r--src/dev/alpha/tsunami_pchip.cc (renamed from src/dev/tsunami_pchip.cc)6
-rw-r--r--src/dev/alpha/tsunami_pchip.hh (renamed from src/dev/tsunami_pchip.hh)2
-rw-r--r--src/dev/alpha/tsunamireg.h (renamed from src/dev/tsunamireg.h)0
-rw-r--r--src/dev/ide_disk.cc4
-rw-r--r--src/dev/isa_fake.hh2
-rw-r--r--src/dev/ns_gige.cc1
-rw-r--r--src/dev/pcidev.cc2
-rw-r--r--src/dev/sparc/SConscript46
-rw-r--r--src/dev/uart8250.cc1
-rw-r--r--src/dev/uart8250.hh2
-rw-r--r--src/kern/SConscript48
-rw-r--r--src/kern/kernel_stats.cc156
-rw-r--r--src/kern/kernel_stats.hh36
-rw-r--r--src/kern/linux/events.cc2
-rw-r--r--src/kern/linux/printk.cc2
-rw-r--r--src/kern/linux/printk.hh6
-rw-r--r--src/kern/system_events.cc24
-rw-r--r--src/kern/system_events.hh11
-rw-r--r--src/kern/tru64/dump_mbuf.cc2
-rw-r--r--src/kern/tru64/dump_mbuf.hh2
-rw-r--r--src/kern/tru64/printf.cc2
-rw-r--r--src/kern/tru64/printf.hh2
-rw-r--r--src/kern/tru64/tru64_events.cc6
-rw-r--r--src/mem/port_impl.hh7
-rw-r--r--src/sim/pseudo_inst.cc16
-rw-r--r--src/sim/pseudo_inst.hh2
-rw-r--r--src/sim/system.cc2
-rw-r--r--src/sim/system.hh7
-rw-r--r--util/m5/m5.c4
-rw-r--r--util/m5/m5op.S17
-rw-r--r--util/m5/m5op.h2
120 files changed, 3964 insertions, 2267 deletions
diff --git a/SConstruct b/SConstruct
index 59d40d5cc..d047f99d3 100644
--- a/SConstruct
+++ b/SConstruct
@@ -461,6 +461,46 @@ env.SConscript('ext/libelf/SConscript',
###################################################
#
+# This function is used to set up a directory with switching headers
+#
+###################################################
+
+def make_switching_dir(dirname, switch_headers, env):
+ # Generate the header. target[0] is the full path of the output
+ # header to generate. 'source' is a dummy variable, since we get the
+ # list of ISAs from env['ALL_ISA_LIST'].
+ def gen_switch_hdr(target, source, env):
+ fname = str(target[0])
+ basename = os.path.basename(fname)
+ f = open(fname, 'w')
+ f.write('#include "arch/isa_specific.hh"\n')
+ cond = '#if'
+ for isa in env['ALL_ISA_LIST']:
+ f.write('%s THE_ISA == %s_ISA\n#include "%s/%s/%s"\n'
+ % (cond, isa.upper(), dirname, isa, basename))
+ cond = '#elif'
+ f.write('#else\n#error "THE_ISA not set"\n#endif\n')
+ f.close()
+ return 0
+
+ # String to print when generating header
+ def gen_switch_hdr_string(target, source, env):
+ return "Generating switch header " + str(target[0])
+
+ # Build SCons Action object. 'varlist' specifies env vars that this
+ # action depends on; when env['ALL_ISA_LIST'] changes these actions
+ # should get re-executed.
+ switch_hdr_action = Action(gen_switch_hdr, gen_switch_hdr_string,
+ varlist=['ALL_ISA_LIST'])
+
+ # Instantiate actions for each header
+ for hdr in switch_headers:
+ env.Command(hdr, [], switch_hdr_action)
+
+env.make_switching_dir = make_switching_dir
+
+###################################################
+#
# Define build environments for selected configurations.
#
###################################################
@@ -566,6 +606,7 @@ for build_path in build_paths:
Help(help_text)
+
###################################################
#
# Let SCons do its thing. At this point SCons will use the defined
diff --git a/src/SConscript b/src/SConscript
index 8d2c8566b..b9664dd39 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -211,40 +211,9 @@ full_system_sources = Split('''
cpu/intr_control.cc
cpu/profile.cc
- dev/alpha_console.cc
- dev/baddev.cc
- dev/disk_image.cc
- dev/etherbus.cc
- dev/etherdump.cc
- dev/etherint.cc
- dev/etherlink.cc
- dev/etherpkt.cc
- dev/ethertap.cc
- dev/ide_ctrl.cc
- dev/ide_disk.cc
- dev/io_device.cc
- dev/isa_fake.cc
- dev/ns_gige.cc
- dev/pciconfigall.cc
- dev/pcidev.cc
- dev/pktfifo.cc
- dev/platform.cc
- dev/simconsole.cc
- dev/simple_disk.cc
- dev/tsunami.cc
- dev/tsunami_cchip.cc
- dev/tsunami_io.cc
- dev/tsunami_pchip.cc
-
dev/uart.cc
dev/uart8250.cc
- kern/kernel_stats.cc
- kern/system_events.cc
- kern/linux/events.cc
- kern/linux/linux_syscalls.cc
- kern/linux/printk.cc
-
mem/vport.cc
sim/pseudo_inst.cc
@@ -252,7 +221,6 @@ full_system_sources = Split('''
#dev/sinic.cc
#dev/i8254xGBe.cc
-
if env['TARGET_ISA'] == 'alpha':
full_system_sources += Split('''
kern/tru64/dump_mbuf.cc
@@ -316,9 +284,16 @@ env.Append(CPPPATH=Dir('.'))
# Add a flag defining what THE_ISA should be for all compilation
env.Append(CPPDEFINES=[('THE_ISA','%s_ISA' % env['TARGET_ISA'].upper())])
-arch_sources = SConscript('arch/SConscript', exports = 'env')
+arch_sources = SConscript(os.path.join('arch', 'SConscript'), exports = 'env')
+
+cpu_sources = SConscript(os.path.join('cpu', 'SConscript'), exports = 'env')
+
+if env['FULL_SYSTEM']:
+ dev_sources = SConscript(os.path.join('dev', 'SConscript'), exports = 'env')
+ full_system_sources += dev_sources
-cpu_sources = SConscript('cpu/SConscript', exports = 'env')
+ kern_sources = SConscript(os.path.join('kern', 'SConscript'), exports = 'env')
+ full_system_sources += kern_sources
# This is outside of cpu/SConscript since the source directory isn't
# underneath 'cpu'.
diff --git a/src/arch/SConscript b/src/arch/SConscript
index dda1dea53..bbe3c4e3a 100644
--- a/src/arch/SConscript
+++ b/src/arch/SConscript
@@ -49,10 +49,13 @@ sources = []
isa_switch_hdrs = Split('''
arguments.hh
faults.hh
+ interrupts.hh
isa_traits.hh
+ kernel_stats.hh
locked_mem.hh
process.hh
regfile.hh
+ remote_gdb.hh
stacktrace.hh
syscallreturn.hh
tlb.hh
@@ -61,36 +64,8 @@ isa_switch_hdrs = Split('''
vtophys.hh
''')
-# Generate the header. target[0] is the full path of the output
-# header to generate. 'source' is a dummy variable, since we get the
-# list of ISAs from env['ALL_ISA_LIST'].
-def gen_switch_hdr(target, source, env):
- fname = str(target[0])
- basename = os.path.basename(fname)
- f = open(fname, 'w')
- f.write('#include "arch/isa_specific.hh"\n')
- cond = '#if'
- for isa in env['ALL_ISA_LIST']:
- f.write('%s THE_ISA == %s_ISA\n#include "arch/%s/%s"\n'
- % (cond, isa.upper(), isa, basename))
- cond = '#elif'
- f.write('#else\n#error "THE_ISA not set"\n#endif\n')
- f.close()
- return 0
-
-# String to print when generating header
-def gen_switch_hdr_string(target, source, env):
- return "Generating ISA switch header " + str(target[0])
-
-# Build SCons Action object. 'varlist' specifies env vars that this
-# action depends on; when env['ALL_ISA_LIST'] changes these actions
-# should get re-executed.
-switch_hdr_action = Action(gen_switch_hdr, gen_switch_hdr_string,
- varlist=['ALL_ISA_LIST'])
-
-# Instantiate actions for each header
-for hdr in isa_switch_hdrs:
- env.Command(hdr, [], switch_hdr_action)
+# Set up this directory to support switching headers
+env.make_switching_dir('arch', isa_switch_hdrs, env)
#################################################################
#
diff --git a/src/arch/alpha/SConscript b/src/arch/alpha/SConscript
index 9a5680649..3947ec23a 100644
--- a/src/arch/alpha/SConscript
+++ b/src/arch/alpha/SConscript
@@ -56,10 +56,13 @@ full_system_sources = Split('''
tlb.cc
arguments.cc
ev5.cc
+ idle_event.cc
ipr.cc
+ kernel_stats.cc
osfpal.cc
stacktrace.cc
vtophys.cc
+ remote_gdb.cc
system.cc
freebsd/system.cc
linux/system.cc
diff --git a/src/arch/alpha/arguments.cc b/src/arch/alpha/arguments.cc
index 9f9002003..e89bd70b0 100644
--- a/src/arch/alpha/arguments.cc
+++ b/src/arch/alpha/arguments.cc
@@ -35,7 +35,7 @@
using namespace AlphaISA;
-AlphaArguments::Data::~Data()
+Arguments::Data::~Data()
{
while (!data.empty()) {
delete [] data.front();
@@ -44,7 +44,7 @@ AlphaArguments::Data::~Data()
}
char *
-AlphaArguments::Data::alloc(size_t size)
+Arguments::Data::alloc(size_t size)
{
char *buf = new char[size];
data.push_back(buf);
@@ -52,7 +52,7 @@ AlphaArguments::Data::alloc(size_t size)
}
uint64_t
-AlphaArguments::getArg(bool fp)
+Arguments::getArg(bool fp)
{
if (number < 6) {
if (fp)
diff --git a/src/arch/alpha/arguments.hh b/src/arch/alpha/arguments.hh
index d977d48d6..c44181a8d 100644
--- a/src/arch/alpha/arguments.hh
+++ b/src/arch/alpha/arguments.hh
@@ -41,7 +41,7 @@ class ThreadContext;
namespace AlphaISA {
-class AlphaArguments
+class Arguments
{
protected:
ThreadContext *tc;
@@ -65,62 +65,62 @@ class AlphaArguments
RefCountingPtr<Data> data;
public:
- AlphaArguments(ThreadContext *ctx, int n = 0)
+ Arguments(ThreadContext *ctx, int n = 0)
: tc(ctx), number(n), data(NULL)
{ assert(number >= 0); data = new Data;}
- AlphaArguments(const AlphaArguments &args)
+ Arguments(const Arguments &args)
: tc(args.tc), number(args.number), data(args.data) {}
- ~AlphaArguments() {}
+ ~Arguments() {}
ThreadContext *getThreadContext() const { return tc; }
- const AlphaArguments &operator=(const AlphaArguments &args) {
+ const Arguments &operator=(const Arguments &args) {
tc = args.tc;
number = args.number;
data = args.data;
return *this;
}
- AlphaArguments &operator++() {
+ Arguments &operator++() {
++number;
assert(number >= 0);
return *this;
}
- AlphaArguments operator++(int) {
- AlphaArguments args = *this;
+ Arguments operator++(int) {
+ Arguments args = *this;
++number;
assert(number >= 0);
return args;
}
- AlphaArguments &operator--() {
+ Arguments &operator--() {
--number;
assert(number >= 0);
return *this;
}
- AlphaArguments operator--(int) {
- AlphaArguments args = *this;
+ Arguments operator--(int) {
+ Arguments args = *this;
--number;
assert(number >= 0);
return args;
}
- const AlphaArguments &operator+=(int index) {
+ const Arguments &operator+=(int index) {
number += index;
assert(number >= 0);
return *this;
}
- const AlphaArguments &operator-=(int index) {
+ const Arguments &operator-=(int index) {
number -= index;
assert(number >= 0);
return *this;
}
- AlphaArguments operator[](int index) {
- return AlphaArguments(tc, index);
+ Arguments operator[](int index) {
+ return Arguments(tc, index);
}
template <class T>
diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc
index 314b445e0..59f9d2fb5 100644
--- a/src/arch/alpha/ev5.cc
+++ b/src/arch/alpha/ev5.cc
@@ -31,16 +31,16 @@
#include "arch/alpha/faults.hh"
#include "arch/alpha/isa_traits.hh"
+#include "arch/alpha/kernel_stats.hh"
#include "arch/alpha/osfpal.hh"
#include "arch/alpha/tlb.hh"
-#include "base/kgdb.h"
+#include "arch/alpha/kgdb.h"
#include "base/remote_gdb.hh"
#include "base/stats/events.hh"
#include "config/full_system.hh"
#include "cpu/base.hh"
#include "cpu/simple_thread.hh"
#include "cpu/thread_context.hh"
-#include "kern/kernel_stats.hh"
#include "sim/debug.hh"
#include "sim/sim_exit.hh"
@@ -147,7 +147,7 @@ AlphaISA::zeroRegisters(CPU *cpu)
Fault
SimpleThread::hwrei()
{
- if (!inPalMode())
+ if (!(readPC() & 0x3))
return new UnimplementedOpcodeFault;
setNextPC(readMiscReg(AlphaISA::IPR_EXC_ADDR));
@@ -379,10 +379,10 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc)
case AlphaISA::IPR_DTB_CM:
if (val & 0x18) {
if (tc->getKernelStats())
- tc->getKernelStats()->mode(Kernel::user, tc);
+ tc->getKernelStats()->mode(TheISA::Kernel::user, tc);
} else {
if (tc->getKernelStats())
- tc->getKernelStats()->mode(Kernel::kernel, tc);
+ tc->getKernelStats()->mode(TheISA::Kernel::kernel, tc);
}
case AlphaISA::IPR_ICM:
diff --git a/src/arch/alpha/faults.cc b/src/arch/alpha/faults.cc
index 7179bf025..5efcf92e4 100644
--- a/src/arch/alpha/faults.cc
+++ b/src/arch/alpha/faults.cc
@@ -125,7 +125,7 @@ void AlphaFault::invoke(ThreadContext * tc)
countStat()++;
// exception restart address
- if (setRestartAddress() || !tc->inPalMode())
+ if (setRestartAddress() || !(tc->readPC() & 0x3))
tc->setMiscReg(AlphaISA::IPR_EXC_ADDR, tc->readPC());
if (skipFaultingInstruction()) {
diff --git a/src/arch/alpha/idle_event.cc b/src/arch/alpha/idle_event.cc
new file mode 100644
index 000000000..0f6806319
--- /dev/null
+++ b/src/arch/alpha/idle_event.cc
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Lisa Hsu
+ * Nathan Binkert
+ */
+
+#include "arch/alpha/idle_event.hh"
+#include "arch/alpha/kernel_stats.hh"
+#include "cpu/thread_context.hh"
+
+using namespace TheISA;
+
+void
+IdleStartEvent::process(ThreadContext *tc)
+{
+ if (tc->getKernelStats())
+ tc->getKernelStats()->setIdleProcess(
+ tc->readMiscReg(AlphaISA::IPR_PALtemp23), tc);
+ remove();
+}
diff --git a/src/arch/alpha/idle_event.hh b/src/arch/alpha/idle_event.hh
new file mode 100644
index 000000000..97d5bdd6e
--- /dev/null
+++ b/src/arch/alpha/idle_event.hh
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Nathan Binkert
+ * Lisa Hsu
+ * Ali Saidi
+ */
+
+#ifndef __KERN_ALPHA_IDLE_EVENT_HH__
+#define __KERN_ALPHA_IDLE_EVENT_HH__
+
+#include "cpu/pc_event.hh"
+
+class IdleStartEvent : public PCEvent
+{
+ public:
+ IdleStartEvent(PCEventQueue *q, const std::string &desc, Addr addr)
+ : PCEvent(q, desc, addr)
+ {}
+ virtual void process(ThreadContext *tc);
+};
+
+#endif // __KERN_ALPHA_IDLE_EVENT_HH__
diff --git a/src/arch/alpha/interrupts.hh b/src/arch/alpha/interrupts.hh
new file mode 100644
index 000000000..75031ae47
--- /dev/null
+++ b/src/arch/alpha/interrupts.hh
@@ -0,0 +1,166 @@
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Steve Reinhardt
+ * Kevin Lim
+ */
+
+#ifndef __ARCH_ALPHA_INTERRUPT_HH__
+#define __ARCH_ALPHA_INTERRUPT_HH__
+
+#include "arch/alpha/faults.hh"
+#include "arch/alpha/isa_traits.hh"
+#include "cpu/thread_context.hh"
+
+namespace AlphaISA
+{
+ class Interrupts
+ {
+ protected:
+ uint64_t interrupts[NumInterruptLevels];
+ uint64_t intstatus;
+
+ public:
+ Interrupts()
+ {
+ memset(interrupts, 0, sizeof(interrupts));
+ intstatus = 0;
+ }
+
+ void post(int int_num, int index)
+ {
+ DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index);
+
+ if (int_num < 0 || int_num >= NumInterruptLevels)
+ panic("int_num out of bounds\n");
+
+ if (index < 0 || index >= sizeof(uint64_t) * 8)
+ panic("int_num out of bounds\n");
+
+ interrupts[int_num] |= 1 << index;
+ intstatus |= (ULL(1) << int_num);
+ }
+
+ void clear(int int_num, int index)
+ {
+ DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index);
+
+ if (int_num < 0 || int_num >= TheISA::NumInterruptLevels)
+ panic("int_num out of bounds\n");
+
+ if (index < 0 || index >= sizeof(uint64_t) * 8)
+ panic("int_num out of bounds\n");
+
+ interrupts[int_num] &= ~(1 << index);
+ if (interrupts[int_num] == 0)
+ intstatus &= ~(ULL(1) << int_num);
+ }
+
+ void clear_all()
+ {
+ DPRINTF(Interrupt, "Interrupts all cleared\n");
+
+ memset(interrupts, 0, sizeof(interrupts));
+ intstatus = 0;
+ }
+
+ void serialize(std::ostream &os)
+ {
+ SERIALIZE_ARRAY(interrupts, NumInterruptLevels);
+ SERIALIZE_SCALAR(intstatus);
+ }
+
+ void unserialize(Checkpoint *cp, const std::string &section)
+ {
+ UNSERIALIZE_ARRAY(interrupts, NumInterruptLevels);
+ UNSERIALIZE_SCALAR(intstatus);
+ }
+
+ bool check_interrupts(ThreadContext * tc) const
+ {
+ return (intstatus != 0) && !(tc->readPC() & 0x3);
+ }
+
+ Fault getInterrupt(ThreadContext * tc)
+ {
+ int ipl = 0;
+ int summary = 0;
+
+ if (tc->readMiscReg(IPR_ASTRR))
+ panic("asynchronous traps not implemented\n");
+
+ if (tc->readMiscReg(IPR_SIRR)) {
+ for (int i = INTLEVEL_SOFTWARE_MIN;
+ i < INTLEVEL_SOFTWARE_MAX; i++) {
+ if (tc->readMiscReg(IPR_SIRR) & (ULL(1) << i)) {
+ // See table 4-19 of 21164 hardware reference
+ ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
+ summary |= (ULL(1) << i);
+ }
+ }
+ }
+
+ uint64_t interrupts = intstatus;
+ if (interrupts) {
+ for (int i = INTLEVEL_EXTERNAL_MIN;
+ i < INTLEVEL_EXTERNAL_MAX; i++) {
+ if (interrupts & (ULL(1) << i)) {
+ // See table 4-19 of 21164 hardware reference
+ ipl = i;
+ summary |= (ULL(1) << i);
+ }
+ }
+ }
+
+ if (ipl && ipl > tc->readMiscReg(IPR_IPLR)) {
+ tc->setMiscReg(IPR_ISR, summary);
+ tc->setMiscReg(IPR_INTID, ipl);
+
+ /* The following needs to be added back in somehow */
+ // Checker needs to know these two registers were updated.
+/*#if USE_CHECKER
+ if (this->checker) {
+ this->checker->threadBase()->setMiscReg(IPR_ISR, summary);
+ this->checker->threadBase()->setMiscReg(IPR_INTID, ipl);
+ }
+#endif*/
+
+ DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
+ tc->readMiscReg(IPR_IPLR), ipl, summary);
+
+ return new InterruptFault;
+ } else {
+ return NoFault;
+ }
+ }
+
+ private:
+ };
+}
+
+#endif
+
diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa
index be6f574a9..7014d4c22 100644
--- a/src/arch/alpha/isa/decoder.isa
+++ b/src/arch/alpha/isa/decoder.isa
@@ -795,12 +795,6 @@ decode OPCODE default Unknown::unknown() {
0x04: quiesceTime({{
R0 = AlphaPseudo::quiesceTime(xc->tcBase());
}}, IsNonSpeculative, IsUnverifiable);
- 0x10: ivlb({{
- AlphaPseudo::ivlb(xc->tcBase());
- }}, No_OpClass, IsNonSpeculative);
- 0x11: ivle({{
- AlphaPseudo::ivle(xc->tcBase());
- }}, No_OpClass, IsNonSpeculative);
0x20: m5exit_old({{
AlphaPseudo::m5exit_old(xc->tcBase());
}}, No_OpClass, IsNonSpeculative);
diff --git a/src/arch/alpha/kernel_stats.cc b/src/arch/alpha/kernel_stats.cc
new file mode 100644
index 000000000..6fc3cb72f
--- /dev/null
+++ b/src/arch/alpha/kernel_stats.cc
@@ -0,0 +1,211 @@
+/*
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Lisa Hsu
+ * Nathan Binkert
+ */
+
+#include <map>
+#include <stack>
+#include <string>
+
+#include "arch/alpha/kernel_stats.hh"
+#include "arch/alpha/osfpal.hh"
+#include "base/trace.hh"
+#include "cpu/thread_context.hh"
+#include "kern/tru64/tru64_syscalls.hh"
+#include "sim/system.hh"
+
+using namespace std;
+using namespace Stats;
+
+namespace AlphaISA {
+namespace Kernel {
+
+const char *modestr[] = { "kernel", "user", "idle" };
+
+Statistics::Statistics(System *system)
+ : ::Kernel::Statistics(system),
+ idleProcess((Addr)-1), themode(kernel), lastModeTick(0)
+{
+}
+
+void
+Statistics::regStats(const string &_name)
+{
+ ::Kernel::Statistics::regStats(_name);
+
+ _callpal
+ .init(256)
+ .name(name() + ".callpal")
+ .desc("number of callpals executed")
+ .flags(total | pdf | nozero | nonan)
+ ;
+
+ for (int i = 0; i < PAL::NumCodes; ++i) {
+ const char *str = PAL::name(i);
+ if (str)
+ _callpal.subname(i, str);
+ }
+
+ _hwrei
+ .name(name() + ".inst.hwrei")
+ .desc("number of hwrei instructions executed")
+ ;
+
+ _mode
+ .init(cpu_mode_num)
+ .name(name() + ".mode_switch")
+ .desc("number of protection mode switches")
+ ;
+
+ for (int i = 0; i < cpu_mode_num; ++i)
+ _mode.subname(i, modestr[i]);
+
+ _modeGood
+ .init(cpu_mode_num)
+ .name(name() + ".mode_good")
+ ;
+
+ for (int i = 0; i < cpu_mode_num; ++i)
+ _modeGood.subname(i, modestr[i]);
+
+ _modeFraction
+ .name(name() + ".mode_switch_good")
+ .desc("fraction of useful protection mode switches")
+ .flags(total)
+ ;
+
+ for (int i = 0; i < cpu_mode_num; ++i)
+ _modeFraction.subname(i, modestr[i]);
+
+ _modeFraction = _modeGood / _mode;
+
+ _modeTicks
+ .init(cpu_mode_num)
+ .name(name() + ".mode_ticks")
+ .desc("number of ticks spent at the given mode")
+ .flags(pdf)
+ ;
+ for (int i = 0; i < cpu_mode_num; ++i)
+ _modeTicks.subname(i, modestr[i]);
+
+ _swap_context
+ .name(name() + ".swap_context")
+ .desc("number of times the context was actually changed")
+ ;
+}
+
+void
+Statistics::setIdleProcess(Addr idlepcbb, ThreadContext *tc)
+{
+ assert(themode == kernel);
+ idleProcess = idlepcbb;
+ themode = idle;
+ changeMode(themode, tc);
+}
+
+void
+Statistics::changeMode(cpu_mode newmode, ThreadContext *tc)
+{
+ _mode[newmode]++;
+
+ if (newmode == themode)
+ return;
+
+ DPRINTF(Context, "old mode=%-8s new mode=%-8s\n",
+ modestr[themode], modestr[newmode]);
+
+ _modeGood[newmode]++;
+ _modeTicks[themode] += curTick - lastModeTick;
+
+ lastModeTick = curTick;
+ themode = newmode;
+}
+
+void
+Statistics::mode(cpu_mode newmode, ThreadContext *tc)
+{
+ Addr pcbb = tc->readMiscReg(AlphaISA::IPR_PALtemp23);
+
+ if (newmode == kernel && pcbb == idleProcess)
+ newmode = idle;
+
+ changeMode(newmode, tc);
+}
+
+void
+Statistics::context(Addr oldpcbb, Addr newpcbb, ThreadContext *tc)
+{
+ assert(themode != user);
+
+ _swap_context++;
+ changeMode(newpcbb == idleProcess ? idle : kernel, tc);
+}
+
+void
+Statistics::callpal(int code, ThreadContext *tc)
+{
+ if (!PAL::name(code))
+ return;
+
+ _callpal[code]++;
+
+ switch (code) {
+ case PAL::callsys: {
+ int number = tc->readIntReg(0);
+ if (SystemCalls<Tru64>::validSyscallNumber(number)) {
+ int cvtnum = SystemCalls<Tru64>::convert(number);
+ _syscall[cvtnum]++;
+ }
+ } break;
+ }
+}
+
+void
+Statistics::serialize(ostream &os)
+{
+ ::Kernel::Statistics::serialize(os);
+ int exemode = themode;
+ SERIALIZE_SCALAR(exemode);
+ SERIALIZE_SCALAR(idleProcess);
+ SERIALIZE_SCALAR(lastModeTick);
+}
+
+void
+Statistics::unserialize(Checkpoint *cp, const string &section)
+{
+ ::Kernel::Statistics::unserialize(cp, section);
+ int exemode;
+ UNSERIALIZE_SCALAR(exemode);
+ UNSERIALIZE_SCALAR(idleProcess);
+ UNSERIALIZE_SCALAR(lastModeTick);
+ themode = (cpu_mode)exemode;
+}
+
+} /* end namespace AlphaISA::Kernel */
+} /* end namespace AlphaISA */
diff --git a/src/arch/alpha/kernel_stats.hh b/src/arch/alpha/kernel_stats.hh
new file mode 100644
index 000000000..7b8640ad7
--- /dev/null
+++ b/src/arch/alpha/kernel_stats.hh
@@ -0,0 +1,96 @@
+/*
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Lisa Hsu
+ * Nathan Binkert
+ */
+
+#ifndef __ARCH_ALPHA_KERNEL_STATS_HH__
+#define __ARCH_ALPHA_KERNEL_STATS_HH__
+
+#include <map>
+#include <stack>
+#include <string>
+#include <vector>
+
+#include "cpu/static_inst.hh"
+#include "kern/kernel_stats.hh"
+
+class BaseCPU;
+class ThreadContext;
+class FnEvent;
+// What does kernel stats expect is included?
+class System;
+
+namespace AlphaISA {
+namespace Kernel {
+
+enum cpu_mode { kernel, user, idle, cpu_mode_num };
+extern const char *modestr[];
+
+class Statistics : public ::Kernel::Statistics
+{
+ protected:
+ Addr idleProcess;
+ cpu_mode themode;
+ Tick lastModeTick;
+
+ void changeMode(cpu_mode newmode, ThreadContext *tc);
+
+ private:
+ Stats::Vector<> _callpal;
+// Stats::Vector<> _faults;
+
+ Stats::Vector<> _mode;
+ Stats::Vector<> _modeGood;
+ Stats::Formula _modeFraction;
+ Stats::Vector<> _modeTicks;
+
+ Stats::Scalar<> _swap_context;
+
+ public:
+ Statistics(System *system);
+
+ void regStats(const std::string &name);
+
+ public:
+ void mode(cpu_mode newmode, ThreadContext *tc);
+ void context(Addr oldpcbb, Addr newpcbb, ThreadContext *tc);
+ void callpal(int code, ThreadContext *tc);
+ void hwrei() { _hwrei++; }
+
+ void setIdleProcess(Addr idle, ThreadContext *tc);
+
+ public:
+ void serialize(std::ostream &os);
+ void unserialize(Checkpoint *cp, const std::string &section);
+};
+
+} /* end namespace AlphaISA::Kernel */
+} /* end namespace AlphaISA */
+
+#endif // __ARCH_ALPHA_KERNEL_STATS_HH__
diff --git a/src/base/kgdb.h b/src/arch/alpha/kgdb.h
index 104244d0b..912cf6d45 100644
--- a/src/base/kgdb.h
+++ b/src/arch/alpha/kgdb.h
@@ -160,15 +160,4 @@
/* Too much? Must be large enough for register transfer. */
#define KGDB_BUFLEN 1024
-/*
- * Kernel Entry Vectors. [OSF/1 PALcode Specific]
- */
-
-#define ALPHA_KENTRY_INT 0
-#define ALPHA_KENTRY_ARITH 1
-#define ALPHA_KENTRY_MM 2
-#define ALPHA_KENTRY_IF 3
-#define ALPHA_KENTRY_UNA 4
-#define ALPHA_KENTRY_SYS 5
-
#endif /* __KGDB_H__ */
diff --git a/src/arch/alpha/linux/system.cc b/src/arch/alpha/linux/system.cc
index 7cf234eeb..9a452e10f 100644
--- a/src/arch/alpha/linux/system.cc
+++ b/src/arch/alpha/linux/system.cc
@@ -42,6 +42,7 @@
#include "arch/arguments.hh"
#include "arch/vtophys.hh"
+#include "arch/alpha/idle_event.hh"
#include "arch/alpha/linux/system.hh"
#include "arch/alpha/linux/threadinfo.hh"
#include "arch/alpha/system.hh"
diff --git a/src/arch/alpha/linux/system.hh b/src/arch/alpha/linux/system.hh
index 6921ba820..14396f8ab 100644
--- a/src/arch/alpha/linux/system.hh
+++ b/src/arch/alpha/linux/system.hh
@@ -38,6 +38,7 @@ class ThreadContext;
class BreakPCEvent;
class IdleStartEvent;
+#include "arch/alpha/idle_event.hh"
#include "arch/alpha/system.hh"
#include "kern/linux/events.hh"
diff --git a/src/arch/alpha/remote_gdb.cc b/src/arch/alpha/remote_gdb.cc
new file mode 100644
index 000000000..f23fc3205
--- /dev/null
+++ b/src/arch/alpha/remote_gdb.cc
@@ -0,0 +1,309 @@
+/*
+ * Copyright (c) 2002-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Nathan Binkert
+ */
+
+/*
+ * Copyright (c) 1990, 1993
+ * The Regents of the University of California. All rights reserved.
+ *
+ * This software was developed by the Computer Systems Engineering group
+ * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
+ * contributed to Berkeley.
+ *
+ * All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by the University of
+ * California, Lawrence Berkeley Laboratories.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by the University of
+ * California, Berkeley and its contributors.
+ * 4. Neither the name of the University nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * @(#)kgdb_stub.c 8.4 (Berkeley) 1/12/94
+ */
+
+/*-
+ * Copyright (c) 2001 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Jason R. Thorpe.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by the NetBSD
+ * Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * $NetBSD: kgdb_stub.c,v 1.8 2001/07/07 22:58:00 wdk Exp $
+ *
+ * Taken from NetBSD
+ *
+ * "Stub" to allow remote cpu to debug over a serial line using gdb.
+ */
+
+#include <sys/signal.h>
+
+#include <string>
+#include <unistd.h>
+
+#include "arch/alpha/kgdb.h"
+#include "arch/alpha/remote_gdb.hh"
+#include "arch/vtophys.hh"
+#include "base/intmath.hh"
+#include "base/remote_gdb.hh"
+#include "base/socket.hh"
+#include "base/trace.hh"
+#include "config/full_system.hh"
+#include "cpu/thread_context.hh"
+#include "cpu/static_inst.hh"
+#include "mem/physical.hh"
+#include "mem/port.hh"
+#include "sim/system.hh"
+
+using namespace std;
+using namespace TheISA;
+
+RemoteGDB::RemoteGDB(System *_system, ThreadContext *c)
+ : BaseRemoteGDB(_system, c, KGDB_NUMREGS)
+{
+ memset(gdbregs.regs, 0, gdbregs.bytes());
+}
+
+///////////////////////////////////////////////////////////
+// RemoteGDB::acc
+//
+// Determine if the mapping at va..(va+len) is valid.
+//
+bool
+RemoteGDB::acc(Addr va, size_t len)
+{
+ Addr last_va;
+
+ va = TheISA::TruncPage(va);
+ last_va = TheISA::RoundPage(va + len);
+
+ do {
+ if (TheISA::IsK0Seg(va)) {
+ if (va < (TheISA::K0SegBase + pmem->size())) {
+ DPRINTF(GDBAcc, "acc: Mapping is valid K0SEG <= "
+ "%#x < K0SEG + size\n", va);
+ return true;
+ } else {
+ DPRINTF(GDBAcc, "acc: Mapping invalid %#x > K0SEG + size\n",
+ va);
+ return false;
+ }
+ }
+
+ /**
+ * This code says that all accesses to palcode (instruction and data)
+ * are valid since there isn't a va->pa mapping because palcode is
+ * accessed physically. At some point this should probably be cleaned up
+ * but there is no easy way to do it.
+ */
+
+ if (AlphaISA::PcPAL(va) || va < 0x10000)
+ return true;
+
+ Addr ptbr = context->readMiscReg(AlphaISA::IPR_PALtemp20);
+ TheISA::PageTableEntry pte = TheISA::kernel_pte_lookup(context->getPhysPort(), ptbr, va);
+ if (!pte.valid()) {
+ DPRINTF(GDBAcc, "acc: %#x pte is invalid\n", va);
+ return false;
+ }
+ va += TheISA::PageBytes;
+ } while (va < last_va);
+
+ DPRINTF(GDBAcc, "acc: %#x mapping is valid\n", va);
+ return true;
+}
+
+///////////////////////////////////////////////////////////
+// RemoteGDB::getregs
+//
+// Translate the kernel debugger register format into
+// the GDB register format.
+void
+RemoteGDB::getregs()
+{
+ memset(gdbregs.regs, 0, gdbregs.bytes());
+
+ gdbregs.regs[KGDB_REG_PC] = context->readPC();
+
+ // @todo: Currently this is very Alpha specific.
+ if (AlphaISA::PcPAL(gdbregs.regs[KGDB_REG_PC])) {
+ for (int i = 0; i < TheISA::NumIntArchRegs; ++i) {
+ gdbregs.regs[i] = context->readIntReg(AlphaISA::reg_redir[i]);
+ }
+ } else {
+ for (int i = 0; i < TheISA::NumIntArchRegs; ++i) {
+ gdbregs.regs[i] = context->readIntReg(i);
+ }
+ }
+
+#ifdef KGDB_FP_REGS
+ for (int i = 0; i < TheISA::NumFloatArchRegs; ++i) {
+ gdbregs.regs[i + KGDB_REG_F0] = context->readFloatRegBits(i);
+ }
+#endif
+}
+
+///////////////////////////////////////////////////////////
+// RemoteGDB::setregs
+//
+// Translate the GDB register format into the kernel
+// debugger register format.
+//
+void
+RemoteGDB::setregs()
+{
+ // @todo: Currently this is very Alpha specific.
+ if (AlphaISA::PcPAL(gdbregs.regs[KGDB_REG_PC])) {
+ for (int i = 0; i < TheISA::NumIntArchRegs; ++i) {
+ context->setIntReg(AlphaISA::reg_redir[i], gdbregs.regs[i]);
+ }
+ } else {
+ for (int i = 0; i < TheISA::NumIntArchRegs; ++i) {
+ context->setIntReg(i, gdbregs.regs[i]);
+ }
+ }
+
+#ifdef KGDB_FP_REGS
+ for (int i = 0; i < TheISA::NumFloatArchRegs; ++i) {
+ context->setFloatRegBits(i, gdbregs.regs[i + KGDB_REG_F0]);
+ }
+#endif
+ context->setPC(gdbregs.regs[KGDB_REG_PC]);
+}
+
+void
+RemoteGDB::clearSingleStep()
+{
+ DPRINTF(GDBMisc, "clearSingleStep bt_addr=%#x nt_addr=%#x\n",
+ takenBkpt, notTakenBkpt);
+
+ if (takenBkpt != 0)
+ clearTempBreakpoint(takenBkpt);
+
+ if (notTakenBkpt != 0)
+ clearTempBreakpoint(notTakenBkpt);
+}
+
+void
+RemoteGDB::setSingleStep()
+{
+ Addr pc = context->readPC();
+ Addr npc, bpc;
+ bool set_bt = false;
+
+ npc = pc + sizeof(MachInst);
+
+ // User was stopped at pc, e.g. the instruction at pc was not
+ // executed.
+ MachInst inst = read<MachInst>(pc);
+ StaticInstPtr si(inst);
+ if (si->hasBranchTarget(pc, context, bpc)) {
+ // Don't bother setting a breakpoint on the taken branch if it
+ // is the same as the next pc
+ if (bpc != npc)
+ set_bt = true;
+ }
+
+ DPRINTF(GDBMisc, "setSingleStep bt_addr=%#x nt_addr=%#x\n",
+ takenBkpt, notTakenBkpt);
+
+ setTempBreakpoint(notTakenBkpt = npc);
+
+ if (set_bt)
+ setTempBreakpoint(takenBkpt = bpc);
+}
+
+// Write bytes to kernel address space for debugger.
+bool
+RemoteGDB::write(Addr vaddr, size_t size, const char *data)
+{
+ if (BaseRemoteGDB::write(vaddr, size, data)) {
+#ifdef IMB
+ alpha_pal_imb();
+#endif
+ return true;
+ } else {
+ return false;
+ }
+}
+
diff --git a/src/arch/alpha/remote_gdb.hh b/src/arch/alpha/remote_gdb.hh
new file mode 100644
index 000000000..7bef183c3
--- /dev/null
+++ b/src/arch/alpha/remote_gdb.hh
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2002-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Nathan Binkert
+ */
+
+#ifndef __ARCH_ALPHA_REMOTE_GDB_HH__
+#define __ARCH_ALPHA_REMOTE_GDB_HH__
+
+#include <map>
+
+#include "arch/alpha/types.hh"
+#include "arch/alpha/kgdb.h"
+#include "base/remote_gdb.hh"
+#include "cpu/pc_event.hh"
+#include "base/pollevent.hh"
+#include "base/socket.hh"
+
+class System;
+class ThreadContext;
+class PhysicalMemory;
+
+namespace AlphaISA
+{
+ class RemoteGDB : public BaseRemoteGDB
+ {
+ protected:
+ // Machine memory
+ bool write(Addr addr, size_t size, const char *data);
+
+ public:
+ RemoteGDB(System *system, ThreadContext *context);
+
+ bool acc(Addr addr, size_t len);
+
+ protected:
+ void getregs();
+ void setregs();
+
+ void clearSingleStep();
+ void setSingleStep();
+
+ protected:
+
+ Addr notTakenBkpt;
+ Addr takenBkpt;
+ };
+}
+
+#endif /* __ARCH_ALPHA_REMOTE_GDB_H__ */
diff --git a/src/arch/alpha/stacktrace.cc b/src/arch/alpha/stacktrace.cc
index d70a4d6dd..c4612e156 100644
--- a/src/arch/alpha/stacktrace.cc
+++ b/src/arch/alpha/stacktrace.cc
@@ -40,329 +40,331 @@
#include "sim/system.hh"
using namespace std;
-using namespace AlphaISA;
-ProcessInfo::ProcessInfo(ThreadContext *_tc)
- : tc(_tc)
+namespace AlphaISA
{
- Addr addr = 0;
+ ProcessInfo::ProcessInfo(ThreadContext *_tc)
+ : tc(_tc)
+ {
+ Addr addr = 0;
- VirtualPort *vp;
+ VirtualPort *vp;
- vp = tc->getVirtPort();
+ vp = tc->getVirtPort();
- if (!tc->getSystemPtr()->kernelSymtab->findAddress("thread_info_size", addr))
- panic("thread info not compiled into kernel\n");
- thread_info_size = vp->readGtoH<int32_t>(addr);
+ if (!tc->getSystemPtr()->kernelSymtab->findAddress("thread_info_size", addr))
+ panic("thread info not compiled into kernel\n");
+ thread_info_size = vp->readGtoH<int32_t>(addr);
- if (!tc->getSystemPtr()->kernelSymtab->findAddress("task_struct_size", addr))
- panic("thread info not compiled into kernel\n");
- task_struct_size = vp->readGtoH<int32_t>(addr);
+ if (!tc->getSystemPtr()->kernelSymtab->findAddress("task_struct_size", addr))
+ panic("thread info not compiled into kernel\n");
+ task_struct_size = vp->readGtoH<int32_t>(addr);
- if (!tc->getSystemPtr()->kernelSymtab->findAddress("thread_info_task", addr))
- panic("thread info not compiled into kernel\n");
- task_off = vp->readGtoH<int32_t>(addr);
+ if (!tc->getSystemPtr()->kernelSymtab->findAddress("thread_info_task", addr))
+ panic("thread info not compiled into kernel\n");
+ task_off = vp->readGtoH<int32_t>(addr);
- if (!tc->getSystemPtr()->kernelSymtab->findAddress("task_struct_pid", addr))
- panic("thread info not compiled into kernel\n");
- pid_off = vp->readGtoH<int32_t>(addr);
+ if (!tc->getSystemPtr()->kernelSymtab->findAddress("task_struct_pid", addr))
+ panic("thread info not compiled into kernel\n");
+ pid_off = vp->readGtoH<int32_t>(addr);
- if (!tc->getSystemPtr()->kernelSymtab->findAddress("task_struct_comm", addr))
- panic("thread info not compiled into kernel\n");
- name_off = vp->readGtoH<int32_t>(addr);
+ if (!tc->getSystemPtr()->kernelSymtab->findAddress("task_struct_comm", addr))
+ panic("thread info not compiled into kernel\n");
+ name_off = vp->readGtoH<int32_t>(addr);
- tc->delVirtPort(vp);
-}
-
-Addr
-ProcessInfo::task(Addr ksp) const
-{
- Addr base = ksp & ~0x3fff;
- if (base == ULL(0xfffffc0000000000))
- return 0;
+ tc->delVirtPort(vp);
+ }
- Addr tsk;
+ Addr
+ ProcessInfo::task(Addr ksp) const
+ {
+ Addr base = ksp & ~0x3fff;
+ if (base == ULL(0xfffffc0000000000))
+ return 0;
- VirtualPort *vp;
+ Addr tsk;
- vp = tc->getVirtPort();
- tsk = vp->readGtoH<Addr>(base + task_off);
- tc->delVirtPort(vp);
+ VirtualPort *vp;
- return tsk;
-}
+ vp = tc->getVirtPort();
+ tsk = vp->readGtoH<Addr>(base + task_off);
+ tc->delVirtPort(vp);
-int
-ProcessInfo::pid(Addr ksp) const
-{
- Addr task = this->task(ksp);
- if (!task)
- return -1;
+ return tsk;
+ }
- uint16_t pd;
+ int
+ ProcessInfo::pid(Addr ksp) const
+ {
+ Addr task = this->task(ksp);
+ if (!task)
+ return -1;
- VirtualPort *vp;
+ uint16_t pd;
- vp = tc->getVirtPort();
- pd = vp->readGtoH<uint16_t>(task + pid_off);
- tc->delVirtPort(vp);
+ VirtualPort *vp;
- return pd;
-}
+ vp = tc->getVirtPort();
+ pd = vp->readGtoH<uint16_t>(task + pid_off);
+ tc->delVirtPort(vp);
-string
-ProcessInfo::name(Addr ksp) const
-{
- Addr task = this->task(ksp);
- if (!task)
- return "console";
+ return pd;
+ }
- char comm[256];
- CopyStringOut(tc, comm, task + name_off, sizeof(comm));
- if (!comm[0])
- return "startup";
+ string
+ ProcessInfo::name(Addr ksp) const
+ {
+ Addr task = this->task(ksp);
+ if (!task)
+ return "console";
- return comm;
-}
+ char comm[256];
+ CopyStringOut(tc, comm, task + name_off, sizeof(comm));
+ if (!comm[0])
+ return "startup";
-StackTrace::StackTrace()
- : tc(0), stack(64)
-{
-}
+ return comm;
+ }
-StackTrace::StackTrace(ThreadContext *_tc, StaticInstPtr inst)
- : tc(0), stack(64)
-{
- trace(_tc, inst);
-}
+ StackTrace::StackTrace()
+ : tc(0), stack(64)
+ {
+ }
-StackTrace::~StackTrace()
-{
-}
+ StackTrace::StackTrace(ThreadContext *_tc, StaticInstPtr inst)
+ : tc(0), stack(64)
+ {
+ trace(_tc, inst);
+ }
-void
-StackTrace::trace(ThreadContext *_tc, bool is_call)
-{
- tc = _tc;
+ StackTrace::~StackTrace()
+ {
+ }
- bool usermode = (tc->readMiscReg(AlphaISA::IPR_DTB_CM) & 0x18) != 0;
+ void
+ StackTrace::trace(ThreadContext *_tc, bool is_call)
+ {
+ tc = _tc;
- Addr pc = tc->readNextPC();
- bool kernel = tc->getSystemPtr()->kernelStart <= pc &&
- pc <= tc->getSystemPtr()->kernelEnd;
+ bool usermode = (tc->readMiscReg(AlphaISA::IPR_DTB_CM) & 0x18) != 0;
- if (usermode) {
- stack.push_back(user);
- return;
- }
+ Addr pc = tc->readNextPC();
+ bool kernel = tc->getSystemPtr()->kernelStart <= pc &&
+ pc <= tc->getSystemPtr()->kernelEnd;
- if (!kernel) {
- stack.push_back(console);
- return;
- }
+ if (usermode) {
+ stack.push_back(user);
+ return;
+ }
- SymbolTable *symtab = tc->getSystemPtr()->kernelSymtab;
- Addr ksp = tc->readIntReg(TheISA::StackPointerReg);
- Addr bottom = ksp & ~0x3fff;
- Addr addr;
+ if (!kernel) {
+ stack.push_back(console);
+ return;
+ }
- if (is_call) {
- if (!symtab->findNearestAddr(pc, addr))
- panic("could not find address %#x", pc);
+ SymbolTable *symtab = tc->getSystemPtr()->kernelSymtab;
+ Addr ksp = tc->readIntReg(TheISA::StackPointerReg);
+ Addr bottom = ksp & ~0x3fff;
+ Addr addr;
- stack.push_back(addr);
- pc = tc->readPC();
- }
+ if (is_call) {
+ if (!symtab->findNearestAddr(pc, addr))
+ panic("could not find address %#x", pc);
- Addr ra;
- int size;
+ stack.push_back(addr);
+ pc = tc->readPC();
+ }
- while (ksp > bottom) {
- if (!symtab->findNearestAddr(pc, addr))
- panic("could not find symbol for pc=%#x", pc);
- assert(pc >= addr && "symbol botch: callpc < func");
+ Addr ra;
+ int size;
- stack.push_back(addr);
+ while (ksp > bottom) {
+ if (!symtab->findNearestAddr(pc, addr))
+ panic("could not find symbol for pc=%#x", pc);
+ assert(pc >= addr && "symbol botch: callpc < func");
- if (isEntry(addr))
- return;
+ stack.push_back(addr);
- if (decodePrologue(ksp, pc, addr, size, ra)) {
- if (!ra)
+ if (isEntry(addr))
return;
- if (size <= 0) {
+ if (decodePrologue(ksp, pc, addr, size, ra)) {
+ if (!ra)
+ return;
+
+ if (size <= 0) {
+ stack.push_back(unknown);
+ return;
+ }
+
+ pc = ra;
+ ksp += size;
+ } else {
stack.push_back(unknown);
return;
}
- pc = ra;
- ksp += size;
- } else {
- stack.push_back(unknown);
- return;
- }
+ bool kernel = tc->getSystemPtr()->kernelStart <= pc &&
+ pc <= tc->getSystemPtr()->kernelEnd;
+ if (!kernel)
+ return;
- bool kernel = tc->getSystemPtr()->kernelStart <= pc &&
- pc <= tc->getSystemPtr()->kernelEnd;
- if (!kernel)
- return;
+ if (stack.size() >= 1000)
+ panic("unwinding too far");
+ }
- if (stack.size() >= 1000)
- panic("unwinding too far");
+ panic("unwinding too far");
}
- panic("unwinding too far");
-}
+ bool
+ StackTrace::isEntry(Addr addr)
+ {
+ if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp12))
+ return true;
-bool
-StackTrace::isEntry(Addr addr)
-{
- if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp12))
- return true;
+ if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp7))
+ return true;
- if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp7))
- return true;
+ if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp11))
+ return true;
- if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp11))
- return true;
+ if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp21))
+ return true;
- if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp21))
- return true;
+ if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp9))
+ return true;
- if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp9))
- return true;
-
- if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp2))
- return true;
+ if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp2))
+ return true;
- return false;
-}
-
-bool
-StackTrace::decodeStack(MachInst inst, int &disp)
-{
- // lda $sp, -disp($sp)
- //
- // Opcode<31:26> == 0x08
- // RA<25:21> == 30
- // RB<20:16> == 30
- // Disp<15:0>
- const MachInst mem_mask = 0xffff0000;
- const MachInst lda_pattern = 0x23de0000;
- const MachInst lda_disp_mask = 0x0000ffff;
-
- // subq $sp, disp, $sp
- // addq $sp, disp, $sp
- //
- // Opcode<31:26> == 0x10
- // RA<25:21> == 30
- // Lit<20:13>
- // One<12> = 1
- // Func<11:5> == 0x20 (addq)
- // Func<11:5> == 0x29 (subq)
- // RC<4:0> == 30
- const MachInst intop_mask = 0xffe01fff;
- const MachInst addq_pattern = 0x43c0141e;
- const MachInst subq_pattern = 0x43c0153e;
- const MachInst intop_disp_mask = 0x001fe000;
- const int intop_disp_shift = 13;
-
- if ((inst & mem_mask) == lda_pattern)
- disp = -sext<16>(inst & lda_disp_mask);
- else if ((inst & intop_mask) == addq_pattern)
- disp = -int((inst & intop_disp_mask) >> intop_disp_shift);
- else if ((inst & intop_mask) == subq_pattern)
- disp = int((inst & intop_disp_mask) >> intop_disp_shift);
- else
return false;
+ }
- return true;
-}
+ bool
+ StackTrace::decodeStack(MachInst inst, int &disp)
+ {
+ // lda $sp, -disp($sp)
+ //
+ // Opcode<31:26> == 0x08
+ // RA<25:21> == 30
+ // RB<20:16> == 30
+ // Disp<15:0>
+ const MachInst mem_mask = 0xffff0000;
+ const MachInst lda_pattern = 0x23de0000;
+ const MachInst lda_disp_mask = 0x0000ffff;
+
+ // subq $sp, disp, $sp
+ // addq $sp, disp, $sp
+ //
+ // Opcode<31:26> == 0x10
+ // RA<25:21> == 30
+ // Lit<20:13>
+ // One<12> = 1
+ // Func<11:5> == 0x20 (addq)
+ // Func<11:5> == 0x29 (subq)
+ // RC<4:0> == 30
+ const MachInst intop_mask = 0xffe01fff;
+ const MachInst addq_pattern = 0x43c0141e;
+ const MachInst subq_pattern = 0x43c0153e;
+ const MachInst intop_disp_mask = 0x001fe000;
+ const int intop_disp_shift = 13;
+
+ if ((inst & mem_mask) == lda_pattern)
+ disp = -sext<16>(inst & lda_disp_mask);
+ else if ((inst & intop_mask) == addq_pattern)
+ disp = -int((inst & intop_disp_mask) >> intop_disp_shift);
+ else if ((inst & intop_mask) == subq_pattern)
+ disp = int((inst & intop_disp_mask) >> intop_disp_shift);
+ else
+ return false;
-bool
-StackTrace::decodeSave(MachInst inst, int &reg, int &disp)
-{
- // lda $stq, disp($sp)
- //
- // Opcode<31:26> == 0x08
- // RA<25:21> == ?
- // RB<20:16> == 30
- // Disp<15:0>
- const MachInst stq_mask = 0xfc1f0000;
- const MachInst stq_pattern = 0xb41e0000;
- const MachInst stq_disp_mask = 0x0000ffff;
- const MachInst reg_mask = 0x03e00000;
- const int reg_shift = 21;
-
- if ((inst & stq_mask) == stq_pattern) {
- reg = (inst & reg_mask) >> reg_shift;
- disp = sext<16>(inst & stq_disp_mask);
- } else {
- return false;
+ return true;
}
- return true;
-}
+ bool
+ StackTrace::decodeSave(MachInst inst, int &reg, int &disp)
+ {
+ // lda $stq, disp($sp)
+ //
+ // Opcode<31:26> == 0x08
+ // RA<25:21> == ?
+ // RB<20:16> == 30
+ // Disp<15:0>
+ const MachInst stq_mask = 0xfc1f0000;
+ const MachInst stq_pattern = 0xb41e0000;
+ const MachInst stq_disp_mask = 0x0000ffff;
+ const MachInst reg_mask = 0x03e00000;
+ const int reg_shift = 21;
+
+ if ((inst & stq_mask) == stq_pattern) {
+ reg = (inst & reg_mask) >> reg_shift;
+ disp = sext<16>(inst & stq_disp_mask);
+ } else {
+ return false;
+ }
-/*
- * Decode the function prologue for the function we're in, and note
- * which registers are stored where, and how large the stack frame is.
- */
-bool
-StackTrace::decodePrologue(Addr sp, Addr callpc, Addr func,
- int &size, Addr &ra)
-{
- size = 0;
- ra = 0;
-
- for (Addr pc = func; pc < callpc; pc += sizeof(MachInst)) {
- MachInst inst;
- CopyOut(tc, (uint8_t *)&inst, pc, sizeof(MachInst));
-
- int reg, disp;
- if (decodeStack(inst, disp)) {
- if (size) {
- // panic("decoding frame size again");
- return true;
- }
- size += disp;
- } else if (decodeSave(inst, reg, disp)) {
- if (!ra && reg == ReturnAddressReg) {
- CopyOut(tc, (uint8_t *)&ra, sp + disp, sizeof(Addr));
- if (!ra) {
- // panic("no return address value pc=%#x\n", pc);
- return false;
+ return true;
+ }
+
+ /*
+ * Decode the function prologue for the function we're in, and note
+ * which registers are stored where, and how large the stack frame is.
+ */
+ bool
+ StackTrace::decodePrologue(Addr sp, Addr callpc, Addr func,
+ int &size, Addr &ra)
+ {
+ size = 0;
+ ra = 0;
+
+ for (Addr pc = func; pc < callpc; pc += sizeof(MachInst)) {
+ MachInst inst;
+ CopyOut(tc, (uint8_t *)&inst, pc, sizeof(MachInst));
+
+ int reg, disp;
+ if (decodeStack(inst, disp)) {
+ if (size) {
+ // panic("decoding frame size again");
+ return true;
+ }
+ size += disp;
+ } else if (decodeSave(inst, reg, disp)) {
+ if (!ra && reg == ReturnAddressReg) {
+ CopyOut(tc, (uint8_t *)&ra, sp + disp, sizeof(Addr));
+ if (!ra) {
+ // panic("no return address value pc=%#x\n", pc);
+ return false;
+ }
}
}
}
- }
- return true;
-}
+ return true;
+ }
#if TRACING_ON
-void
-StackTrace::dump()
-{
- StringWrap name(tc->getCpuPtr()->name());
- SymbolTable *symtab = tc->getSystemPtr()->kernelSymtab;
-
- DPRINTFN("------ Stack ------\n");
-
- string symbol;
- for (int i = 0, size = stack.size(); i < size; ++i) {
- Addr addr = stack[size - i - 1];
- if (addr == user)
- symbol = "user";
- else if (addr == console)
- symbol = "console";
- else if (addr == unknown)
- symbol = "unknown";
- else
- symtab->findSymbol(addr, symbol);
-
- DPRINTFN("%#x: %s\n", addr, symbol);
+ void
+ StackTrace::dump()
+ {
+ StringWrap name(tc->getCpuPtr()->name());
+ SymbolTable *symtab = tc->getSystemPtr()->kernelSymtab;
+
+ DPRINTFN("------ Stack ------\n");
+
+ string symbol;
+ for (int i = 0, size = stack.size(); i < size; ++i) {
+ Addr addr = stack[size - i - 1];
+ if (addr == user)
+ symbol = "user";
+ else if (addr == console)
+ symbol = "console";
+ else if (addr == unknown)
+ symbol = "unknown";
+ else
+ symtab->findSymbol(addr, symbol);
+
+ DPRINTFN("%#x: %s\n", addr, symbol);
+ }
}
-}
#endif
+}
diff --git a/src/arch/alpha/stacktrace.hh b/src/arch/alpha/stacktrace.hh
index d12aee211..834abbc2f 100644
--- a/src/arch/alpha/stacktrace.hh
+++ b/src/arch/alpha/stacktrace.hh
@@ -35,87 +35,91 @@
#include "cpu/static_inst.hh"
class ThreadContext;
-class StackTrace;
-class ProcessInfo
+namespace AlphaISA
{
- private:
- ThreadContext *tc;
+ class StackTrace;
- int thread_info_size;
- int task_struct_size;
- int task_off;
- int pid_off;
- int name_off;
+ class ProcessInfo
+ {
+ private:
+ ThreadContext *tc;
- public:
- ProcessInfo(ThreadContext *_tc);
+ int thread_info_size;
+ int task_struct_size;
+ int task_off;
+ int pid_off;
+ int name_off;
- Addr task(Addr ksp) const;
- int pid(Addr ksp) const;
- std::string name(Addr ksp) const;
-};
+ public:
+ ProcessInfo(ThreadContext *_tc);
-class StackTrace
-{
- protected:
- typedef TheISA::MachInst MachInst;
- private:
- ThreadContext *tc;
- std::vector<Addr> stack;
-
- private:
- bool isEntry(Addr addr);
- bool decodePrologue(Addr sp, Addr callpc, Addr func, int &size, Addr &ra);
- bool decodeSave(MachInst inst, int &reg, int &disp);
- bool decodeStack(MachInst inst, int &disp);
-
- void trace(ThreadContext *tc, bool is_call);
-
- public:
- StackTrace();
- StackTrace(ThreadContext *tc, StaticInstPtr inst);
- ~StackTrace();
-
- void clear()
+ Addr task(Addr ksp) const;
+ int pid(Addr ksp) const;
+ std::string name(Addr ksp) const;
+ };
+
+ class StackTrace
{
- tc = 0;
- stack.clear();
- }
+ protected:
+ typedef TheISA::MachInst MachInst;
+ private:
+ ThreadContext *tc;
+ std::vector<Addr> stack;
+
+ private:
+ bool isEntry(Addr addr);
+ bool decodePrologue(Addr sp, Addr callpc, Addr func, int &size, Addr &ra);
+ bool decodeSave(MachInst inst, int &reg, int &disp);
+ bool decodeStack(MachInst inst, int &disp);
+
+ void trace(ThreadContext *tc, bool is_call);
- bool valid() const { return tc != NULL; }
- bool trace(ThreadContext *tc, StaticInstPtr inst);
+ public:
+ StackTrace();
+ StackTrace(ThreadContext *tc, StaticInstPtr inst);
+ ~StackTrace();
- public:
- const std::vector<Addr> &getstack() const { return stack; }
+ void clear()
+ {
+ tc = 0;
+ stack.clear();
+ }
- static const int user = 1;
- static const int console = 2;
- static const int unknown = 3;
+ bool valid() const { return tc != NULL; }
+ bool trace(ThreadContext *tc, StaticInstPtr inst);
+
+ public:
+ const std::vector<Addr> &getstack() const { return stack; }
+
+ static const int user = 1;
+ static const int console = 2;
+ static const int unknown = 3;
#if TRACING_ON
- private:
- void dump();
+ private:
+ void dump();
- public:
- void dprintf() { if (DTRACE(Stack)) dump(); }
+ public:
+ void dprintf() { if (DTRACE(Stack)) dump(); }
#else
- public:
- void dprintf() {}
+ public:
+ void dprintf() {}
#endif
-};
+ };
-inline bool
-StackTrace::trace(ThreadContext *tc, StaticInstPtr inst)
-{
- if (!inst->isCall() && !inst->isReturn())
- return false;
+ inline bool
+ StackTrace::trace(ThreadContext *tc, StaticInstPtr inst)
+ {
+ if (!inst->isCall() && !inst->isReturn())
+ return false;
- if (valid())
- clear();
+ if (valid())
+ clear();
- trace(tc, !inst->isReturn());
- return true;
+ trace(tc, !inst->isReturn());
+ return true;
+ }
}
#endif // __ARCH_ALPHA_STACKTRACE_HH__
diff --git a/src/arch/alpha/system.cc b/src/arch/alpha/system.cc
index 5597eaedc..cd923948c 100644
--- a/src/arch/alpha/system.cc
+++ b/src/arch/alpha/system.cc
@@ -29,10 +29,12 @@
* Nathan Binkert
*/
+#include <sys/signal.h>
+
#include "arch/alpha/ev5.hh"
#include "arch/alpha/system.hh"
+#include "arch/alpha/remote_gdb.hh"
#include "arch/vtophys.hh"
-#include "base/remote_gdb.hh"
#include "base/loader/object_file.hh"
#include "base/loader/symtab.hh"
#include "base/trace.hh"
@@ -196,7 +198,7 @@ AlphaSystem::setAlphaAccess(Addr access)
bool
AlphaSystem::breakpoint()
{
- return remoteGDB[0]->trap(ALPHA_KENTRY_INT);
+ return remoteGDB[0]->trap(SIGTRAP);
}
void
diff --git a/src/arch/alpha/utility.hh b/src/arch/alpha/utility.hh
index cb86c7e9e..100736555 100644
--- a/src/arch/alpha/utility.hh
+++ b/src/arch/alpha/utility.hh
@@ -42,6 +42,12 @@
namespace AlphaISA
{
+ static inline bool
+ inUserMode(ThreadContext *tc)
+ {
+ return (tc->readMiscReg(AlphaISA::IPR_DTB_CM) & 0x18) != 0;
+ }
+
static inline ExtMachInst
makeExtMI(MachInst inst, Addr pc) {
#if FULL_SYSTEM
diff --git a/src/arch/mips/stacktrace.hh b/src/arch/mips/stacktrace.hh
index f9e092dbd..c854f63ca 100644
--- a/src/arch/mips/stacktrace.hh
+++ b/src/arch/mips/stacktrace.hh
@@ -37,6 +37,9 @@
class ThreadContext;
class StackTrace;
+namespace MipsISA
+{
+
class ProcessInfo
{
private:
@@ -118,4 +121,6 @@ StackTrace::trace(ThreadContext *tc, StaticInstPtr inst)
return true;
}
+}
+
#endif // __ARCH_MIPS_STACKTRACE_HH__
diff --git a/src/arch/sparc/SConscript b/src/arch/sparc/SConscript
index e317502e0..281c166c0 100644
--- a/src/arch/sparc/SConscript
+++ b/src/arch/sparc/SConscript
@@ -54,7 +54,11 @@ base_sources = Split('''
# Full-system sources
full_system_sources = Split('''
- ua2005.cc
+ arguments.cc
+ remote_gdb.cc
+ stacktrace.cc
+ system.cc
+ tlb.cc
vtophys.cc
''')
diff --git a/src/arch/sparc/arguments.cc b/src/arch/sparc/arguments.cc
new file mode 100644
index 000000000..44adf4a15
--- /dev/null
+++ b/src/arch/sparc/arguments.cc
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Nathan Binkert
+ */
+
+#include "arch/sparc/arguments.hh"
+#include "arch/sparc/vtophys.hh"
+#include "cpu/thread_context.hh"
+#include "mem/vport.hh"
+
+using namespace SparcISA;
+
+Arguments::Data::~Data()
+{
+ while (!data.empty()) {
+ delete [] data.front();
+ data.pop_front();
+ }
+}
+
+char *
+Arguments::Data::alloc(size_t size)
+{
+ char *buf = new char[size];
+ data.push_back(buf);
+ return buf;
+}
+
+uint64_t
+Arguments::getArg(bool fp)
+{
+ //The caller uses %o0-%05 for the first 6 arguments even if their floating
+ //point. Double precision floating point values take two registers/args.
+ //Quads, structs, and unions are passed as pointers. All arguments beyond
+ //the sixth are passed on the stack past the 16 word window save area,
+ //space for the struct/union return pointer, and space reserved for the
+ //first 6 arguments which the caller may use but doesn't have to.
+ if (number < 6) {
+ return tc->readIntReg(8 + number);
+ } else {
+ Addr sp = tc->readIntReg(14);
+ VirtualPort *vp = tc->getVirtPort(tc);
+ uint64_t arg = vp->read<uint64_t>(sp + 92 + (number-6) * sizeof(uint64_t));
+ tc->delVirtPort(vp);
+ return arg;
+ }
+}
+
diff --git a/src/arch/sparc/arguments.hh b/src/arch/sparc/arguments.hh
new file mode 100644
index 000000000..8f925dd25
--- /dev/null
+++ b/src/arch/sparc/arguments.hh
@@ -0,0 +1,149 @@
+/*
+ * Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Nathan Binkert
+ */
+
+#ifndef __ARCH_SPARC_ARGUMENTS_HH__
+#define __ARCH_SPARC_ARGUMENTS_HH__
+
+#include <assert.h>
+
+#include "arch/sparc/vtophys.hh"
+#include "base/refcnt.hh"
+#include "sim/host.hh"
+
+class ThreadContext;
+
+namespace SparcISA {
+
+class Arguments
+{
+ protected:
+ ThreadContext *tc;
+ int number;
+ uint64_t getArg(bool fp = false);
+
+ protected:
+ class Data : public RefCounted
+ {
+ public:
+ Data(){}
+ ~Data();
+
+ private:
+ std::list<char *> data;
+
+ public:
+ char *alloc(size_t size);
+ };
+
+ RefCountingPtr<Data> data;
+
+ public:
+ Arguments(ThreadContext *ctx, int n = 0)
+ : tc(ctx), number(n), data(NULL)
+ { assert(number >= 0); data = new Data;}
+ Arguments(const Arguments &args)
+ : tc(args.tc), number(args.number), data(args.data) {}
+ ~Arguments() {}
+
+ ThreadContext *getThreadContext() const { return tc; }
+
+ const Arguments &operator=(const Arguments &args) {
+ tc = args.tc;
+ number = args.number;
+ data = args.data;
+ return *this;
+ }
+
+ Arguments &operator++() {
+ ++number;
+ assert(number >= 0);
+ return *this;
+ }
+
+ Arguments operator++(int) {
+ Arguments args = *this;
+ ++number;
+ assert(number >= 0);
+ return args;
+ }
+
+ Arguments &operator--() {
+ --number;
+ assert(number >= 0);
+ return *this;
+ }
+
+ Arguments operator--(int) {
+ Arguments args = *this;
+ --number;
+ assert(number >= 0);
+ return args;
+ }
+
+ const Arguments &operator+=(int index) {
+ number += index;
+ assert(number >= 0);
+ return *this;
+ }
+
+ const Arguments &operator-=(int index) {
+ number -= index;
+ assert(number >= 0);
+ return *this;
+ }
+
+ Arguments operator[](int index) {
+ return Arguments(tc, index);
+ }
+
+ template <class T>
+ operator T() {
+ assert(sizeof(T) <= sizeof(uint64_t));
+ T data = static_cast<T>(getArg());
+ return data;
+ }
+
+ template <class T>
+ operator T *() {
+ T *buf = (T *)data->alloc(sizeof(T));
+ CopyData(tc, buf, getArg(), sizeof(T));
+ return buf;
+ }
+
+ operator char *() {
+ char *buf = data->alloc(2048);
+ CopyStringOut(tc, buf, getArg(), 2048);
+ return buf;
+ }
+};
+
+}; // namespace SparcISA
+
+#endif // __ARCH_SPARC_ARGUMENTS_HH__
diff --git a/src/arch/sparc/asi.hh b/src/arch/sparc/asi.hh
index 876567225..6677b23df 100644
--- a/src/arch/sparc/asi.hh
+++ b/src/arch/sparc/asi.hh
@@ -219,4 +219,4 @@ namespace SparcISA
};
-#endif // __ARCH_SPARC_TLB_HH__
+#endif // __ARCH_SPARC_ASI_HH__
diff --git a/src/arch/sparc/faults.cc b/src/arch/sparc/faults.cc
index 567ca5f5c..e895c02db 100644
--- a/src/arch/sparc/faults.cc
+++ b/src/arch/sparc/faults.cc
@@ -33,12 +33,14 @@
#include "arch/sparc/faults.hh"
#include "arch/sparc/isa_traits.hh"
-#include "arch/sparc/process.hh"
+#include "arch/sparc/types.hh"
#include "base/bitfield.hh"
#include "base/trace.hh"
+#include "config/full_system.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#if !FULL_SYSTEM
+#include "arch/sparc/process.hh"
#include "mem/page_table.hh"
#include "sim/process.hh"
#endif
@@ -48,214 +50,352 @@ using namespace std;
namespace SparcISA
{
-FaultName InternalProcessorError::_name = "intprocerr";
-TrapType InternalProcessorError::_trapType = 0x029;
-FaultPriority InternalProcessorError::_priority = 4;
-FaultStat InternalProcessorError::_count;
-
-FaultName MemAddressNotAligned::_name = "unalign";
-TrapType MemAddressNotAligned::_trapType = 0x034;
-FaultPriority MemAddressNotAligned::_priority = 10;
-FaultStat MemAddressNotAligned::_count;
-
-FaultName PowerOnReset::_name = "pow_reset";
-TrapType PowerOnReset::_trapType = 0x001;
-FaultPriority PowerOnReset::_priority = 0;
-FaultStat PowerOnReset::_count;
-
-FaultName WatchDogReset::_name = "watch_dog_reset";
-TrapType WatchDogReset::_trapType = 0x002;
-FaultPriority WatchDogReset::_priority = 1;
-FaultStat WatchDogReset::_count;
-
-FaultName ExternallyInitiatedReset::_name = "extern_reset";
-TrapType ExternallyInitiatedReset::_trapType = 0x003;
-FaultPriority ExternallyInitiatedReset::_priority = 1;
-FaultStat ExternallyInitiatedReset::_count;
-
-FaultName SoftwareInitiatedReset::_name = "software_reset";
-TrapType SoftwareInitiatedReset::_trapType = 0x004;
-FaultPriority SoftwareInitiatedReset::_priority = 1;
-FaultStat SoftwareInitiatedReset::_count;
-
-FaultName REDStateException::_name = "red_counte";
-TrapType REDStateException::_trapType = 0x005;
-FaultPriority REDStateException::_priority = 1;
-FaultStat REDStateException::_count;
-
-FaultName InstructionAccessException::_name = "inst_access";
-TrapType InstructionAccessException::_trapType = 0x008;
-FaultPriority InstructionAccessException::_priority = 5;
-FaultStat InstructionAccessException::_count;
-
-FaultName InstructionAccessMMUMiss::_name = "inst_mmu";
-TrapType InstructionAccessMMUMiss::_trapType = 0x009;
-FaultPriority InstructionAccessMMUMiss::_priority = 2;
-FaultStat InstructionAccessMMUMiss::_count;
-
-FaultName InstructionAccessError::_name = "inst_error";
-TrapType InstructionAccessError::_trapType = 0x00A;
-FaultPriority InstructionAccessError::_priority = 3;
-FaultStat InstructionAccessError::_count;
-
-FaultName IllegalInstruction::_name = "illegal_inst";
-TrapType IllegalInstruction::_trapType = 0x010;
-FaultPriority IllegalInstruction::_priority = 7;
-FaultStat IllegalInstruction::_count;
-
-FaultName PrivilegedOpcode::_name = "priv_opcode";
-TrapType PrivilegedOpcode::_trapType = 0x011;
-FaultPriority PrivilegedOpcode::_priority = 6;
-FaultStat PrivilegedOpcode::_count;
-
-FaultName UnimplementedLDD::_name = "unimp_ldd";
-TrapType UnimplementedLDD::_trapType = 0x012;
-FaultPriority UnimplementedLDD::_priority = 6;
-FaultStat UnimplementedLDD::_count;
-
-FaultName UnimplementedSTD::_name = "unimp_std";
-TrapType UnimplementedSTD::_trapType = 0x013;
-FaultPriority UnimplementedSTD::_priority = 6;
-FaultStat UnimplementedSTD::_count;
-
-FaultName FpDisabled::_name = "fp_disabled";
-TrapType FpDisabled::_trapType = 0x020;
-FaultPriority FpDisabled::_priority = 8;
-FaultStat FpDisabled::_count;
-
-FaultName FpExceptionIEEE754::_name = "fp_754";
-TrapType FpExceptionIEEE754::_trapType = 0x021;
-FaultPriority FpExceptionIEEE754::_priority = 11;
-FaultStat FpExceptionIEEE754::_count;
-
-FaultName FpExceptionOther::_name = "fp_other";
-TrapType FpExceptionOther::_trapType = 0x022;
-FaultPriority FpExceptionOther::_priority = 11;
-FaultStat FpExceptionOther::_count;
-
-FaultName TagOverflow::_name = "tag_overflow";
-TrapType TagOverflow::_trapType = 0x023;
-FaultPriority TagOverflow::_priority = 14;
-FaultStat TagOverflow::_count;
-
-FaultName DivisionByZero::_name = "div_by_zero";
-TrapType DivisionByZero::_trapType = 0x028;
-FaultPriority DivisionByZero::_priority = 15;
-FaultStat DivisionByZero::_count;
-
-FaultName DataAccessException::_name = "data_access";
-TrapType DataAccessException::_trapType = 0x030;
-FaultPriority DataAccessException::_priority = 12;
-FaultStat DataAccessException::_count;
-
-FaultName DataAccessMMUMiss::_name = "data_mmu";
-TrapType DataAccessMMUMiss::_trapType = 0x031;
-FaultPriority DataAccessMMUMiss::_priority = 12;
-FaultStat DataAccessMMUMiss::_count;
-
-FaultName DataAccessError::_name = "data_error";
-TrapType DataAccessError::_trapType = 0x032;
-FaultPriority DataAccessError::_priority = 12;
-FaultStat DataAccessError::_count;
-
-FaultName DataAccessProtection::_name = "data_protection";
-TrapType DataAccessProtection::_trapType = 0x033;
-FaultPriority DataAccessProtection::_priority = 12;
-FaultStat DataAccessProtection::_count;
-
-FaultName LDDFMemAddressNotAligned::_name = "unalign_lddf";
-TrapType LDDFMemAddressNotAligned::_trapType = 0x035;
-FaultPriority LDDFMemAddressNotAligned::_priority = 10;
-FaultStat LDDFMemAddressNotAligned::_count;
-
-FaultName STDFMemAddressNotAligned::_name = "unalign_stdf";
-TrapType STDFMemAddressNotAligned::_trapType = 0x036;
-FaultPriority STDFMemAddressNotAligned::_priority = 10;
-FaultStat STDFMemAddressNotAligned::_count;
-
-FaultName PrivilegedAction::_name = "priv_action";
-TrapType PrivilegedAction::_trapType = 0x037;
-FaultPriority PrivilegedAction::_priority = 11;
-FaultStat PrivilegedAction::_count;
-
-FaultName LDQFMemAddressNotAligned::_name = "unalign_ldqf";
-TrapType LDQFMemAddressNotAligned::_trapType = 0x038;
-FaultPriority LDQFMemAddressNotAligned::_priority = 10;
-FaultStat LDQFMemAddressNotAligned::_count;
-
-FaultName STQFMemAddressNotAligned::_name = "unalign_stqf";
-TrapType STQFMemAddressNotAligned::_trapType = 0x039;
-FaultPriority STQFMemAddressNotAligned::_priority = 10;
-FaultStat STQFMemAddressNotAligned::_count;
-
-FaultName AsyncDataError::_name = "async_data";
-TrapType AsyncDataError::_trapType = 0x040;
-FaultPriority AsyncDataError::_priority = 2;
-FaultStat AsyncDataError::_count;
-
-FaultName CleanWindow::_name = "clean_win";
-TrapType CleanWindow::_trapType = 0x024;
-FaultPriority CleanWindow::_priority = 10;
-FaultStat CleanWindow::_count;
-
-//The enumerated faults
-
-FaultName InterruptLevelN::_name = "interrupt_n";
-TrapType InterruptLevelN::_baseTrapType = 0x041;
-FaultStat InterruptLevelN::_count;
-
-FaultName SpillNNormal::_name = "spill_n_normal";
-TrapType SpillNNormal::_baseTrapType = 0x080;
-FaultPriority SpillNNormal::_priority = 9;
-FaultStat SpillNNormal::_count;
-
-FaultName SpillNOther::_name = "spill_n_other";
-TrapType SpillNOther::_baseTrapType = 0x0A0;
-FaultPriority SpillNOther::_priority = 9;
-FaultStat SpillNOther::_count;
-
-FaultName FillNNormal::_name = "fill_n_normal";
-TrapType FillNNormal::_baseTrapType = 0x0C0;
-FaultPriority FillNNormal::_priority = 9;
-FaultStat FillNNormal::_count;
-
-FaultName FillNOther::_name = "fill_n_other";
-TrapType FillNOther::_baseTrapType = 0x0E0;
-FaultPriority FillNOther::_priority = 9;
-FaultStat FillNOther::_count;
-
-FaultName TrapInstruction::_name = "trap_inst_n";
-TrapType TrapInstruction::_baseTrapType = 0x100;
-FaultPriority TrapInstruction::_priority = 16;
-FaultStat TrapInstruction::_count;
+template<> SparcFaultBase::FaultVals
+ SparcFault<PowerOnReset>::vals =
+ {"power_on_reset", 0x001, 0, {H, H, H}};
+
+template<> SparcFaultBase::FaultVals
+ SparcFault<WatchDogReset>::vals =
+ {"watch_dog_reset", 0x002, 120, {H, H, H}};
+
+template<> SparcFaultBase::FaultVals
+ SparcFault<ExternallyInitiatedReset>::vals =
+ {"externally_initiated_reset", 0x003, 110, {H, H, H}};
+
+template<> SparcFaultBase::FaultVals
+ SparcFault<SoftwareInitiatedReset>::vals =
+ {"software_initiated_reset", 0x004, 130, {SH, SH, H}};
+
+template<> SparcFaultBase::FaultVals
+ SparcFault<REDStateException>::vals =
+ {"RED_state_exception", 0x005, 1, {H, H, H}};
+
+template<> SparcFaultBase::FaultVals
+ SparcFault<StoreError>::vals =
+ {"store_error", 0x007, 201, {H, H, H}};
+
+template<> SparcFaultBase::FaultVals
+ SparcFault<InstructionAccessException>::vals =
+ {"instruction_access_exception", 0x008, 300, {H, H, H}};
+
+//XXX This trap is apparently dropped from ua2005
+/*template<> SparcFaultBase::FaultVals
+ SparcFault<InstructionAccessMMUMiss>::vals =
+ {"inst_mmu", 0x009, 2, {H, H, H}};*/
+
+template<> SparcFaultBase::FaultVals
+ SparcFault<InstructionAccessError>::vals =
+ {"instruction_access_error", 0x00A, 400, {H, H, H}};
+
+template<> SparcFaultBase::FaultVals
+ SparcFault<IllegalInstruction>::vals =
+ {"illegal_instruction", 0x010, 620, {H, H, H}};
+
+template<> SparcFaultBase::FaultVals
+ SparcFault<PrivilegedOpcode>::vals =
+ {"privileged_opcode", 0x011, 700, {P, SH, SH}};
+
+//XXX This trap is apparently dropped from ua2005
+/*template<> SparcFaultBase::FaultVals
+ SparcFault<UnimplementedLDD>::vals =
+ {"unimp_ldd", 0x012, 6, {H, H, H}};*/
+
+//XXX This trap is apparently dropped from ua2005
+/*template<> SparcFaultBase::FaultVals
+ SparcFault<UnimplementedSTD>::vals =
+ {"unimp_std", 0x013, 6, {H, H, H}};*/
+
+template<> SparcFaultBase::FaultVals
+ SparcFault<FpDisabled>::vals =
+ {"fp_disabled", 0x020, 800, {P, P, H}};
+
+template<> SparcFaultBase::FaultVals
+ SparcFault<FpExceptionIEEE754>::vals =
+ {"fp_exception_ieee_754", 0x021, 1110, {P, P, H}};
+
+template<> SparcFaultBase::FaultVals
+ SparcFault<FpExceptionOther>::vals =
+ {"fp_exception_other", 0x022, 1110, {P, P, H}};
+
+template<> SparcFaultBase::FaultVals
+ SparcFault<TagOverflow>::vals =
+ {"tag_overflow", 0x023, 1400, {P, P, H}};
+
+template<> SparcFaultBase::FaultVals
+ SparcFault<CleanWindow>::vals =
+ {"clean_window", 0x024, 1010, {P, P, H}};
+
+template<> SparcFaultBase::FaultVals
+ SparcFault<DivisionByZero>::vals =
+ {"division_by_zero", 0x028, 1500, {P, P, H}};
+
+template<> SparcFaultBase::FaultVals
+ SparcFault<InternalProcessorError>::vals =
+ {"internal_processor_error", 0x029, 4, {H, H, H}};
+
+template<> SparcFaultBase::FaultVals
+ SparcFault<InstructionInvalidTSBEntry>::vals =
+ {"instruction_invalid_tsb_entry", 0x02A, 210, {H, H, SH}};
+
+template<> SparcFaultBase::FaultVals
+ SparcFault<DataInvalidTSBEntry>::vals =
+ {"data_invalid_tsb_entry", 0x02B, 1203, {H, H, H}};
+
+template<> SparcFaultBase::FaultVals
+ SparcFault<DataAccessException>::vals =
+ {"data_access_exception", 0x030, 1201, {H, H, H}};
+
+//XXX This trap is apparently dropped from ua2005
+/*template<> SparcFaultBase::FaultVals
+ SparcFault<DataAccessMMUMiss>::vals =
+ {"data_mmu", 0x031, 12, {H, H, H}};*/
+
+template<> SparcFaultBase::FaultVals
+ SparcFault<DataAccessError>::vals =
+ {"data_access_error", 0x032, 1210, {H, H, H}};
+
+template<> SparcFaultBase::FaultVals
+ SparcFault<DataAccessProtection>::vals =
+ {"data_access_protection", 0x033, 1207, {H, H, H}};
+
+template<> SparcFaultBase::FaultVals
+ SparcFault<MemAddressNotAligned>::vals =
+ {"mem_address_not_aligned", 0x034, 1020, {H, H, H}};
+
+template<> SparcFaultBase::FaultVals
+ SparcFault<LDDFMemAddressNotAligned>::vals =
+ {"LDDF_mem_address_not_aligned", 0x035, 1010, {H, H, H}};
+
+template<> SparcFaultBase::FaultVals
+ SparcFault<STDFMemAddressNotAligned>::vals =
+ {"STDF_mem_address_not_aligned", 0x036, 1010, {H, H, H}};
+
+template<> SparcFaultBase::FaultVals
+ SparcFault<PrivilegedAction>::vals =
+ {"privileged_action", 0x037, 1110, {H, H, SH}};
+
+template<> SparcFaultBase::FaultVals
+ SparcFault<LDQFMemAddressNotAligned>::vals =
+ {"LDQF_mem_address_not_aligned", 0x038, 1010, {H, H, H}};
+
+template<> SparcFaultBase::FaultVals
+ SparcFault<STQFMemAddressNotAligned>::vals =
+ {"STQF_mem_address_not_aligned", 0x039, 1010, {H, H, H}};
+
+template<> SparcFaultBase::FaultVals
+ SparcFault<InstructionRealTranslationMiss>::vals =
+ {"instruction_real_translation_miss", 0x03E, 208, {H, H, SH}};
+
+template<> SparcFaultBase::FaultVals
+ SparcFault<DataRealTranslationMiss>::vals =
+ {"data_real_translation_miss", 0x03F, 1203, {H, H, H}};
+
+//XXX This trap is apparently dropped from ua2005
+/*template<> SparcFaultBase::FaultVals
+ SparcFault<AsyncDataError>::vals =
+ {"async_data", 0x040, 2, {H, H, H}};*/
+
+template<> SparcFaultBase::FaultVals
+ SparcFault<InterruptLevelN>::vals =
+ {"interrupt_level_n", 0x041, 0, {P, P, SH}};
+
+template<> SparcFaultBase::FaultVals
+ SparcFault<HstickMatch>::vals =
+ {"hstick_match", 0x05E, 1601, {H, H, H}};
+
+template<> SparcFaultBase::FaultVals
+ SparcFault<TrapLevelZero>::vals =
+ {"trap_level_zero", 0x05F, 202, {H, H, SH}};
+
+template<> SparcFaultBase::FaultVals
+ SparcFault<PAWatchpoint>::vals =
+ {"PA_watchpoint", 0x061, 1209, {H, H, H}};
+
+template<> SparcFaultBase::FaultVals
+ SparcFault<VAWatchpoint>::vals =
+ {"VA_watchpoint", 0x062, 1120, {P, P, SH}};
+
+template<> SparcFaultBase::FaultVals
+ SparcFault<FastInstructionAccessMMUMiss>::vals =
+ {"fast_instruction_access_MMU_miss", 0x064, 208, {H, H, SH}};
+
+template<> SparcFaultBase::FaultVals
+ SparcFault<FastDataAccessMMUMiss>::vals =
+ {"fast_data_access_MMU_miss", 0x068, 1203, {H, H, H}};
+
+template<> SparcFaultBase::FaultVals
+ SparcFault<FastDataAccessProtection>::vals =
+ {"fast_data_access_protection", 0x06C, 1207, {H, H, H}};
+
+template<> SparcFaultBase::FaultVals
+ SparcFault<InstructionBreakpoint>::vals =
+ {"instruction_break", 0x076, 610, {H, H, H}};
+
+template<> SparcFaultBase::FaultVals
+ SparcFault<CpuMondo>::vals =
+ {"cpu_mondo", 0x07C, 1608, {P, P, SH}};
+
+template<> SparcFaultBase::FaultVals
+ SparcFault<DevMondo>::vals =
+ {"dev_mondo", 0x07D, 1611, {P, P, SH}};
+
+template<> SparcFaultBase::FaultVals
+ SparcFault<ResumeableError>::vals =
+ {"resume_error", 0x07E, 3330, {P, P, SH}};
+
+template<> SparcFaultBase::FaultVals
+ SparcFault<SpillNNormal>::vals =
+ {"spill_n_normal", 0x080, 900, {P, P, H}};
+
+template<> SparcFaultBase::FaultVals
+ SparcFault<SpillNOther>::vals =
+ {"spill_n_other", 0x0A0, 900, {P, P, H}};
+
+template<> SparcFaultBase::FaultVals
+ SparcFault<FillNNormal>::vals =
+ {"fill_n_normal", 0x0C0, 900, {P, P, H}};
+
+template<> SparcFaultBase::FaultVals
+ SparcFault<FillNOther>::vals =
+ {"fill_n_other", 0x0E0, 900, {P, P, H}};
+
+template<> SparcFaultBase::FaultVals
+ SparcFault<TrapInstruction>::vals =
+ {"trap_instruction", 0x100, 1602, {P, P, H}};
#if !FULL_SYSTEM
-FaultName PageTableFault::_name = "page_table_fault";
-TrapType PageTableFault::_trapType = 0x0000;
-FaultPriority PageTableFault::_priority = 0;
-FaultStat PageTableFault::_count;
+template<> SparcFaultBase::FaultVals
+ SparcFault<PageTableFault>::vals =
+ {"page_table_fault", 0x0000, 0, {SH, SH, SH}};
#endif
/**
+ * This causes the thread context to enter RED state. This causes the side
+ * effects which go with entering RED state because of a trap.
+ */
+
+void enterREDState(ThreadContext *tc)
+{
+ //@todo Disable the mmu?
+ //@todo Disable watchpoints?
+ MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE);
+ //HPSTATE.red = 1
+ HPSTATE |= (1 << 5);
+ //HPSTATE.hpriv = 1
+ HPSTATE |= (1 << 2);
+ tc->setMiscReg(MISCREG_HPSTATE, HPSTATE);
+}
+
+/**
+ * This sets everything up for a RED state trap except for actually jumping to
+ * the handler.
+ */
+
+void doREDFault(ThreadContext *tc, TrapType tt)
+{
+ MiscReg TL = tc->readMiscReg(MISCREG_TL);
+ MiscReg TSTATE = tc->readMiscReg(MISCREG_TSTATE);
+ MiscReg PSTATE = tc->readMiscReg(MISCREG_PSTATE);
+ MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE);
+ MiscReg CCR = tc->readMiscReg(MISCREG_CCR);
+ MiscReg ASI = tc->readMiscReg(MISCREG_ASI);
+ MiscReg CWP = tc->readMiscReg(MISCREG_CWP);
+ MiscReg CANSAVE = tc->readMiscReg(MISCREG_CANSAVE);
+ MiscReg GL = tc->readMiscReg(MISCREG_GL);
+ MiscReg PC = tc->readPC();
+ MiscReg NPC = tc->readNextPC();
+
+ TL++;
+
+ //set TSTATE.gl to gl
+ replaceBits(TSTATE, 42, 40, GL);
+ //set TSTATE.ccr to ccr
+ replaceBits(TSTATE, 39, 32, CCR);
+ //set TSTATE.asi to asi
+ replaceBits(TSTATE, 31, 24, ASI);
+ //set TSTATE.pstate to pstate
+ replaceBits(TSTATE, 20, 8, PSTATE);
+ //set TSTATE.cwp to cwp
+ replaceBits(TSTATE, 4, 0, CWP);
+
+ //Write back TSTATE
+ tc->setMiscReg(MISCREG_TSTATE, TSTATE);
+
+ //set TPC to PC
+ tc->setMiscReg(MISCREG_TPC, PC);
+ //set TNPC to NPC
+ tc->setMiscReg(MISCREG_TNPC, NPC);
+
+ //set HTSTATE.hpstate to hpstate
+ tc->setMiscReg(MISCREG_HTSTATE, HPSTATE);
+
+ //TT = trap type;
+ tc->setMiscReg(MISCREG_TT, tt);
+
+ //Update GL
+ tc->setMiscRegWithEffect(MISCREG_GL, min<int>(GL+1, MaxGL));
+
+ //set PSTATE.mm to 00
+ //set PSTATE.pef to 1
+ PSTATE |= (1 << 4);
+ //set PSTATE.am to 0
+ PSTATE &= ~(1 << 3);
+ //set PSTATE.priv to 0
+ PSTATE &= ~(1 << 2);
+ //set PSTATE.ie to 0
+ PSTATE &= ~(1 << 1);
+ //set PSTATE.cle to 0
+ PSTATE &= ~(1 << 9);
+ //PSTATE.tle is unchanged
+ //XXX Where is the tct bit?
+ //set PSTATE.tct to 0
+ tc->setMiscReg(MISCREG_PSTATE, PSTATE);
+
+ //set HPSTATE.red to 1
+ HPSTATE |= (1 << 5);
+ //set HPSTATE.hpriv to 1
+ HPSTATE |= (1 << 2);
+ //set HPSTATE.ibe to 0
+ HPSTATE &= ~(1 << 10);
+ //set HPSTATE.tlz to 0
+ HPSTATE &= ~(1 << 0);
+ tc->setMiscReg(MISCREG_HPSTATE, HPSTATE);
+
+ bool changedCWP = true;
+ if(tt == 0x24)
+ CWP++;
+ else if(0x80 <= tt && tt <= 0xbf)
+ CWP += (CANSAVE + 2);
+ else if(0xc0 <= tt && tt <= 0xff)
+ CWP--;
+ else
+ changedCWP = false;
+
+ if(changedCWP)
+ {
+ CWP = (CWP + NWindows) % NWindows;
+ tc->setMiscRegWithEffect(MISCREG_CWP, CWP);
+ }
+}
+
+/**
* This sets everything up for a normal trap except for actually jumping to
- * the handler. It will need to be expanded to include the state machine in
- * the manual. Right now it assumes that traps will always be to the
- * privileged level.
+ * the handler.
*/
-void doNormalFault(ThreadContext *tc, TrapType tt)
+void doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv)
{
- uint64_t TL = tc->readMiscReg(MISCREG_TL);
- uint64_t TSTATE = tc->readMiscReg(MISCREG_TSTATE);
- uint64_t PSTATE = tc->readMiscReg(MISCREG_PSTATE);
- uint64_t HPSTATE = tc->readMiscReg(MISCREG_HPSTATE);
- uint64_t CCR = tc->readMiscReg(MISCREG_CCR);
- uint64_t ASI = tc->readMiscReg(MISCREG_ASI);
- uint64_t CWP = tc->readMiscReg(MISCREG_CWP);
- uint64_t CANSAVE = tc->readMiscReg(MISCREG_CANSAVE);
- uint64_t GL = tc->readMiscReg(MISCREG_GL);
- uint64_t PC = tc->readPC();
- uint64_t NPC = tc->readNextPC();
+ MiscReg TL = tc->readMiscReg(MISCREG_TL);
+ MiscReg TSTATE = tc->readMiscReg(MISCREG_TSTATE);
+ MiscReg PSTATE = tc->readMiscReg(MISCREG_PSTATE);
+ MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE);
+ MiscReg CCR = tc->readMiscReg(MISCREG_CCR);
+ MiscReg ASI = tc->readMiscReg(MISCREG_ASI);
+ MiscReg CWP = tc->readMiscReg(MISCREG_CWP);
+ MiscReg CANSAVE = tc->readMiscReg(MISCREG_CANSAVE);
+ MiscReg GL = tc->readMiscReg(MISCREG_GL);
+ MiscReg PC = tc->readPC();
+ MiscReg NPC = tc->readNextPC();
//Increment the trap level
TL++;
@@ -289,10 +429,10 @@ void doNormalFault(ThreadContext *tc, TrapType tt)
tc->setMiscReg(MISCREG_TT, tt);
//Update the global register level
- if(1/*We're delivering the trap in priveleged mode*/)
- tc->setMiscReg(MISCREG_GL, max<int>(GL+1, MaxGL));
+ if(!gotoHpriv)
+ tc->setMiscRegWithEffect(MISCREG_GL, min<int>(GL+1, MaxPGL));
else
- tc->setMiscReg(MISCREG_GL, max<int>(GL+1, MaxPGL));
+ tc->setMiscRegWithEffect(MISCREG_GL, min<int>(GL+1, MaxGL));
//PSTATE.mm is unchanged
//PSTATE.pef = whether or not an fpu is present
@@ -301,7 +441,7 @@ void doNormalFault(ThreadContext *tc, TrapType tt)
PSTATE |= (1 << 4);
//PSTATE.am = 0
PSTATE &= ~(1 << 3);
- if(1/*We're delivering the trap in priveleged mode*/)
+ if(!gotoHpriv)
{
//PSTATE.priv = 1
PSTATE |= (1 << 2);
@@ -322,7 +462,7 @@ void doNormalFault(ThreadContext *tc, TrapType tt)
//XXX Where exactly is this field?
tc->setMiscReg(MISCREG_PSTATE, PSTATE);
- if(0/*We're delivering the trap in hyperprivileged mode*/)
+ if(gotoHpriv)
{
//HPSTATE.red = 0
HPSTATE &= ~(1 << 5);
@@ -351,32 +491,134 @@ void doNormalFault(ThreadContext *tc, TrapType tt)
}
}
+void getREDVector(Addr & PC, Addr & NPC)
+{
+ const Addr RSTVAddr = 0xFFFFFFFFF0000000ULL;
+ PC = RSTVAddr | 0xA0;
+ NPC = PC + sizeof(MachInst);
+}
+
+void getHyperVector(Addr & PC, Addr & NPC, MiscReg TT)
+{
+ Addr HTBA ;
+ PC = (HTBA & ~mask(14)) | ((TT << 5) & mask(14));
+ NPC = PC + sizeof(MachInst);
+}
+
+void getPrivVector(Addr & PC, Addr & NPC, MiscReg TT, MiscReg TL)
+{
+ Addr TBA ;
+ PC = (TBA & ~mask(15)) |
+ (TL > 1 ? (1 << 14) : 0) |
+ ((TT << 5) & mask(14));
+ NPC = PC + sizeof(MachInst);
+}
+
#if FULL_SYSTEM
-void SparcFault::invoke(ThreadContext * tc)
+void SparcFaultBase::invoke(ThreadContext * tc)
{
FaultBase::invoke(tc);
countStat()++;
- //Use the SPARC trap state machine
-}
+ //We can refer to this to see what the trap level -was-, but something
+ //in the middle could change it in the regfile out from under us.
+ MiscReg TL = tc->readMiscReg(MISCREG_TL);
+ MiscReg TT = tc->readMiscReg(MISCREG_TT);
+ MiscReg PSTATE = tc->readMiscReg(MISCREG_PSTATE);
+ MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE);
-#endif
+ Addr PC, NPC;
-#if !FULL_SYSTEM
+ PrivilegeLevel current;
+ if(!(PSTATE & (1 << 2)))
+ current = User;
+ else if(!(HPSTATE & (1 << 2)))
+ current = Privileged;
+ else
+ current = Hyperprivileged;
+
+ PrivilegeLevel level = getNextLevel(current);
-void TrapInstruction::invoke(ThreadContext * tc)
+ if(HPSTATE & (1 << 5) || TL == MaxTL - 1)
+ {
+ getREDVector(PC, NPC);
+ enterREDState(tc);
+ doREDFault(tc, TT);
+ }
+ else if(TL == MaxTL)
+ {
+ //Do error_state somehow?
+ //Probably inject a WDR fault using the interrupt mechanism.
+ //What should the PC and NPC be set to?
+ }
+ else if(TL > MaxPTL && level == Privileged)
+ {
+ //guest_watchdog fault
+ doNormalFault(tc, trapType(), true);
+ getHyperVector(PC, NPC, 2);
+ }
+ else if(level == Hyperprivileged)
+ {
+ doNormalFault(tc, trapType(), true);
+ getHyperVector(PC, NPC, trapType());
+ }
+ else
+ {
+ doNormalFault(tc, trapType(), false);
+ getPrivVector(PC, NPC, trapType(), TL+1);
+ }
+
+ tc->setPC(PC);
+ tc->setNextPC(NPC);
+ tc->setNextNPC(NPC + sizeof(MachInst));
+}
+
+void PowerOnReset::invoke(ThreadContext * tc)
{
- // Should be handled in ISA.
+ //First, enter RED state.
+ enterREDState(tc);
+
+ //For SPARC, when a system is first started, there is a power
+ //on reset Trap which sets the processor into the following state.
+ //Bits that aren't set aren't defined on startup.
+ /*
+ tl = MaxTL;
+ gl = MaxGL;
+
+ tickFields.counter = 0; //The TICK register is unreadable bya
+ tickFields.npt = 1; //The TICK register is unreadable by by !priv
+
+ softint = 0; // Clear all the soft interrupt bits
+ tick_cmprFields.int_dis = 1; // disable timer compare interrupts
+ tick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
+ stickFields.npt = 1; //The TICK register is unreadable by by !priv
+ stick_cmprFields.int_dis = 1; // disable timer compare interrupts
+ stick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
+
+ tt[tl] = _trapType;
+ pstate = 0; // fields 0 but pef
+ pstateFields.pef = 1;
+
+ hpstate = 0;
+ hpstateFields.red = 1;
+ hpstateFields.hpriv = 1;
+ hpstateFields.tlz = 0; // this is a guess
+ hintp = 0; // no interrupts pending
+ hstick_cmprFields.int_dis = 1; // disable timer compare interrupts
+ hstick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
+ */
}
+#else // !FULL_SYSTEM
+
void SpillNNormal::invoke(ThreadContext *tc)
{
- doNormalFault(tc, trapType());
+ doNormalFault(tc, trapType(), false);
Process *p = tc->getProcessPtr();
- //This will only work in faults from a SparcLiveProcess
+ //XXX This will only work in faults from a SparcLiveProcess
SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
assert(lp);
@@ -389,15 +631,15 @@ void SpillNNormal::invoke(ThreadContext *tc)
void FillNNormal::invoke(ThreadContext *tc)
{
- doNormalFault(tc, trapType());
+ doNormalFault(tc, trapType(), false);
Process * p = tc->getProcessPtr();
- //This will only work in faults from a SparcLiveProcess
+ //XXX This will only work in faults from a SparcLiveProcess
SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
assert(lp);
- //The adjust the PC and NPC
+ //Then adjust the PC and NPC
Addr fillStart = lp->readFillStart();
tc->setPC(fillStart);
tc->setNextPC(fillStart + sizeof(MachInst));
diff --git a/src/arch/sparc/faults.hh b/src/arch/sparc/faults.hh
index 394a06294..e632502aa 100644
--- a/src/arch/sparc/faults.hh
+++ b/src/arch/sparc/faults.hh
@@ -42,579 +42,240 @@ namespace SparcISA
typedef uint32_t TrapType;
typedef uint32_t FaultPriority;
-class SparcFault : public FaultBase
-{
- public:
+class SparcFaultBase : public FaultBase
+{
+ public:
+ enum PrivilegeLevel
+ {
+ U, User = U,
+ P, Privileged = P,
+ H, Hyperprivileged = H,
+ NumLevels,
+ SH = -1,
+ ShouldntHappen = SH
+ };
+ struct FaultVals
+ {
+ const FaultName name;
+ const TrapType trapType;
+ const FaultPriority priority;
+ const PrivilegeLevel nextPrivilegeLevel[NumLevels];
+ FaultStat count;
+ };
#if FULL_SYSTEM
void invoke(ThreadContext * tc);
#endif
+ virtual FaultName name() = 0;
virtual TrapType trapType() = 0;
virtual FaultPriority priority() = 0;
virtual FaultStat & countStat() = 0;
+ virtual PrivilegeLevel getNextLevel(PrivilegeLevel current) = 0;
};
-class InternalProcessorError : public SparcFault
-{
- private:
- static FaultName _name;
- static TrapType _trapType;
- static FaultPriority _priority;
- static FaultStat _count;
- public:
- FaultName name() {return _name;}
- TrapType trapType() {return _trapType;}
- FaultPriority priority() {return _priority;}
- FaultStat & countStat() {return _count;}
- bool isMachineCheckFault() {return true;}
-};
-
-class MemAddressNotAligned : public SparcFault
+template<typename T>
+class SparcFault : public SparcFaultBase
{
- private:
- static FaultName _name;
- static TrapType _trapType;
- static FaultPriority _priority;
- static FaultStat _count;
+ protected:
+ static FaultVals vals;
public:
- FaultName name() {return _name;}
- TrapType trapType() {return _trapType;}
- FaultPriority priority() {return _priority;}
- FaultStat & countStat() {return _count;}
- bool isAlignmentFault() {return true;}
+ FaultName name() {return vals.name;}
+ TrapType trapType() {return vals.trapType;}
+ FaultPriority priority() {return vals.priority;}
+ FaultStat & countStat() {return vals.count;}
+ PrivilegeLevel getNextLevel(PrivilegeLevel current)
+ {
+ return vals.nextPrivilegeLevel[current];
+ }
};
-#if !FULL_SYSTEM
-class PageTableFault : public SparcFault
+class PowerOnReset : public SparcFault<PowerOnReset>
{
- private:
- Addr vaddr;
- static FaultName _name;
- static TrapType _trapType;
- static FaultPriority _priority;
- static FaultStat _count;
- public:
- PageTableFault(Addr va)
- : vaddr(va) {}
- FaultName name() {return _name;}
- TrapType trapType() {return _trapType;}
- FaultPriority priority() {return _priority;}
- FaultStat & countStat() {return _count;}
void invoke(ThreadContext * tc);
};
-static inline Fault genPageTableFault(Addr va)
-{
- return new PageTableFault(va);
-}
-#endif
+class WatchDogReset : public SparcFault<WatchDogReset> {};
-static inline Fault genMachineCheckFault()
-{
- return new InternalProcessorError;
-}
+class ExternallyInitiatedReset : public SparcFault<ExternallyInitiatedReset> {};
-static inline Fault genAlignmentFault()
-{
- return new MemAddressNotAligned;
-}
+class SoftwareInitiatedReset : public SparcFault<SoftwareInitiatedReset> {};
-class PowerOnReset : public SparcFault
-{
- private:
- static FaultName _name;
- static TrapType _trapType;
- static FaultPriority _priority;
- static FaultStat _count;
- public:
- FaultName name() {return _name;}
- TrapType trapType() {return _trapType;}
- FaultPriority priority() {return _priority;}
- FaultStat & countStat() {return _count;}
-};
+class REDStateException : public SparcFault<REDStateException> {};
-class WatchDogReset : public SparcFault
-{
- private:
- static FaultName _name;
- static TrapType _trapType;
- static FaultPriority _priority;
- static FaultStat _count;
- public:
- FaultName name() {return _name;}
- TrapType trapType() {return _trapType;}
- FaultPriority priority() {return _priority;}
- FaultStat & countStat() {return _count;}
-};
+class StoreError : public SparcFault<StoreError> {};
-class ExternallyInitiatedReset : public SparcFault
-{
- private:
- static FaultName _name;
- static TrapType _trapType;
- static FaultPriority _priority;
- static FaultStat _count;
- public:
- FaultName name() {return _name;}
- TrapType trapType() {return _trapType;}
- FaultPriority priority() {return _priority;}
- FaultStat & countStat() {return _count;}
-};
+class InstructionAccessException : public SparcFault<InstructionAccessException> {};
-class SoftwareInitiatedReset : public SparcFault
-{
- private:
- static FaultName _name;
- static TrapType _trapType;
- static FaultPriority _priority;
- static FaultStat _count;
- public:
- FaultName name() {return _name;}
- TrapType trapType() {return _trapType;}
- FaultPriority priority() {return _priority;}
- FaultStat & countStat() {return _count;}
-};
+//class InstructionAccessMMUMiss : public SparcFault<InstructionAccessMMUMiss> {};
-class REDStateException : public SparcFault
-{
- private:
- static FaultName _name;
- static TrapType _trapType;
- static FaultPriority _priority;
- static FaultStat _count;
- public:
- FaultName name() {return _name;}
- TrapType trapType() {return _trapType;}
- FaultPriority priority() {return _priority;}
- FaultStat & countStat() {return _count;}
-};
+class InstructionAccessError : public SparcFault<InstructionAccessError> {};
-class InstructionAccessException : public SparcFault
-{
- private:
- static FaultName _name;
- static TrapType _trapType;
- static FaultPriority _priority;
- static FaultStat _count;
- public:
- FaultName name() {return _name;}
- TrapType trapType() {return _trapType;}
- FaultPriority priority() {return _priority;}
- FaultStat & countStat() {return _count;}
-};
+class IllegalInstruction : public SparcFault<IllegalInstruction> {};
-class InstructionAccessMMUMiss : public SparcFault
-{
- private:
- static FaultName _name;
- static TrapType _trapType;
- static FaultPriority _priority;
- static FaultStat _count;
- public:
- FaultName name() {return _name;}
- TrapType trapType() {return _trapType;}
- FaultPriority priority() {return _priority;}
- FaultStat & countStat() {return _count;}
-};
+class PrivilegedOpcode : public SparcFault<PrivilegedOpcode> {};
-class InstructionAccessError : public SparcFault
-{
- private:
- static FaultName _name;
- static TrapType _trapType;
- static FaultPriority _priority;
- static FaultStat _count;
- public:
- FaultName name() {return _name;}
- TrapType trapType() {return _trapType;}
- FaultPriority priority() {return _priority;}
- FaultStat & countStat() {return _count;}
-};
+//class UnimplementedLDD : public SparcFault<UnimplementedLDD> {};
-class IllegalInstruction : public SparcFault
-{
- private:
- static FaultName _name;
- static TrapType _trapType;
- static FaultPriority _priority;
- static FaultStat _count;
- public:
- FaultName name() {return _name;}
- TrapType trapType() {return _trapType;}
- FaultPriority priority() {return _priority;}
- FaultStat & countStat() {return _count;}
-};
+//class UnimplementedSTD : public SparcFault<UnimplementedSTD> {};
-class PrivilegedOpcode : public SparcFault
-{
- private:
- static FaultName _name;
- static TrapType _trapType;
- static FaultPriority _priority;
- static FaultStat _count;
- public:
- FaultName name() {return _name;}
- TrapType trapType() {return _trapType;}
- FaultPriority priority() {return _priority;}
- FaultStat & countStat() {return _count;}
-};
+class FpDisabled : public SparcFault<FpDisabled> {};
-class UnimplementedLDD : public SparcFault
-{
- private:
- static FaultName _name;
- static TrapType _trapType;
- static FaultPriority _priority;
- static FaultStat _count;
- public:
- FaultName name() {return _name;}
- TrapType trapType() {return _trapType;}
- FaultPriority priority() {return _priority;}
- FaultStat & countStat() {return _count;}
-};
+class FpExceptionIEEE754 : public SparcFault<FpExceptionIEEE754> {};
-class UnimplementedSTD : public SparcFault
-{
- private:
- static FaultName _name;
- static TrapType _trapType;
- static FaultPriority _priority;
- static FaultStat _count;
- public:
- FaultName name() {return _name;}
- TrapType trapType() {return _trapType;}
- FaultPriority priority() {return _priority;}
- FaultStat & countStat() {return _count;}
-};
+class FpExceptionOther : public SparcFault<FpExceptionOther> {};
-class FpDisabled : public SparcFault
-{
- private:
- static FaultName _name;
- static TrapType _trapType;
- static FaultPriority _priority;
- static FaultStat _count;
- public:
- FaultName name() {return _name;}
- TrapType trapType() {return _trapType;}
- FaultPriority priority() {return _priority;}
- FaultStat & countStat() {return _count;}
-};
+class TagOverflow : public SparcFault<TagOverflow> {};
-class FpExceptionIEEE754 : public SparcFault
-{
- private:
- static FaultName _name;
- static TrapType _trapType;
- static FaultPriority _priority;
- static FaultStat _count;
- public:
- FaultName name() {return _name;}
- TrapType trapType() {return _trapType;}
- FaultPriority priority() {return _priority;}
- FaultStat & countStat() {return _count;}
-};
+class CleanWindow : public SparcFault<CleanWindow> {};
-class FpExceptionOther : public SparcFault
-{
- private:
- static FaultName _name;
- static TrapType _trapType;
- static FaultPriority _priority;
- static FaultStat _count;
- public:
- FaultName name() {return _name;}
- TrapType trapType() {return _trapType;}
- FaultPriority priority() {return _priority;}
- FaultStat & countStat() {return _count;}
-};
+class DivisionByZero : public SparcFault<DivisionByZero> {};
-class TagOverflow : public SparcFault
+class InternalProcessorError :
+ public SparcFault<InternalProcessorError>
{
- private:
- static FaultName _name;
- static TrapType _trapType;
- static FaultPriority _priority;
- static FaultStat _count;
public:
- FaultName name() {return _name;}
- TrapType trapType() {return _trapType;}
- FaultPriority priority() {return _priority;}
- FaultStat & countStat() {return _count;}
+ bool isMachineCheckFault() {return true;}
};
-class DivisionByZero : public SparcFault
-{
- private:
- static FaultName _name;
- static TrapType _trapType;
- static FaultPriority _priority;
- static FaultStat _count;
- public:
- FaultName name() {return _name;}
- TrapType trapType() {return _trapType;}
- FaultPriority priority() {return _priority;}
- FaultStat & countStat() {return _count;}
-};
+class InstructionInvalidTSBEntry : public SparcFault<InstructionInvalidTSBEntry> {};
-class DataAccessException : public SparcFault
-{
- private:
- static FaultName _name;
- static TrapType _trapType;
- static FaultPriority _priority;
- static FaultStat _count;
- public:
- FaultName name() {return _name;}
- TrapType trapType() {return _trapType;}
- FaultPriority priority() {return _priority;}
- FaultStat & countStat() {return _count;}
-};
+class DataInvalidTSBEntry : public SparcFault<DataInvalidTSBEntry> {};
-class DataAccessMMUMiss : public SparcFault
-{
- private:
- static FaultName _name;
- static TrapType _trapType;
- static FaultPriority _priority;
- static FaultStat _count;
- public:
- FaultName name() {return _name;}
- TrapType trapType() {return _trapType;}
- FaultPriority priority() {return _priority;}
- FaultStat & countStat() {return _count;}
-};
+class DataAccessException : public SparcFault<DataAccessException> {};
-class DataAccessError : public SparcFault
-{
- private:
- static FaultName _name;
- static TrapType _trapType;
- static FaultPriority _priority;
- static FaultStat _count;
- public:
- FaultName name() {return _name;}
- TrapType trapType() {return _trapType;}
- FaultPriority priority() {return _priority;}
- FaultStat & countStat() {return _count;}
-};
+//class DataAccessMMUMiss : public SparcFault<DataAccessMMUMiss> {};
-class DataAccessProtection : public SparcFault
-{
- private:
- static FaultName _name;
- static TrapType _trapType;
- static FaultPriority _priority;
- static FaultStat _count;
- public:
- FaultName name() {return _name;}
- TrapType trapType() {return _trapType;}
- FaultPriority priority() {return _priority;}
- FaultStat & countStat() {return _count;}
-};
+class DataAccessError : public SparcFault<DataAccessError> {};
-class LDDFMemAddressNotAligned : public SparcFault
-{
- private:
- static FaultName _name;
- static TrapType _trapType;
- static FaultPriority _priority;
- static FaultStat _count;
- public:
- FaultName name() {return _name;}
- TrapType trapType() {return _trapType;}
- FaultPriority priority() {return _priority;}
- FaultStat & countStat() {return _count;}
-};
+class DataAccessProtection : public SparcFault<DataAccessProtection> {};
-class STDFMemAddressNotAligned : public SparcFault
+class MemAddressNotAligned :
+ public SparcFault<MemAddressNotAligned>
{
- private:
- static FaultName _name;
- static TrapType _trapType;
- static FaultPriority _priority;
- static FaultStat _count;
public:
- FaultName name() {return _name;}
- TrapType trapType() {return _trapType;}
- FaultPriority priority() {return _priority;}
- FaultStat & countStat() {return _count;}
+ bool isAlignmentFault() {return true;}
};
-class PrivilegedAction : public SparcFault
-{
- private:
- static FaultName _name;
- static TrapType _trapType;
- static FaultPriority _priority;
- static FaultStat _count;
- public:
- FaultName name() {return _name;}
- TrapType trapType() {return _trapType;}
- FaultPriority priority() {return _priority;}
- FaultStat & countStat() {return _count;}
-};
+class LDDFMemAddressNotAligned : public SparcFault<LDDFMemAddressNotAligned> {};
-class LDQFMemAddressNotAligned : public SparcFault
-{
- private:
- static FaultName _name;
- static TrapType _trapType;
- static FaultPriority _priority;
- static FaultStat _count;
- public:
- FaultName name() {return _name;}
- TrapType trapType() {return _trapType;}
- FaultPriority priority() {return _priority;}
- FaultStat & countStat() {return _count;}
-};
+class STDFMemAddressNotAligned : public SparcFault<STDFMemAddressNotAligned> {};
-class STQFMemAddressNotAligned : public SparcFault
-{
- private:
- static FaultName _name;
- static TrapType _trapType;
- static FaultPriority _priority;
- static FaultStat _count;
- public:
- FaultName name() {return _name;}
- TrapType trapType() {return _trapType;}
- FaultPriority priority() {return _priority;}
- FaultStat & countStat() {return _count;}
-};
+class PrivilegedAction : public SparcFault<PrivilegedAction> {};
+
+class LDQFMemAddressNotAligned : public SparcFault<LDQFMemAddressNotAligned> {};
+
+class STQFMemAddressNotAligned : public SparcFault<STQFMemAddressNotAligned> {};
+
+class InstructionRealTranslationMiss :
+ public SparcFault<InstructionRealTranslationMiss> {};
+
+class DataRealTranslationMiss : public SparcFault<DataRealTranslationMiss> {};
-class AsyncDataError : public SparcFault
+//class AsyncDataError : public SparcFault<AsyncDataError> {};
+
+template <class T>
+class EnumeratedFault : public SparcFault<T>
{
- private:
- static FaultName _name;
- static TrapType _trapType;
- static FaultPriority _priority;
- static FaultStat _count;
+ protected:
+ uint32_t _n;
public:
- FaultName name() {return _name;}
- TrapType trapType() {return _trapType;}
- FaultPriority priority() {return _priority;}
- FaultStat & countStat() {return _count;}
+ EnumeratedFault(uint32_t n) : SparcFault<T>(), _n(n) {}
+ TrapType trapType() {return SparcFault<T>::trapType() + _n;}
};
-class CleanWindow : public SparcFault
+class InterruptLevelN : public EnumeratedFault<InterruptLevelN>
{
- private:
- static FaultName _name;
- static TrapType _trapType;
- static FaultPriority _priority;
- static FaultStat _count;
public:
- FaultName name() {return _name;}
- TrapType trapType() {return _trapType;}
- FaultPriority priority() {return _priority;}
- FaultStat & countStat() {return _count;}
+ InterruptLevelN(uint32_t n) : EnumeratedFault<InterruptLevelN>(n) {;}
+ FaultPriority priority() {return 3200 - _n*100;}
};
-class EnumeratedFault : public SparcFault
+class HstickMatch : public SparcFault<HstickMatch> {};
+
+class TrapLevelZero : public SparcFault<TrapLevelZero> {};
+
+class PAWatchpoint : public SparcFault<PAWatchpoint> {};
+
+class VAWatchpoint : public SparcFault<VAWatchpoint> {};
+
+class FastInstructionAccessMMUMiss :
+ public SparcFault<FastInstructionAccessMMUMiss> {};
+
+class FastDataAccessMMUMiss : public SparcFault<FastDataAccessMMUMiss> {};
+
+class FastDataAccessProtection : public SparcFault<FastDataAccessProtection> {};
+
+class InstructionBreakpoint : public SparcFault<InstructionBreakpoint> {};
+
+class CpuMondo : public SparcFault<CpuMondo> {};
+
+class DevMondo : public SparcFault<DevMondo> {};
+
+class ResumeableError : public SparcFault<ResumeableError> {};
+
+class SpillNNormal : public EnumeratedFault<SpillNNormal>
{
- protected:
- uint32_t _n;
- virtual TrapType baseTrapType() = 0;
public:
- EnumeratedFault(uint32_t n) : SparcFault() {_n = n;}
- TrapType trapType() {return baseTrapType() + _n;}
+ SpillNNormal(uint32_t n) : EnumeratedFault<SpillNNormal>(n) {;}
+ //These need to be handled specially to enable spill traps in SE
+#if !FULL_SYSTEM
+ void invoke(ThreadContext * tc);
+#endif
};
-class InterruptLevelN : public EnumeratedFault
+class SpillNOther : public EnumeratedFault<SpillNOther>
{
- private:
- static FaultName _name;
- static TrapType _baseTrapType;
- static FaultStat _count;
- TrapType baseTrapType() {return _baseTrapType;}
public:
- InterruptLevelN(uint32_t n) : EnumeratedFault(n) {;}
- FaultName name() {return _name;}
- FaultPriority priority() {return 32 - _n;}
- FaultStat & countStat() {return _count;}
+ SpillNOther(uint32_t n) : EnumeratedFault<SpillNOther>(n) {;}
};
-class SpillNNormal : public EnumeratedFault
+class FillNNormal : public EnumeratedFault<FillNNormal>
{
- private:
- static FaultName _name;
- static TrapType _baseTrapType;
- static FaultPriority _priority;
- static FaultStat _count;
- TrapType baseTrapType() {return _baseTrapType;}
public:
- SpillNNormal(uint32_t n) : EnumeratedFault(n) {;}
- FaultName name() {return _name;}
- FaultPriority priority() {return _priority;}
- FaultStat & countStat() {return _count;}
+ FillNNormal(uint32_t n) : EnumeratedFault<FillNNormal>(n) {;}
+ //These need to be handled specially to enable fill traps in SE
+#if !FULL_SYSTEM
void invoke(ThreadContext * tc);
+#endif
};
-class SpillNOther : public EnumeratedFault
+class FillNOther : public EnumeratedFault<FillNOther>
{
- private:
- static FaultName _name;
- static TrapType _baseTrapType;
- static FaultPriority _priority;
- static FaultStat _count;
- TrapType baseTrapType() {return _baseTrapType;}
public:
- SpillNOther(uint32_t n) : EnumeratedFault(n) {;}
- FaultName name() {return _name;}
- FaultPriority priority() {return _priority;}
- FaultStat & countStat() {return _count;}
+ FillNOther(uint32_t n) : EnumeratedFault<FillNOther>(n) {;}
};
-class FillNNormal : public EnumeratedFault
+class TrapInstruction : public EnumeratedFault<TrapInstruction>
{
- private:
- static FaultName _name;
- static TrapType _baseTrapType;
- static FaultPriority _priority;
- static FaultStat _count;
- TrapType baseTrapType() {return _baseTrapType;}
+
public:
- FillNNormal(uint32_t n) : EnumeratedFault(n) {;}
- FaultName name() {return _name;}
- FaultPriority priority() {return _priority;}
- FaultStat & countStat() {return _count;}
- void invoke(ThreadContext * tc);
+ TrapInstruction(uint32_t n) : EnumeratedFault<TrapInstruction>(n) {;}
};
-class FillNOther : public EnumeratedFault
+#if !FULL_SYSTEM
+class PageTableFault : public SparcFault<PageTableFault>
{
private:
- static FaultName _name;
- static TrapType _baseTrapType;
- static FaultPriority _priority;
- static FaultStat _count;
- TrapType baseTrapType() {return _baseTrapType;}
+ Addr vaddr;
public:
- FillNOther(uint32_t n) : EnumeratedFault(n) {;}
- FaultName name() {return _name;}
- FaultPriority priority() {return _priority;}
- FaultStat & countStat() {return _count;}
+ PageTableFault(Addr va) : vaddr(va) {}
+ void invoke(ThreadContext * tc);
};
-class TrapInstruction : public EnumeratedFault
+static inline Fault genPageTableFault(Addr va)
{
- private:
- static FaultName _name;
- static TrapType _baseTrapType;
- static FaultPriority _priority;
- static FaultStat _count;
- uint64_t syscall_num;
- TrapType baseTrapType() {return _baseTrapType;}
- public:
- TrapInstruction(uint32_t n, uint64_t syscall) :
- EnumeratedFault(n), syscall_num(syscall) {;}
- FaultName name() {return _name;}
- FaultPriority priority() {return _priority;}
- FaultStat & countStat() {return _count;}
-#if !FULL_SYSTEM
- void invoke(ThreadContext * tc);
+ return new PageTableFault(va);
+}
#endif
-};
+
+static inline Fault genMachineCheckFault()
+{
+ return new InternalProcessorError;
+}
+
+static inline Fault genAlignmentFault()
+{
+ return new MemAddressNotAligned;
+}
} // SparcISA namespace
diff --git a/src/arch/sparc/interrupts.hh b/src/arch/sparc/interrupts.hh
new file mode 100644
index 000000000..0072f4184
--- /dev/null
+++ b/src/arch/sparc/interrupts.hh
@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __ARCH_SPARC_INTERRUPT_HH__
+#define __ARCH_SPARC_INTERRUPT_HH__
+
+#include "arch/sparc/faults.hh"
+
+namespace SparcISA
+{
+ class Interrupts
+ {
+ protected:
+ Fault interrupts[NumInterruptLevels];
+ bool requested[NumInterruptLevels];
+
+ public:
+ Interrupts()
+ {
+ for(int x = 0; x < NumInterruptLevels; x++)
+ {
+ interrupts[x] = new InterruptLevelN(x);
+ requested[x] = false;
+ }
+ }
+ void post(int int_num, int index)
+ {
+ if(int_num < 0 || int_num >= NumInterruptLevels)
+ panic("int_num out of bounds\n");
+
+ requested[int_num] = true;
+ }
+
+ void clear(int int_num, int index)
+ {
+ requested[int_num] = false;
+ }
+
+ void clear_all()
+ {
+ for(int x = 0; x < NumInterruptLevels; x++)
+ requested[x] = false;
+ }
+
+ bool check_interrupts(ThreadContext * tc) const
+ {
+ return true;
+ }
+
+ Fault getInterrupt(ThreadContext * tc)
+ {
+ return NoFault;
+ }
+
+ void serialize(std::ostream &os)
+ {
+ }
+
+ void unserialize(Checkpoint *cp, const std::string &section)
+ {
+ }
+ };
+}
+
+#endif // __ARCH_SPARC_INTERRUPT_HH__
diff --git a/src/arch/sparc/kernel_stats.hh b/src/arch/sparc/kernel_stats.hh
new file mode 100644
index 000000000..c007c54c2
--- /dev/null
+++ b/src/arch/sparc/kernel_stats.hh
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __ARCH_SPARC_KERNEL_STATS_HH__
+#define __ARCH_SPARC_KERNEL_STATS_HH__
+
+#include <map>
+#include <stack>
+#include <string>
+#include <vector>
+
+#include "kern/kernel_stats.hh"
+
+namespace SparcISA {
+namespace Kernel {
+
+enum cpu_mode { hypervisor, kernel, user, idle, cpu_mode_num };
+extern const char *modestr[];
+
+class Statistics : public ::Kernel::Statistics
+{
+ public:
+ Statistics(System *system) : ::Kernel::Statistics(system)
+ {}
+};
+
+} /* end namespace AlphaISA::Kernel */
+} /* end namespace AlphaISA */
+
+#endif // __ARCH_SPARC_KERNEL_STATS_HH__
diff --git a/src/arch/sparc/miscregfile.cc b/src/arch/sparc/miscregfile.cc
index 2f3cfb417..217fba0bd 100644
--- a/src/arch/sparc/miscregfile.cc
+++ b/src/arch/sparc/miscregfile.cc
@@ -31,9 +31,14 @@
#include "arch/sparc/miscregfile.hh"
#include "base/trace.hh"
+#include "config/full_system.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
+#if FULL_SYSTEM
+#include "arch/sparc/system.hh"
+#endif
+
using namespace SparcISA;
using namespace std;
@@ -55,51 +60,8 @@ string SparcISA::getMiscRegName(RegIndex index)
return miscRegName[index];
}
-#if FULL_SYSTEM
-
-//XXX These need an implementation someplace
-/** Fullsystem only register version of ReadRegWithEffect() */
-MiscReg MiscRegFile::readFSRegWithEffect(int miscReg, ThreadContext *tc);
-/** Fullsystem only register version of SetRegWithEffect() */
-void MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
- ThreadContext * tc);
-#endif
-
void MiscRegFile::reset()
{
- //pstateFields.pef = 0; //No FPU
- //pstateFields.pef = 1; //FPU
-#if FULL_SYSTEM
- //For SPARC, when a system is first started, there is a power
- //on reset Trap which sets the processor into the following state.
- //Bits that aren't set aren't defined on startup.
- //XXX this code should be moved into the POR fault.
- tl = MaxTL;
- gl = MaxGL;
-
- tickFields.counter = 0; //The TICK register is unreadable bya
- tickFields.npt = 1; //The TICK register is unreadable by by !priv
-
- softint = 0; // Clear all the soft interrupt bits
- tick_cmprFields.int_dis = 1; // disable timer compare interrupts
- tick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
- stickFields.npt = 1; //The TICK register is unreadable by by !priv
- stick_cmprFields.int_dis = 1; // disable timer compare interrupts
- stick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
-
-
- tt[tl] = power_on_reset;
- pstate = 0; // fields 0 but pef
- pstateFields.pef = 1;
-
- hpstate = 0;
- hpstateFields.red = 1;
- hpstateFields.hpriv = 1;
- hpstateFields.tlz = 0; // this is a guess
- hintp = 0; // no interrupts pending
- hstick_cmprFields.int_dis = 1; // disable timer compare interrupts
- hstick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
-#endif
}
MiscReg MiscRegFile::readReg(int miscReg)
@@ -199,10 +161,20 @@ MiscReg MiscRegFile::readRegWithEffect(int miscReg, ThreadContext * tc)
case MISCREG_PCR:
case MISCREG_PIC:
panic("Performance Instrumentation not impl\n");
-
/** Floating Point Status Register */
case MISCREG_FSR:
panic("Floating Point not implemented\n");
+//We'll include this only in FS so we don't need the SparcSystem type around
+//in SE.
+#if FULL_SYSTEM
+ case MISCREG_STICK:
+ SparcSystem *sys;
+ sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());
+ assert(sys != NULL);
+ return curTick/Clock::Int::ns - sys->sysTick | stickFields.npt << 63;
+#endif
+ case MISCREG_HVER:
+ return NWindows | MaxTL << 8 | MaxGL << 16;
}
return readReg(miscReg);
}
@@ -350,6 +322,10 @@ void MiscRegFile::setRegWithEffect(int miscReg,
const MiscReg &val, ThreadContext * tc)
{
const uint64_t Bit64 = (1ULL << 63);
+#if FULL_SYSTEM
+ uint64_t time;
+ SparcSystem *sys;
+#endif
switch (miscReg) {
case MISCREG_TICK:
tickFields.counter = tc->getCpuPtr()->curCycle() - val & ~Bit64;
@@ -375,6 +351,70 @@ void MiscRegFile::setRegWithEffect(int miscReg,
case MISCREG_GL:
tc->changeRegFileContext(CONTEXT_GLOBALS, val);
break;
+ case MISCREG_SOFTINT:
+ //We need to inject interrupts, and or notify the interrupt
+ //object that it needs to use a different interrupt level.
+ //Any newly appropriate interrupts will happen when the cpu gets
+ //around to checking for them. This might not be quite what we
+ //want.
+ break;
+ case MISCREG_SOFTINT_CLR:
+ //Do whatever this is supposed to do...
+ break;
+ case MISCREG_SOFTINT_SET:
+ //Do whatever this is supposed to do...
+ break;
+#if FULL_SYSTEM
+ case MISCREG_TICK_CMPR:
+ if (tickCompare == NULL)
+ tickCompare = new TickCompareEvent(this, tc);
+ setReg(miscReg, val);
+ if (tick_cmprFields.int_dis && tickCompare->scheduled())
+ tickCompare->deschedule();
+ time = tick_cmprFields.tick_cmpr - tickFields.counter;
+ if (!tick_cmprFields.int_dis && time > 0)
+ tickCompare->schedule(time * tc->getCpuPtr()->cycles(1));
+ break;
+#endif
+ case MISCREG_PIL:
+ //We need to inject interrupts, and or notify the interrupt
+ //object that it needs to use a different interrupt level.
+ //Any newly appropriate interrupts will happen when the cpu gets
+ //around to checking for them. This might not be quite what we
+ //want.
+ break;
+//We'll include this only in FS so we don't need the SparcSystem type around
+//in SE.
+#if FULL_SYSTEM
+ case MISCREG_STICK:
+ sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());
+ assert(sys != NULL);
+ sys->sysTick = curTick/Clock::Int::ns - val & ~Bit64;
+ stickFields.npt = val & Bit64 ? 1 : 0;
+ break;
+ case MISCREG_STICK_CMPR:
+ if (sTickCompare == NULL)
+ sTickCompare = new STickCompareEvent(this, tc);
+ sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());
+ assert(sys != NULL);
+ if (stick_cmprFields.int_dis && sTickCompare->scheduled())
+ sTickCompare->deschedule();
+ time = stick_cmprFields.tick_cmpr - sys->sysTick;
+ if (!stick_cmprFields.int_dis && time > 0)
+ sTickCompare->schedule(time * Clock::Int::ns);
+ break;
+ case MISCREG_HSTICK_CMPR:
+ if (hSTickCompare == NULL)
+ hSTickCompare = new HSTickCompareEvent(this, tc);
+ sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());
+ assert(sys != NULL);
+ if (hstick_cmprFields.int_dis && hSTickCompare->scheduled())
+ hSTickCompare->deschedule();
+ int64_t time = hstick_cmprFields.tick_cmpr - sys->sysTick;
+ if (!hstick_cmprFields.int_dis && time > 0)
+ hSTickCompare->schedule(time * Clock::Int::ns);
+ break;
+#endif
}
setReg(miscReg, val);
}
@@ -444,3 +484,22 @@ void MiscRegFile::unserialize(Checkpoint * cp, const std::string & section)
implicitDataAsi = (ASI)temp;
}
+#if FULL_SYSTEM
+void
+MiscRegFile::processTickCompare(ThreadContext *tc)
+{
+ panic("tick compare not implemented\n");
+}
+
+void
+MiscRegFile::processSTickCompare(ThreadContext *tc)
+{
+ panic("tick compare not implemented\n");
+}
+
+void
+MiscRegFile::processHSTickCompare(ThreadContext *tc)
+{
+ panic("tick compare not implemented\n");
+}
+#endif
diff --git a/src/arch/sparc/miscregfile.hh b/src/arch/sparc/miscregfile.hh
index ac1ad90b9..0e424dbd2 100644
--- a/src/arch/sparc/miscregfile.hh
+++ b/src/arch/sparc/miscregfile.hh
@@ -354,12 +354,6 @@ namespace SparcISA
typedef CpuEventWrapper<MiscRegFile,
&MiscRegFile::processHSTickCompare> HSTickCompareEvent;
HSTickCompareEvent *hSTickCompare;
-
- /** Fullsystem only register version of ReadRegWithEffect() */
- MiscReg readFSRegWithEffect(int miscReg, Fault &fault, ThreadContext *tc);
- /** Fullsystem only register version of SetRegWithEffect() */
- Fault setFSRegWithEffect(int miscReg, const MiscReg &val,
- ThreadContext * tc);
#endif
public:
diff --git a/src/arch/sparc/remote_gdb.cc b/src/arch/sparc/remote_gdb.cc
new file mode 100644
index 000000000..c76f8b820
--- /dev/null
+++ b/src/arch/sparc/remote_gdb.cc
@@ -0,0 +1,203 @@
+/*
+ * Copyright (c) 2002-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Nathan Binkert
+ */
+
+/*
+ * Copyright (c) 1990, 1993
+ * The Regents of the University of California. All rights reserved.
+ *
+ * This software was developed by the Computer Systems Engineering group
+ * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
+ * contributed to Berkeley.
+ *
+ * All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by the University of
+ * California, Lawrence Berkeley Laboratories.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by the University of
+ * California, Berkeley and its contributors.
+ * 4. Neither the name of the University nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * @(#)kgdb_stub.c 8.4 (Berkeley) 1/12/94
+ */
+
+/*-
+ * Copyright (c) 2001 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Jason R. Thorpe.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by the NetBSD
+ * Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * $NetBSD: kgdb_stub.c,v 1.8 2001/07/07 22:58:00 wdk Exp $
+ *
+ * Taken from NetBSD
+ *
+ * "Stub" to allow remote cpu to debug over a serial line using gdb.
+ */
+
+#include <sys/signal.h>
+
+#include <string>
+#include <unistd.h>
+
+#include "arch/vtophys.hh"
+#include "arch/sparc/remote_gdb.hh"
+#include "base/intmath.hh"
+#include "base/remote_gdb.hh"
+#include "base/socket.hh"
+#include "base/trace.hh"
+#include "config/full_system.hh"
+#include "cpu/thread_context.hh"
+#include "cpu/static_inst.hh"
+#include "mem/physical.hh"
+#include "mem/port.hh"
+#include "sim/system.hh"
+
+using namespace std;
+using namespace TheISA;
+
+RemoteGDB::RemoteGDB(System *_system, ThreadContext *c)
+ : BaseRemoteGDB(_system, c, NumGDBRegs)
+{}
+
+///////////////////////////////////////////////////////////
+// RemoteGDB::acc
+//
+// Determine if the mapping at va..(va+len) is valid.
+//
+bool
+RemoteGDB::acc(Addr va, size_t len)
+{
+ //@Todo In NetBSD, this function checks if all addresses
+ //from va to va + len have valid page mape entries. Not
+ //sure how this will work for other OSes or in general.
+ return true;
+}
+
+///////////////////////////////////////////////////////////
+// RemoteGDB::getregs
+//
+// Translate the kernel debugger register format into
+// the GDB register format.
+void
+RemoteGDB::getregs()
+{
+ memset(gdbregs.regs, 0, gdbregs.size);
+
+ gdbregs.regs[RegPc] = context->readPC();
+ gdbregs.regs[RegNpc] = context->readNextPC();
+ for(int x = RegG0; x <= RegI0 + 7; x++)
+ gdbregs.regs[x] = context->readIntReg(x - RegG0);
+ //Floating point registers are left at 0 in netbsd
+ //All registers other than the pc, npc and int regs
+ //are ignored as well.
+}
+
+///////////////////////////////////////////////////////////
+// RemoteGDB::setregs
+//
+// Translate the GDB register format into the kernel
+// debugger register format.
+//
+void
+RemoteGDB::setregs()
+{
+ context->setPC(gdbregs.regs[RegPc]);
+ context->setNextPC(gdbregs.regs[RegNpc]);
+ for(int x = RegG0; x <= RegI0 + 7; x++)
+ context->setIntReg(x - RegG0, gdbregs.regs[x]);
+ //Only the integer registers, pc and npc are set in netbsd
+}
+
+void
+RemoteGDB::clearSingleStep()
+{
+ panic("SPARC does not support hardware single stepping\n");
+}
+
+void
+RemoteGDB::setSingleStep()
+{
+ panic("SPARC does not support hardware single stepping\n");
+}
diff --git a/src/arch/sparc/remote_gdb.hh b/src/arch/sparc/remote_gdb.hh
new file mode 100644
index 000000000..e4b66b783
--- /dev/null
+++ b/src/arch/sparc/remote_gdb.hh
@@ -0,0 +1,78 @@
+/*
+ * Copyright (c) 2002-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Nathan Binkert
+ */
+
+#ifndef __ARCH_ALPHA_REMOTE_GDB_HH__
+#define __ARCH_ALPHA_REMOTE_GDB_HH__
+
+#include <map>
+
+#include "arch/types.hh"
+#include "base/remote_gdb.hh"
+#include "cpu/pc_event.hh"
+#include "base/pollevent.hh"
+
+class System;
+class ThreadContext;
+class PhysicalMemory;
+
+namespace SparcISA
+{
+ class RemoteGDB : public BaseRemoteGDB
+ {
+ protected:
+ enum RegisterConstants
+ {
+ RegG0 = 0, RegO0 = 8, RegL0 = 16, RegI0 = 24,
+ RegF0 = 32, RegF32 = 64,
+ RegPc = 80, RegNpc, RegCcr, RegFsr, RegFprs, RegY, RegAsi,
+ RegVer, RegTick, RegPil, RegPstate,
+ RegTstate, RegTba, RegTl, RegTt, RegTpc, RegTnpc, RegWstate,
+ RegCwp, RegCansave, RegCanrestore, RegCleanwin, RegOtherwin,
+ RegAsr16 = 103,
+ RegIcc = 119, RegXcc,
+ RegFcc0 = 121,
+ NumGDBRegs
+ };
+
+ public:
+ RemoteGDB(System *system, ThreadContext *context);
+
+ bool acc(Addr addr, size_t len);
+
+ protected:
+ void getregs();
+ void setregs();
+
+ void clearSingleStep();
+ void setSingleStep();
+ };
+}
+
+#endif /* __ARCH_ALPHA_REMOTE_GDB_H__ */
diff --git a/src/arch/sparc/stacktrace.cc b/src/arch/sparc/stacktrace.cc
new file mode 100644
index 000000000..2eb697bf2
--- /dev/null
+++ b/src/arch/sparc/stacktrace.cc
@@ -0,0 +1,372 @@
+/*
+ * Copyright (c) 2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Nathan Binkert
+ */
+
+#include <string>
+
+#include "arch/sparc/isa_traits.hh"
+#include "arch/sparc/stacktrace.hh"
+#include "arch/sparc/vtophys.hh"
+#include "base/bitfield.hh"
+#include "base/trace.hh"
+#include "cpu/base.hh"
+#include "cpu/thread_context.hh"
+#include "sim/system.hh"
+
+using namespace std;
+namespace SparcISA
+{
+ ProcessInfo::ProcessInfo(ThreadContext *_tc)
+ : tc(_tc)
+ {
+ Addr addr = 0;
+
+ VirtualPort *vp;
+
+ vp = tc->getVirtPort();
+
+ if (!tc->getSystemPtr()->kernelSymtab->findAddress("thread_info_size", addr))
+ panic("thread info not compiled into kernel\n");
+ thread_info_size = vp->readGtoH<int32_t>(addr);
+
+ if (!tc->getSystemPtr()->kernelSymtab->findAddress("task_struct_size", addr))
+ panic("thread info not compiled into kernel\n");
+ task_struct_size = vp->readGtoH<int32_t>(addr);
+
+ if (!tc->getSystemPtr()->kernelSymtab->findAddress("thread_info_task", addr))
+ panic("thread info not compiled into kernel\n");
+ task_off = vp->readGtoH<int32_t>(addr);
+
+ if (!tc->getSystemPtr()->kernelSymtab->findAddress("task_struct_pid", addr))
+ panic("thread info not compiled into kernel\n");
+ pid_off = vp->readGtoH<int32_t>(addr);
+
+ if (!tc->getSystemPtr()->kernelSymtab->findAddress("task_struct_comm", addr))
+ panic("thread info not compiled into kernel\n");
+ name_off = vp->readGtoH<int32_t>(addr);
+
+ tc->delVirtPort(vp);
+ }
+
+ Addr
+ ProcessInfo::task(Addr ksp) const
+ {
+ Addr base = ksp & ~0x3fff;
+ if (base == ULL(0xfffffc0000000000))
+ return 0;
+
+ Addr tsk;
+
+ VirtualPort *vp;
+
+ vp = tc->getVirtPort();
+ tsk = vp->readGtoH<Addr>(base + task_off);
+ tc->delVirtPort(vp);
+
+ return tsk;
+ }
+
+ int
+ ProcessInfo::pid(Addr ksp) const
+ {
+ Addr task = this->task(ksp);
+ if (!task)
+ return -1;
+
+ uint16_t pd;
+
+ VirtualPort *vp;
+
+ vp = tc->getVirtPort();
+ pd = vp->readGtoH<uint16_t>(task + pid_off);
+ tc->delVirtPort(vp);
+
+ return pd;
+ }
+
+ string
+ ProcessInfo::name(Addr ksp) const
+ {
+ Addr task = this->task(ksp);
+ if (!task)
+ return "console";
+
+ char comm[256];
+ CopyStringOut(tc, comm, task + name_off, sizeof(comm));
+ if (!comm[0])
+ return "startup";
+
+ return comm;
+ }
+
+ StackTrace::StackTrace()
+ : tc(0), stack(64)
+ {
+ }
+
+ StackTrace::StackTrace(ThreadContext *_tc, StaticInstPtr inst)
+ : tc(0), stack(64)
+ {
+ trace(_tc, inst);
+ }
+
+ StackTrace::~StackTrace()
+ {
+ }
+
+ void
+ StackTrace::trace(ThreadContext *_tc, bool is_call)
+ {
+#if 0
+ tc = _tc;
+
+ bool usermode = (tc->readMiscReg(AlphaISA::IPR_DTB_CM) & 0x18) != 0;
+
+ Addr pc = tc->readNextPC();
+ bool kernel = tc->getSystemPtr()->kernelStart <= pc &&
+ pc <= tc->getSystemPtr()->kernelEnd;
+
+ if (usermode) {
+ stack.push_back(user);
+ return;
+ }
+
+ if (!kernel) {
+ stack.push_back(console);
+ return;
+ }
+
+ SymbolTable *symtab = tc->getSystemPtr()->kernelSymtab;
+ Addr ksp = tc->readIntReg(TheISA::StackPointerReg);
+ Addr bottom = ksp & ~0x3fff;
+ Addr addr;
+
+ if (is_call) {
+ if (!symtab->findNearestAddr(pc, addr))
+ panic("could not find address %#x", pc);
+
+ stack.push_back(addr);
+ pc = tc->readPC();
+ }
+
+ Addr ra;
+ int size;
+
+ while (ksp > bottom) {
+ if (!symtab->findNearestAddr(pc, addr))
+ panic("could not find symbol for pc=%#x", pc);
+ assert(pc >= addr && "symbol botch: callpc < func");
+
+ stack.push_back(addr);
+
+ if (isEntry(addr))
+ return;
+
+ if (decodePrologue(ksp, pc, addr, size, ra)) {
+ if (!ra)
+ return;
+
+ if (size <= 0) {
+ stack.push_back(unknown);
+ return;
+ }
+
+ pc = ra;
+ ksp += size;
+ } else {
+ stack.push_back(unknown);
+ return;
+ }
+
+ bool kernel = tc->getSystemPtr()->kernelStart <= pc &&
+ pc <= tc->getSystemPtr()->kernelEnd;
+ if (!kernel)
+ return;
+
+ if (stack.size() >= 1000)
+ panic("unwinding too far");
+ }
+
+ panic("unwinding too far");
+#endif
+ }
+
+ bool
+ StackTrace::isEntry(Addr addr)
+ {
+#if 0
+ if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp12))
+ return true;
+
+ if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp7))
+ return true;
+
+ if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp11))
+ return true;
+
+ if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp21))
+ return true;
+
+ if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp9))
+ return true;
+
+ if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp2))
+ return true;
+#endif
+ return false;
+ }
+
+ bool
+ StackTrace::decodeStack(MachInst inst, int &disp)
+ {
+ // lda $sp, -disp($sp)
+ //
+ // Opcode<31:26> == 0x08
+ // RA<25:21> == 30
+ // RB<20:16> == 30
+ // Disp<15:0>
+ const MachInst mem_mask = 0xffff0000;
+ const MachInst lda_pattern = 0x23de0000;
+ const MachInst lda_disp_mask = 0x0000ffff;
+
+ // subq $sp, disp, $sp
+ // addq $sp, disp, $sp
+ //
+ // Opcode<31:26> == 0x10
+ // RA<25:21> == 30
+ // Lit<20:13>
+ // One<12> = 1
+ // Func<11:5> == 0x20 (addq)
+ // Func<11:5> == 0x29 (subq)
+ // RC<4:0> == 30
+ const MachInst intop_mask = 0xffe01fff;
+ const MachInst addq_pattern = 0x43c0141e;
+ const MachInst subq_pattern = 0x43c0153e;
+ const MachInst intop_disp_mask = 0x001fe000;
+ const int intop_disp_shift = 13;
+
+ if ((inst & mem_mask) == lda_pattern)
+ disp = -sext<16>(inst & lda_disp_mask);
+ else if ((inst & intop_mask) == addq_pattern)
+ disp = -int((inst & intop_disp_mask) >> intop_disp_shift);
+ else if ((inst & intop_mask) == subq_pattern)
+ disp = int((inst & intop_disp_mask) >> intop_disp_shift);
+ else
+ return false;
+
+ return true;
+ }
+
+ bool
+ StackTrace::decodeSave(MachInst inst, int &reg, int &disp)
+ {
+ // lda $stq, disp($sp)
+ //
+ // Opcode<31:26> == 0x08
+ // RA<25:21> == ?
+ // RB<20:16> == 30
+ // Disp<15:0>
+ const MachInst stq_mask = 0xfc1f0000;
+ const MachInst stq_pattern = 0xb41e0000;
+ const MachInst stq_disp_mask = 0x0000ffff;
+ const MachInst reg_mask = 0x03e00000;
+ const int reg_shift = 21;
+
+ if ((inst & stq_mask) == stq_pattern) {
+ reg = (inst & reg_mask) >> reg_shift;
+ disp = sext<16>(inst & stq_disp_mask);
+ } else {
+ return false;
+ }
+
+ return true;
+ }
+
+ /*
+ * Decode the function prologue for the function we're in, and note
+ * which registers are stored where, and how large the stack frame is.
+ */
+ bool
+ StackTrace::decodePrologue(Addr sp, Addr callpc, Addr func,
+ int &size, Addr &ra)
+ {
+ size = 0;
+ ra = 0;
+
+ for (Addr pc = func; pc < callpc; pc += sizeof(MachInst)) {
+ MachInst inst;
+ CopyOut(tc, (uint8_t *)&inst, pc, sizeof(MachInst));
+
+ int reg, disp;
+ if (decodeStack(inst, disp)) {
+ if (size) {
+ // panic("decoding frame size again");
+ return true;
+ }
+ size += disp;
+ } else if (decodeSave(inst, reg, disp)) {
+ if (!ra && reg == ReturnAddressReg) {
+ CopyOut(tc, (uint8_t *)&ra, sp + disp, sizeof(Addr));
+ if (!ra) {
+ // panic("no return address value pc=%#x\n", pc);
+ return false;
+ }
+ }
+ }
+ }
+
+ return true;
+ }
+
+#if TRACING_ON
+ void
+ StackTrace::dump()
+ {
+ StringWrap name(tc->getCpuPtr()->name());
+ SymbolTable *symtab = tc->getSystemPtr()->kernelSymtab;
+
+ DPRINTFN("------ Stack ------\n");
+
+ string symbol;
+ for (int i = 0, size = stack.size(); i < size; ++i) {
+ Addr addr = stack[size - i - 1];
+ if (addr == user)
+ symbol = "user";
+ else if (addr == console)
+ symbol = "console";
+ else if (addr == unknown)
+ symbol = "unknown";
+ else
+ symtab->findSymbol(addr, symbol);
+
+ DPRINTFN("%#x: %s\n", addr, symbol);
+ }
+ }
+#endif
+}
diff --git a/src/arch/sparc/stacktrace.hh b/src/arch/sparc/stacktrace.hh
index 54d3d17be..4bc5d779b 100644
--- a/src/arch/sparc/stacktrace.hh
+++ b/src/arch/sparc/stacktrace.hh
@@ -35,87 +35,90 @@
#include "cpu/static_inst.hh"
class ThreadContext;
-class StackTrace;
-
-class ProcessInfo
+namespace SparcISA
{
- private:
- ThreadContext *tc;
+ class StackTrace;
- int thread_info_size;
- int task_struct_size;
- int task_off;
- int pid_off;
- int name_off;
+ class ProcessInfo
+ {
+ private:
+ ThreadContext *tc;
- public:
- ProcessInfo(ThreadContext *_tc);
+ int thread_info_size;
+ int task_struct_size;
+ int task_off;
+ int pid_off;
+ int name_off;
- Addr task(Addr ksp) const;
- int pid(Addr ksp) const;
- std::string name(Addr ksp) const;
-};
+ public:
+ ProcessInfo(ThreadContext *_tc);
-class StackTrace
-{
- protected:
- typedef TheISA::MachInst MachInst;
- private:
- ThreadContext *tc;
- std::vector<Addr> stack;
-
- private:
- bool isEntry(Addr addr);
- bool decodePrologue(Addr sp, Addr callpc, Addr func, int &size, Addr &ra);
- bool decodeSave(MachInst inst, int &reg, int &disp);
- bool decodeStack(MachInst inst, int &disp);
-
- void trace(ThreadContext *tc, bool is_call);
-
- public:
- StackTrace();
- StackTrace(ThreadContext *tc, StaticInstPtr inst);
- ~StackTrace();
-
- void clear()
+ Addr task(Addr ksp) const;
+ int pid(Addr ksp) const;
+ std::string name(Addr ksp) const;
+ };
+
+ class StackTrace
{
- tc = 0;
- stack.clear();
- }
+ protected:
+ typedef TheISA::MachInst MachInst;
+ private:
+ ThreadContext *tc;
+ std::vector<Addr> stack;
+
+ private:
+ bool isEntry(Addr addr);
+ bool decodePrologue(Addr sp, Addr callpc, Addr func, int &size, Addr &ra);
+ bool decodeSave(MachInst inst, int &reg, int &disp);
+ bool decodeStack(MachInst inst, int &disp);
- bool valid() const { return tc != NULL; }
- bool trace(ThreadContext *tc, StaticInstPtr inst);
+ void trace(ThreadContext *tc, bool is_call);
- public:
- const std::vector<Addr> &getstack() const { return stack; }
+ public:
+ StackTrace();
+ StackTrace(ThreadContext *tc, StaticInstPtr inst);
+ ~StackTrace();
- static const int user = 1;
- static const int console = 2;
- static const int unknown = 3;
+ void clear()
+ {
+ tc = 0;
+ stack.clear();
+ }
+
+ bool valid() const { return tc != NULL; }
+ bool trace(ThreadContext *tc, StaticInstPtr inst);
+
+ public:
+ const std::vector<Addr> &getstack() const { return stack; }
+
+ static const int user = 1;
+ static const int console = 2;
+ static const int unknown = 3;
#if TRACING_ON
- private:
- void dump();
+ private:
+ void dump();
- public:
- void dprintf() { if (DTRACE(Stack)) dump(); }
+ public:
+ void dprintf() { if (DTRACE(Stack)) dump(); }
#else
- public:
- void dprintf() {}
+ public:
+ void dprintf() {}
#endif
-};
+ };
-inline bool
-StackTrace::trace(ThreadContext *tc, StaticInstPtr inst)
-{
- if (!inst->isCall() && !inst->isReturn())
- return false;
+ inline bool
+ StackTrace::trace(ThreadContext *tc, StaticInstPtr inst)
+ {
+ if (!inst->isCall() && !inst->isReturn())
+ return false;
- if (valid())
- clear();
+ if (valid())
+ clear();
- trace(tc, !inst->isReturn());
- return true;
+ trace(tc, !inst->isReturn());
+ return true;
+ }
}
#endif // __ARCH_SPARC_STACKTRACE_HH__
diff --git a/src/arch/sparc/system.cc b/src/arch/sparc/system.cc
index ef6443d17..952ac2deb 100644
--- a/src/arch/sparc/system.cc
+++ b/src/arch/sparc/system.cc
@@ -77,7 +77,7 @@ SparcSystem::SparcSystem(Params *p)
hypervisor->loadSections(&functionalPort, SparcISA::LoadAddrMask);
// load symbols
- if (!reset->loadGlobalSymbols(reset))
+ if (!reset->loadGlobalSymbols(resetSymtab))
panic("could not load reset symbols\n");
if (!openboot->loadGlobalSymbols(openbootSymtab))
@@ -148,7 +148,10 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(SparcSystem)
Param<std::string> hypervisor_bin;
Param<std::string> openboot_bin;
+ Param<Tick> boot_cpu_frequency;
Param<std::string> boot_osflags;
+ Param<uint64_t> system_type;
+ Param<uint64_t> system_rev;
Param<std::string> readfile;
Param<unsigned int> init_param;
@@ -156,7 +159,6 @@ END_DECLARE_SIM_OBJECT_PARAMS(SparcSystem)
BEGIN_INIT_SIM_OBJECT_PARAMS(SparcSystem)
- INIT_PARAM(boot_cpu_frequency, "Frequency of the boot CPU"),
INIT_PARAM(physmem, "phsyical memory"),
INIT_ENUM_PARAM(mem_mode, "Memory Mode, (1=atomic, 2=timing)",
System::MemoryModeStrings),
@@ -164,12 +166,13 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(SparcSystem)
INIT_PARAM(reset_bin, "file that contains the reset code"),
INIT_PARAM(hypervisor_bin, "file that contains the hypervisor code"),
INIT_PARAM(openboot_bin, "file that contains the openboot code"),
+ INIT_PARAM(boot_cpu_frequency, "Frequency of the boot CPU"),
INIT_PARAM_DFLT(boot_osflags, "flags to pass to the kernel during boot",
"a"),
- INIT_PARAM_DFLT(readfile, "file to read startup script from", ""),
- INIT_PARAM_DFLT(init_param, "numerical value to pass into simulator", 0),
INIT_PARAM_DFLT(system_type, "Type of system we are emulating", 34),
- INIT_PARAM_DFLT(system_rev, "Revision of system we are emulating", 1<<10)
+ INIT_PARAM_DFLT(system_rev, "Revision of system we are emulating", 1<<10),
+ INIT_PARAM_DFLT(readfile, "file to read startup script from", ""),
+ INIT_PARAM_DFLT(init_param, "numerical value to pass into simulator", 0)
END_INIT_SIM_OBJECT_PARAMS(SparcSystem)
diff --git a/src/arch/sparc/system.hh b/src/arch/sparc/system.hh
index 614707f6c..0b79eda38 100644
--- a/src/arch/sparc/system.hh
+++ b/src/arch/sparc/system.hh
@@ -46,7 +46,7 @@ class SparcSystem : public System
struct Params : public System::Params
{
std::string reset_bin;
- std::string hypervison_bin;
+ std::string hypervisor_bin;
std::string openboot_bin;
std::string boot_osflags;
uint64_t system_type;
@@ -111,8 +111,11 @@ class SparcSystem : public System
return addFuncEvent<T>(openbootSymtab, lbl);
}
- virtual Addr fixFuncEventAddr(Addr addr);
-
+ virtual Addr fixFuncEventAddr(Addr addr)
+ {
+ //XXX This may eventually have to do something useful.
+ return addr;
+ }
};
#endif
diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc
new file mode 100644
index 000000000..0b1a2ff5f
--- /dev/null
+++ b/src/arch/sparc/tlb.cc
@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2001-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Nathan Binkert
+ * Steve Reinhardt
+ * Andrew Schultz
+ */
+
+#include "arch/sparc/tlb.hh"
+#include "sim/builder.hh"
+
+namespace SparcISA
+{
+ DEFINE_SIM_OBJECT_CLASS_NAME("SparcTLB", TLB)
+
+ BEGIN_DECLARE_SIM_OBJECT_PARAMS(ITB)
+
+ Param<int> size;
+
+ END_DECLARE_SIM_OBJECT_PARAMS(ITB)
+
+ BEGIN_INIT_SIM_OBJECT_PARAMS(ITB)
+
+ INIT_PARAM_DFLT(size, "TLB size", 48)
+
+ END_INIT_SIM_OBJECT_PARAMS(ITB)
+
+
+ CREATE_SIM_OBJECT(ITB)
+ {
+ return new ITB(getInstanceName(), size);
+ }
+
+ REGISTER_SIM_OBJECT("SparcITB", ITB)
+
+ BEGIN_DECLARE_SIM_OBJECT_PARAMS(DTB)
+
+ Param<int> size;
+
+ END_DECLARE_SIM_OBJECT_PARAMS(DTB)
+
+ BEGIN_INIT_SIM_OBJECT_PARAMS(DTB)
+
+ INIT_PARAM_DFLT(size, "TLB size", 64)
+
+ END_INIT_SIM_OBJECT_PARAMS(DTB)
+
+
+ CREATE_SIM_OBJECT(DTB)
+ {
+ return new DTB(getInstanceName(), size);
+ }
+
+ REGISTER_SIM_OBJECT("SparcDTB", DTB)
+}
diff --git a/src/arch/sparc/tlb.hh b/src/arch/sparc/tlb.hh
index 0d42e2c97..0fdba6baf 100644
--- a/src/arch/sparc/tlb.hh
+++ b/src/arch/sparc/tlb.hh
@@ -31,19 +31,29 @@
#ifndef __ARCH_SPARC_TLB_HH__
#define __ARCH_SPARC_TLB_HH__
+#include "mem/request.hh"
#include "sim/faults.hh"
+#include "sim/sim_object.hh"
class ThreadContext;
namespace SparcISA
{
- class TLB
+ class TLB : public SimObject
{
+ public:
+ TLB(const std::string &name, int size) : SimObject(name)
+ {
+ }
};
class ITB : public TLB
{
public:
+ ITB(const std::string &name, int size) : TLB(name, size)
+ {
+ }
+
Fault translate(RequestPtr &req, ThreadContext *tc) const
{
return NoFault;
@@ -53,6 +63,10 @@ namespace SparcISA
class DTB : public TLB
{
public:
+ DTB(const std::string &name, int size) : TLB(name, size)
+ {
+ }
+
Fault translate(RequestPtr &req, ThreadContext *tc, bool write) const
{
return NoFault;
diff --git a/src/arch/sparc/utility.hh b/src/arch/sparc/utility.hh
index 23fddf0e9..e51677cdf 100644
--- a/src/arch/sparc/utility.hh
+++ b/src/arch/sparc/utility.hh
@@ -31,6 +31,7 @@
#ifndef __ARCH_SPARC_UTILITY_HH__
#define __ARCH_SPARC_UTILITY_HH__
+#include "arch/sparc/faults.hh"
#include "arch/sparc/isa_traits.hh"
#include "base/misc.hh"
#include "base/bitfield.hh"
@@ -38,6 +39,14 @@
namespace SparcISA
{
+
+ static inline bool
+ inUserMode(ThreadContext *tc)
+ {
+ return !(tc->readMiscReg(MISCREG_PSTATE & (1 << 2)) ||
+ tc->readMiscReg(MISCREG_HPSTATE & (1 << 2)));
+ }
+
inline ExtMachInst
makeExtMI(MachInst inst, ThreadContext * xc) {
ExtMachInst emi = (unsigned MachInst) inst;
@@ -99,6 +108,12 @@ namespace SparcISA
template <class TC>
void zeroRegisters(TC *tc);
+ inline void initCPU(ThreadContext *tc, int cpuId)
+ {
+ static Fault por = new PowerOnReset();
+ por->invoke(tc);
+ }
+
} // namespace SparcISA
#endif
diff --git a/src/arch/sparc/vtophys.cc b/src/arch/sparc/vtophys.cc
index f7fd92c15..429126b70 100644
--- a/src/arch/sparc/vtophys.cc
+++ b/src/arch/sparc/vtophys.cc
@@ -32,135 +32,47 @@
#include <string>
-#include "arch/alpha/ev5.hh"
-#include "arch/alpha/vtophys.hh"
+#include "arch/sparc/vtophys.hh"
#include "base/chunk_generator.hh"
#include "base/trace.hh"
#include "cpu/thread_context.hh"
#include "mem/vport.hh"
using namespace std;
-using namespace AlphaISA;
-AlphaISA::PageTableEntry
-AlphaISA::kernel_pte_lookup(FunctionalPort *mem, Addr ptbr, AlphaISA::VAddr vaddr)
+namespace SparcISA
{
- Addr level1_pte = ptbr + vaddr.level1();
- AlphaISA::PageTableEntry level1 = mem->read<uint64_t>(level1_pte);
- if (!level1.valid()) {
- DPRINTF(VtoPhys, "level 1 PTE not valid, va = %#\n", vaddr);
- return 0;
+ PageTableEntry kernel_pte_lookup(FunctionalPort *mem,
+ Addr ptbr, VAddr vaddr)
+ {
+ PageTableEntry pte(4);
+ return pte;
}
- Addr level2_pte = level1.paddr() + vaddr.level2();
- AlphaISA::PageTableEntry level2 = mem->read<uint64_t>(level2_pte);
- if (!level2.valid()) {
- DPRINTF(VtoPhys, "level 2 PTE not valid, va = %#x\n", vaddr);
- return 0;
+ Addr vtophys(Addr vaddr)
+ {
+ return vaddr;
}
- Addr level3_pte = level2.paddr() + vaddr.level3();
- AlphaISA::PageTableEntry level3 = mem->read<uint64_t>(level3_pte);
- if (!level3.valid()) {
- DPRINTF(VtoPhys, "level 3 PTE not valid, va = %#x\n", vaddr);
- return 0;
+ Addr vtophys(ThreadContext *tc, Addr addr)
+ {
+ return addr;
}
- return level3;
-}
-Addr
-AlphaISA::vtophys(Addr vaddr)
-{
- Addr paddr = 0;
- if (AlphaISA::IsUSeg(vaddr))
- DPRINTF(VtoPhys, "vtophys: invalid vaddr %#x", vaddr);
- else if (AlphaISA::IsK0Seg(vaddr))
- paddr = AlphaISA::K0Seg2Phys(vaddr);
- else
- panic("vtophys: ptbr is not set on virtual lookup");
- DPRINTF(VtoPhys, "vtophys(%#x) -> %#x\n", vaddr, paddr);
-
- return paddr;
-}
-
-Addr
-AlphaISA::vtophys(ThreadContext *tc, Addr addr)
-{
- AlphaISA::VAddr vaddr = addr;
- Addr ptbr = tc->readMiscReg(AlphaISA::IPR_PALtemp20);
- Addr paddr = 0;
- //@todo Andrew couldn't remember why he commented some of this code
- //so I put it back in. Perhaps something to do with gdb debugging?
- if (AlphaISA::PcPAL(vaddr) && (vaddr < EV5::PalMax)) {
- paddr = vaddr & ~ULL(1);
- } else {
- if (AlphaISA::IsK0Seg(vaddr)) {
- paddr = AlphaISA::K0Seg2Phys(vaddr);
- } else if (!ptbr) {
- paddr = vaddr;
- } else {
- AlphaISA::PageTableEntry pte =
- kernel_pte_lookup(tc->getPhysPort(), ptbr, vaddr);
- if (pte.valid())
- paddr = pte.paddr() | vaddr.offset();
- }
+ void CopyOut(ThreadContext *tc, void *dest, Addr src, size_t cplen)
+ {
}
+ void CopyIn(ThreadContext *tc, Addr dest, void *source, size_t cplen)
+ {
+ }
- DPRINTF(VtoPhys, "vtophys(%#x) -> %#x\n", vaddr, paddr);
-
- return paddr;
-}
-
-
-void
-AlphaISA::CopyOut(ThreadContext *tc, void *dest, Addr src, size_t cplen)
-{
- uint8_t *dst = (uint8_t *)dest;
- VirtualPort *vp = tc->getVirtPort(tc);
-
- vp->readBlob(src, dst, cplen);
-
- tc->delVirtPort(vp);
-
-}
-
-void
-AlphaISA::CopyIn(ThreadContext *tc, Addr dest, void *source, size_t cplen)
-{
- uint8_t *src = (uint8_t *)source;
- VirtualPort *vp = tc->getVirtPort(tc);
-
- vp->writeBlob(dest, src, cplen);
-
- tc->delVirtPort(vp);
-}
-
-void
-AlphaISA::CopyStringOut(ThreadContext *tc, char *dst, Addr vaddr, size_t maxlen)
-{
- int len = 0;
- VirtualPort *vp = tc->getVirtPort(tc);
-
- do {
- vp->readBlob(vaddr++, (uint8_t*)dst++, 1);
- len++;
- } while (len < maxlen && dst[len] != 0 );
-
- tc->delVirtPort(vp);
- dst[len] = 0;
-}
+ void CopyStringOut(ThreadContext *tc, char *dst, Addr vaddr, size_t maxlen)
+ {
+ }
-void
-AlphaISA::CopyStringIn(ThreadContext *tc, char *src, Addr vaddr)
-{
- VirtualPort *vp = tc->getVirtPort(tc);
- for (ChunkGenerator gen(vaddr, strlen(src), AlphaISA::PageBytes); !gen.done();
- gen.next())
+ void CopyStringIn(ThreadContext *tc, char *src, Addr vaddr)
{
- vp->writeBlob(gen.addr(), (uint8_t*)src, gen.size());
- src += gen.size();
}
- tc->delVirtPort(vp);
}
diff --git a/src/base/remote_gdb.cc b/src/base/remote_gdb.cc
index e4efa31e3..55fb97ce9 100644
--- a/src/base/remote_gdb.cc
+++ b/src/base/remote_gdb.cc
@@ -123,7 +123,6 @@
#include "arch/vtophys.hh"
#include "base/intmath.hh"
-#include "base/kgdb.h"
#include "base/remote_gdb.hh"
#include "base/socket.hh"
#include "base/trace.hh"
@@ -138,18 +137,18 @@ using namespace std;
using namespace TheISA;
#ifndef NDEBUG
-vector<RemoteGDB *> debuggers;
-int current_debugger = -1;
+vector<BaseRemoteGDB *> debuggers;
void
debugger()
{
+ static int current_debugger = -1;
if (current_debugger >= 0 && current_debugger < debuggers.size()) {
- RemoteGDB *gdb = debuggers[current_debugger];
+ BaseRemoteGDB *gdb = debuggers[current_debugger];
if (!gdb->isattached())
gdb->listener->accept();
if (gdb->isattached())
- gdb->trap(ALPHA_KENTRY_IF);
+ gdb->trap(SIGILL);
}
}
#endif
@@ -169,7 +168,7 @@ GDBListener::Event::process(int revent)
listener->accept();
}
-GDBListener::GDBListener(RemoteGDB *g, int p)
+GDBListener::GDBListener(BaseRemoteGDB *g, int p)
: event(NULL), gdb(g), port(p)
{
assert(!gdb->listener);
@@ -229,55 +228,46 @@ GDBListener::accept()
}
}
-///////////////////////////////////////////////////////////
-//
-//
-//
-int digit2i(char);
-char i2digit(int);
-void mem2hex(void *, const void *, int);
-const char *hex2mem(void *, const char *, int);
-Addr hex2i(const char **);
-
-RemoteGDB::Event::Event(RemoteGDB *g, int fd, int e)
+BaseRemoteGDB::Event::Event(BaseRemoteGDB *g, int fd, int e)
: PollEvent(fd, e), gdb(g)
{}
void
-RemoteGDB::Event::process(int revent)
+BaseRemoteGDB::Event::process(int revent)
{
if (revent & POLLIN)
- gdb->trap(ALPHA_KENTRY_IF);
+ gdb->trap(SIGILL);
else if (revent & POLLNVAL)
gdb->detach();
}
-RemoteGDB::RemoteGDB(System *_system, ThreadContext *c)
+BaseRemoteGDB::BaseRemoteGDB(System *_system, ThreadContext *c, size_t cacheSize)
: event(NULL), listener(NULL), number(-1), fd(-1),
active(false), attached(false),
- system(_system), pmem(_system->physmem), context(c)
+ system(_system), pmem(_system->physmem), context(c),
+ gdbregs(cacheSize)
{
- memset(gdbregs, 0, sizeof(gdbregs));
+ memset(gdbregs.regs, 0, gdbregs.bytes());
}
-RemoteGDB::~RemoteGDB()
+BaseRemoteGDB::~BaseRemoteGDB()
{
if (event)
delete event;
}
string
-RemoteGDB::name()
+BaseRemoteGDB::name()
{
return system->name() + ".remote_gdb";
}
bool
-RemoteGDB::isattached()
+BaseRemoteGDB::isattached()
{ return attached; }
void
-RemoteGDB::attach(int f)
+BaseRemoteGDB::attach(int f)
{
fd = f;
@@ -289,7 +279,7 @@ RemoteGDB::attach(int f)
}
void
-RemoteGDB::detach()
+BaseRemoteGDB::detach()
{
attached = false;
close(fd);
@@ -300,250 +290,50 @@ RemoteGDB::detach()
}
const char *
-gdb_command(char cmd)
+BaseRemoteGDB::gdb_command(char cmd)
{
switch (cmd) {
- case KGDB_SIGNAL: return "KGDB_SIGNAL";
- case KGDB_SET_BAUD: return "KGDB_SET_BAUD";
- case KGDB_SET_BREAK: return "KGDB_SET_BREAK";
- case KGDB_CONT: return "KGDB_CONT";
- case KGDB_ASYNC_CONT: return "KGDB_ASYNC_CONT";
- case KGDB_DEBUG: return "KGDB_DEBUG";
- case KGDB_DETACH: return "KGDB_DETACH";
- case KGDB_REG_R: return "KGDB_REG_R";
- case KGDB_REG_W: return "KGDB_REG_W";
- case KGDB_SET_THREAD: return "KGDB_SET_THREAD";
- case KGDB_CYCLE_STEP: return "KGDB_CYCLE_STEP";
- case KGDB_SIG_CYCLE_STEP: return "KGDB_SIG_CYCLE_STEP";
- case KGDB_KILL: return "KGDB_KILL";
- case KGDB_MEM_W: return "KGDB_MEM_W";
- case KGDB_MEM_R: return "KGDB_MEM_R";
- case KGDB_SET_REG: return "KGDB_SET_REG";
- case KGDB_READ_REG: return "KGDB_READ_REG";
- case KGDB_QUERY_VAR: return "KGDB_QUERY_VAR";
- case KGDB_SET_VAR: return "KGDB_SET_VAR";
- case KGDB_RESET: return "KGDB_RESET";
- case KGDB_STEP: return "KGDB_STEP";
- case KGDB_ASYNC_STEP: return "KGDB_ASYNC_STEP";
- case KGDB_THREAD_ALIVE: return "KGDB_THREAD_ALIVE";
- case KGDB_TARGET_EXIT: return "KGDB_TARGET_EXIT";
- case KGDB_BINARY_DLOAD: return "KGDB_BINARY_DLOAD";
- case KGDB_CLR_HW_BKPT: return "KGDB_CLR_HW_BKPT";
- case KGDB_SET_HW_BKPT: return "KGDB_SET_HW_BKPT";
- case KGDB_START: return "KGDB_START";
- case KGDB_END: return "KGDB_END";
- case KGDB_GOODP: return "KGDB_GOODP";
- case KGDB_BADP: return "KGDB_BADP";
+ case GDBSignal: return "KGDB_SIGNAL";
+ case GDBSetBaud: return "KGDB_SET_BAUD";
+ case GDBSetBreak: return "KGDB_SET_BREAK";
+ case GDBCont: return "KGDB_CONT";
+ case GDBAsyncCont: return "KGDB_ASYNC_CONT";
+ case GDBDebug: return "KGDB_DEBUG";
+ case GDBDetach: return "KGDB_DETACH";
+ case GDBRegR: return "KGDB_REG_R";
+ case GDBRegW: return "KGDB_REG_W";
+ case GDBSetThread: return "KGDB_SET_THREAD";
+ case GDBCycleStep: return "KGDB_CYCLE_STEP";
+ case GDBSigCycleStep: return "KGDB_SIG_CYCLE_STEP";
+ case GDBKill: return "KGDB_KILL";
+ case GDBMemW: return "KGDB_MEM_W";
+ case GDBMemR: return "KGDB_MEM_R";
+ case GDBSetReg: return "KGDB_SET_REG";
+ case GDBReadReg: return "KGDB_READ_REG";
+ case GDBQueryVar: return "KGDB_QUERY_VAR";
+ case GDBSetVar: return "KGDB_SET_VAR";
+ case GDBReset: return "KGDB_RESET";
+ case GDBStep: return "KGDB_STEP";
+ case GDBAsyncStep: return "KGDB_ASYNC_STEP";
+ case GDBThreadAlive: return "KGDB_THREAD_ALIVE";
+ case GDBTargetExit: return "KGDB_TARGET_EXIT";
+ case GDBBinaryDload: return "KGDB_BINARY_DLOAD";
+ case GDBClrHwBkpt: return "KGDB_CLR_HW_BKPT";
+ case GDBSetHwBkpt: return "KGDB_SET_HW_BKPT";
+ case GDBStart: return "KGDB_START";
+ case GDBEnd: return "KGDB_END";
+ case GDBGoodP: return "KGDB_GOODP";
+ case GDBBadP: return "KGDB_BADP";
default: return "KGDB_UNKNOWN";
}
}
-///////////////////////////////////////////////////////////
-// RemoteGDB::acc
-//
-// Determine if the mapping at va..(va+len) is valid.
-//
-bool
-RemoteGDB::acc(Addr va, size_t len)
-{
- Addr last_va;
-
- va = TheISA::TruncPage(va);
- last_va = TheISA::RoundPage(va + len);
-
- do {
- if (TheISA::IsK0Seg(va)) {
- if (va < (TheISA::K0SegBase + pmem->size())) {
- DPRINTF(GDBAcc, "acc: Mapping is valid K0SEG <= "
- "%#x < K0SEG + size\n", va);
- return true;
- } else {
- DPRINTF(GDBAcc, "acc: Mapping invalid %#x > K0SEG + size\n",
- va);
- return false;
- }
- }
-
- /**
- * This code says that all accesses to palcode (instruction and data)
- * are valid since there isn't a va->pa mapping because palcode is
- * accessed physically. At some point this should probably be cleaned up
- * but there is no easy way to do it.
- */
-
- if (AlphaISA::PcPAL(va) || va < 0x10000)
- return true;
-
- Addr ptbr = context->readMiscReg(AlphaISA::IPR_PALtemp20);
- TheISA::PageTableEntry pte = TheISA::kernel_pte_lookup(context->getPhysPort(), ptbr, va);
- if (!pte.valid()) {
- DPRINTF(GDBAcc, "acc: %#x pte is invalid\n", va);
- return false;
- }
- va += TheISA::PageBytes;
- } while (va < last_va);
-
- DPRINTF(GDBAcc, "acc: %#x mapping is valid\n", va);
- return true;
-}
-
-///////////////////////////////////////////////////////////
-// RemoteGDB::signal
-//
-// Translate a trap number into a Unix-compatible signal number.
-// (GDB only understands Unix signal numbers.)
-//
-int
-RemoteGDB::signal(int type)
-{
- switch (type) {
- case ALPHA_KENTRY_INT:
- return (SIGTRAP);
-
- case ALPHA_KENTRY_UNA:
- return (SIGBUS);
-
- case ALPHA_KENTRY_ARITH:
- return (SIGFPE);
-
- case ALPHA_KENTRY_IF:
- return (SIGILL);
-
- case ALPHA_KENTRY_MM:
- return (SIGSEGV);
-
- default:
- panic("unknown signal type");
- return 0;
- }
-}
-
-///////////////////////////////////////////////////////////
-// RemoteGDB::getregs
-//
-// Translate the kernel debugger register format into
-// the GDB register format.
-void
-RemoteGDB::getregs()
-{
- memset(gdbregs, 0, sizeof(gdbregs));
-
- gdbregs[KGDB_REG_PC] = context->readPC();
-
- // @todo: Currently this is very Alpha specific.
- if (AlphaISA::PcPAL(gdbregs[KGDB_REG_PC])) {
- for (int i = 0; i < TheISA::NumIntArchRegs; ++i) {
- gdbregs[i] = context->readIntReg(AlphaISA::reg_redir[i]);
- }
- } else {
- for (int i = 0; i < TheISA::NumIntArchRegs; ++i) {
- gdbregs[i] = context->readIntReg(i);
- }
- }
-
-#ifdef KGDB_FP_REGS
- for (int i = 0; i < TheISA::NumFloatArchRegs; ++i) {
- gdbregs[i + KGDB_REG_F0] = context->readFloatRegBits(i);
- }
-#endif
-}
-
-///////////////////////////////////////////////////////////
-// RemoteGDB::setregs
-//
-// Translate the GDB register format into the kernel
-// debugger register format.
-//
-void
-RemoteGDB::setregs()
-{
- // @todo: Currently this is very Alpha specific.
- if (AlphaISA::PcPAL(gdbregs[KGDB_REG_PC])) {
- for (int i = 0; i < TheISA::NumIntArchRegs; ++i) {
- context->setIntReg(AlphaISA::reg_redir[i], gdbregs[i]);
- }
- } else {
- for (int i = 0; i < TheISA::NumIntArchRegs; ++i) {
- context->setIntReg(i, gdbregs[i]);
- }
- }
-
-#ifdef KGDB_FP_REGS
- for (int i = 0; i < TheISA::NumFloatArchRegs; ++i) {
- context->setFloatRegBits(i, gdbregs[i + KGDB_REG_F0]);
- }
-#endif
- context->setPC(gdbregs[KGDB_REG_PC]);
-}
-
-void
-RemoteGDB::setTempBreakpoint(TempBreakpoint &bkpt, Addr addr)
-{
- DPRINTF(GDBMisc, "setTempBreakpoint: addr=%#x\n", addr);
-
- bkpt.address = addr;
- insertHardBreak(addr, 4);
-}
-
-void
-RemoteGDB::clearTempBreakpoint(TempBreakpoint &bkpt)
-{
- DPRINTF(GDBMisc, "setTempBreakpoint: addr=%#x\n",
- bkpt.address);
-
-
- removeHardBreak(bkpt.address, 4);
- bkpt.address = 0;
-}
-
-void
-RemoteGDB::clearSingleStep()
-{
- DPRINTF(GDBMisc, "clearSingleStep bt_addr=%#x nt_addr=%#x\n",
- takenBkpt.address, notTakenBkpt.address);
-
- if (takenBkpt.address != 0)
- clearTempBreakpoint(takenBkpt);
-
- if (notTakenBkpt.address != 0)
- clearTempBreakpoint(notTakenBkpt);
-}
-
-void
-RemoteGDB::setSingleStep()
-{
- Addr pc = context->readPC();
- Addr npc, bpc;
- bool set_bt = false;
-
- npc = pc + sizeof(MachInst);
-
- // User was stopped at pc, e.g. the instruction at pc was not
- // executed.
- MachInst inst = read<MachInst>(pc);
- StaticInstPtr si(inst);
- if (si->hasBranchTarget(pc, context, bpc)) {
- // Don't bother setting a breakpoint on the taken branch if it
- // is the same as the next pc
- if (bpc != npc)
- set_bt = true;
- }
-
- DPRINTF(GDBMisc, "setSingleStep bt_addr=%#x nt_addr=%#x\n",
- takenBkpt.address, notTakenBkpt.address);
-
- setTempBreakpoint(notTakenBkpt, npc);
-
- if (set_bt)
- setTempBreakpoint(takenBkpt, bpc);
-}
-
/////////////////////////
//
//
uint8_t
-RemoteGDB::getbyte()
+BaseRemoteGDB::getbyte()
{
uint8_t b;
::read(fd, &b, 1);
@@ -551,14 +341,14 @@ RemoteGDB::getbyte()
}
void
-RemoteGDB::putbyte(uint8_t b)
+BaseRemoteGDB::putbyte(uint8_t b)
{
::write(fd, &b, 1);
}
// Send a packet to gdb
void
-RemoteGDB::send(const char *bp)
+BaseRemoteGDB::send(const char *bp)
{
const char *p;
uint8_t csum, c;
@@ -567,20 +357,26 @@ RemoteGDB::send(const char *bp)
do {
p = bp;
- putbyte(KGDB_START);
+ //Start sending a packet
+ putbyte(GDBStart);
+ //Send the contents, and also keep a check sum.
for (csum = 0; (c = *p); p++) {
putbyte(c);
csum += c;
}
- putbyte(KGDB_END);
+ //Send the ending character.
+ putbyte(GDBEnd);
+ //Sent the checksum.
putbyte(i2digit(csum >> 4));
putbyte(i2digit(csum));
- } while ((c = getbyte() & 0x7f) == KGDB_BADP);
+ //Try transmitting over and over again until the other end doesn't send an
+ //error back.
+ } while ((c = getbyte() & 0x7f) == GDBBadP);
}
// Receive a packet from gdb
int
-RemoteGDB::recv(char *bp, int maxlen)
+BaseRemoteGDB::recv(char *bp, int maxlen)
{
char *p;
int c, csum;
@@ -589,28 +385,37 @@ RemoteGDB::recv(char *bp, int maxlen)
do {
p = bp;
csum = len = 0;
- while ((c = getbyte()) != KGDB_START)
+ //Find the beginning of a packet
+ while ((c = getbyte()) != GDBStart)
;
- while ((c = getbyte()) != KGDB_END && len < maxlen) {
+ //Read until you find the end of the data in the packet, and keep
+ //track of the check sum.
+ while ((c = getbyte()) != GDBEnd && len < maxlen) {
c &= 0x7f;
csum += c;
*p++ = c;
len++;
}
+
+ //Mask the check sum, and terminate the command string.
csum &= 0xff;
*p = '\0';
+ //If the command was too long, report an error.
if (len >= maxlen) {
- putbyte(KGDB_BADP);
+ putbyte(GDBBadP);
continue;
}
+ //Bring in the checksum. If the check sum matches, csum will be 0.
csum -= digit2i(getbyte()) * 16;
csum -= digit2i(getbyte());
+ //If the check sum was correct
if (csum == 0) {
- putbyte(KGDB_GOODP);
+ //Report that the packet was received correctly
+ putbyte(GDBGoodP);
// Sequence present?
if (bp[2] == ':') {
putbyte(bp[0]);
@@ -620,7 +425,8 @@ RemoteGDB::recv(char *bp, int maxlen)
}
break;
}
- putbyte(KGDB_BADP);
+ //Otherwise, report that there was a mistake.
+ putbyte(GDBBadP);
} while (1);
DPRINTF(GDBRecv, "recv: %s: %s\n", gdb_command(*bp), bp);
@@ -630,7 +436,7 @@ RemoteGDB::recv(char *bp, int maxlen)
// Read bytes from kernel address space for debugger.
bool
-RemoteGDB::read(Addr vaddr, size_t size, char *data)
+BaseRemoteGDB::read(Addr vaddr, size_t size, char *data)
{
static Addr lastaddr = 0;
static size_t lastsize = 0;
@@ -662,7 +468,7 @@ RemoteGDB::read(Addr vaddr, size_t size, char *data)
// Write bytes to kernel address space for debugger.
bool
-RemoteGDB::write(Addr vaddr, size_t size, const char *data)
+BaseRemoteGDB::write(Addr vaddr, size_t size, const char *data)
{
static Addr lastaddr = 0;
static size_t lastsize = 0;
@@ -685,21 +491,15 @@ RemoteGDB::write(Addr vaddr, size_t size, const char *data)
vp->writeBlob(vaddr, (uint8_t*)data, size);
context->delVirtPort(vp);
-#ifdef IMB
- alpha_pal_imb();
-#endif
-
return true;
}
-
-PCEventQueue *RemoteGDB::getPcEventQueue()
+PCEventQueue *BaseRemoteGDB::getPcEventQueue()
{
return &system->pcEventQueue;
}
-
-RemoteGDB::HardBreakpoint::HardBreakpoint(RemoteGDB *_gdb, Addr pc)
+BaseRemoteGDB::HardBreakpoint::HardBreakpoint(BaseRemoteGDB *_gdb, Addr pc)
: PCEvent(_gdb->getPcEventQueue(), "HardBreakpoint Event", pc),
gdb(_gdb), refcount(0)
{
@@ -707,25 +507,25 @@ RemoteGDB::HardBreakpoint::HardBreakpoint(RemoteGDB *_gdb, Addr pc)
}
void
-RemoteGDB::HardBreakpoint::process(ThreadContext *tc)
+BaseRemoteGDB::HardBreakpoint::process(ThreadContext *tc)
{
DPRINTF(GDBMisc, "handling hardware breakpoint at %#x\n", pc());
if (tc == gdb->context)
- gdb->trap(ALPHA_KENTRY_INT);
+ gdb->trap(SIGTRAP);
}
bool
-RemoteGDB::insertSoftBreak(Addr addr, size_t len)
+BaseRemoteGDB::insertSoftBreak(Addr addr, size_t len)
{
- if (len != sizeof(MachInst))
+ if (len != sizeof(TheISA::MachInst))
panic("invalid length\n");
return insertHardBreak(addr, len);
}
bool
-RemoteGDB::removeSoftBreak(Addr addr, size_t len)
+BaseRemoteGDB::removeSoftBreak(Addr addr, size_t len)
{
if (len != sizeof(MachInst))
panic("invalid length\n");
@@ -734,7 +534,7 @@ RemoteGDB::removeSoftBreak(Addr addr, size_t len)
}
bool
-RemoteGDB::insertHardBreak(Addr addr, size_t len)
+BaseRemoteGDB::insertHardBreak(Addr addr, size_t len)
{
if (len != sizeof(MachInst))
panic("invalid length\n");
@@ -751,7 +551,7 @@ RemoteGDB::insertHardBreak(Addr addr, size_t len)
}
bool
-RemoteGDB::removeHardBreak(Addr addr, size_t len)
+BaseRemoteGDB::removeHardBreak(Addr addr, size_t len)
{
if (len != sizeof(MachInst))
panic("invalid length\n");
@@ -771,8 +571,23 @@ RemoteGDB::removeHardBreak(Addr addr, size_t len)
return true;
}
+void
+BaseRemoteGDB::setTempBreakpoint(Addr bkpt)
+{
+ DPRINTF(GDBMisc, "setTempBreakpoint: addr=%#x\n", bkpt);
+ insertHardBreak(bkpt, sizeof(TheISA::MachInst));
+}
+
+void
+BaseRemoteGDB::clearTempBreakpoint(Addr &bkpt)
+{
+ DPRINTF(GDBMisc, "setTempBreakpoint: addr=%#x\n", bkpt);
+ removeHardBreak(bkpt, sizeof(TheISA::MachInst));
+ bkpt = 0;
+}
+
const char *
-break_type(char c)
+BaseRemoteGDB::break_type(char c)
{
switch(c) {
case '0': return "software breakpoint";
@@ -790,12 +605,12 @@ break_type(char c)
// makes sense to use POSIX errno values, because that is what the
// gdb/remote.c functions want to return.
bool
-RemoteGDB::trap(int type)
+BaseRemoteGDB::trap(int type)
{
uint64_t val;
size_t datalen, len;
- char data[KGDB_BUFLEN + 1];
- char buffer[sizeof(gdbregs) * 2 + 256];
+ char data[GDBPacketBufLen + 1];
+ char buffer[gdbregs.bytes() * 2 + 256];
const char *p;
char command, subcmd;
string var;
@@ -823,7 +638,7 @@ RemoteGDB::trap(int type)
active = true;
else
// Tell remote host that an exception has occurred.
- snprintf((char *)buffer, sizeof(buffer), "S%02x", signal(type));
+ snprintf((char *)buffer, sizeof(buffer), "S%02x", type);
send(buffer);
// Stick frame regs into our reg cache.
@@ -837,24 +652,25 @@ RemoteGDB::trap(int type)
p = data + 1;
switch (command) {
- case KGDB_SIGNAL:
+ case GDBSignal:
// if this command came from a running gdb, answer it --
// the other guy has no way of knowing if we're in or out
// of this loop when he issues a "remote-signal".
- snprintf((char *)buffer, sizeof(buffer), "S%02x", signal(type));
+ snprintf((char *)buffer, sizeof(buffer),
+ "S%02x", type);
send(buffer);
continue;
- case KGDB_REG_R:
- if (2 * sizeof(gdbregs) > sizeof(buffer))
+ case GDBRegR:
+ if (2 * gdbregs.bytes() > sizeof(buffer))
panic("buffer too small");
- mem2hex(buffer, gdbregs, sizeof(gdbregs));
+ mem2hex(buffer, gdbregs.regs, gdbregs.bytes());
send(buffer);
continue;
- case KGDB_REG_W:
- p = hex2mem(gdbregs, p, sizeof(gdbregs));
+ case GDBRegW:
+ p = hex2mem(gdbregs.regs, p, gdbregs.bytes());
if (p == NULL || *p != '\0')
send("E01");
else {
@@ -864,7 +680,7 @@ RemoteGDB::trap(int type)
continue;
#if 0
- case KGDB_SET_REG:
+ case GDBSetReg:
val = hex2i(&p);
if (*p++ != '=') {
send("E01");
@@ -875,14 +691,14 @@ RemoteGDB::trap(int type)
continue;
}
- gdbregs[val] = hex2i(&p);
+ gdbregs.regs[val] = hex2i(&p);
setregs();
send("OK");
continue;
#endif
- case KGDB_MEM_R:
+ case GDBMemR:
val = hex2i(&p);
if (*p++ != ',') {
send("E02");
@@ -914,7 +730,7 @@ RemoteGDB::trap(int type)
}
continue;
- case KGDB_MEM_W:
+ case GDBMemW:
val = hex2i(&p);
if (*p++ != ',') {
send("E06");
@@ -944,7 +760,7 @@ RemoteGDB::trap(int type)
send("E0B");
continue;
- case KGDB_SET_THREAD:
+ case GDBSetThread:
subcmd = *p++;
val = hex2i(&p);
if (val == 0)
@@ -953,14 +769,14 @@ RemoteGDB::trap(int type)
send("E01");
continue;
- case KGDB_DETACH:
- case KGDB_KILL:
+ case GDBDetach:
+ case GDBKill:
active = false;
clearSingleStep();
detach();
goto out;
- case KGDB_ASYNC_CONT:
+ case GDBAsyncCont:
subcmd = hex2i(&p);
if (*p++ == ';') {
val = hex2i(&p);
@@ -970,7 +786,7 @@ RemoteGDB::trap(int type)
clearSingleStep();
goto out;
- case KGDB_CONT:
+ case GDBCont:
if (p - data < datalen) {
val = hex2i(&p);
context->setPC(val);
@@ -979,7 +795,7 @@ RemoteGDB::trap(int type)
clearSingleStep();
goto out;
- case KGDB_ASYNC_STEP:
+ case GDBAsyncStep:
subcmd = hex2i(&p);
if (*p++ == ';') {
val = hex2i(&p);
@@ -989,7 +805,7 @@ RemoteGDB::trap(int type)
setSingleStep();
goto out;
- case KGDB_STEP:
+ case GDBStep:
if (p - data < datalen) {
val = hex2i(&p);
context->setPC(val);
@@ -998,7 +814,7 @@ RemoteGDB::trap(int type)
setSingleStep();
goto out;
- case KGDB_CLR_HW_BKPT:
+ case GDBClrHwBkpt:
subcmd = *p++;
if (*p++ != ',') send("E0D");
val = hex2i(&p);
@@ -1030,7 +846,7 @@ RemoteGDB::trap(int type)
send(ret ? "OK" : "E0C");
continue;
- case KGDB_SET_HW_BKPT:
+ case GDBSetHwBkpt:
subcmd = *p++;
if (*p++ != ',') send("E0D");
val = hex2i(&p);
@@ -1062,7 +878,7 @@ RemoteGDB::trap(int type)
send(ret ? "OK" : "E0C");
continue;
- case KGDB_QUERY_VAR:
+ case GDBQueryVar:
var = string(p, datalen - 1);
if (var == "C")
send("QC0");
@@ -1070,17 +886,17 @@ RemoteGDB::trap(int type)
send("");
continue;
- case KGDB_SET_BAUD:
- case KGDB_SET_BREAK:
- case KGDB_DEBUG:
- case KGDB_CYCLE_STEP:
- case KGDB_SIG_CYCLE_STEP:
- case KGDB_READ_REG:
- case KGDB_SET_VAR:
- case KGDB_RESET:
- case KGDB_THREAD_ALIVE:
- case KGDB_TARGET_EXIT:
- case KGDB_BINARY_DLOAD:
+ case GDBSetBaud:
+ case GDBSetBreak:
+ case GDBDebug:
+ case GDBCycleStep:
+ case GDBSigCycleStep:
+ case GDBReadReg:
+ case GDBSetVar:
+ case GDBReset:
+ case GDBThreadAlive:
+ case GDBTargetExit:
+ case GDBBinaryDload:
// Unsupported command
DPRINTF(GDBMisc, "Unsupported command: %s\n",
gdb_command(command));
@@ -1106,7 +922,7 @@ RemoteGDB::trap(int type)
// Convert a hex digit into an integer.
// This returns -1 if the argument passed is no valid hex digit.
int
-digit2i(char c)
+BaseRemoteGDB::digit2i(char c)
{
if (c >= '0' && c <= '9')
return (c - '0');
@@ -1121,14 +937,14 @@ digit2i(char c)
// Convert the low 4 bits of an integer into an hex digit.
char
-i2digit(int n)
+BaseRemoteGDB::i2digit(int n)
{
return ("0123456789abcdef"[n & 0x0f]);
}
// Convert a byte array into an hex string.
void
-mem2hex(void *vdst, const void *vsrc, int len)
+BaseRemoteGDB::mem2hex(void *vdst, const void *vsrc, int len)
{
char *dst = (char *)vdst;
const char *src = (const char *)vsrc;
@@ -1145,7 +961,7 @@ mem2hex(void *vdst, const void *vsrc, int len)
// hex digit. If the string ends in the middle of a byte, NULL is
// returned.
const char *
-hex2mem(void *vdst, const char *src, int maxlen)
+BaseRemoteGDB::hex2mem(void *vdst, const char *src, int maxlen)
{
char *dst = (char *)vdst;
int msb, lsb;
@@ -1166,7 +982,7 @@ hex2mem(void *vdst, const char *src, int maxlen)
// This returns a pointer to the character following the last valid
// hex digit.
Addr
-hex2i(const char **srcp)
+BaseRemoteGDB::hex2i(const char **srcp)
{
const char *src = *srcp;
Addr r = 0;
diff --git a/src/base/remote_gdb.hh b/src/base/remote_gdb.hh
index 8c3ce7572..9a3201c95 100644
--- a/src/base/remote_gdb.hh
+++ b/src/base/remote_gdb.hh
@@ -34,7 +34,6 @@
#include <map>
#include "arch/types.hh"
-#include "base/kgdb.h"
#include "cpu/pc_event.hh"
#include "base/pollevent.hh"
#include "base/socket.hh"
@@ -44,22 +43,72 @@ class ThreadContext;
class PhysicalMemory;
class GDBListener;
-class RemoteGDB
+
+enum GDBCommands
+{
+ GDBSignal = '?', // last signal
+ GDBSetBaud = 'b', // set baud (depracated)
+ GDBSetBreak = 'B', // set breakpoint (depracated)
+ GDBCont = 'c', // resume
+ GDBAsyncCont = 'C', // continue with signal
+ GDBDebug = 'd', // toggle debug flags (deprecated)
+ GDBDetach = 'D', // detach remote gdb
+ GDBRegR = 'g', // read general registers
+ GDBRegW = 'G', // write general registers
+ GDBSetThread = 'H', // set thread
+ GDBCycleStep = 'i', // step a single cycle
+ GDBSigCycleStep = 'I', // signal then cycle step
+ GDBKill = 'k', // kill program
+ GDBMemR = 'm', // read memory
+ GDBMemW = 'M', // write memory
+ GDBReadReg = 'p', // read register
+ GDBSetReg = 'P', // write register
+ GDBQueryVar = 'q', // query variable
+ GDBSetVar = 'Q', // set variable
+ GDBReset = 'r', // reset system. (Deprecated)
+ GDBStep = 's', // step
+ GDBAsyncStep = 'S', // signal and step
+ GDBThreadAlive = 'T', // find out if the thread is alive
+ GDBTargetExit = 'W', // target exited
+ GDBBinaryDload = 'X', // write memory
+ GDBClrHwBkpt = 'z', // remove breakpoint or watchpoint
+ GDBSetHwBkpt = 'Z' // insert breakpoint or watchpoint
+};
+
+const char GDBStart = '$';
+const char GDBEnd = '#';
+const char GDBGoodP = '+';
+const char GDBBadP = '-';
+
+const int GDBPacketBufLen = 1024;
+
+class BaseRemoteGDB
{
- protected:
- typedef TheISA::MachInst MachInst;
private:
friend void debugger();
friend class GDBListener;
+ //Helper functions
+ protected:
+ int digit2i(char);
+ char i2digit(int);
+ Addr hex2i(const char **);
+ //Address formats, break types, and gdb commands may change
+ //between architectures, so they're defined as virtual
+ //functions.
+ virtual void mem2hex(void *, const void *, int);
+ virtual const char * hex2mem(void *, const char *, int);
+ virtual const char * break_type(char c);
+ virtual const char * gdb_command(char cmd);
+
protected:
class Event : public PollEvent
{
protected:
- RemoteGDB *gdb;
+ BaseRemoteGDB *gdb;
public:
- Event(RemoteGDB *g, int fd, int e);
+ Event(BaseRemoteGDB *g, int fd, int e);
void process(int revent);
};
@@ -69,8 +118,8 @@ class RemoteGDB
int number;
protected:
+ //The socket commands come in through
int fd;
- uint64_t gdbregs[KGDB_NUMREGS];
protected:
#ifdef notyet
@@ -84,6 +133,24 @@ class RemoteGDB
ThreadContext *context;
protected:
+ class GdbRegCache
+ {
+ public:
+ GdbRegCache(size_t newSize) : regs(new uint64_t[newSize]), size(newSize)
+ {}
+ ~GdbRegCache()
+ {
+ delete [] regs;
+ }
+
+ uint64_t * regs;
+ size_t size;
+ size_t bytes() { return size * sizeof(uint64_t); }
+ };
+
+ GdbRegCache gdbregs;
+
+ protected:
uint8_t getbyte();
void putbyte(uint8_t b);
@@ -92,15 +159,15 @@ class RemoteGDB
protected:
// Machine memory
- bool read(Addr addr, size_t size, char *data);
- bool write(Addr addr, size_t size, const char *data);
+ virtual bool read(Addr addr, size_t size, char *data);
+ virtual bool write(Addr addr, size_t size, const char *data);
template <class T> T read(Addr addr);
template <class T> void write(Addr addr, T data);
public:
- RemoteGDB(System *system, ThreadContext *context);
- ~RemoteGDB();
+ BaseRemoteGDB(System *system, ThreadContext *context, size_t cacheSize);
+ virtual ~BaseRemoteGDB();
void replaceThreadContext(ThreadContext *tc) { context = tc; }
@@ -108,16 +175,15 @@ class RemoteGDB
void detach();
bool isattached();
- bool acc(Addr addr, size_t len);
- static int signal(int type);
+ virtual bool acc(Addr addr, size_t len) = 0;
bool trap(int type);
protected:
- void getregs();
- void setregs();
+ virtual void getregs() = 0;
+ virtual void setregs() = 0;
- void clearSingleStep();
- void setSingleStep();
+ virtual void clearSingleStep() = 0;
+ virtual void setSingleStep() = 0;
PCEventQueue *getPcEventQueue();
@@ -125,13 +191,13 @@ class RemoteGDB
class HardBreakpoint : public PCEvent
{
private:
- RemoteGDB *gdb;
+ BaseRemoteGDB *gdb;
public:
int refcount;
public:
- HardBreakpoint(RemoteGDB *_gdb, Addr addr);
+ HardBreakpoint(BaseRemoteGDB *_gdb, Addr addr);
std::string name() { return gdb->name() + ".hwbkpt"; }
virtual void process(ThreadContext *tc);
@@ -148,18 +214,8 @@ class RemoteGDB
bool removeHardBreak(Addr addr, size_t len);
protected:
- struct TempBreakpoint {
- Addr address; // set here
- MachInst bkpt_inst; // saved instruction at bkpt
- int init_count; // number of times to skip bkpt
- int count; // current count
- };
-
- TempBreakpoint notTakenBkpt;
- TempBreakpoint takenBkpt;
-
- void clearTempBreakpoint(TempBreakpoint &bkpt);
- void setTempBreakpoint(TempBreakpoint &bkpt, Addr addr);
+ void clearTempBreakpoint(Addr &bkpt);
+ void setTempBreakpoint(Addr bkpt);
public:
std::string name();
@@ -167,7 +223,7 @@ class RemoteGDB
template <class T>
inline T
-RemoteGDB::read(Addr addr)
+BaseRemoteGDB::read(Addr addr)
{
T temp;
read(addr, sizeof(T), (char *)&temp);
@@ -176,7 +232,7 @@ RemoteGDB::read(Addr addr)
template <class T>
inline void
-RemoteGDB::write(Addr addr, T data)
+BaseRemoteGDB::write(Addr addr, T data)
{ write(addr, sizeof(T), (const char *)&data); }
class GDBListener
@@ -197,11 +253,11 @@ class GDBListener
protected:
ListenSocket listener;
- RemoteGDB *gdb;
+ BaseRemoteGDB *gdb;
int port;
public:
- GDBListener(RemoteGDB *g, int p);
+ GDBListener(BaseRemoteGDB *g, int p);
~GDBListener();
void accept();
diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index 55ceea8fb..4c243a2e9 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -168,11 +168,6 @@ BaseCPU::BaseCPU(Params *p)
p->max_loads_all_threads, *counter);
}
-#if FULL_SYSTEM
- memset(interrupts, 0, sizeof(interrupts));
- intstatus = 0;
-#endif
-
functionTracingEnabled = false;
if (p->functionTrace) {
functionTraceStream = simout.find(csprintf("ftrace.%s", name()));
@@ -334,9 +329,7 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU)
}
#if FULL_SYSTEM
- for (int i = 0; i < TheISA::NumInterruptLevels; ++i)
- interrupts[i] = oldCPU->interrupts[i];
- intstatus = oldCPU->intstatus;
+ interrupts = oldCPU->interrupts;
checkInterrupts = oldCPU->checkInterrupts;
for (int i = 0; i < threadContexts.size(); ++i)
@@ -368,57 +361,33 @@ BaseCPU::ProfileEvent::process()
void
BaseCPU::post_interrupt(int int_num, int index)
{
- DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index);
-
- if (int_num < 0 || int_num >= TheISA::NumInterruptLevels)
- panic("int_num out of bounds\n");
-
- if (index < 0 || index >= sizeof(uint64_t) * 8)
- panic("int_num out of bounds\n");
-
checkInterrupts = true;
- interrupts[int_num] |= 1 << index;
- intstatus |= (ULL(1) << int_num);
+ interrupts.post(int_num, index);
}
void
BaseCPU::clear_interrupt(int int_num, int index)
{
- DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index);
-
- if (int_num < 0 || int_num >= TheISA::NumInterruptLevels)
- panic("int_num out of bounds\n");
-
- if (index < 0 || index >= sizeof(uint64_t) * 8)
- panic("int_num out of bounds\n");
-
- interrupts[int_num] &= ~(1 << index);
- if (interrupts[int_num] == 0)
- intstatus &= ~(ULL(1) << int_num);
+ interrupts.clear(int_num, index);
}
void
BaseCPU::clear_interrupts()
{
- DPRINTF(Interrupt, "Interrupts all cleared\n");
-
- memset(interrupts, 0, sizeof(interrupts));
- intstatus = 0;
+ interrupts.clear_all();
}
void
BaseCPU::serialize(std::ostream &os)
{
- SERIALIZE_ARRAY(interrupts, TheISA::NumInterruptLevels);
- SERIALIZE_SCALAR(intstatus);
+ interrupts.serialize(os);
}
void
BaseCPU::unserialize(Checkpoint *cp, const std::string &section)
{
- UNSERIALIZE_ARRAY(interrupts, TheISA::NumInterruptLevels);
- UNSERIALIZE_SCALAR(intstatus);
+ interrupts.unserialize(cp, section);
}
#endif // FULL_SYSTEM
diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index df665ed23..9257778ef 100644
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -40,6 +40,10 @@
#include "mem/mem_object.hh"
#include "arch/isa_traits.hh"
+#if FULL_SYSTEM
+#include "arch/interrupts.hh"
+#endif
+
class BranchPred;
class CheckerCPU;
class ThreadContext;
@@ -89,8 +93,9 @@ class BaseCPU : public MemObject
#if FULL_SYSTEM
protected:
- uint64_t interrupts[TheISA::NumInterruptLevels];
- uint64_t intstatus;
+// uint64_t interrupts[TheISA::NumInterruptLevels];
+// uint64_t intstatus;
+ TheISA::Interrupts interrupts;
public:
virtual void post_interrupt(int int_num, int index);
@@ -98,15 +103,8 @@ class BaseCPU : public MemObject
virtual void clear_interrupts();
bool checkInterrupts;
- bool check_interrupt(int int_num) const {
- if (int_num > TheISA::NumInterruptLevels)
- panic("int_num out of bounds\n");
-
- return interrupts[int_num] != 0;
- }
-
- bool check_interrupts() const { return intstatus != 0; }
- uint64_t intr_status() const { return intstatus; }
+ bool check_interrupts(ThreadContext * tc) const
+ { return interrupts.check_interrupts(tc); }
class ProfileEvent : public Event
{
diff --git a/src/cpu/checker/cpu.cc b/src/cpu/checker/cpu.cc
index 2e81b7b31..d6cd9409b 100644
--- a/src/cpu/checker/cpu.cc
+++ b/src/cpu/checker/cpu.cc
@@ -38,8 +38,8 @@
#include "cpu/thread_context.hh"
#if FULL_SYSTEM
+#include "arch/kernel_stats.hh"
#include "arch/vtophys.hh"
-#include "kern/kernel_stats.hh"
#endif // FULL_SYSTEM
using namespace std;
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 454f3892b..9be54529f 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -327,7 +327,6 @@ class CheckerCPU : public BaseCPU
#if FULL_SYSTEM
Fault hwrei() { return thread->hwrei(); }
- bool inPalMode() { return thread->inPalMode(); }
void ev5_trap(Fault fault) { fault->invoke(tc); }
bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
#else
diff --git a/src/cpu/checker/thread_context.hh b/src/cpu/checker/thread_context.hh
index cd399dd22..cf36d8392 100644
--- a/src/cpu/checker/thread_context.hh
+++ b/src/cpu/checker/thread_context.hh
@@ -37,8 +37,10 @@
#include "cpu/thread_context.hh"
class EndQuiesceEvent;
-namespace Kernel {
- class Statistics;
+namespace TheISA {
+ namespace Kernel {
+ class Statistics;
+ };
};
/**
@@ -91,7 +93,8 @@ class CheckerThreadContext : public ThreadContext
TheISA::DTB *getDTBPtr() { return actualTC->getDTBPtr(); }
- Kernel::Statistics *getKernelStats() { return actualTC->getKernelStats(); }
+ TheISA::Kernel::Statistics *getKernelStats()
+ { return actualTC->getKernelStats(); }
FunctionalPort *getPhysPort() { return actualTC->getPhysPort(); }
@@ -271,9 +274,6 @@ class CheckerThreadContext : public ThreadContext
checkerTC->setStCondFailures(sc_failures);
actualTC->setStCondFailures(sc_failures);
}
-#if FULL_SYSTEM
- bool inPalMode() { return actualTC->inPalMode(); }
-#endif
// @todo: Fix this!
bool misspeculating() { return actualTC->misspeculating(); }
diff --git a/src/cpu/cpuevent.hh b/src/cpu/cpuevent.hh
index 9dfae27cf..3339f8252 100644
--- a/src/cpu/cpuevent.hh
+++ b/src/cpu/cpuevent.hh
@@ -44,7 +44,7 @@ class ThreadContext;
* */
class CpuEvent : public Event
{
- private:
+ protected:
/** type of global list of cpu events. */
typedef std::vector<CpuEvent *> CpuEventList;
diff --git a/src/cpu/o3/alpha/cpu.hh b/src/cpu/o3/alpha/cpu.hh
index 01749a2a2..b62550062 100644
--- a/src/cpu/o3/alpha/cpu.hh
+++ b/src/cpu/o3/alpha/cpu.hh
@@ -153,9 +153,6 @@ class AlphaO3CPU : public FullO3CPU<Impl>
void post_interrupt(int int_num, int index);
/** HW return from error interrupt. */
Fault hwrei(unsigned tid);
- /** Returns if a specific PC is a PAL mode PC. */
- bool inPalMode(uint64_t PC)
- { return AlphaISA::PcPAL(PC); }
bool simPalCheck(int palFunc, unsigned tid);
diff --git a/src/cpu/o3/alpha/cpu_impl.hh b/src/cpu/o3/alpha/cpu_impl.hh
index f5c2170ce..04eadfa5a 100644
--- a/src/cpu/o3/alpha/cpu_impl.hh
+++ b/src/cpu/o3/alpha/cpu_impl.hh
@@ -48,8 +48,8 @@
#if FULL_SYSTEM
#include "arch/alpha/osfpal.hh"
#include "arch/isa_traits.hh"
+#include "arch/kernel_stats.hh"
#include "cpu/quiesce_event.hh"
-#include "kern/kernel_stats.hh"
#include "sim/sim_exit.hh"
#include "sim/system.hh"
#endif
@@ -270,7 +270,6 @@ template <class Impl>
void
AlphaO3CPU<Impl>::processInterrupts()
{
- using namespace TheISA;
// Check for interrupts here. For now can copy the code that
// exists within isa_fullsys_traits.hh. Also assume that thread 0
// is the one that handles the interrupts.
@@ -279,51 +278,11 @@ AlphaO3CPU<Impl>::processInterrupts()
// Check if there are any outstanding interrupts
//Handle the interrupts
- int ipl = 0;
- int summary = 0;
-
- this->checkInterrupts = false;
-
- if (this->readMiscReg(IPR_ASTRR, 0))
- panic("asynchronous traps not implemented\n");
-
- if (this->readMiscReg(IPR_SIRR, 0)) {
- for (int i = INTLEVEL_SOFTWARE_MIN;
- i < INTLEVEL_SOFTWARE_MAX; i++) {
- if (this->readMiscReg(IPR_SIRR, 0) & (ULL(1) << i)) {
- // See table 4-19 of the 21164 hardware reference
- ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
- summary |= (ULL(1) << i);
- }
- }
- }
-
- uint64_t interrupts = this->intr_status();
+ Fault interrupt = this->interrupts.getInterrupt(this->tcBase(0));
- if (interrupts) {
- for (int i = INTLEVEL_EXTERNAL_MIN;
- i < INTLEVEL_EXTERNAL_MAX; i++) {
- if (interrupts & (ULL(1) << i)) {
- // See table 4-19 of the 21164 hardware reference
- ipl = i;
- summary |= (ULL(1) << i);
- }
- }
- }
-
- if (ipl && ipl > this->readMiscReg(IPR_IPLR, 0)) {
- this->setMiscReg(IPR_ISR, summary, 0);
- this->setMiscReg(IPR_INTID, ipl, 0);
- // Checker needs to know these two registers were updated.
-#if USE_CHECKER
- if (this->checker) {
- this->checker->threadBase()->setMiscReg(IPR_ISR, summary);
- this->checker->threadBase()->setMiscReg(IPR_INTID, ipl);
- }
-#endif
- this->trap(Fault(new InterruptFault), 0);
- DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
- this->readMiscReg(IPR_IPLR, 0), ipl, summary);
+ if (interrupt != NoFault) {
+ this->checkInterrupts = false;
+ this->trap(interrupt, 0);
}
}
diff --git a/src/cpu/o3/alpha/dyn_inst.hh b/src/cpu/o3/alpha/dyn_inst.hh
index e711de510..31df8ff78 100644
--- a/src/cpu/o3/alpha/dyn_inst.hh
+++ b/src/cpu/o3/alpha/dyn_inst.hh
@@ -126,8 +126,6 @@ class AlphaDynInst : public BaseDynInst<Impl>
#if FULL_SYSTEM
/** Calls hardware return from error interrupt. */
Fault hwrei();
- /** Checks if system is in PAL mode. */
- bool inPalMode();
/** Traps to handle specified fault. */
void trap(Fault fault);
bool simPalCheck(int palFunc);
diff --git a/src/cpu/o3/alpha/dyn_inst_impl.hh b/src/cpu/o3/alpha/dyn_inst_impl.hh
index f27cd5961..6fc548a85 100644
--- a/src/cpu/o3/alpha/dyn_inst_impl.hh
+++ b/src/cpu/o3/alpha/dyn_inst_impl.hh
@@ -113,7 +113,7 @@ Fault
AlphaDynInst<Impl>::hwrei()
{
// Can only do a hwrei when in pal mode.
- if (!this->cpu->inPalMode(this->readPC()))
+ if (!(this->readPC() & 0x3))
return new AlphaISA::UnimplementedOpcodeFault;
// Set the next PC based on the value of the EXC_ADDR IPR.
@@ -128,13 +128,6 @@ AlphaDynInst<Impl>::hwrei()
}
template <class Impl>
-bool
-AlphaDynInst<Impl>::inPalMode()
-{
- return this->cpu->inPalMode(this->PC);
-}
-
-template <class Impl>
void
AlphaDynInst<Impl>::trap(Fault fault)
{
diff --git a/src/cpu/o3/alpha/thread_context.hh b/src/cpu/o3/alpha/thread_context.hh
index f0cecee35..bcecb7087 100644
--- a/src/cpu/o3/alpha/thread_context.hh
+++ b/src/cpu/o3/alpha/thread_context.hh
@@ -47,11 +47,6 @@ class AlphaTC : public O3ThreadContext<Impl>
{
return this->thread->quiesceEvent;
}
-
- /** Returns if the thread is currently in PAL mode, based on
- * the PC's value. */
- virtual bool inPalMode()
- { return TheISA::PcPAL(this->cpu->readPC(this->thread->readTid())); }
#endif
virtual uint64_t readNextNPC()
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index ecf6ed632..30052a148 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -35,6 +35,7 @@
#include <algorithm>
#include <string>
+#include "arch/utility.hh"
#include "base/loader/symtab.hh"
#include "base/timebuf.hh"
#include "cpu/exetrace.hh"
@@ -638,8 +639,7 @@ DefaultCommit<Impl>::commit()
// and no other traps or external squashes are currently pending.
// @todo: Allow other threads to handle interrupts.
if (cpu->checkInterrupts &&
- cpu->check_interrupts() &&
- !cpu->inPalMode(readPC()) &&
+ cpu->check_interrupts(cpu->tcBase(0)) &&
!trapSquash[0] &&
!tcSquash[0]) {
// Tell fetch that there is an interrupt pending. This will
@@ -1085,8 +1085,7 @@ DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
#if FULL_SYSTEM
if (thread[tid]->profile) {
-// bool usermode =
-// (cpu->readMiscReg(AlphaISA::IPR_DTB_CM, tid) & 0x18) != 0;
+// bool usermode = TheISA::inUserMode(thread[tid]->getTC());
// thread[tid]->profilePC = usermode ? 1 : head_inst->readPC();
thread[tid]->profilePC = head_inst->readPC();
ProfileNode *node = thread[tid]->profile->consume(thread[tid]->getTC(),
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index 31f3b96d6..5ef6e27ea 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -45,7 +45,6 @@
#if FULL_SYSTEM
#include "arch/tlb.hh"
#include "arch/vtophys.hh"
-#include "base/remote_gdb.hh"
#include "sim/system.hh"
#endif // FULL_SYSTEM
@@ -559,14 +558,9 @@ DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid
{
Fault fault = NoFault;
-#if FULL_SYSTEM
- // Flag to say whether or not address is physical addr.
- unsigned flags = cpu->inPalMode(fetch_PC) ? PHYSICAL : 0;
-#else
- unsigned flags = 0;
-#endif // FULL_SYSTEM
-
- if (cacheBlocked || isSwitchedOut() || (interruptPending && flags == 0)) {
+ //AlphaDep
+ if (cacheBlocked || isSwitchedOut() ||
+ (interruptPending && (fetch_PC & 0x3))) {
// Hold off fetch from getting new instructions when:
// Cache is blocked, or
// while an interrupt is pending and we're not in PAL mode, or
@@ -585,7 +579,7 @@ DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid
// Setup the memReq to do a read of the first instruction's address.
// Set the appropriate read size and flags as well.
// Build request here.
- RequestPtr mem_req = new Request(tid, fetch_PC, cacheBlkSize, flags,
+ RequestPtr mem_req = new Request(tid, fetch_PC, cacheBlkSize, 0,
fetch_PC, cpu->readCpuId(), tid);
memReq[tid] = mem_req;
diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh
index 29ee19e49..598af123e 100644
--- a/src/cpu/o3/regfile.hh
+++ b/src/cpu/o3/regfile.hh
@@ -39,8 +39,7 @@
#include "cpu/o3/comm.hh"
#if FULL_SYSTEM
-#include "kern/kernel_stats.hh"
-
+#include "arch/kernel_stats.hh"
#endif
#include <vector>
diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh
index 4556c5e22..daee2fc7d 100755
--- a/src/cpu/o3/thread_context.hh
+++ b/src/cpu/o3/thread_context.hh
@@ -83,7 +83,7 @@ class O3ThreadContext : public ThreadContext
virtual PhysicalMemory *getPhysMemPtr() { return cpu->physmem; }
/** Returns a pointer to this thread's kernel statistics. */
- virtual Kernel::Statistics *getKernelStats()
+ virtual TheISA::Kernel::Statistics *getKernelStats()
{ return thread->kernelStats; }
virtual FunctionalPort *getPhysPort() { return thread->getPhysPort(); }
diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh
index 81750ada7..8d623f5b8 100755
--- a/src/cpu/o3/thread_context_impl.hh
+++ b/src/cpu/o3/thread_context_impl.hh
@@ -194,7 +194,7 @@ void
O3ThreadContext<Impl>::regStats(const std::string &name)
{
#if FULL_SYSTEM
- thread->kernelStats = new Kernel::Statistics(cpu->system);
+ thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system);
thread->kernelStats->regStats(name + ".kern");
#endif
}
diff --git a/src/cpu/ozone/cpu.hh b/src/cpu/ozone/cpu.hh
index ccb467394..c1373944d 100644
--- a/src/cpu/ozone/cpu.hh
+++ b/src/cpu/ozone/cpu.hh
@@ -62,8 +62,10 @@ class MemoryController;
class RemoteGDB;
class GDBListener;
-namespace Kernel {
- class Statistics;
+namespace TheISA {
+ namespace Kernel {
+ class Statistics;
+ };
};
#else
@@ -127,7 +129,7 @@ class OzoneCPU : public BaseCPU
TheISA::DTB * getDTBPtr() { return cpu->dtb; }
- Kernel::Statistics *getKernelStats()
+ TheISA::Kernel::Statistics *getKernelStats()
{ return thread->getKernelStats(); }
FunctionalPort *getPhysPort() { return thread->getPhysPort(); }
@@ -239,10 +241,6 @@ class OzoneCPU : public BaseCPU
void setStCondFailures(unsigned sc_failures)
{ thread->storeCondFailures = sc_failures; }
-#if FULL_SYSTEM
- bool inPalMode() { return cpu->inPalMode(); }
-#endif
-
bool misspeculating() { return false; }
#if !FULL_SYSTEM
@@ -584,8 +582,6 @@ class OzoneCPU : public BaseCPU
#if FULL_SYSTEM
Fault hwrei();
- bool inPalMode() { return AlphaISA::PcPAL(thread.PC); }
- bool inPalMode(Addr pc) { return AlphaISA::PcPAL(pc); }
bool simPalCheck(int palFunc);
void processInterrupts();
#else
diff --git a/src/cpu/ozone/cpu_impl.hh b/src/cpu/ozone/cpu_impl.hh
index 6f5dede3e..86c973a0f 100644
--- a/src/cpu/ozone/cpu_impl.hh
+++ b/src/cpu/ozone/cpu_impl.hh
@@ -47,12 +47,12 @@
#if FULL_SYSTEM
#include "arch/faults.hh"
#include "arch/alpha/osfpal.hh"
-#include "arch/alpha/tlb.hh"
-#include "arch/alpha/types.hh"
+#include "arch/tlb.hh"
+#include "arch/types.hh"
+#include "arch/kernel_stats.hh"
#include "arch/vtophys.hh"
#include "base/callback.hh"
#include "cpu/profile.hh"
-#include "kern/kernel_stats.hh"
#include "mem/physical.hh"
#include "sim/faults.hh"
#include "sim/sim_events.hh"
@@ -891,7 +891,7 @@ void
OzoneCPU<Impl>::OzoneTC::regStats(const std::string &name)
{
#if FULL_SYSTEM
- thread->kernelStats = new Kernel::Statistics(cpu->system);
+ thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system);
thread->kernelStats->regStats(name + ".kern");
#endif
}
diff --git a/src/cpu/ozone/dyn_inst.hh b/src/cpu/ozone/dyn_inst.hh
index 532317b08..9445a5309 100644
--- a/src/cpu/ozone/dyn_inst.hh
+++ b/src/cpu/ozone/dyn_inst.hh
@@ -238,7 +238,6 @@ class OzoneDynInst : public BaseDynInst<Impl>
#if FULL_SYSTEM
Fault hwrei();
- bool inPalMode();
void trap(Fault fault);
bool simPalCheck(int palFunc);
#else
diff --git a/src/cpu/ozone/dyn_inst_impl.hh b/src/cpu/ozone/dyn_inst_impl.hh
index 68736ae61..05a66d77a 100644
--- a/src/cpu/ozone/dyn_inst_impl.hh
+++ b/src/cpu/ozone/dyn_inst_impl.hh
@@ -31,7 +31,10 @@
#include "sim/faults.hh"
#include "config/full_system.hh"
#include "cpu/ozone/dyn_inst.hh"
+
+#if FULL_SYSTEM
#include "kern/kernel_stats.hh"
+#endif
template <class Impl>
OzoneDynInst<Impl>::OzoneDynInst(OzoneCPU *cpu)
@@ -249,7 +252,7 @@ template <class Impl>
Fault
OzoneDynInst<Impl>::hwrei()
{
- if (!this->cpu->inPalMode(this->readPC()))
+ if (!(this->readPC() & 0x3))
return new AlphaISA::UnimplementedOpcodeFault;
this->setNextPC(this->thread->readMiscReg(AlphaISA::IPR_EXC_ADDR));
@@ -261,13 +264,6 @@ OzoneDynInst<Impl>::hwrei()
}
template <class Impl>
-bool
-OzoneDynInst<Impl>::inPalMode()
-{
- return this->cpu->inPalMode();
-}
-
-template <class Impl>
void
OzoneDynInst<Impl>::trap(Fault fault)
{
diff --git a/src/cpu/ozone/front_end_impl.hh b/src/cpu/ozone/front_end_impl.hh
index 6d02c58cb..73ca6afbe 100644
--- a/src/cpu/ozone/front_end_impl.hh
+++ b/src/cpu/ozone/front_end_impl.hh
@@ -462,15 +462,10 @@ Fault
FrontEnd<Impl>::fetchCacheLine()
{
// Read a cache line, based on the current PC.
-#if FULL_SYSTEM
- // Flag to say whether or not address is physical addr.
- unsigned flags = cpu->inPalMode(PC) ? PHYSICAL : 0;
-#else
- unsigned flags = 0;
-#endif // FULL_SYSTEM
Fault fault = NoFault;
- if (interruptPending && flags == 0) {
+ //AlphaDep
+ if (interruptPending && (PC & 0x3)) {
return fault;
}
diff --git a/src/cpu/ozone/inorder_back_end_impl.hh b/src/cpu/ozone/inorder_back_end_impl.hh
index 8aef9c074..87bf0a7a2 100644
--- a/src/cpu/ozone/inorder_back_end_impl.hh
+++ b/src/cpu/ozone/inorder_back_end_impl.hh
@@ -152,11 +152,11 @@ InorderBackEnd<Impl>::tick()
#if FULL_SYSTEM
if (interruptBlocked ||
(cpu->checkInterrupts &&
- cpu->check_interrupts() &&
- !cpu->inPalMode())) {
+ cpu->check_interrupts(tc))) {
if (!robEmpty()) {
interruptBlocked = true;
- } else if (robEmpty() && cpu->inPalMode()) {
+ //AlphaDep
+ } else if (robEmpty() && (PC & 0x3)) {
// Will need to let the front end continue a bit until
// we're out of pal mode. Hopefully we never get into an
// infinite loop...
diff --git a/src/cpu/ozone/lw_back_end_impl.hh b/src/cpu/ozone/lw_back_end_impl.hh
index c39b9e08b..a181c93f4 100644
--- a/src/cpu/ozone/lw_back_end_impl.hh
+++ b/src/cpu/ozone/lw_back_end_impl.hh
@@ -526,8 +526,7 @@ void
LWBackEnd<Impl>::checkInterrupts()
{
if (cpu->checkInterrupts &&
- cpu->check_interrupts() &&
- !cpu->inPalMode(thread->readPC()) &&
+ cpu->check_interrupts(tc) &&
!trapSquash &&
!tcSquash) {
frontEnd->interruptPending = true;
diff --git a/src/cpu/pc_event.hh b/src/cpu/pc_event.hh
index 6b048b2c2..3709dcd59 100644
--- a/src/cpu/pc_event.hh
+++ b/src/cpu/pc_event.hh
@@ -35,6 +35,7 @@
#include <vector>
#include "base/misc.hh"
+#include "sim/host.hh"
class ThreadContext;
class PCEventQueue;
diff --git a/src/cpu/profile.hh b/src/cpu/profile.hh
index 7f9625241..27bb4efec 100644
--- a/src/cpu/profile.hh
+++ b/src/cpu/profile.hh
@@ -33,9 +33,9 @@
#include <map>
+#include "arch/stacktrace.hh"
#include "cpu/static_inst.hh"
#include "sim/host.hh"
-#include "arch/stacktrace.hh"
class ThreadContext;
@@ -66,7 +66,7 @@ class FunctionProfile
const SymbolTable *symtab;
ProfileNode top;
std::map<Addr, Counter> pc_count;
- StackTrace trace;
+ TheISA::StackTrace trace;
public:
FunctionProfile(const SymbolTable *symtab);
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 6a2c0bbe9..ab438aa77 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -46,7 +46,6 @@
#include "cpu/smt.hh"
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
-#include "kern/kernel_stats.hh"
#include "mem/packet.hh"
#include "sim/builder.hh"
#include "sim/byteswap.hh"
@@ -58,10 +57,11 @@
#include "sim/system.hh"
#if FULL_SYSTEM
-#include "base/remote_gdb.hh"
-#include "arch/tlb.hh"
+#include "arch/kernel_stats.hh"
#include "arch/stacktrace.hh"
+#include "arch/tlb.hh"
#include "arch/vtophys.hh"
+#include "base/remote_gdb.hh"
#else // !FULL_SYSTEM
#include "mem/mem_object.hh"
#endif // FULL_SYSTEM
@@ -311,43 +311,12 @@ void
BaseSimpleCPU::checkForInterrupts()
{
#if FULL_SYSTEM
- if (checkInterrupts && check_interrupts() && !thread->inPalMode()) {
- int ipl = 0;
- int summary = 0;
- checkInterrupts = false;
-
- if (thread->readMiscReg(IPR_SIRR)) {
- for (int i = INTLEVEL_SOFTWARE_MIN;
- i < INTLEVEL_SOFTWARE_MAX; i++) {
- if (thread->readMiscReg(IPR_SIRR) & (ULL(1) << i)) {
- // See table 4-19 of 21164 hardware reference
- ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
- summary |= (ULL(1) << i);
- }
- }
- }
-
- uint64_t interrupts = thread->cpu->intr_status();
- for (int i = INTLEVEL_EXTERNAL_MIN;
- i < INTLEVEL_EXTERNAL_MAX; i++) {
- if (interrupts & (ULL(1) << i)) {
- // See table 4-19 of 21164 hardware reference
- ipl = i;
- summary |= (ULL(1) << i);
- }
- }
-
- if (thread->readMiscReg(IPR_ASTRR))
- panic("asynchronous traps not implemented\n");
-
- if (ipl && ipl > thread->readMiscReg(IPR_IPLR)) {
- thread->setMiscReg(IPR_ISR, summary);
- thread->setMiscReg(IPR_INTID, ipl);
-
- Fault(new InterruptFault)->invoke(tc);
+ if (checkInterrupts && check_interrupts(tc)) {
+ Fault interrupt = interrupts.getInterrupt(tc);
- DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
- thread->readMiscReg(IPR_IPLR), ipl, summary);
+ if (interrupt != NoFault) {
+ checkInterrupts = false;
+ interrupt->invoke(tc);
}
}
#endif
@@ -402,6 +371,10 @@ BaseSimpleCPU::preExecute()
StaticInstPtr instPtr = StaticInst::decode(makeExtMI(inst, thread->readPC()));
#elif THE_ISA == SPARC_ISA
StaticInstPtr instPtr = StaticInst::decode(makeExtMI(inst, thread->getTC()));
+#elif THE_ISA == MIPS_ISA
+ //Mips doesn't do anything in it's MakeExtMI function right now,
+ //so it won't be called.
+ StaticInstPtr instPtr = StaticInst::decode(inst);
#endif
if (instPtr->isMacroOp()) {
curMacroStaticInst = instPtr;
@@ -434,8 +407,7 @@ BaseSimpleCPU::postExecute()
{
#if FULL_SYSTEM
if (thread->profile) {
- bool usermode =
- (thread->readMiscReg(AlphaISA::IPR_DTB_CM) & 0x18) != 0;
+ bool usermode = TheISA::inUserMode(tc);
thread->profilePC = usermode ? 1 : thread->readPC();
ProfileNode *node = thread->profile->consume(tc, inst);
if (node)
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index d13be2877..efb884325 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -302,7 +302,6 @@ class BaseSimpleCPU : public BaseCPU
#if FULL_SYSTEM
Fault hwrei() { return thread->hwrei(); }
- bool inPalMode() { return thread->inPalMode(); }
void ev5_trap(Fault fault) { fault->invoke(tc); }
bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
#else
diff --git a/src/cpu/simple_thread.cc b/src/cpu/simple_thread.cc
index 8bb4ec46b..1edcbf352 100644
--- a/src/cpu/simple_thread.cc
+++ b/src/cpu/simple_thread.cc
@@ -39,13 +39,13 @@
#include "cpu/thread_context.hh"
#if FULL_SYSTEM
+#include "arch/kernel_stats.hh"
#include "base/callback.hh"
#include "base/cprintf.hh"
#include "base/output.hh"
#include "base/trace.hh"
#include "cpu/profile.hh"
#include "cpu/quiesce_event.hh"
-#include "kern/kernel_stats.hh"
#include "sim/serialize.hh"
#include "sim/sim_exit.hh"
#include "arch/stacktrace.hh"
@@ -87,7 +87,7 @@ SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
profilePC = 3;
if (use_kernel_stats) {
- kernelStats = new Kernel::Statistics(system);
+ kernelStats = new TheISA::Kernel::Statistics(system);
} else {
kernelStats = NULL;
}
@@ -158,7 +158,7 @@ SimpleThread::takeOverFrom(ThreadContext *oldContext)
quiesceEvent->tc = tc;
}
- Kernel::Statistics *stats = oldContext->getKernelStats();
+ TheISA::Kernel::Statistics *stats = oldContext->getKernelStats();
if (stats) {
kernelStats = stats;
}
@@ -179,7 +179,7 @@ SimpleThread::copyTC(ThreadContext *context)
if (quiesce) {
quiesceEvent = quiesce;
}
- Kernel::Statistics *stats = context->getKernelStats();
+ TheISA::Kernel::Statistics *stats = context->getKernelStats();
if (stats) {
kernelStats = stats;
}
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 9a575f06b..e8757c8c2 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -55,8 +55,10 @@ class ProfileNode;
class FunctionalPort;
class PhysicalPort;
-namespace Kernel {
- class Statistics;
+namespace TheISA {
+ namespace Kernel {
+ class Statistics;
+ };
};
#else // !FULL_SYSTEM
@@ -440,10 +442,6 @@ class SimpleThread : public ThreadState
void setStCondFailures(unsigned sc_failures)
{ storeCondFailures = sc_failures; }
-#if FULL_SYSTEM
- bool inPalMode() { return AlphaISA::PcPAL(regs.readPC()); }
-#endif
-
#if !FULL_SYSTEM
TheISA::IntReg getSyscallArg(int i)
{
diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index dfc6fbc2a..1e6a907f8 100644
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -56,8 +56,10 @@ class FunctionalPort;
class VirtualPort;
class Process;
class System;
-namespace Kernel {
- class Statistics;
+namespace TheISA {
+ namespace Kernel {
+ class Statistics;
+ };
};
/**
@@ -124,7 +126,7 @@ class ThreadContext
virtual TheISA::DTB *getDTBPtr() = 0;
- virtual Kernel::Statistics *getKernelStats() = 0;
+ virtual TheISA::Kernel::Statistics *getKernelStats() = 0;
virtual FunctionalPort *getPhysPort() = 0;
@@ -236,10 +238,6 @@ class ThreadContext
virtual void setStCondFailures(unsigned sc_failures) = 0;
-#if FULL_SYSTEM
- virtual bool inPalMode() = 0;
-#endif
-
// Only really makes sense for old CPU model. Still could be useful though.
virtual bool misspeculating() = 0;
@@ -299,7 +297,8 @@ class ProxyThreadContext : public ThreadContext
TheISA::DTB *getDTBPtr() { return actualTC->getDTBPtr(); }
- Kernel::Statistics *getKernelStats() { return actualTC->getKernelStats(); }
+ TheISA::Kernel::Statistics *getKernelStats()
+ { return actualTC->getKernelStats(); }
FunctionalPort *getPhysPort() { return actualTC->getPhysPort(); }
@@ -424,9 +423,6 @@ class ProxyThreadContext : public ThreadContext
void setStCondFailures(unsigned sc_failures)
{ actualTC->setStCondFailures(sc_failures); }
-#if FULL_SYSTEM
- bool inPalMode() { return actualTC->inPalMode(); }
-#endif
// @todo: Fix this!
bool misspeculating() { return actualTC->misspeculating(); }
diff --git a/src/cpu/thread_state.cc b/src/cpu/thread_state.cc
index a6fff5fc3..8602f8a50 100644
--- a/src/cpu/thread_state.cc
+++ b/src/cpu/thread_state.cc
@@ -37,8 +37,8 @@
#include "sim/serialize.hh"
#if FULL_SYSTEM
+#include "arch/kernel_stats.hh"
#include "cpu/quiesce_event.hh"
-#include "kern/kernel_stats.hh"
#endif
#if FULL_SYSTEM
diff --git a/src/cpu/thread_state.hh b/src/cpu/thread_state.hh
index 862d671f2..0a0af8b71 100644
--- a/src/cpu/thread_state.hh
+++ b/src/cpu/thread_state.hh
@@ -44,8 +44,10 @@
class EndQuiesceEvent;
class FunctionProfile;
class ProfileNode;
-namespace Kernel {
- class Statistics;
+namespace TheISA {
+ namespace Kernel {
+ class Statistics;
+ };
};
#endif
@@ -97,7 +99,7 @@ struct ThreadState {
void profileSample();
- Kernel::Statistics *getKernelStats() { return kernelStats; }
+ TheISA::Kernel::Statistics *getKernelStats() { return kernelStats; }
FunctionalPort *getPhysPort() { return physPort; }
@@ -187,7 +189,7 @@ struct ThreadState {
Addr profilePC;
EndQuiesceEvent *quiesceEvent;
- Kernel::Statistics *kernelStats;
+ TheISA::Kernel::Statistics *kernelStats;
protected:
/** A functional port outgoing only for functional accesses to physical
* addresses.*/
diff --git a/src/dev/SConscript b/src/dev/SConscript
new file mode 100644
index 000000000..951bc29d1
--- /dev/null
+++ b/src/dev/SConscript
@@ -0,0 +1,79 @@
+# -*- mode:python -*-
+
+# Copyright (c) 2006 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Steve Reinhardt
+# Gabe Black
+
+import os.path, sys
+
+# Import build environment variable from SConstruct.
+Import('env')
+
+# Right now there are no source files immediately in this directory
+sources = []
+
+#
+# Now include other ISA-specific sources from the ISA subdirectories.
+#
+
+isa = env['TARGET_ISA'] # someday this may be a list of ISAs
+
+#
+# These source files can be used by any architecture
+#
+
+sources += Split('''
+ baddev.cc
+ disk_image.cc
+ etherbus.cc
+ etherdump.cc
+ etherint.cc
+ etherlink.cc
+ etherpkt.cc
+ ethertap.cc
+ ide_ctrl.cc
+ ide_disk.cc
+ io_device.cc
+ isa_fake.cc
+ ns_gige.cc
+ pciconfigall.cc
+ pcidev.cc
+ pktfifo.cc
+ platform.cc
+ simconsole.cc
+ simple_disk.cc
+ ''')
+
+# Let the target architecture define what additional sources it needs
+sources += SConscript(os.path.join(isa, 'SConscript'), exports = 'env')
+
+# Convert file names to SCons File objects. This takes care of the
+# path relative to the top of the directory tree.
+sources = [File(s) for s in sources]
+
+Return('sources')
diff --git a/src/dev/alpha/SConscript b/src/dev/alpha/SConscript
new file mode 100644
index 000000000..fb0e626d3
--- /dev/null
+++ b/src/dev/alpha/SConscript
@@ -0,0 +1,68 @@
+# -*- mode:python -*-
+
+# Copyright (c) 2006 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Steve Reinhardt
+# Gabe Black
+
+import os.path, sys
+
+# Import build environment variable from SConstruct.
+Import('env')
+
+sources = Split('''
+ console.cc
+ tsunami.cc
+ tsunami_cchip.cc
+ tsunami_io.cc
+ tsunami_pchip.cc
+ ''')
+# baddev.cc
+# disk_image.cc
+# etherbus.cc
+# etherdump.cc
+# etherint.cc
+# etherlink.cc
+# etherpkt.cc
+# ethertap.cc
+# ide_ctrl.cc
+# ide_disk.cc
+# io_device.cc
+# isa_fake.cc
+# ns_gige.cc
+# pciconfigall.cc
+# pcidev.cc
+# pktfifo.cc
+# platform.cc
+# simconsole.cc
+# simple_disk.cc
+
+# Convert file names to SCons File objects. This takes care of the
+# path relative to the top of the directory tree.
+sources = [File(s) for s in sources]
+
+Return('sources')
diff --git a/src/dev/alpha_access.h b/src/dev/alpha/access.h
index 4adeaf84b..4adeaf84b 100644
--- a/src/dev/alpha_access.h
+++ b/src/dev/alpha/access.h
diff --git a/src/dev/alpha_console.cc b/src/dev/alpha/console.cc
index 40868de51..f077efe6c 100644
--- a/src/dev/alpha_console.cc
+++ b/src/dev/alpha/console.cc
@@ -44,7 +44,7 @@
#include "base/trace.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
-#include "dev/alpha_console.hh"
+#include "dev/alpha/console.hh"
#include "dev/platform.hh"
#include "dev/simconsole.hh"
#include "dev/simple_disk.hh"
diff --git a/src/dev/alpha_console.hh b/src/dev/alpha/console.hh
index 7d6d1e679..b8d21ad5d 100644
--- a/src/dev/alpha_console.hh
+++ b/src/dev/alpha/console.hh
@@ -36,7 +36,7 @@
#define __ALPHA_CONSOLE_HH__
#include "base/range.hh"
-#include "dev/alpha_access.h"
+#include "dev/alpha/access.h"
#include "dev/io_device.hh"
#include "sim/host.hh"
#include "sim/sim_object.hh"
diff --git a/src/dev/tsunami.cc b/src/dev/alpha/tsunami.cc
index 8e740a72f..608e88846 100644
--- a/src/dev/tsunami.cc
+++ b/src/dev/alpha/tsunami.cc
@@ -38,10 +38,10 @@
#include "cpu/intr_control.hh"
#include "dev/simconsole.hh"
-#include "dev/tsunami_cchip.hh"
-#include "dev/tsunami_pchip.hh"
-#include "dev/tsunami_io.hh"
-#include "dev/tsunami.hh"
+#include "dev/alpha/tsunami_cchip.hh"
+#include "dev/alpha/tsunami_pchip.hh"
+#include "dev/alpha/tsunami_io.hh"
+#include "dev/alpha/tsunami.hh"
#include "sim/builder.hh"
#include "sim/system.hh"
diff --git a/src/dev/tsunami.hh b/src/dev/alpha/tsunami.hh
index 6fbfac851..6fbfac851 100644
--- a/src/dev/tsunami.hh
+++ b/src/dev/alpha/tsunami.hh
diff --git a/src/dev/tsunami_cchip.cc b/src/dev/alpha/tsunami_cchip.cc
index 74a68566c..924e1d462 100644
--- a/src/dev/tsunami_cchip.cc
+++ b/src/dev/alpha/tsunami_cchip.cc
@@ -41,9 +41,9 @@
#include "base/trace.hh"
#include "cpu/intr_control.hh"
#include "cpu/thread_context.hh"
-#include "dev/tsunami.hh"
-#include "dev/tsunami_cchip.hh"
-#include "dev/tsunamireg.h"
+#include "dev/alpha/tsunami.hh"
+#include "dev/alpha/tsunami_cchip.hh"
+#include "dev/alpha/tsunamireg.h"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "mem/port.hh"
diff --git a/src/dev/tsunami_cchip.hh b/src/dev/alpha/tsunami_cchip.hh
index 297a94129..004c3cd29 100644
--- a/src/dev/tsunami_cchip.hh
+++ b/src/dev/alpha/tsunami_cchip.hh
@@ -35,7 +35,7 @@
#ifndef __TSUNAMI_CCHIP_HH__
#define __TSUNAMI_CCHIP_HH__
-#include "dev/tsunami.hh"
+#include "dev/alpha/tsunami.hh"
#include "base/range.hh"
#include "dev/io_device.hh"
diff --git a/src/dev/tsunami_io.cc b/src/dev/alpha/tsunami_io.cc
index 73af6c2ef..def214a95 100644
--- a/src/dev/tsunami_io.cc
+++ b/src/dev/alpha/tsunami_io.cc
@@ -43,10 +43,10 @@
#include "base/trace.hh"
#include "dev/pitreg.h"
#include "dev/rtcreg.h"
-#include "dev/tsunami_cchip.hh"
-#include "dev/tsunami.hh"
-#include "dev/tsunami_io.hh"
-#include "dev/tsunamireg.h"
+#include "dev/alpha/tsunami_cchip.hh"
+#include "dev/alpha/tsunami.hh"
+#include "dev/alpha/tsunami_io.hh"
+#include "dev/alpha/tsunamireg.h"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "mem/port.hh"
diff --git a/src/dev/tsunami_io.hh b/src/dev/alpha/tsunami_io.hh
index 5ea3628c1..54acefc25 100644
--- a/src/dev/tsunami_io.hh
+++ b/src/dev/alpha/tsunami_io.hh
@@ -39,7 +39,7 @@
#include "dev/io_device.hh"
#include "base/range.hh"
-#include "dev/tsunami.hh"
+#include "dev/alpha/tsunami.hh"
#include "sim/eventq.hh"
/**
diff --git a/src/dev/tsunami_pchip.cc b/src/dev/alpha/tsunami_pchip.cc
index 549db1a50..94a7f96e5 100644
--- a/src/dev/tsunami_pchip.cc
+++ b/src/dev/alpha/tsunami_pchip.cc
@@ -38,9 +38,9 @@
#include <vector>
#include "base/trace.hh"
-#include "dev/tsunami_pchip.hh"
-#include "dev/tsunamireg.h"
-#include "dev/tsunami.hh"
+#include "dev/alpha/tsunami_pchip.hh"
+#include "dev/alpha/tsunamireg.h"
+#include "dev/alpha/tsunami.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "sim/builder.hh"
diff --git a/src/dev/tsunami_pchip.hh b/src/dev/alpha/tsunami_pchip.hh
index d0a9c3157..1632a36d4 100644
--- a/src/dev/tsunami_pchip.hh
+++ b/src/dev/alpha/tsunami_pchip.hh
@@ -35,7 +35,7 @@
#ifndef __TSUNAMI_PCHIP_HH__
#define __TSUNAMI_PCHIP_HH__
-#include "dev/tsunami.hh"
+#include "dev/alpha/tsunami.hh"
#include "base/range.hh"
#include "dev/io_device.hh"
diff --git a/src/dev/tsunamireg.h b/src/dev/alpha/tsunamireg.h
index d603972be..d603972be 100644
--- a/src/dev/tsunamireg.h
+++ b/src/dev/alpha/tsunamireg.h
diff --git a/src/dev/ide_disk.cc b/src/dev/ide_disk.cc
index 5d3346b1e..5083c9c8d 100644
--- a/src/dev/ide_disk.cc
+++ b/src/dev/ide_disk.cc
@@ -44,8 +44,8 @@
#include "dev/disk_image.hh"
#include "dev/ide_disk.hh"
#include "dev/ide_ctrl.hh"
-#include "dev/tsunami.hh"
-#include "dev/tsunami_pchip.hh"
+#include "dev/alpha/tsunami.hh"
+#include "dev/alpha/tsunami_pchip.hh"
#include "sim/builder.hh"
#include "sim/sim_object.hh"
#include "sim/root.hh"
diff --git a/src/dev/isa_fake.hh b/src/dev/isa_fake.hh
index e35b9c58f..fee41e325 100644
--- a/src/dev/isa_fake.hh
+++ b/src/dev/isa_fake.hh
@@ -37,7 +37,7 @@
#include "base/range.hh"
#include "dev/io_device.hh"
-#include "dev/tsunami.hh"
+#include "dev/alpha/tsunami.hh"
#include "mem/packet.hh"
/**
diff --git a/src/dev/ns_gige.cc b/src/dev/ns_gige.cc
index 19c553d87..74f9d88d1 100644
--- a/src/dev/ns_gige.cc
+++ b/src/dev/ns_gige.cc
@@ -36,7 +36,6 @@
#include <deque>
#include <string>
-#include "arch/alpha/ev5.hh"
#include "base/inet.hh"
#include "cpu/thread_context.hh"
#include "dev/etherlink.hh"
diff --git a/src/dev/pcidev.cc b/src/dev/pcidev.cc
index 8c0d03817..383fc494f 100644
--- a/src/dev/pcidev.cc
+++ b/src/dev/pcidev.cc
@@ -45,7 +45,7 @@
#include "base/trace.hh"
#include "dev/pciconfigall.hh"
#include "dev/pcidev.hh"
-#include "dev/tsunamireg.h"
+#include "dev/alpha/tsunamireg.h"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "sim/builder.hh"
diff --git a/src/dev/sparc/SConscript b/src/dev/sparc/SConscript
new file mode 100644
index 000000000..701e533a8
--- /dev/null
+++ b/src/dev/sparc/SConscript
@@ -0,0 +1,46 @@
+# -*- mode:python -*-
+
+# Copyright (c) 2006 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Steve Reinhardt
+# Gabe Black
+
+import os.path, sys
+
+# Import build environment variable from SConstruct.
+Import('env')
+
+sources = []
+
+sources += Split('''
+ ''')
+
+# Convert file names to SCons File objects. This takes care of the
+# path relative to the top of the directory tree.
+sources = [File(s) for s in sources]
+
+Return('sources')
diff --git a/src/dev/uart8250.cc b/src/dev/uart8250.cc
index 9051a26a2..ddee33695 100644
--- a/src/dev/uart8250.cc
+++ b/src/dev/uart8250.cc
@@ -35,7 +35,6 @@
#include <string>
#include <vector>
-#include "arch/alpha/ev5.hh"
#include "base/inifile.hh"
#include "base/str.hh" // for to_number
#include "base/trace.hh"
diff --git a/src/dev/uart8250.hh b/src/dev/uart8250.hh
index 2e768216a..a0620c7e0 100644
--- a/src/dev/uart8250.hh
+++ b/src/dev/uart8250.hh
@@ -35,7 +35,7 @@
#ifndef __DEV_UART8250_HH__
#define __DEV_UART8250_HH__
-#include "dev/tsunamireg.h"
+#include "dev/alpha/tsunamireg.h"
#include "base/range.hh"
#include "dev/io_device.hh"
#include "dev/uart.hh"
diff --git a/src/kern/SConscript b/src/kern/SConscript
new file mode 100644
index 000000000..12df28836
--- /dev/null
+++ b/src/kern/SConscript
@@ -0,0 +1,48 @@
+# -*- mode:python -*-
+
+# Copyright (c) 2006 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Steve Reinhardt
+
+import os.path, sys
+
+# Import build environment variable from SConstruct.
+Import('env')
+
+sources = Split('''
+ kernel_stats.cc
+ system_events.cc
+ linux/events.cc
+ linux/linux_syscalls.cc
+ linux/printk.cc
+ ''')
+
+# Convert file names to SCons File objects. This takes care of the
+# path relative to the top of the directory tree.
+sources = [File(s) for s in sources]
+
+Return('sources')
diff --git a/src/kern/kernel_stats.cc b/src/kern/kernel_stats.cc
index f7868b50f..29c77b3d9 100644
--- a/src/kern/kernel_stats.cc
+++ b/src/kern/kernel_stats.cc
@@ -29,11 +29,8 @@
* Nathan Binkert
*/
-#include <map>
-#include <stack>
#include <string>
-#include "arch/alpha/osfpal.hh"
#include "base/trace.hh"
#include "cpu/thread_context.hh"
#include "kern/kernel_stats.hh"
@@ -45,11 +42,8 @@ using namespace Stats;
namespace Kernel {
-const char *modestr[] = { "kernel", "user", "idle" };
-
Statistics::Statistics(System *system)
- : idleProcess((Addr)-1), themode(kernel), lastModeTick(0),
- iplLast(0), iplLastTick(0)
+ : iplLast(0), iplLastTick(0)
{
}
@@ -68,21 +62,6 @@ Statistics::regStats(const string &_name)
.desc("number of quiesce instructions executed")
;
- _ivlb
- .name(name() + ".inst.ivlb")
- .desc("number of ivlb instructions executed")
- ;
-
- _ivle
- .name(name() + ".inst.ivle")
- .desc("number of ivle instructions executed")
- ;
-
- _hwrei
- .name(name() + ".inst.hwrei")
- .desc("number of hwrei instructions executed")
- ;
-
_iplCount
.init(32)
.name(name() + ".ipl_count")
@@ -112,19 +91,6 @@ Statistics::regStats(const string &_name)
_iplUsed = _iplGood / _iplCount;
- _callpal
- .init(256)
- .name(name() + ".callpal")
- .desc("number of callpals executed")
- .flags(total | pdf | nozero | nonan)
- ;
-
- for (int i = 0; i < PAL::NumCodes; ++i) {
- const char *str = PAL::name(i);
- if (str)
- _callpal.subname(i, str);
- }
-
_syscall
.init(SystemCalls<Tru64>::Number)
.name(name() + ".syscall")
@@ -132,81 +98,15 @@ Statistics::regStats(const string &_name)
.flags(total | pdf | nozero | nonan)
;
+ //@todo This needs to get the names of syscalls from an appropriate place.
+#if 0
for (int i = 0; i < SystemCalls<Tru64>::Number; ++i) {
const char *str = SystemCalls<Tru64>::name(i);
if (str) {
_syscall.subname(i, str);
}
}
-
- _mode
- .init(cpu_mode_num)
- .name(name() + ".mode_switch")
- .desc("number of protection mode switches")
- ;
-
- for (int i = 0; i < cpu_mode_num; ++i)
- _mode.subname(i, modestr[i]);
-
- _modeGood
- .init(cpu_mode_num)
- .name(name() + ".mode_good")
- ;
-
- for (int i = 0; i < cpu_mode_num; ++i)
- _modeGood.subname(i, modestr[i]);
-
- _modeFraction
- .name(name() + ".mode_switch_good")
- .desc("fraction of useful protection mode switches")
- .flags(total)
- ;
-
- for (int i = 0; i < cpu_mode_num; ++i)
- _modeFraction.subname(i, modestr[i]);
-
- _modeFraction = _modeGood / _mode;
-
- _modeTicks
- .init(cpu_mode_num)
- .name(name() + ".mode_ticks")
- .desc("number of ticks spent at the given mode")
- .flags(pdf)
- ;
- for (int i = 0; i < cpu_mode_num; ++i)
- _modeTicks.subname(i, modestr[i]);
-
- _swap_context
- .name(name() + ".swap_context")
- .desc("number of times the context was actually changed")
- ;
-}
-
-void
-Statistics::setIdleProcess(Addr idlepcbb, ThreadContext *tc)
-{
- assert(themode == kernel);
- idleProcess = idlepcbb;
- themode = idle;
- changeMode(themode, tc);
-}
-
-void
-Statistics::changeMode(cpu_mode newmode, ThreadContext *tc)
-{
- _mode[newmode]++;
-
- if (newmode == themode)
- return;
-
- DPRINTF(Context, "old mode=%-8s new mode=%-8s\n",
- modestr[themode], modestr[newmode]);
-
- _modeGood[newmode]++;
- _modeTicks[themode] += curTick - lastModeTick;
-
- lastModeTick = curTick;
- themode = newmode;
+#endif
}
void
@@ -226,65 +126,17 @@ Statistics::swpipl(int ipl)
}
void
-Statistics::mode(cpu_mode newmode, ThreadContext *tc)
-{
- Addr pcbb = tc->readMiscReg(AlphaISA::IPR_PALtemp23);
-
- if (newmode == kernel && pcbb == idleProcess)
- newmode = idle;
-
- changeMode(newmode, tc);
-}
-
-void
-Statistics::context(Addr oldpcbb, Addr newpcbb, ThreadContext *tc)
-{
- assert(themode != user);
-
- _swap_context++;
- changeMode(newpcbb == idleProcess ? idle : kernel, tc);
-}
-
-void
-Statistics::callpal(int code, ThreadContext *tc)
-{
- if (!PAL::name(code))
- return;
-
- _callpal[code]++;
-
- switch (code) {
- case PAL::callsys: {
- int number = tc->readIntReg(0);
- if (SystemCalls<Tru64>::validSyscallNumber(number)) {
- int cvtnum = SystemCalls<Tru64>::convert(number);
- _syscall[cvtnum]++;
- }
- } break;
- }
-}
-
-void
Statistics::serialize(ostream &os)
{
- int exemode = themode;
- SERIALIZE_SCALAR(exemode);
- SERIALIZE_SCALAR(idleProcess);
SERIALIZE_SCALAR(iplLast);
SERIALIZE_SCALAR(iplLastTick);
- SERIALIZE_SCALAR(lastModeTick);
}
void
Statistics::unserialize(Checkpoint *cp, const string &section)
{
- int exemode;
- UNSERIALIZE_SCALAR(exemode);
- UNSERIALIZE_SCALAR(idleProcess);
UNSERIALIZE_SCALAR(iplLast);
UNSERIALIZE_SCALAR(iplLastTick);
- UNSERIALIZE_SCALAR(lastModeTick);
- themode = (cpu_mode)exemode;
}
/* end namespace Kernel */ }
diff --git a/src/kern/kernel_stats.hh b/src/kern/kernel_stats.hh
index c691ad8cf..66248c9c8 100644
--- a/src/kern/kernel_stats.hh
+++ b/src/kern/kernel_stats.hh
@@ -32,12 +32,10 @@
#ifndef __KERNEL_STATS_HH__
#define __KERNEL_STATS_HH__
-#include <map>
-#include <stack>
#include <string>
-#include <vector>
#include "cpu/static_inst.hh"
+#include "sim/serialize.hh"
class BaseCPU;
class ThreadContext;
@@ -47,25 +45,14 @@ class System;
namespace Kernel {
-enum cpu_mode { kernel, user, idle, cpu_mode_num };
-extern const char *modestr[];
-
class Statistics : public Serializable
{
- private:
+ protected:
std::string myname;
- Addr idleProcess;
- cpu_mode themode;
- Tick lastModeTick;
-
- void changeMode(cpu_mode newmode, ThreadContext *tc);
-
- private:
+ protected:
Stats::Scalar<> _arm;
Stats::Scalar<> _quiesce;
- Stats::Scalar<> _ivlb;
- Stats::Scalar<> _ivle;
Stats::Scalar<> _hwrei;
Stats::Vector<> _iplCount;
@@ -73,23 +60,16 @@ class Statistics : public Serializable
Stats::Vector<> _iplTicks;
Stats::Formula _iplUsed;
- Stats::Vector<> _callpal;
Stats::Vector<> _syscall;
// Stats::Vector<> _faults;
- Stats::Vector<> _mode;
- Stats::Vector<> _modeGood;
- Stats::Formula _modeFraction;
- Stats::Vector<> _modeTicks;
-
- Stats::Scalar<> _swap_context;
-
private:
int iplLast;
Tick iplLastTick;
public:
Statistics(System *system);
+ virtual ~Statistics() {}
const std::string name() const { return myname; }
void regStats(const std::string &name);
@@ -97,15 +77,7 @@ class Statistics : public Serializable
public:
void arm() { _arm++; }
void quiesce() { _quiesce++; }
- void ivlb() { _ivlb++; }
- void ivle() { _ivle++; }
- void hwrei() { _hwrei++; }
void swpipl(int ipl);
- void mode(cpu_mode newmode, ThreadContext *tc);
- void context(Addr oldpcbb, Addr newpcbb, ThreadContext *tc);
- void callpal(int code, ThreadContext *tc);
-
- void setIdleProcess(Addr idle, ThreadContext *tc);
public:
virtual void serialize(std::ostream &os);
diff --git a/src/kern/linux/events.cc b/src/kern/linux/events.cc
index 289ece5ce..ba52e040a 100644
--- a/src/kern/linux/events.cc
+++ b/src/kern/linux/events.cc
@@ -49,7 +49,7 @@ DebugPrintkEvent::process(ThreadContext *tc)
DPRINTFN("");
}
- AlphaISA::AlphaArguments args(tc);
+ TheISA::Arguments args(tc);
Printk(args);
SkipFuncEvent::process(tc);
}
diff --git a/src/kern/linux/printk.cc b/src/kern/linux/printk.cc
index 004d1be2f..ea3d59f19 100644
--- a/src/kern/linux/printk.cc
+++ b/src/kern/linux/printk.cc
@@ -39,7 +39,7 @@ using namespace std;
void
-Printk(AlphaISA::AlphaArguments args)
+Printk(TheISA::Arguments args)
{
char *p = (char *)args++;
diff --git a/src/kern/linux/printk.hh b/src/kern/linux/printk.hh
index 5ddf0a018..17d59b765 100644
--- a/src/kern/linux/printk.hh
+++ b/src/kern/linux/printk.hh
@@ -32,8 +32,10 @@
#ifndef __PRINTK_HH__
#define __PRINTK_HH__
-class AlphaISA::AlphaArguments;
+#include "arch/isa_specific.hh"
-void Printk(AlphaISA::AlphaArguments args);
+class TheISA::Arguments;
+
+void Printk(TheISA::Arguments args);
#endif // __PRINTK_HH__
diff --git a/src/kern/system_events.cc b/src/kern/system_events.cc
index 177ce96d1..6fd9e1563 100644
--- a/src/kern/system_events.cc
+++ b/src/kern/system_events.cc
@@ -29,11 +29,11 @@
* Nathan Binkert
*/
-#include "cpu/base.hh"
+//For ISA_HAS_DELAY_SLOT
+#include "arch/isa_traits.hh"
+#include "base/trace.hh"
#include "cpu/thread_context.hh"
-#include "kern/kernel_stats.hh"
#include "kern/system_events.hh"
-#include "sim/system.hh"
using namespace TheISA;
@@ -47,19 +47,7 @@ SkipFuncEvent::process(ThreadContext *tc)
tc->setPC(newpc);
tc->setNextPC(tc->readPC() + sizeof(TheISA::MachInst));
-/*
- BranchPred *bp = tc->getCpuPtr()->getBranchPred();
- if (bp != NULL) {
- bp->popRAS(tc->getThreadNum());
- }
-*/
-}
-
-void
-IdleStartEvent::process(ThreadContext *tc)
-{
- if (tc->getKernelStats())
- tc->getKernelStats()->setIdleProcess(
- tc->readMiscReg(AlphaISA::IPR_PALtemp23), tc);
- remove();
+#if ISA_HAS_DELAY_SLOT
+ tc->setNextPC(tc->readNextPC() + sizeof(TheISA::MachInst));
+#endif
}
diff --git a/src/kern/system_events.hh b/src/kern/system_events.hh
index 93b5eb528..58cbc4808 100644
--- a/src/kern/system_events.hh
+++ b/src/kern/system_events.hh
@@ -35,8 +35,6 @@
#include "cpu/pc_event.hh"
-class System;
-
class SkipFuncEvent : public PCEvent
{
public:
@@ -46,13 +44,4 @@ class SkipFuncEvent : public PCEvent
virtual void process(ThreadContext *tc);
};
-class IdleStartEvent : public PCEvent
-{
- public:
- IdleStartEvent(PCEventQueue *q, const std::string &desc, Addr addr)
- : PCEvent(q, desc, addr)
- {}
- virtual void process(ThreadContext *tc);
-};
-
#endif // __SYSTEM_EVENTS_HH__
diff --git a/src/kern/tru64/dump_mbuf.cc b/src/kern/tru64/dump_mbuf.cc
index 8f88f8904..22d2228f0 100644
--- a/src/kern/tru64/dump_mbuf.cc
+++ b/src/kern/tru64/dump_mbuf.cc
@@ -47,7 +47,7 @@ using namespace TheISA;
namespace tru64 {
void
-DumpMbuf(AlphaArguments args)
+DumpMbuf(Arguments args)
{
ThreadContext *tc = args.getThreadContext();
Addr addr = (Addr)args;
diff --git a/src/kern/tru64/dump_mbuf.hh b/src/kern/tru64/dump_mbuf.hh
index 25c6fd31d..30b1102b9 100644
--- a/src/kern/tru64/dump_mbuf.hh
+++ b/src/kern/tru64/dump_mbuf.hh
@@ -34,7 +34,7 @@
#include "arch/arguments.hh"
namespace tru64 {
- void DumpMbuf(AlphaISA::AlphaArguments args);
+ void DumpMbuf(TheISA::Arguments args);
}
#endif // __DUMP_MBUF_HH__
diff --git a/src/kern/tru64/printf.cc b/src/kern/tru64/printf.cc
index 29dd443d2..2c767c4d2 100644
--- a/src/kern/tru64/printf.cc
+++ b/src/kern/tru64/printf.cc
@@ -42,7 +42,7 @@ using namespace std;
namespace tru64 {
void
-Printf(AlphaISA::AlphaArguments args)
+Printf(TheISA::Arguments args)
{
char *p = (char *)args++;
diff --git a/src/kern/tru64/printf.hh b/src/kern/tru64/printf.hh
index f6a4544ad..ff453b1c1 100644
--- a/src/kern/tru64/printf.hh
+++ b/src/kern/tru64/printf.hh
@@ -34,7 +34,7 @@
#include "arch/arguments.hh"
namespace tru64 {
- void Printf(AlphaISA::AlphaArguments args);
+ void Printf(TheISA::Arguments args);
}
#endif // __PRINTF_HH__
diff --git a/src/kern/tru64/tru64_events.cc b/src/kern/tru64/tru64_events.cc
index 69638bde1..851b3a526 100644
--- a/src/kern/tru64/tru64_events.cc
+++ b/src/kern/tru64/tru64_events.cc
@@ -81,7 +81,7 @@ PrintfEvent::process(ThreadContext *tc)
if (DTRACE(Printf)) {
DebugOut() << curTick << ": " << tc->getCpuPtr()->name() << ": ";
- AlphaArguments args(tc);
+ Arguments args(tc);
tru64::Printf(args);
}
}
@@ -93,7 +93,7 @@ DebugPrintfEvent::process(ThreadContext *tc)
if (!raw)
DebugOut() << curTick << ": " << tc->getCpuPtr()->name() << ": ";
- AlphaArguments args(tc);
+ Arguments args(tc);
tru64::Printf(args);
}
}
@@ -102,7 +102,7 @@ void
DumpMbufEvent::process(ThreadContext *tc)
{
if (DTRACE(DebugPrintf)) {
- AlphaArguments args(tc);
+ Arguments args(tc);
tru64::DumpMbuf(args);
}
}
diff --git a/src/mem/port_impl.hh b/src/mem/port_impl.hh
index b7980bdd2..989cfd338 100644
--- a/src/mem/port_impl.hh
+++ b/src/mem/port_impl.hh
@@ -28,6 +28,9 @@
* Authors: Ali Saidi
*/
+//To get endianness
+#include "arch/isa_traits.hh"
+
#include "mem/port.hh"
#include "sim/byteswap.hh"
@@ -35,7 +38,7 @@ template <typename T>
void
FunctionalPort::writeHtoG(Addr addr, T d)
{
- d = htog(d);
+ d = TheISA::htog(d);
writeBlob(addr, (uint8_t*)&d, sizeof(T));
}
@@ -46,6 +49,6 @@ FunctionalPort::readGtoH(Addr addr)
{
T d;
readBlob(addr, (uint8_t*)&d, sizeof(T));
- return gtoh(d);
+ return TheISA::gtoh(d);
}
diff --git a/src/sim/pseudo_inst.cc b/src/sim/pseudo_inst.cc
index d913e159b..66036def1 100644
--- a/src/sim/pseudo_inst.cc
+++ b/src/sim/pseudo_inst.cc
@@ -34,14 +34,14 @@
#include <string>
-#include "sim/pseudo_inst.hh"
#include "arch/vtophys.hh"
#include "base/annotate.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "cpu/quiesce_event.hh"
-#include "kern/kernel_stats.hh"
+#include "arch/kernel_stats.hh"
#include "sim/param.hh"
+#include "sim/pseudo_inst.hh"
#include "sim/serialize.hh"
#include "sim/sim_exit.hh"
#include "sim/stat_control.hh"
@@ -134,18 +134,6 @@ namespace AlphaPseudo
}
void
- ivlb(ThreadContext *tc)
- {
- if (tc->getKernelStats())
- tc->getKernelStats()->ivlb();
- }
-
- void
- ivle(ThreadContext *tc)
- {
- }
-
- void
m5exit_old(ThreadContext *tc)
{
exitSimLoop("m5_exit_old instruction encountered");
diff --git a/src/sim/pseudo_inst.hh b/src/sim/pseudo_inst.hh
index d211de44e..bc71a7e64 100644
--- a/src/sim/pseudo_inst.hh
+++ b/src/sim/pseudo_inst.hh
@@ -47,8 +47,6 @@ namespace AlphaPseudo
void quiesceNs(ThreadContext *tc, uint64_t ns);
void quiesceCycles(ThreadContext *tc, uint64_t cycles);
uint64_t quiesceTime(ThreadContext *tc);
- void ivlb(ThreadContext *tc);
- void ivle(ThreadContext *tc);
void m5exit(ThreadContext *tc, Tick delay);
void m5exit_old(ThreadContext *tc);
void loadsymbol(ThreadContext *xc);
diff --git a/src/sim/system.cc b/src/sim/system.cc
index 11ae492b9..4b42d41fc 100644
--- a/src/sim/system.cc
+++ b/src/sim/system.cc
@@ -43,7 +43,7 @@
#include "sim/system.hh"
#if FULL_SYSTEM
#include "arch/vtophys.hh"
-#include "base/remote_gdb.hh"
+#include "arch/remote_gdb.hh"
#include "kern/kernel_stats.hh"
#endif
diff --git a/src/sim/system.hh b/src/sim/system.hh
index 827fe5c78..b3a67bf7a 100644
--- a/src/sim/system.hh
+++ b/src/sim/system.hh
@@ -56,7 +56,10 @@ class PhysicalMemory;
#if FULL_SYSTEM
class Platform;
class GDBListener;
-class RemoteGDB;
+namespace TheISA
+{
+ class RemoteGDB;
+}
#endif
class System : public SimObject
@@ -157,7 +160,7 @@ class System : public SimObject
#endif
public:
#if FULL_SYSTEM
- std::vector<RemoteGDB *> remoteGDB;
+ std::vector<TheISA::RemoteGDB *> remoteGDB;
std::vector<GDBListener *> gdbListen;
virtual bool breakpoint() = 0;
#endif // FULL_SYSTEM
diff --git a/util/m5/m5.c b/util/m5/m5.c
index 23401aea5..ca555ed12 100644
--- a/util/m5/m5.c
+++ b/util/m5/m5.c
@@ -41,9 +41,7 @@ char *progname;
void
usage()
{
- printf("usage: m5 ivlb <interval>\n"
- " m5 ivle <interval>\n"
- " m5 initparam\n"
+ printf("usage: m5 initparam\n"
" m5 sw99param\n"
" m5 exit [delay]\n"
" m5 resetstats [delay [period]]\n"
diff --git a/util/m5/m5op.S b/util/m5/m5op.S
index a19113e62..c47bd15b0 100644
--- a/util/m5/m5op.S
+++ b/util/m5/m5op.S
@@ -36,8 +36,6 @@
#define quiescens_func 0x02
#define quiescecycle_func 0x03
#define quiescetime_func 0x04
-#define ivlb_func 0x10
-#define ivle_func 0x11
#define exit_old_func 0x20 // deprectated!
#define exit_func 0x21
#define initparam_func 0x30
@@ -74,8 +72,6 @@ func:
#define QUIESCENS(r1) INST(m5_op, r1, 0, quiescens_func)
#define QUIESCECYC(r1) INST(m5_op, r1, 0, quiescecycle_func)
#define QUIESCETIME INST(m5_op, 0, 0, quiescetime_func)
-#define IVLB(reg) INST(m5_op, reg, 0, ivlb_func)
-#define IVLE(reg) INST(m5_op, reg, 0, ivle_func)
#define M5EXIT(reg) INST(m5_op, reg, 0, exit_func)
#define INITPARAM(reg) INST(m5_op, reg, 0, initparam_func)
#define LOADSYMBOL(reg) INST(m5_op, reg, 0, loadsymbol_func)
@@ -123,19 +119,6 @@ LEAF(quiesceTime)
RET
END(quiesceTime)
-
- .align 4
-LEAF(m5_ivlb)
- IVLB(16)
- RET
-END(m5_ivlb)
-
- .align 4
-LEAF(m5_ivle)
- IVLE(16)
- RET
-END(m5_ivle)
-
.align 4
LEAF(m5_exit)
M5EXIT(16)
diff --git a/util/m5/m5op.h b/util/m5/m5op.h
index eab4e7fd5..e8f2baaac 100644
--- a/util/m5/m5op.h
+++ b/util/m5/m5op.h
@@ -40,8 +40,6 @@ void quiesceNs(uint64_t ns);
void quiesceCycle(uint64_t cycles);
uint64_t quiesceTime(void);
-void m5_ivlb(uint64_t interval);
-void m5_ivle(uint64_t interval);
void m5_exit(uint64_t ns_delay);
uint64_t m5_initparam(void);
void m5_checkpoint(uint64_t ns_delay, uint64_t ns_period);