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-rw-r--r--src/cpu/inorder/inorder_dyn_inst.cc8
-rw-r--r--src/cpu/inorder/inorder_dyn_inst.hh4
-rw-r--r--src/cpu/o3/dyn_inst.hh6
-rw-r--r--src/cpu/o3/dyn_inst_impl.hh8
-rw-r--r--src/cpu/simple/base.hh10
5 files changed, 26 insertions, 10 deletions
diff --git a/src/cpu/inorder/inorder_dyn_inst.cc b/src/cpu/inorder/inorder_dyn_inst.cc
index f65d2ea9f..ff178f6d3 100644
--- a/src/cpu/inorder/inorder_dyn_inst.cc
+++ b/src/cpu/inorder/inorder_dyn_inst.cc
@@ -311,14 +311,18 @@ InOrderDynInst::simPalCheck(int palFunc)
#endif
return this->cpu->simPalCheck(palFunc, this->threadNumber);
}
-#else
+#endif
+
void
InOrderDynInst::syscall(int64_t callnum)
{
+#if FULL_SYSTEM
+ panic("Syscall emulation isn't available in FS mode.\n");
+#else
syscallNum = callnum;
cpu->syscallContext(NoFault, this->threadNumber, this);
-}
#endif
+}
void
InOrderDynInst::setSquashInfo(unsigned stage_num)
diff --git a/src/cpu/inorder/inorder_dyn_inst.hh b/src/cpu/inorder/inorder_dyn_inst.hh
index 3427af86b..f49476ec5 100644
--- a/src/cpu/inorder/inorder_dyn_inst.hh
+++ b/src/cpu/inorder/inorder_dyn_inst.hh
@@ -525,10 +525,10 @@ class InOrderDynInst : public FastAlloc, public RefCounted
bool simPalCheck(int palFunc);
#else
short syscallNum;
+#endif
- /** Calls a syscall. */
+ /** Emulates a syscall. */
void syscall(int64_t callnum);
-#endif
////////////////////////////////////////////////////////////
//
diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index 399240d69..e58eb99c5 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -205,11 +205,11 @@ class BaseO3DynInst : public BaseDynInst<Impl>
/** Traps to handle specified fault. */
void trap(Fault fault);
bool simPalCheck(int palFunc);
-#else
- /** Calls a syscall. */
- void syscall(int64_t callnum);
#endif
+ /** Emulates a syscall. */
+ void syscall(int64_t callnum);
+
public:
// The register accessor methods provide the index of the
diff --git a/src/cpu/o3/dyn_inst_impl.hh b/src/cpu/o3/dyn_inst_impl.hh
index eceb0b49f..500d63de8 100644
--- a/src/cpu/o3/dyn_inst_impl.hh
+++ b/src/cpu/o3/dyn_inst_impl.hh
@@ -188,11 +188,15 @@ BaseO3DynInst<Impl>::simPalCheck(int palFunc)
#endif
return this->cpu->simPalCheck(palFunc, this->threadNumber);
}
-#else
+#endif
+
template <class Impl>
void
BaseO3DynInst<Impl>::syscall(int64_t callnum)
{
+#if FULL_SYSTEM
+ panic("Syscall emulation isn't available in FS mode.\n");
+#else
// HACK: check CPU's nextPC before and after syscall. If it
// changes, update this instruction's nextPC because the syscall
// must have changed the nextPC.
@@ -202,6 +206,6 @@ BaseO3DynInst<Impl>::syscall(int64_t callnum)
if (!(curPC == newPC)) {
this->pcState(newPC);
}
-}
#endif
+}
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index b27ebf998..ad281aa2b 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -402,9 +402,17 @@ class BaseSimpleCPU : public BaseCPU
#if FULL_SYSTEM
Fault hwrei() { return thread->hwrei(); }
bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
+#endif
+
+ void
+ syscall(int64_t callnum)
+ {
+#if FULL_SYSTEM
+ panic("Syscall emulation isn't available in FS mode.\n");
#else
- void syscall(int64_t callnum) { thread->syscall(callnum); }
+ thread->syscall(callnum);
#endif
+ }
bool misspeculating() { return thread->misspeculating(); }
ThreadContext *tcBase() { return tc; }