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-rw-r--r--configs/common/CacheConfig.py10
-rw-r--r--configs/common/Caches.py8
-rw-r--r--src/cpu/BaseCPU.py16
-rw-r--r--src/cpu/o3/O3CPU.py4
4 files changed, 29 insertions, 9 deletions
diff --git a/configs/common/CacheConfig.py b/configs/common/CacheConfig.py
index 075f6d235..c4f91fd9e 100644
--- a/configs/common/CacheConfig.py
+++ b/configs/common/CacheConfig.py
@@ -43,8 +43,14 @@ def config_cache(options, system):
for i in xrange(options.num_cpus):
if options.caches:
- system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
- L1Cache(size = '64kB'))
+ if buildEnv['TARGET_ISA'] == 'x86':
+ system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
+ L1Cache(size = '64kB'),
+ PageTableWalkerCache(),
+ PageTableWalkerCache())
+ else:
+ system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
+ L1Cache(size = '64kB'))
if options.l2cache:
system.cpu[i].connectMemPorts(system.tol2bus)
else:
diff --git a/configs/common/Caches.py b/configs/common/Caches.py
index 412cfd3b1..3adc7e5c9 100644
--- a/configs/common/Caches.py
+++ b/configs/common/Caches.py
@@ -42,6 +42,14 @@ class L2Cache(BaseCache):
mshrs = 20
tgts_per_mshr = 12
+class PageTableWalkerCache(BaseCache):
+ assoc = 2
+ block_size = 64
+ latency = '1ns'
+ mshrs = 10
+ size = '1kB'
+ tgts_per_mshr = 12
+
class IOCache(BaseCache):
assoc = 8
block_size = 64
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index 868f47015..0669a7de4 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -166,7 +166,7 @@ class BaseCPU(MemObject):
if p != 'physmem_port':
exec('self.%s = bus.port' % p)
- def addPrivateSplitL1Caches(self, ic, dc):
+ def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None):
assert(len(self._mem_ports) < 8)
self.icache = ic
self.dcache = dc
@@ -174,13 +174,19 @@ class BaseCPU(MemObject):
self.dcache_port = dc.cpu_side
self._mem_ports = ['icache.mem_side', 'dcache.mem_side']
if buildEnv['FULL_SYSTEM']:
- if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
- self._mem_ports += ["itb.walker.port", "dtb.walker.port"]
if buildEnv['TARGET_ISA'] == 'x86':
+ self.itb_walker_cache = iwc
+ self.dtb_walker_cache = dwc
+ self.itb.walker.port = iwc.cpu_side
+ self.dtb.walker.port = dwc.cpu_side
+ self._mem_ports += ["itb_walker_cache.mem_side", \
+ "dtb_walker_cache.mem_side"]
self._mem_ports += ["interrupts.pio", "interrupts.int_port"]
+ elif buildEnv['TARGET_ISA'] == 'arm':
+ self._mem_ports += ["itb.walker.port", "dtb.walker.port"]
- def addTwoLevelCacheHierarchy(self, ic, dc, l2c):
- self.addPrivateSplitL1Caches(ic, dc)
+ def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None):
+ self.addPrivateSplitL1Caches(ic, dc, iwc, dwc)
self.toL2Bus = Bus()
self.connectMemPorts(self.toL2Bus)
self.l2cache = l2c
diff --git a/src/cpu/o3/O3CPU.py b/src/cpu/o3/O3CPU.py
index 3f2210e44..38fee369c 100644
--- a/src/cpu/o3/O3CPU.py
+++ b/src/cpu/o3/O3CPU.py
@@ -141,7 +141,7 @@ class DerivO3CPU(BaseCPU):
smtROBThreshold = Param.Int(100, "SMT ROB Threshold Sharing Parameter")
smtCommitPolicy = Param.String('RoundRobin', "SMT Commit Policy")
- def addPrivateSplitL1Caches(self, ic, dc):
- BaseCPU.addPrivateSplitL1Caches(self, ic, dc)
+ def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None):
+ BaseCPU.addPrivateSplitL1Caches(self, ic, dc, iwc, dwc)
self.icache.tgts_per_mshr = 20
self.dcache.tgts_per_mshr = 20