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-rw-r--r--src/base/traceflags.py1
-rw-r--r--src/mem/cache/tags/lru.cc4
2 files changed, 3 insertions, 2 deletions
diff --git a/src/base/traceflags.py b/src/base/traceflags.py
index 70fadb210..8573eb9bf 100644
--- a/src/base/traceflags.py
+++ b/src/base/traceflags.py
@@ -47,6 +47,7 @@ baseFlags = [
'BusBridge',
'Cache',
'CachePort',
+ 'CacheRepl',
'Chains',
'Checker',
'Clock',
diff --git a/src/mem/cache/tags/lru.cc b/src/mem/cache/tags/lru.cc
index 3269aa4db..0a8587c20 100644
--- a/src/mem/cache/tags/lru.cc
+++ b/src/mem/cache/tags/lru.cc
@@ -173,7 +173,7 @@ LRU::findBlock(Addr addr, int &lat)
if (blk != NULL) {
// move this block to head of the MRU list
sets[set].moveToHead(blk);
- DPRINTF(Cache, "set %x: moving blk %x to MRU\n",
+ DPRINTF(CacheRepl, "set %x: moving blk %x to MRU\n",
set, regenerateBlkAddr(tag, set));
if (blk->whenReady > curTick
&& blk->whenReady - curTick > hitLatency) {
@@ -208,7 +208,7 @@ LRU::findReplacement(Addr addr, PacketList &writebacks)
++sampledRefs;
blk->refCount = 0;
- DPRINTF(Cache, "set %x: selecting blk %x for replacement\n",
+ DPRINTF(CacheRepl, "set %x: selecting blk %x for replacement\n",
set, regenerateBlkAddr(blk->tag, set));
} else if (!blk->isTouched) {
tagsInUse++;