diff options
| -rw-r--r-- | src/cpu/simple/timing.cc | 13 | ||||
| -rw-r--r-- | src/mem/cache/cache_impl.hh | 1 |
2 files changed, 8 insertions, 6 deletions
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index 492a669b8..0c03815b5 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -356,8 +356,6 @@ TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) MemCmd cmd = MemCmd::WriteReq; // default bool do_access = true; // flag to suppress cache access - assert(dcache_pkt == NULL); - if (req->isLocked()) { cmd = MemCmd::StoreCondReq; do_access = TheISA::handleLockedWrite(thread, req); @@ -369,11 +367,14 @@ TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) } } - if (do_access) { - dcache_pkt = new Packet(req, cmd, Packet::Broadcast); - dcache_pkt->allocate(); - dcache_pkt->set(data); + // Note: need to allocate dcache_pkt even if do_access is + // false, as it's used unconditionally to call completeAcc(). + assert(dcache_pkt == NULL); + dcache_pkt = new Packet(req, cmd, Packet::Broadcast); + dcache_pkt->allocate(); + dcache_pkt->set(data); + if (do_access) { if (!dcachePort.sendTiming(dcache_pkt)) { _status = DcacheRetry; } else { diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh index b4c3c6359..0d76b6bec 100644 --- a/src/mem/cache/cache_impl.hh +++ b/src/mem/cache/cache_impl.hh @@ -698,6 +698,7 @@ Cache<TagStore>::handleResponse(PacketPtr pkt) if (pkt->isRead()) { target->pkt->setData(pkt->getPtr<uint8_t>()); } + target->pkt->makeTimingResponse(); cpuSidePort->respond(target->pkt, time); } assert(!mshr->hasTargets()); |