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-rw-r--r--src/arch/arm/isa/decoder.isa2
-rw-r--r--src/arch/arm/isa/formats/branch.isa4
-rw-r--r--src/arch/arm/isa/formats/fp.isa2
-rw-r--r--src/arch/arm/isa/formats/mem.isa24
-rw-r--r--src/arch/arm/isa/formats/pred.isa92
-rw-r--r--src/arch/arm/isa/operands.isa4
-rw-r--r--src/arch/arm/miscregs.hh83
-rw-r--r--src/arch/arm/regfile/misc_regfile.hh16
-rw-r--r--src/arch/arm/utility.hh27
9 files changed, 138 insertions, 116 deletions
diff --git a/src/arch/arm/isa/decoder.isa b/src/arch/arm/isa/decoder.isa
index 459c9788e..b84109546 100644
--- a/src/arch/arm/isa/decoder.isa
+++ b/src/arch/arm/isa/decoder.isa
@@ -830,7 +830,7 @@ decode COND_CODE default Unknown::unknown() {
}
format PredOp {
// ARM System Call (SoftWare Interrupt)
- 1: swi({{ if (arm_predicate(xc->readMiscReg(ArmISA::CPSR),
+ 1: swi({{ if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR),
condCode))
{
//xc->syscall(R7);
diff --git a/src/arch/arm/isa/formats/branch.isa b/src/arch/arm/isa/formats/branch.isa
index 40aa4a952..15965d3e0 100644
--- a/src/arch/arm/isa/formats/branch.isa
+++ b/src/arch/arm/isa/formats/branch.isa
@@ -234,7 +234,7 @@ def format Branch(code,*opt_flags) {{
else:
inst_flags += ('IsCondControl', )
- icode = 'if (arm_predicate(xc->readMiscReg(ArmISA::CPSR), condCode)) {\n'
+ icode = 'if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode)) {\n'
icode += code
icode += ' NPC = NPC + 4 + disp;\n'
icode += '} else {\n'
@@ -268,7 +268,7 @@ def format BranchExchange(code,*opt_flags) {{
#Condition code
- icode = 'if (arm_predicate(xc->readMiscReg(ArmISA::CPSR), condCode)) {\n'
+ icode = 'if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode)) {\n'
icode += code
icode += ' NPC = Rm & 0xfffffffe; // Masks off bottom bit\n'
icode += '} else {\n'
diff --git a/src/arch/arm/isa/formats/fp.isa b/src/arch/arm/isa/formats/fp.isa
index 682c76079..1dd05c223 100644
--- a/src/arch/arm/isa/formats/fp.isa
+++ b/src/arch/arm/isa/formats/fp.isa
@@ -67,7 +67,7 @@ def template FPAExecute {{
%(code)s;
- if (arm_predicate(xc->readMiscReg(ArmISA::CPSR), condCode) &&
+ if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode) &&
fault == NoFault)
{
%(op_wb)s;
diff --git a/src/arch/arm/isa/formats/mem.isa b/src/arch/arm/isa/formats/mem.isa
index df1d067dc..4da37c3e7 100644
--- a/src/arch/arm/isa/formats/mem.isa
+++ b/src/arch/arm/isa/formats/mem.isa
@@ -216,7 +216,7 @@ def template EACompExecute {{
%(op_rd)s;
%(ea_code)s;
- if (arm_predicate(xc->readMiscReg(ArmISA::CPSR), condCode))
+ if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode))
{
if (fault == NoFault) {
%(op_wb)s;
@@ -241,7 +241,7 @@ def template LoadMemAccExecute {{
%(op_rd)s;
EA = xc->getEA();
- if (arm_predicate(xc->readMiscReg(ArmISA::CPSR), condCode))
+ if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode))
{
if (fault == NoFault) {
fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
@@ -270,7 +270,7 @@ def template LoadExecute {{
%(op_rd)s;
%(ea_code)s;
- if (arm_predicate(xc->readMiscReg(ArmISA::CPSR), condCode))
+ if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode))
{
if (fault == NoFault) {
fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
@@ -299,7 +299,7 @@ def template LoadInitiateAcc {{
%(op_rd)s;
%(ea_code)s;
- if (arm_predicate(xc->readMiscReg(ArmISA::CPSR), condCode))
+ if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode))
{
if (fault == NoFault) {
fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags);
@@ -322,7 +322,7 @@ def template LoadCompleteAcc {{
%(op_decl)s;
%(op_rd)s;
- if (arm_predicate(xc->readMiscReg(ArmISA::CPSR), condCode))
+ if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode))
{
// ARM instructions will not have a pkt if the predicate is false
Mem = pkt->get<typeof(Mem)>();
@@ -353,7 +353,7 @@ def template StoreMemAccExecute {{
%(op_decl)s;
%(op_rd)s;
- if (arm_predicate(xc->readMiscReg(ArmISA::CPSR), condCode))
+ if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode))
{
EA = xc->getEA();
@@ -385,7 +385,7 @@ def template StoreExecute {{
%(op_rd)s;
%(ea_code)s;
- if (arm_predicate(xc->readMiscReg(ArmISA::CPSR), condCode))
+ if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode))
{
if (fault == NoFault) {
%(memacc_code)s;
@@ -418,7 +418,7 @@ def template StoreInitiateAcc {{
%(op_rd)s;
%(ea_code)s;
- if (arm_predicate(xc->readMiscReg(ArmISA::CPSR), condCode))
+ if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode))
{
if (fault == NoFault) {
%(memacc_code)s;
@@ -451,7 +451,7 @@ def template StoreCompleteAcc {{
%(fp_enable_check)s;
%(op_dest_decl)s;
- if (arm_predicate(xc->readMiscReg(ArmISA::CPSR), condCode))
+ if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode))
{
if (fault == NoFault) {
%(op_wb)s;
@@ -472,7 +472,7 @@ def template StoreCondCompleteAcc {{
%(fp_enable_check)s;
%(op_dest_decl)s;
- if (arm_predicate(xc->readMiscReg(ArmISA::CPSR), condCode))
+ if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode))
{
if (fault == NoFault) {
%(op_wb)s;
@@ -495,7 +495,7 @@ def template MiscMemAccExecute {{
%(op_decl)s;
%(op_rd)s;
- if (arm_predicate(xc->readMiscReg(ArmISA::CPSR), condCode))
+ if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode))
{
EA = xc->getEA();
@@ -520,7 +520,7 @@ def template MiscExecute {{
%(op_rd)s;
%(ea_code)s;
- if (arm_predicate(xc->readMiscReg(ArmISA::CPSR), condCode))
+ if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode))
{
if (fault == NoFault) {
%(memacc_code)s;
diff --git a/src/arch/arm/isa/formats/pred.isa b/src/arch/arm/isa/formats/pred.isa
index 1e9dba07e..de9f4d316 100644
--- a/src/arch/arm/isa/formats/pred.isa
+++ b/src/arch/arm/isa/formats/pred.isa
@@ -36,25 +36,6 @@
output header {{
#include <iostream>
- enum ArmPredicateBits {
- COND_EQ = 0,
- COND_NE, // 1
- COND_CS, // 2
- COND_CC, // 3
- COND_MI, // 4
- COND_PL, // 5
- COND_VS, // 6
- COND_VC, // 7
- COND_HI, // 8
- COND_LS, // 9
- COND_GE, // 10
- COND_LT, // 11
- COND_GT, // 12
- COND_LE, // 13
- COND_AL, // 14
- COND_NV // 15
- };
-
inline uint32_t
rotate_imm(uint32_t immValue, uint32_t rotateValue)
{
@@ -62,76 +43,23 @@ output header {{
(immValue << (32 - (int)(rotateValue & 31))));
}
- inline uint32_t nSet(uint32_t cpsr) { return cpsr & (1<<31); }
- inline uint32_t zSet(uint32_t cpsr) { return cpsr & (1<<30); }
- inline uint32_t cSet(uint32_t cpsr) { return cpsr & (1<<29); }
- inline uint32_t vSet(uint32_t cpsr) { return cpsr & (1<<28); }
-
- inline bool arm_predicate(uint32_t cpsr, uint32_t predBits)
- {
-
- enum ArmPredicateBits armPredBits = (enum ArmPredicateBits) predBits;
- uint32_t result = 0;
- switch (armPredBits)
- {
- case COND_EQ:
- result = zSet(cpsr); break;
- case COND_NE:
- result = !zSet(cpsr); break;
- case COND_CS:
- result = cSet(cpsr); break;
- case COND_CC:
- result = !cSet(cpsr); break;
- case COND_MI:
- result = nSet(cpsr); break;
- case COND_PL:
- result = !nSet(cpsr); break;
- case COND_VS:
- result = vSet(cpsr); break;
- case COND_VC:
- result = !vSet(cpsr); break;
- case COND_HI:
- result = cSet(cpsr) && !zSet(cpsr); break;
- case COND_LS:
- result = !cSet(cpsr) || zSet(cpsr); break;
- case COND_GE:
- result = (!nSet(cpsr) && !vSet(cpsr)) || (nSet(cpsr) && vSet(cpsr)); break;
- case COND_LT:
- result = (nSet(cpsr) && !vSet(cpsr)) || (!nSet(cpsr) && vSet(cpsr)); break;
- case COND_GT:
- result = (!nSet(cpsr) && !vSet(cpsr) && !zSet(cpsr)) || (nSet(cpsr) && vSet(cpsr) && !zSet(cpsr)); break;
- case COND_LE:
- result = (nSet(cpsr) && !vSet(cpsr)) || (!nSet(cpsr) && vSet(cpsr)) || zSet(cpsr); break;
- case COND_AL: result = 1; break;
- case COND_NV: result = 0; break;
- default:
- fprintf(stderr, "Unhandled predicate condition: %d\n", armPredBits);
- exit(1);
- }
- if (result)
- return true;
- else
- return false;
- }
-
-
/**
* Base class for predicated integer operations.
*/
class PredOp : public ArmStaticInst
{
- protected:
+ protected:
- uint32_t condCode;
+ ArmISA::ConditionCode condCode;
- /// Constructor
- PredOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
- ArmStaticInst(mnem, _machInst, __opClass),
- condCode(COND_CODE)
- {
- }
+ /// Constructor
+ PredOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
+ ArmStaticInst(mnem, _machInst, __opClass),
+ condCode((ArmISA::ConditionCode)COND_CODE)
+ {
+ }
- std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+ std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
/**
@@ -243,7 +171,7 @@ def template PredOpExecute {{
%(op_rd)s;
%(code)s;
- if (arm_predicate(xc->readMiscReg(ArmISA::CPSR), condCode))
+ if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode))
{
if (fault == NoFault)
{
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
index b2c4f8420..f82e49109 100644
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -64,8 +64,8 @@ def operands {{
#Memory Operand
'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 8),
- 'Cpsr': ('ControlReg', 'uw', 'CPSR', 'IsInteger', 7),
- 'Fpsr': ('ControlReg', 'uw', 'FPSR', 'IsInteger', 7),
+ 'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', 'IsInteger', 7),
+ 'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', 'IsInteger', 7),
'NPC': ('NPC', 'uw', None, (None, None, 'IsControl'), 9),
'NNPC': ('NNPC', 'uw', None, (None, None, 'IsControl'), 9),
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
new file mode 100644
index 000000000..d939fabcf
--- /dev/null
+++ b/src/arch/arm/miscregs.hh
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2009 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+#ifndef __ARCH_ARM_MISCREGS_HH__
+#define __ARCH_ARM_MISCREGS_HH__
+
+#include "base/bitunion.hh"
+
+namespace ArmISA
+{
+ enum ConditionCode {
+ COND_EQ = 0,
+ COND_NE, // 1
+ COND_CS, // 2
+ COND_CC, // 3
+ COND_MI, // 4
+ COND_PL, // 5
+ COND_VS, // 6
+ COND_VC, // 7
+ COND_HI, // 8
+ COND_LS, // 9
+ COND_GE, // 10
+ COND_LT, // 11
+ COND_GT, // 12
+ COND_LE, // 13
+ COND_AL, // 14
+ COND_NV // 15
+ };
+
+ enum MiscRegIndex {
+ MISCREG_CPSR = 0,
+ MISCREG_SPSR_FIQ,
+ MISCREG_SPSR_IRQ,
+ MISCREG_SPSR_SVC,
+ MISCREG_SPSR_UND,
+ MISCREG_SPSR_ABT,
+ MISCREG_FPSR
+ };
+
+ BitUnion32(CPSR)
+ Bitfield<31> n;
+ Bitfield<30> z;
+ Bitfield<29> c;
+ Bitfield<28> v;
+ Bitfield<27> q;
+ Bitfield<24> j;
+ Bitfield<19, 16> ge;
+ Bitfield<9> e;
+ Bitfield<8> a;
+ Bitfield<7> i;
+ Bitfield<6> f;
+ Bitfield<5> t;
+ Bitfield<4, 0> mode;
+ EndBitUnion(CPSR)
+};
+
+#endif // __ARCH_ARM_MISCREGS_HH__
diff --git a/src/arch/arm/regfile/misc_regfile.hh b/src/arch/arm/regfile/misc_regfile.hh
index f8301bed2..f7e5fbd98 100644
--- a/src/arch/arm/regfile/misc_regfile.hh
+++ b/src/arch/arm/regfile/misc_regfile.hh
@@ -43,22 +43,6 @@ namespace ArmISA
return "";
}
- //Coprocessor 0 Register Names
- enum MiscRegTags {
- // Status Registers for the ARM
- //
- // CPSR Layout
- // 31302928 ... 7 6 5 4 3 2 1 0
- // N Z C V ... I F T { MODE }
- CPSR = 0,
- SPSR_FIQ,
- SPSR_IRQ,
- SPSR_SVC,
- SPSR_UND,
- SPSR_ABT,
- FPSR
- };
-
class MiscRegFile {
protected:
diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh
index e0ae7cd2e..a31fcd841 100644
--- a/src/arch/arm/utility.hh
+++ b/src/arch/arm/utility.hh
@@ -33,6 +33,7 @@
#ifndef __ARCH_ARM_UTILITY_HH__
#define __ARCH_ARM_UTILITY_HH__
+#include "arch/arm/miscregs.hh"
#include "arch/arm/types.hh"
#include "base/misc.hh"
#include "base/types.hh"
@@ -43,6 +44,32 @@ class ThreadContext;
namespace ArmISA {
+ inline bool
+ testPredicate(CPSR cpsr, ConditionCode code)
+ {
+ switch (code)
+ {
+ case COND_EQ: return cpsr.z;
+ case COND_NE: return !cpsr.z;
+ case COND_CS: return cpsr.c;
+ case COND_CC: return !cpsr.c;
+ case COND_MI: return cpsr.n;
+ case COND_PL: return !cpsr.n;
+ case COND_VS: return cpsr.v;
+ case COND_VC: return !cpsr.v;
+ case COND_HI: return (cpsr.c && !cpsr.z);
+ case COND_LS: return !(cpsr.c && !cpsr.z);
+ case COND_GE: return !(cpsr.n ^ cpsr.v);
+ case COND_LT: return (cpsr.n ^ cpsr.v);
+ case COND_GT: return !(cpsr.n ^ cpsr.v || cpsr.z);
+ case COND_LE: return (cpsr.n ^ cpsr.v || cpsr.z);
+ case COND_AL: return true;
+ case COND_NV: return false;
+ default:
+ panic("Unhandled predicate condition: %d\n", code);
+ }
+ }
+
//Floating Point Utility Functions
uint64_t fpConvert(ConvertType cvt_type, double fp_val);
double roundFP(double val, int digits);
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-30 20:42:19 +0000