summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
Diffstat
-rw-r--r--src/mem/protocol/MI_example-cache.sm11
-rw-r--r--src/mem/ruby/config/MI_example-homogeneous.rb7
-rw-r--r--src/mem/ruby/config/TwoLevel_SplitL1UnifiedL2.rb29
-rw-r--r--src/mem/ruby/config/cfg.rb48
-rw-r--r--src/mem/ruby/config/defaults.rb64
-rw-r--r--src/mem/ruby/libruby.cc4
-rw-r--r--src/mem/ruby/libruby.hh8
-rw-r--r--src/mem/ruby/system/CacheMemory.hh18
-rw-r--r--src/mem/ruby/system/DMASequencer.hh1
-rw-r--r--src/mem/ruby/system/RubyPort.hh2
-rw-r--r--src/mem/ruby/system/Sequencer.cc60
-rw-r--r--src/mem/ruby/system/Sequencer.hh4
-rw-r--r--tests/configs/memtest-ruby.py2
-rw-r--r--util/style.py6
14 files changed, 161 insertions, 103 deletions
diff --git a/src/mem/protocol/MI_example-cache.sm b/src/mem/protocol/MI_example-cache.sm
index 915a0eb99..64771bac5 100644
--- a/src/mem/protocol/MI_example-cache.sm
+++ b/src/mem/protocol/MI_example-cache.sm
@@ -17,6 +17,7 @@ machine(L1Cache, "MI Example L1 Cache")
II, desc="Not Present/Invalid, issued PUT";
M, desc="Modified";
MI, desc="Modified, issued PUT";
+ MII, desc="Modified, issued PUTX, received nack";
IS, desc="Issued request for LOAD/IFETCH";
IM, desc="Issued request for STORE/ATOMIC";
@@ -388,6 +389,16 @@ machine(L1Cache, "MI Example L1 Cache")
o_popForwardedRequestQueue;
}
+ transition(MI, Writeback_Nack, MII) {
+ o_popForwardedRequestQueue;
+ }
+
+ transition(MII, Fwd_GETX, I) {
+ ee_sendDataFromTBE;
+ w_deallocateTBE;
+ o_popForwardedRequestQueue;
+ }
+
transition(II, Writeback_Nack, I) {
w_deallocateTBE;
o_popForwardedRequestQueue;
diff --git a/src/mem/ruby/config/MI_example-homogeneous.rb b/src/mem/ruby/config/MI_example-homogeneous.rb
index 2b416e647..409d0fe3a 100644
--- a/src/mem/ruby/config/MI_example-homogeneous.rb
+++ b/src/mem/ruby/config/MI_example-homogeneous.rb
@@ -34,6 +34,13 @@ for i in 0..$*.size-1 do
elsif $*[i] == "-m"
num_memories = $*[i+1].to_i
i = i+1
+ elsif $*[i] == "-R"
+ if $*[i+1] == "rand"
+ RubySystem.random_seed = "rand"
+ else
+ RubySystem.random_seed = $*[i+1].to_i
+ end
+ i = i+ 1
elsif $*[i] == "-s"
memory_size_mb = $*[i+1].to_i
i = i + 1
diff --git a/src/mem/ruby/config/TwoLevel_SplitL1UnifiedL2.rb b/src/mem/ruby/config/TwoLevel_SplitL1UnifiedL2.rb
index 83020742e..b44813ab6 100644
--- a/src/mem/ruby/config/TwoLevel_SplitL1UnifiedL2.rb
+++ b/src/mem/ruby/config/TwoLevel_SplitL1UnifiedL2.rb
@@ -26,6 +26,7 @@ num_memories = 1
memory_size_mb = 1024
num_dma = 1
+#default protocol
protocol = "MESI_CMP_directory"
# check for overrides
@@ -40,6 +41,13 @@ for i in 0..$*.size-1 do
elsif $*[i] == "-p"
num_cores = $*[i+1].to_i
i = i+1
+ elsif $*[i] == "-R"
+ if $*[i+1] == "rand"
+ RubySystem.random_seed = "rand"
+ else
+ RubySystem.random_seed = $*[i+1].to_i
+ end
+ i = i+ 1
elsif $*[i] == "-s"
memory_size_mb = $*[i+1].to_i
i = i + 1
@@ -49,7 +57,7 @@ end
net_ports = Array.new
iface_ports = Array.new
-#assert(protocol == "MESI_CMP_directory", __FILE__+" cannot be used with protocol "+protocol);
+assert((protocol == "MESI_CMP_directory" or protocol == "MOESI_CMP_directory"), __FILE__+" cannot be used with protocol "+protocol);
require protocol+".rb"
@@ -64,9 +72,7 @@ num_cores.times { |n|
icache, dcache,
sequencer,
num_l2_banks)
- end
-
- if protocol == "MESI_CMP_directory"
+ elsif protocol == "MESI_CMP_directory"
net_ports << MESI_CMP_directory_L1CacheController.new("L1CacheController_"+n.to_s,
"L1Cache",
icache, dcache,
@@ -80,15 +86,14 @@ num_l2_banks.times { |n|
net_ports << MOESI_CMP_directory_L2CacheController.new("L2CacheController_"+n.to_s,
"L2Cache",
cache)
- end
-
- if protocol == "MESI_CMP_directory"
+ elsif protocol == "MESI_CMP_directory"
net_ports << MESI_CMP_directory_L2CacheController.new("L2CacheController_"+n.to_s,
"L2Cache",
cache)
end
-
+ net_ports.last.request_latency = l2_cache_latency + 2
+ net_ports.last.response_latency = l2_cache_latency + 2
}
num_memories.times { |n|
directory = DirectoryMemory.new("DirectoryMemory_"+n.to_s, memory_size_mb/num_memories)
@@ -98,9 +103,7 @@ num_memories.times { |n|
"Directory",
directory,
memory_control)
- end
-
- if protocol == "MESI_CMP_directory"
+ elsif protocol == "MESI_CMP_directory"
net_ports << MESI_CMP_directory_DirectoryController.new("DirectoryController_"+n.to_s,
"Directory",
directory,
@@ -115,9 +118,7 @@ num_dma.times { |n|
net_ports << MOESI_CMP_directory_DMAController.new("DMAController_"+n.to_s,
"DMA",
dma_sequencer)
- end
-
- if protocol == "MESI_CMP_directory"
+ elsif protocol == "MESI_CMP_directory"
net_ports << MESI_CMP_directory_DMAController.new("DMAController_"+n.to_s,
"DMA",
dma_sequencer)
diff --git a/src/mem/ruby/config/cfg.rb b/src/mem/ruby/config/cfg.rb
index 1c261544d..9ec0df252 100644
--- a/src/mem/ruby/config/cfg.rb
+++ b/src/mem/ruby/config/cfg.rb
@@ -11,7 +11,7 @@ end
def assert(condition,message)
unless condition
- raise AssertionFailure, "\n\nAssertion failed: \n\n #{message}\n\n"
+ raise AssertionFailure.new(message), "\n\nAssertion failed: \n\n #{message}\n\n"
end
end
@@ -296,9 +296,6 @@ private
end
-
-
-
class CacheController < NetPort
@@total_cache_controllers = Hash.new
@@ -438,27 +435,27 @@ class SetAssociativeCache < Cache
cacti_args << 360 << 0 << 0 << 0 << 0 << 1 << 1 << 1 << 1 << 0 << 0
cacti_args << 50 << 10 << 10 << 0 << 1 << 1
-# cacti_cmd = File.dirname(__FILE__) + "/cacti/cacti " + cacti_args.join(" ")
-
-# IO.popen(cacti_cmd) { |pipe|
-# str1 = pipe.readline
-# str2 = pipe.readline
-# results = str2.split(", ")
-# if results.size != 61
-# print "CACTI ERROR: CACTI produced unexpected output.\n"
-# print "Are you using the version shipped with libruby?\n"
-# raise Exception
-# end
-# latency_ns = results[5].to_f
-# if (latency_ns == "1e+39")
-# print "CACTI ERROR: CACTI was unable to realistically model the cache ",@obj_name,"\n"
-# print "Either change the cache parameters or manually set the latency values\n"
-# raise Exception
-# end
-# clk_period_ns = 1e9 * (1.0 / (RubySystem.freq_mhz * 1e6))
-# latency_cycles = (latency_ns / clk_period_ns).ceil
-# @latency = latency_cycles
-# }
+ cacti_cmd = File.dirname(__FILE__) + "/cacti/cacti " + cacti_args.join(" ")
+
+ IO.popen(cacti_cmd) { |pipe|
+ str1 = pipe.readline
+ str2 = pipe.readline
+ results = str2.split(", ")
+ if results.size != 61
+ print "CACTI ERROR: CACTI produced unexpected output.\n"
+ print "Are you using the version shipped with libruby?\n"
+ raise Exception
+ end
+ latency_ns = results[5].to_f
+ if (latency_ns == "1e+39")
+ print "CACTI ERROR: CACTI was unable to realistically model the cache ",@obj_name,"\n"
+ print "Either change the cache parameters or manually set the latency values\n"
+ raise Exception
+ end
+ clk_period_ns = 1e9 * (1.0 / (RubySystem.freq_mhz * 1e6))
+ latency_cycles = (latency_ns / clk_period_ns).ceil
+ @latency = latency_cycles
+ }
elsif @latency.is_a?(Float)
clk_period_ns = 1e9 * (1.0 / (RubySystem.freq_mhz * 1e6))
latency_cycles = (@latency / clk_period_ns).ceil
@@ -757,5 +754,4 @@ class GarnetFlexiblePipeline < GarnetNetwork
end
end
-#added by SS
require "defaults.rb"
diff --git a/src/mem/ruby/config/defaults.rb b/src/mem/ruby/config/defaults.rb
index 60f32ca14..4e3db4495 100644
--- a/src/mem/ruby/config/defaults.rb
+++ b/src/mem/ruby/config/defaults.rb
@@ -9,7 +9,7 @@ class NetPort < LibRubyObject
# buffer_size limits the size of all other buffers connecting to
# SLICC Controllers. When 0, infinite buffering is used.
- default_param :buffer_size, Integer, 0
+ default_param :buffer_size, Integer, 32
# added by SS for TBE
default_param :number_of_TBEs, Integer, 256
@@ -36,19 +36,19 @@ class Debug < LibRubyObject
# 1. change protocol_trace = true
# 2. enable debug in the Ruby Makefile
# 3. set start_time = 1
- default_param :protocol_trace, Boolean, true
+ default_param :protocol_trace, Boolean, false
# a string for filtering debugging output (for all g_debug vars see Debug.h)
- default_param :filter_string, String, "none"
+ default_param :filter_string, String, ""
# filters debugging messages based on priority (low, med, high)
- default_param :verbosity_string, String, "none"
+ default_param :verbosity_string, String, ""
# filters debugging messages based on a ruby time
default_param :start_time, Integer, 1
# sends debugging messages to a output filename
- default_param :output_filename, String, "debug_ss"
+ default_param :output_filename, String, ""
end
class Topology < LibRubyObject
@@ -163,8 +163,34 @@ class MOESI_CMP_directory_DirectoryController < DirectoryController
end
class MOESI_CMP_directory_DMAController < DMAController
+ default_param :request_latency, Integer, 14
+ default_param :response_latency, Integer, 14
+end
+
+class MESI_CMP_directory_L2CacheController < CacheController
+ default_param :l2_request_latency, Integer, 2
+ default_param :l2_response_latency, Integer, 2
+ default_param :to_L1_latency, Integer, 1
+
+#if 0 then automatically calculated
+ default_param :lowest_bit, Integer, 0
+ default_param :highest_bit, Integer, 0
+end
+
+class MESI_CMP_directory_L1CacheController < L1CacheController
+ default_param :l1_request_latency, Integer, 2
+ default_param :l1_response_latency, Integer, 2
+ default_param :to_L2_latency, Integer, 1
+end
+
+
+class MESI_CMP_directory_DirectoryController < DirectoryController
+ default_param :to_mem_ctrl_latency, Integer, 1
+ default_param :directory_latency, Integer, 6
+end
+
+class MESI_CMP_directory_DMAController < DMAController
default_param :request_latency, Integer, 6
- default_param :response_latency, Integer, 6
end
class RubySystem
@@ -179,7 +205,7 @@ class RubySystem
# you can still have a non-deterministic simulation if random seed
# is set to "rand". This is because the Ruby swtiches use random
# link priority elevation
- default_param :randomization, Boolean, false
+ default_param :randomization, Boolean, true
# tech_nm is the device size used to calculate latency and area
# information about system components
@@ -206,29 +232,5 @@ class RubySystem
end
#added by SS
-class MESI_CMP_directory_L2CacheController < CacheController
- default_param :l2_request_latency, Integer, 2
- default_param :l2_response_latency, Integer, 2
- default_param :to_L1_latency, Integer, 1
-#if 0 then automatically calculated
- default_param :lowest_bit, Integer, 0
- default_param :highest_bit, Integer, 0
-end
-
-class MESI_CMP_directory_L1CacheController < L1CacheController
- default_param :l1_request_latency, Integer, 2
- default_param :l1_response_latency, Integer, 2
- default_param :to_L2_latency, Integer, 1
-end
-
-
-class MESI_CMP_directory_DirectoryController < DirectoryController
- default_param :to_mem_ctrl_latency, Integer, 1
- default_param :directory_latency, Integer, 6
-end
-
-class MESI_CMP_directory_DMAController < DMAController
- default_param :request_latency, Integer, 6
-end
diff --git a/src/mem/ruby/libruby.cc b/src/mem/ruby/libruby.cc
index e4e302eba..71f7e383e 100644
--- a/src/mem/ruby/libruby.cc
+++ b/src/mem/ruby/libruby.cc
@@ -133,6 +133,10 @@ void libruby_read_ram(uint64_t paddr, uint8_t* data, int len)
RubySystem::getMemoryVector()->read(Address(paddr), data, len);
}
+bool libruby_isReady(RubyPortHandle p, struct RubyRequest request) {
+ return static_cast<RubyPort*>(p)->isReady(request, true);
+}
+
int64_t libruby_issue_request(RubyPortHandle p, struct RubyRequest request)
{
return static_cast<RubyPort*>(p)->makeRequest(request);
diff --git a/src/mem/ruby/libruby.hh b/src/mem/ruby/libruby.hh
index a73ff5cf4..a5418d9e6 100644
--- a/src/mem/ruby/libruby.hh
+++ b/src/mem/ruby/libruby.hh
@@ -34,7 +34,7 @@ struct RubyRequest {
unsigned proc_id;
RubyRequest() {}
- RubyRequest(uint64_t _paddr, uint8_t* _data, int _len, uint64_t _pc, RubyRequestType _type, RubyAccessMode _access_mode, unsigned _proc_id = 0)
+ RubyRequest(uint64_t _paddr, uint8_t* _data, int _len, uint64_t _pc, RubyRequestType _type, RubyAccessMode _access_mode, unsigned _proc_id = 100)
: paddr(_paddr), data(_data), len(_len), pc(_pc), type(_type), access_mode(_access_mode), proc_id(_proc_id)
{}
};
@@ -76,6 +76,12 @@ RubyPortHandle libruby_get_port_by_name(const char* name);
*/
int64_t libruby_issue_request(RubyPortHandle p, struct RubyRequest request);
+
+/**
+ *
+ */
+bool libruby_isReady(RubyPortHandle p, struct RubyRequest request);
+
/**
* writes data directly into Ruby's data array. Note that this
* ignores caches, and should be considered incoherent after
diff --git a/src/mem/ruby/system/CacheMemory.hh b/src/mem/ruby/system/CacheMemory.hh
index 7a46bd3a5..4b2bc7084 100644
--- a/src/mem/ruby/system/CacheMemory.hh
+++ b/src/mem/ruby/system/CacheMemory.hh
@@ -156,6 +156,7 @@ private:
// The first index is the # of cache lines.
// The second index is the the amount associativity.
+ m5::hash_map<Address, int> m_tag_index;
Vector<Vector<AbstractCacheEntry*> > m_cache;
Vector<Vector<int> > m_locked;
@@ -286,6 +287,12 @@ int CacheMemory::findTagInSet(Index cacheSet, const Address& tag) const
{
assert(tag == line_address(tag));
// search the set for the tags
+ m5::hash_map<Address, int>::const_iterator it = m_tag_index.find(tag);
+ if (it != m_tag_index.end())
+ if (m_cache[cacheSet][it->second]->m_Permission != AccessPermission_NotPresent)
+ return it->second;
+ return -1; // Not found
+ /*
for (int i=0; i < m_cache_assoc; i++) {
if ((m_cache[cacheSet][i] != NULL) &&
(m_cache[cacheSet][i]->m_Address == tag) &&
@@ -294,6 +301,7 @@ int CacheMemory::findTagInSet(Index cacheSet, const Address& tag) const
}
}
return -1; // Not found
+ */
}
// Given a cache index: returns the index of the tag in a set.
@@ -303,11 +311,19 @@ int CacheMemory::findTagInSetIgnorePermissions(Index cacheSet, const Address& ta
{
assert(tag == line_address(tag));
// search the set for the tags
+ m5::hash_map<Address, int>::const_iterator it = m_tag_index.find(tag);
+ if (it != m_tag_index.end())
+ return it->second;
+ return -1; // Not found
+ /*
+ assert(tag == line_address(tag));
+ // search the set for the tags
for (int i=0; i < m_cache_assoc; i++) {
if (m_cache[cacheSet][i] != NULL && m_cache[cacheSet][i]->m_Address == tag)
return i;
}
return -1; // Not found
+ */
}
// PUBLIC METHODS
@@ -418,6 +434,7 @@ void CacheMemory::allocate(const Address& address, AbstractCacheEntry* entry)
m_cache[cacheSet][i]->m_Address = address;
m_cache[cacheSet][i]->m_Permission = AccessPermission_Invalid;
m_locked[cacheSet][i] = -1;
+ m_tag_index[address] = i;
m_replacementPolicy_ptr->touch(cacheSet, i, g_eventQueue_ptr->getTime());
@@ -439,6 +456,7 @@ void CacheMemory::deallocate(const Address& address)
delete m_cache[cacheSet][location];
m_cache[cacheSet][location] = NULL;
m_locked[cacheSet][location] = -1;
+ m_tag_index.erase(address);
}
}
diff --git a/src/mem/ruby/system/DMASequencer.hh b/src/mem/ruby/system/DMASequencer.hh
index 1f60b95ec..77c0a2258 100644
--- a/src/mem/ruby/system/DMASequencer.hh
+++ b/src/mem/ruby/system/DMASequencer.hh
@@ -25,6 +25,7 @@ public:
void init(const vector<string> & argv);
/* external interface */
int64_t makeRequest(const RubyRequest & request);
+ bool isReady(const RubyRequest & request, bool dont_set = false) { assert(0); return false;};
// void issueRequest(uint64_t paddr, uint8* data, int len, bool rw);
bool busy() { return m_is_busy;}
diff --git a/src/mem/ruby/system/RubyPort.hh b/src/mem/ruby/system/RubyPort.hh
index 2f391070f..cc7fd8d1f 100644
--- a/src/mem/ruby/system/RubyPort.hh
+++ b/src/mem/ruby/system/RubyPort.hh
@@ -21,6 +21,8 @@ public:
virtual int64_t makeRequest(const RubyRequest & request) = 0;
+ virtual bool isReady(const RubyRequest & request, bool dont_set = false) = 0;
+
void registerHitCallback(void (*hit_callback)(int64_t request_id)) {
assert(m_hit_callback == NULL); // can't assign hit_callback twice
m_hit_callback = hit_callback;
diff --git a/src/mem/ruby/system/Sequencer.cc b/src/mem/ruby/system/Sequencer.cc
index 780c1128e..7d032992a 100644
--- a/src/mem/ruby/system/Sequencer.cc
+++ b/src/mem/ruby/system/Sequencer.cc
@@ -61,7 +61,7 @@ void Sequencer::init(const vector<string> & argv)
m_instCache_ptr = NULL;
m_dataCache_ptr = NULL;
m_controller = NULL;
- m_servicing_atomic = -1;
+ m_servicing_atomic = 200;
m_atomics_counter = 0;
for (size_t i=0; i<argv.size(); i+=2) {
if ( argv[i] == "controller") {
@@ -108,6 +108,7 @@ void Sequencer::wakeup() {
WARN_MSG("Possible Deadlock detected");
WARN_EXPR(request);
WARN_EXPR(m_version);
+ WARN_EXPR(request->ruby_request.paddr);
WARN_EXPR(keys.size());
WARN_EXPR(current_time);
WARN_EXPR(request->issue_time);
@@ -344,13 +345,22 @@ void Sequencer::hitCallback(SequencerRequest* srequest, DataBlock& data) {
data.setData(ruby_request.data, request_address.getOffset(), ruby_request.len);
}
}
-
+ if (type == RubyRequestType_RMW_Write) {
+ if (m_servicing_atomic != ruby_request.proc_id) {
+ assert(0);
+ }
+ assert(m_atomics_counter > 0);
+ m_atomics_counter--;
+ if (m_atomics_counter == 0) {
+ m_servicing_atomic = 200;
+ }
+ }
m_hit_callback(srequest->id);
delete srequest;
}
// Returns true if the sequencer already has a load or store outstanding
-bool Sequencer::isReady(const RubyRequest& request) {
+bool Sequencer::isReady(const RubyRequest& request, bool dont_set) {
// POLINA: check if we are currently flushing the write buffer, if so Ruby is returned as not ready
// to simulate stalling of the front-end
// Do we stall all the sequencers? If it is atomic instruction - yes!
@@ -365,27 +375,29 @@ bool Sequencer::isReady(const RubyRequest& request) {
return false;
}
- if (m_servicing_atomic != -1 && m_servicing_atomic != (int)request.proc_id) {
+ if (m_servicing_atomic != 200 && m_servicing_atomic != request.proc_id) {
assert(m_atomics_counter > 0);
return false;
}
else {
- if (request.type == RubyRequestType_RMW_Read) {
- if (m_servicing_atomic == -1) {
- assert(m_atomics_counter == 0);
- m_servicing_atomic = (int)request.proc_id;
+ if (!dont_set) {
+ if (request.type == RubyRequestType_RMW_Read) {
+ if (m_servicing_atomic == 200) {
+ assert(m_atomics_counter == 0);
+ m_servicing_atomic = request.proc_id;
+ }
+ else {
+ assert(m_servicing_atomic == request.proc_id);
+ }
+ m_atomics_counter++;
}
else {
- assert(m_servicing_atomic == (int)request.proc_id);
- }
- m_atomics_counter++;
- }
- else if (request.type == RubyRequestType_RMW_Write) {
- assert(m_servicing_atomic == (int)request.proc_id);
- assert(m_atomics_counter > 0);
- m_atomics_counter--;
- if (m_atomics_counter == 0) {
- m_servicing_atomic = -1;
+ if (m_servicing_atomic == request.proc_id) {
+ if (request.type != RubyRequestType_RMW_Write) {
+ m_servicing_atomic = 200;
+ m_atomics_counter = 0;
+ }
+ }
}
}
}
@@ -405,7 +417,7 @@ int64_t Sequencer::makeRequest(const RubyRequest & request)
int64_t id = makeUniqueRequestID();
SequencerRequest *srequest = new SequencerRequest(request, id, g_eventQueue_ptr->getTime());
bool found = insertRequest(srequest);
- if (!found)
+ if (!found) {
if (request.type == RubyRequestType_Locked_Write) {
// NOTE: it is OK to check the locked flag here as the mandatory queue will be checked first
// ensuring that nothing comes between checking the flag and servicing the store
@@ -423,6 +435,10 @@ int64_t Sequencer::makeRequest(const RubyRequest & request)
// TODO: issue hardware prefetches here
return id;
+ }
+ else {
+ assert(0);
+ }
}
else {
return -1;
@@ -444,14 +460,8 @@ void Sequencer::issueRequest(const RubyRequest& request) {
ctype = CacheRequestType_ST;
break;
case RubyRequestType_Locked_Read:
- ctype = CacheRequestType_ST;
- break;
case RubyRequestType_Locked_Write:
- ctype = CacheRequestType_ST;
- break;
case RubyRequestType_RMW_Read:
- ctype = CacheRequestType_ATOMIC;
- break;
case RubyRequestType_RMW_Write:
ctype = CacheRequestType_ATOMIC;
break;
diff --git a/src/mem/ruby/system/Sequencer.hh b/src/mem/ruby/system/Sequencer.hh
index 2b1f023c5..e75cdaa3a 100644
--- a/src/mem/ruby/system/Sequencer.hh
+++ b/src/mem/ruby/system/Sequencer.hh
@@ -84,7 +84,7 @@ public:
// called by Tester or Simics
int64_t makeRequest(const RubyRequest & request);
- bool isReady(const RubyRequest& request);
+ bool isReady(const RubyRequest& request, bool dont_set = false);
bool empty() const;
void print(ostream& out) const;
@@ -125,7 +125,7 @@ private:
// Global outstanding request count, across all request tables
int m_outstanding_count;
bool m_deadlock_check_scheduled;
- int m_servicing_atomic;
+ unsigned m_servicing_atomic;
int m_atomics_counter;
};
diff --git a/tests/configs/memtest-ruby.py b/tests/configs/memtest-ruby.py
index 00a668a7b..d2be2791e 100644
--- a/tests/configs/memtest-ruby.py
+++ b/tests/configs/memtest-ruby.py
@@ -35,7 +35,7 @@ nb_cores = 8
cpus = [ MemTest() for i in xrange(nb_cores) ]
import ruby_config
-ruby_memory = ruby_config.generate("MI_example-homogeneous.rb", nb_cores)
+ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", nb_cores)
# system simulated
system = System(cpu = cpus, funcmem = PhysicalMemory(),
diff --git a/util/style.py b/util/style.py
index 461573941..650c25e78 100644
--- a/util/style.py
+++ b/util/style.py
@@ -65,7 +65,7 @@ def whitespace_file(filename):
if filename.startswith("SCons"):
return True
- return False
+ return True
format_types = ( 'C', 'C++' )
def format_file(filename):
@@ -77,11 +77,11 @@ def format_file(filename):
def checkwhite_line(line):
match = lead.search(line)
if match and match.group(1).find('\t') != -1:
- return False
+ return True
match = trail.search(line)
if match:
- return False
+ return True
return True
generated by cgit v1.2.3 (git 2.25.1) at 2025-02-14 09:09:34 +0000