diff options
| -rw-r--r-- | configs/example/memtest-ruby.py | 7 | ||||
| -rw-r--r-- | src/mem/RubyMemory.py | 1 | ||||
| -rw-r--r-- | src/mem/rubymem.cc | 10 | ||||
| -rw-r--r-- | src/mem/rubymem.hh | 1 | ||||
| -rw-r--r-- | tests/configs/ruby_config.py | 5 |
5 files changed, 16 insertions, 8 deletions
diff --git a/configs/example/memtest-ruby.py b/configs/example/memtest-ruby.py index 0305a3096..e47b8e0a3 100644 --- a/configs/example/memtest-ruby.py +++ b/configs/example/memtest-ruby.py @@ -86,8 +86,11 @@ cpus = [ MemTest(atomic=options.atomic, max_loads=options.maxloads, \ for i in xrange(options.testers) ] # create the desired simulated system -# ruby memory -ruby_memory = ruby_config.generate("MI_example-homogeneous.rb", options.testers) +# ruby memory must be at least 16 MB to work with the mem tester +ruby_memory = ruby_config.generate("MI_example-homogeneous.rb", + cores = options.testers, + memory_size = 16, + ports_per_cpu = 1) system = System(cpu = cpus, funcmem = PhysicalMemory(), physmem = ruby_memory) diff --git a/src/mem/RubyMemory.py b/src/mem/RubyMemory.py index ddd97572c..2ad794a3f 100644 --- a/src/mem/RubyMemory.py +++ b/src/mem/RubyMemory.py @@ -45,3 +45,4 @@ class RubyMemory(PhysicalMemory): num_dmas = Param.Int(0, "Number of DMA ports connected to the Ruby memory") dma_port = VectorPort("Ruby_dma_ports") pio_port = Port("Ruby_pio_port") + ports_per_core = Param.Int(2, "Number of per core. Typical two: icache + dcache") diff --git a/src/mem/rubymem.cc b/src/mem/rubymem.cc index aecc0af32..9a1a7927d 100644 --- a/src/mem/rubymem.cc +++ b/src/mem/rubymem.cc @@ -58,6 +58,8 @@ RubyMemory::RubyMemory(const Params *p) ruby_clock = p->clock; ruby_phase = p->phase; + ports_per_cpu = p->ports_per_core; + DPRINTF(Ruby, "creating Ruby Memory from file %s\n", p->config_file.c_str()); @@ -230,14 +232,14 @@ RubyMemory::getPort(const std::string &if_name, int idx) // // Currently this code assumes that each cpu has both a - // icache and dcache port and therefore divides by two. This will be - // fixed once we unify the configuration systems and Ruby sequencers + // icache and dcache port and therefore divides by ports per cpu. This will + // be fixed once we unify the configuration systems and Ruby sequencers // directly support M5 ports. // - assert(idx/2 < ruby_ports.size()); + assert(idx/ports_per_cpu < ruby_ports.size()); Port *port = new Port(csprintf("%s-port%d", name(), idx), this, - ruby_ports[idx/2]); + ruby_ports[idx/ports_per_cpu]); ports[idx] = port; return port; diff --git a/src/mem/rubymem.hh b/src/mem/rubymem.hh index dd0a492f5..2672dcb77 100644 --- a/src/mem/rubymem.hh +++ b/src/mem/rubymem.hh @@ -130,6 +130,7 @@ class RubyMemory : public PhysicalMemory Tick ruby_clock; Tick ruby_phase; RubyExitCallback* rubyExitCB; + int ports_per_cpu; public: static std::map<int64_t, PacketPtr> pending_requests; diff --git a/tests/configs/ruby_config.py b/tests/configs/ruby_config.py index 000b7d23f..fec7bd36c 100644 --- a/tests/configs/ruby_config.py +++ b/tests/configs/ruby_config.py @@ -8,7 +8,7 @@ from m5.params import * def generate(config_file, cores=1, memories=1, memory_size=1024, \ cache_size=32768, cache_assoc=8, dmas=1, - ruby_tick='1t'): + ruby_tick='1t', ports_per_cpu=2): default = joinpath(dirname(__file__), '../../src/mem/ruby/config') ruby_config = os.environ.get('RUBY_CONFIG', default) args = [ "ruby", "-I", ruby_config, joinpath(ruby_config, "print_cfg.rb"), @@ -25,4 +25,5 @@ def generate(config_file, cores=1, memories=1, memory_size=1024, \ config_file = temp_config, num_cpus = cores, range = AddrRange(str(memory_size)+"MB"), - num_dmas = dmas) + num_dmas = dmas, + ports_per_core = ports_per_cpu) |