diff options
| -rw-r--r-- | src/arch/arm/miscregs.cc | 3 | ||||
| -rw-r--r-- | src/arch/arm/miscregs.hh | 2 |
2 files changed, 0 insertions, 5 deletions
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc index 08e37bb70..31b3580be 100644 --- a/src/arch/arm/miscregs.cc +++ b/src/arch/arm/miscregs.cc @@ -4007,9 +4007,6 @@ ISA::initializeMiscRegMetadata() InitReg(MISCREG_CP15_UNIMPL) .unimplemented() .warnNotFail(); - InitReg(MISCREG_A64_UNIMPL) - .unimplemented() - .warnNotFail(); InitReg(MISCREG_UNKNOWN); // Register mappings for some unimplemented registers: diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh index b43b04f72..b00e5ff66 100644 --- a/src/arch/arm/miscregs.hh +++ b/src/arch/arm/miscregs.hh @@ -689,7 +689,6 @@ namespace ArmISA MISCREG_RAZ, MISCREG_CP14_UNIMPL, MISCREG_CP15_UNIMPL, - MISCREG_A64_UNIMPL, MISCREG_UNKNOWN, // Implementation defined register: this represent @@ -1386,7 +1385,6 @@ namespace ArmISA "raz", "cp14_unimpl", "cp15_unimpl", - "a64_unimpl", "unknown", "impl_defined" }; |