diff options
| -rw-r--r-- | arch/mips/isa/decoder.isa | 9 | ||||
| -rw-r--r-- | arch/mips/isa_traits.cc | 18 | ||||
| -rw-r--r-- | arch/mips/isa_traits.hh | 12 |
3 files changed, 15 insertions, 24 deletions
diff --git a/arch/mips/isa/decoder.isa b/arch/mips/isa/decoder.isa index 9bafe9f34..53bbb94a4 100644 --- a/arch/mips/isa/decoder.isa +++ b/arch/mips/isa/decoder.isa @@ -149,13 +149,13 @@ decode OPCODE_HI default Unknown::unknown() { }}); 0x2: div({{ - xc->setMiscReg(Hi,Rs.sw % Rt.sw); - xc->setMiscReg(Lo,Rs.sw / Rt.sw); + xc->setMiscReg(Hi,Rs.sd % Rt.sd); + xc->setMiscReg(Lo,Rs.sd / Rt.sd); }}); 0x3: divu({{ - xc->setMiscReg(Hi,Rs.uw % Rt.uw); - xc->setMiscReg(Lo,Rs.uw / Rt.uw); + xc->setMiscReg(Hi,Rs.ud % Rt.ud); + xc->setMiscReg(Lo,Rs.ud / Rt.ud); }}); } } @@ -435,6 +435,7 @@ decode OPCODE_HI default Unknown::unknown() { 0x6: ctc1({{ uint32_t fcsr_reg = xc->readMiscReg(FCSR); uint32_t temp; + switch (FS) { case 25: diff --git a/arch/mips/isa_traits.cc b/arch/mips/isa_traits.cc index 20c13fd36..282bb4a41 100644 --- a/arch/mips/isa_traits.cc +++ b/arch/mips/isa_traits.cc @@ -95,29 +95,19 @@ MipsISA::convert_and_round(uint64_t fp_val, ConvertType cvt_type, int rnd_mode) uint64_t -MipsISA::convert_and_round(float fp_val, ConvertType cvt_type, int rnd_mode) +MipsISA::convert_and_round(double fp_val, ConvertType cvt_type, int rnd_mode) { - void * ptr = &fp_val; - uint32_t fp_bits = * (uint32_t *) ptr; - - cout << "Converting " << fp_val << " (" << hex << fp_bits << ") " << endl; - - uint64_t ret_val = 0; - switch (cvt_type) { case SINGLE_TO_DOUBLE: double double_val = fp_val; - void *double_ptr = &double_val; - uint64_t dp_bits = *(uint64_t *) double_ptr ; - cout << "To " << double_val << " (" << hex << dp_bits << ") " << endl; - double_ptr = &dp_bits; - cout << "Testing: " << *(double *) double_ptr << endl; + void *double_ptr = &double_val; + uint64_t dp_bits = *(uint64_t *) double_ptr ; return dp_bits; default: panic("Invalid Floating Point Conversion Type (%d) being used.\n",cvt_type); - return ret_val; + return 0; } } diff --git a/arch/mips/isa_traits.hh b/arch/mips/isa_traits.hh index efa326e1c..3879eaf40 100644 --- a/arch/mips/isa_traits.hh +++ b/arch/mips/isa_traits.hh @@ -248,7 +248,7 @@ namespace MipsISA return regs[floatReg]; case DoubleWidth: - return (FloatReg64)regs[floatReg] << 32 | regs[floatReg + 1]; + return (FloatReg64)regs[floatReg + 1] << 32 | regs[floatReg]; default: panic("Attempted to read a %d bit floating point register!", width); @@ -269,8 +269,8 @@ namespace MipsISA case DoubleWidth: const void *double_ptr = &val; FloatReg64 temp_double = *(FloatReg64 *) double_ptr; - regs[floatReg] = temp_double >> 32; - regs[floatReg + 1] = temp_double; + regs[floatReg + 1] = temp_double >> 32; + regs[floatReg] = temp_double; break; default: @@ -291,8 +291,8 @@ namespace MipsISA break; case DoubleWidth: - regs[floatReg] = val >> 32; - regs[floatReg + 1] = val; + regs[floatReg + 1] = val >> 32; + regs[floatReg] = val; break; default: @@ -336,7 +336,7 @@ namespace MipsISA uint64_t convert_and_round(uint32_t fp_val,ConvertType cvt_type, int rnd_mode = 0); uint64_t convert_and_round(uint64_t fp_val,ConvertType cvt_type, int rnd_mode = 0); - uint64_t convert_and_round(float fp_val,ConvertType cvt_type, int rnd_mode = 0); + uint64_t convert_and_round(double fp_val,ConvertType cvt_type, int rnd_mode = 0); void copyRegs(ExecContext *src, ExecContext *dest); |