diff options
46 files changed, 10491 insertions, 56 deletions
diff --git a/src/arch/isa_parser.py b/src/arch/isa_parser.py index f3981a6eb..a0d671da1 100755 --- a/src/arch/isa_parser.py +++ b/src/arch/isa_parser.py @@ -311,12 +311,19 @@ def p_output_exec(t): def p_global_let(t): 'global_let : LET CODELIT SEMI' updateExportContext() + exportContext["header_output"] = '' + exportContext["decoder_output"] = '' + exportContext["exec_output"] = '' + exportContext["decode_block"] = '' try: exec fixPythonIndentation(t[2]) in exportContext except Exception, exc: error(t.lineno(1), 'error: %s in global let block "%s".' % (exc, t[2])) - t[0] = GenCode() # contributes nothing to the output C++ file + t[0] = GenCode(header_output = exportContext["header_output"], + decoder_output = exportContext["decoder_output"], + exec_output = exportContext["exec_output"], + decode_block = exportContext["decode_block"]) # Define the mapping from operand type extensions to C++ types and bit # widths (stored in operandTypeMap). diff --git a/src/arch/x86/isa/decoder/one_byte_opcodes.isa b/src/arch/x86/isa/decoder/one_byte_opcodes.isa index c56a8bf92..b4aeece07 100644 --- a/src/arch/x86/isa/decoder/one_byte_opcodes.isa +++ b/src/arch/x86/isa/decoder/one_byte_opcodes.isa @@ -64,7 +64,7 @@ 0x6: push_ES(); 0x7: pop_ES(); default: MultiOp::add( - {{out1 = in1 + in2}}, + {{Add %0 %0 %1}}, OPCODE_OP_BOTTOM3, [[Eb,Gb],[Ev,Gv], [Gb,Eb],[Gv,Ev], diff --git a/src/arch/x86/isa/formats/multi.isa b/src/arch/x86/isa/formats/multi.isa index 3e80f9cfb..c14e80095 100644 --- a/src/arch/x86/isa/formats/multi.isa +++ b/src/arch/x86/isa/formats/multi.isa @@ -74,33 +74,81 @@ let {{ }}; def format MultiOp(code, switchVal, opTags, *opt_flags) {{ - # Loads and stores that bring in and write out values from the - # instructions. These are determined by the input and output tags, - # and the resulting instruction will have the right number of micro ops, - # or could be implemented as an atomic macro op. - instNames = [] + # These are C++ statements to create each type of static int. Since we + # don't know what will be microcoded and what won't, we can't assume a + # particular set of arguments for the constructor. + instNew = [] + orig_code = code + opRe = re.compile(r"%(?P<operandNum>[0-9]*)") + # Get all the labels out of the code and make a dict for them. We'll do + # this once since the position of labels shouldn't need to change at all. + ops = assembleMicro(code) + labels = buildLabelDict(ops) for tagSet in opTags: - loads = [] - stores = [] + # A list of strings which either have the register number to use, or + # a piece of code for calculating it. + regNums = [] + code = orig_code + # Build up a name for this instructions class using the argument + # types. Each variation will get its own name this way. postfix = '' for tag in tagSet: postfix += '_' + tag - gather_inputs = '' - if len(loads) + len(stores) == 0: - # If there are no loads or stores, make this a single instruction. - iop = InstObjParams(name, Name + postfix, 'X86StaticInst', - {"code": code, "gather_inputs": gather_inputs}, - opt_flags) + + # Figure out what register indexes to use for each operand. This + # is where loads/stores could be set up. I need to distinguish + # between inputs and outputs. + # For right now, the indexes are just an increasing sequence + counter = 0 + for tag in tagSet: + regNums.append("%d" % counter) + counter += 1 + + # Replace the placeholders %0, %1, etc., with the right register + # indexes. + opMatch = opRe.search(code) + while opMatch: + opNum = opMatch.group("operandNum") + opNum = int(opNum) + if opNum > len(regNums): + print "No operand type specified for operand %d!" % opNum + print "I should bail out here too!" + regNum = regNums[opNum] + code = opRe.sub(regNum, code, 1) + opMatch = opRe.search(code) + + # All the loads which feed this instruction + loads = [] + # All the ops that make up the instruction proper. + ops = assembleMicro(code) + # Get all the labels out and make a dict for them + # All the stores for this instruction's results + stores = [] + + # Various counts + numLoads = len(loads) + numOps = len(ops) + numStores = len(stores) + totalOps = numLoads + numOps + numStores + print "There are %d total ops" % totalOps + + # If we can implement this instruction with exactly one microop, just + # use that directly. + newStmnt = '' + if totalOps == 1: + newStmnt = ops[0].getAllocator(labels) else: # Build up a macro op. We'll punt on this for now pass + instNew.append(newStmnt) + decodeBlob = 'switch(%s) {\n' % switchVal counter = 0 - for inst in instNames: - decodeBlob += '%d: return (X86StaticInst *)(new %s(machInst));\n' % \ - (counter, inst) + for newStmnt in instNew: + decodeBlob += 'case %d: return (X86StaticInst *)(%s);\n' % \ + (counter, newStmnt) counter += 1 decodeBlob += '}\n' - # decode_block = BasicDecodeWithMnemonic.subst(iop) + decode_block = decodeBlob }}; diff --git a/src/arch/x86/isa/main.isa b/src/arch/x86/isa/main.isa index 146f714a7..fe1d4e515 100644 --- a/src/arch/x86/isa/main.isa +++ b/src/arch/x86/isa/main.isa @@ -72,6 +72,9 @@ namespace X86ISA; +//Include the simple microcode assembler +##include "microasm.isa" + //Include the bitfield definitions ##include "bitfields.isa" @@ -84,5 +87,8 @@ namespace X86ISA; //Include the definitions for the instruction formats ##include "formats/formats.isa" +//Include the definitions of the micro ops +##include "microops/microops.isa" + //Include the decoder definition ##include "decoder/decoder.isa" diff --git a/src/arch/x86/isa/microasm.isa b/src/arch/x86/isa/microasm.isa new file mode 100644 index 000000000..2abce6e7f --- /dev/null +++ b/src/arch/x86/isa/microasm.isa @@ -0,0 +1,172 @@ +// -*- mode:c++ -*- + +// Copyright (c) 2007 The Hewlett-Packard Development Company +// All rights reserved. +// +// Redistribution and use of this software in source and binary forms, +// with or without modification, are permitted provided that the +// following conditions are met: +// +// The software must be used only for Non-Commercial Use which means any +// use which is NOT directed to receiving any direct monetary +// compensation for, or commercial advantage from such use. Illustrative +// examples of non-commercial use are academic research, personal study, +// teaching, education and corporate research & development. +// Illustrative examples of commercial use are distributing products for +// commercial advantage and providing services using the software for +// commercial advantage. +// +// If you wish to use this software or functionality therein that may be +// covered by patents for commercial use, please contact: +// Director of Intellectual Property Licensing +// Office of Strategy and Technology +// Hewlett-Packard Company +// 1501 Page Mill Road +// Palo Alto, California 94304 +// +// Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. Redistributions +// in binary form must reproduce the above copyright notice, this list of +// conditions and the following disclaimer in the documentation and/or +// other materials provided with the distribution. Neither the name of +// the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. No right of +// sublicense is granted herewith. Derivatives of the software and +// output created using the software may be prepared, but only for +// Non-Commercial Uses. Derivatives of the software may be shared with +// others provided: (i) the others agree to abide by the list of +// conditions herein which includes the Non-Commercial Use restrictions; +// and (ii) such Derivatives of the software include the above copyright +// notice to acknowledge the contribution from this software where +// applicable, this list of conditions and the disclaimer below. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// Authors: Gabe Black + +//////////////////////////////////////////////////////////////////// +// +// Code to "assemble" microcode sequences +// + +let {{ + class MicroOpStatement: + def __init__(self): + self.className = '' + self.label = '' + self.args = [] + + def getAllocator(self, labelDict = {}): + args = '' + for arg in self.args: + if arg.has_key("operandConst"): + args += ", %s" % arg["operandConst"] + elif arg.has_key("operandCode"): + args += ", %s" % arg["operandCode"] + elif arg.has_key("operandLabel"): + if not labelDict.has_key(arg["operandLabel"]): + print "Unrecognized label %s!" % arg["operandLabel"] + args += ", %s" % labelDict[arg["operandLabel"]] + else: + print "Unrecognized operand type!" + return 'new %s(machInst %s)' % (self.className, args) + + + def assembleMicro(code): + # This function takes in a block of microcode assembly and returns + # a python list of objects which describe it. + + # Keep this around in case we need it later + orig_code = code + # A list of the statements we've found thus far + statements = [] + + # Regular expressions to pull each piece of the statement out at a + # time. Each expression expects the thing it's looking for to be at + # the beginning of the line, so the previous component is stripped + # before continuing. + labelRe = re.compile(r'^[ \t]*(?P<label>[a-zA-Z_]\w*)[ \t]:') + lineRe = re.compile(r'^(?P<line>[^\n][^\n]*)$') + classRe = re.compile(r'^[ \t]*(?P<className>[a-zA-Z_]\w*)') + # This recognizes three different flavors of operands: + # 1. Raw decimal numbers composed of digits between 0 and 9 + # 2. Code beginning with "{" and continuing until the first "}" + # ^ This one might need revising + # 3. A label, which starts with a capital or small letter, or + # underscore, which is optionally followed by a sequence of + # capital or small letters, underscores, or digts between 0 and 9 + opRe = re.compile( \ + r'^[ \t]*((?P<operandLabel>[a-zA-Z_]\w*)|(?P<operandConst>[0-9][0-9]*)|(\{(?P<operandCode>[^}]*)\}))') + lineMatch = lineRe.search(code) + while lineMatch != None: + statement = MicroOpStatement() + # Get a line and seperate it from the rest of the code + line = lineMatch.group("line") + print "Parsing line %s" % line + code = lineRe.sub('', code, 1) + + # Find the label, if any + labelMatch = labelRe.search(line) + if labelMatch != None: + statement.label = labelMatch.group("label") + print "Found label %s." % statement.label + # Clear the label from the statement + line = labelRe.sub('', line, 1) + + # Find the class name which is roughly equivalent to the op name + classMatch = classRe.search(line) + if classMatch == None: + print "Oh no! I can't find what instruction you want!" + print "I should really bail out here, but I don't know how!" + else: + statement.className = classMatch.group("className") + print "Found class name %s." % statement.className + + # Clear the class name from the statement + line = classRe.sub('', line, 1) + + #Find as many arguments as you can + statement.args = [] + opMatch = opRe.search(line) + while opMatch is not None: + statement.args.append({}) + # args is a list of dicts which collect different + # representations of operand values. Different forms might be + # needed in different places, for instance to replace a label + # with an offset. + for opType in ("operandLabel", "operandConst", "operandCode"): + if opMatch.group(opType): + statement.args[-1][opType] = opMatch.group(opType) + if len(statement.args[-1]) == 0: + print "I had a problem parsing an operand!" + line = opRe.sub('', line, 1) + print "Found operand %s." % statement.args[-1] + opMatch = opRe.search(line) + print "Found operands", statement.args + + # Add this statement to our collection + statements.append(statement) + + # Get the next line + lineMatch = lineRe.search(code) + return statements + + def buildLabelDict(ops): + labels = {} + count = 0 + for op in ops: + if op.label: + labels[op.label] = count + count += 1 +}}; diff --git a/src/arch/x86/isa/microops/microops.isa b/src/arch/x86/isa/microops/microops.isa new file mode 100644 index 000000000..bbf26f605 --- /dev/null +++ b/src/arch/x86/isa/microops/microops.isa @@ -0,0 +1,57 @@ +// Copyright (c) 2007 The Hewlett-Packard Development Company +// All rights reserved. +// +// Redistribution and use of this software in source and binary forms, +// with or without modification, are permitted provided that the +// following conditions are met: +// +// The software must be used only for Non-Commercial Use which means any +// use which is NOT directed to receiving any direct monetary +// compensation for, or commercial advantage from such use. Illustrative +// examples of non-commercial use are academic research, personal study, +// teaching, education and corporate research & development. +// Illustrative examples of commercial use are distributing products for +// commercial advantage and providing services using the software for +// commercial advantage. +// +// If you wish to use this software or functionality therein that may be +// covered by patents for commercial use, please contact: +// Director of Intellectual Property Licensing +// Office of Strategy and Technology +// Hewlett-Packard Company +// 1501 Page Mill Road +// Palo Alto, California 94304 +// +// Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. Redistributions +// in binary form must reproduce the above copyright notice, this list of +// conditions and the following disclaimer in the documentation and/or +// other materials provided with the distribution. Neither the name of +// the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. No right of +// sublicense is granted herewith. Derivatives of the software and +// output created using the software may be prepared, but only for +// Non-Commercial Uses. Derivatives of the software may be shared with +// others provided: (i) the others agree to abide by the list of +// conditions herein which includes the Non-Commercial Use restrictions; +// and (ii) such Derivatives of the software include the above copyright +// notice to acknowledge the contribution from this software where +// applicable, this list of conditions and the disclaimer below. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// Authors: Gabe Black + +//Micro ops +##include "int.isa" diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa index 20376f38f..36b0ee4df 100644 --- a/src/arch/x86/isa/operands.isa +++ b/src/arch/x86/isa/operands.isa @@ -96,7 +96,7 @@ def operand_types {{ }}; def operands {{ - # This is just copied from SPARC, because having no operands confuses - # the parser. - 'Rd': ('IntReg', 'udw', 'RD', 'IsInteger', 1) + 'IntRegOp0': ('IntReg', 'udw', 'regIndex0', 'IsInteger', 1), + 'IntRegOp1': ('IntReg', 'udw', 'regIndex1', 'IsInteger', 2), + 'IntRegOp2': ('IntReg', 'udw', 'regIndex2', 'IsInteger', 2), }}; diff --git a/src/base/SConscript b/src/base/SConscript index 788aa3e6f..6fc140145 100644 --- a/src/base/SConscript +++ b/src/base/SConscript @@ -30,10 +30,26 @@ Import('*') -# base/traceflags.{cc,hh} are generated from base/traceflags.py. -# $TARGET.base will expand to "<build-dir>/base/traceflags". -env.Command(['traceflags.hh', 'traceflags.cc'], 'traceflags.py', - 'python $SOURCE $TARGET.base') +def make_cc(target, source, env): + assert(len(source) == 1) + assert(len(target) == 1) + + traceflags = {} + execfile(str(source[0]), traceflags) + func = traceflags['gen_cc'] + func(str(target[0])) + +def make_hh(target, source, env): + assert(len(source) == 1) + assert(len(target) == 1) + + traceflags = {} + execfile(str(source[0]), traceflags) + func = traceflags['gen_hh'] + func(str(target[0])) + +env.Command('traceflags.hh', 'traceflags.py', make_hh) +env.Command('traceflags.cc', 'traceflags.py', make_cc) Source('annotate.cc') Source('bigint.cc') diff --git a/src/base/traceflags.py b/src/base/traceflags.py index e57bfa350..6b241c410 100644 --- a/src/base/traceflags.py +++ b/src/base/traceflags.py @@ -350,16 +350,3 @@ const char *Trace::flagStrings[] = print >>ccfile, '};' ccfile.close() - -if __name__ == '__main__': - # This file generates the header and source files for the flags - # that control the tracing facility. - - import sys - - if len(sys.argv) != 2: - print "%s: Need argument (basename of cc/hh files)" % sys.argv[0] - sys.exit(1) - - gen_hh(sys.argv[1] + '.hh') - gen_cc(sys.argv[1] + '.cc') diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh index da7ce00f5..811f4d2bc 100644 --- a/src/cpu/o3/fetch.hh +++ b/src/cpu/o3/fetch.hh @@ -86,6 +86,8 @@ class DefaultFetch bool snoopRangeSent; + virtual void setPeer(Port *port); + protected: /** Atomic version of receive. Panics. */ virtual Tick recvAtomic(PacketPtr pkt); @@ -184,6 +186,9 @@ class DefaultFetch /** Initialize stage. */ void initStage(); + /** Tells the fetch stage that the Icache is set. */ + void setIcache(); + /** Processes cache completion event. */ void processCacheCompletion(PacketPtr pkt); diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh index 663cd3142..34b06420d 100644 --- a/src/cpu/o3/fetch_impl.hh +++ b/src/cpu/o3/fetch_impl.hh @@ -51,6 +51,15 @@ #include <algorithm> template<class Impl> +void +DefaultFetch<Impl>::IcachePort::setPeer(Port *port) +{ + Port::setPeer(port); + + fetch->setIcache(); +} + +template<class Impl> Tick DefaultFetch<Impl>::IcachePort::recvAtomic(PacketPtr pkt) { @@ -323,12 +332,6 @@ DefaultFetch<Impl>::initStage() nextNPC[tid] = cpu->readNextNPC(tid); } - // Size of cache block. - cacheBlkSize = icachePort->peerBlockSize(); - - // Create mask to get rid of offset bits. - cacheBlkMask = (cacheBlkSize - 1); - for (int tid=0; tid < numThreads; tid++) { fetchStatus[tid] = Running; @@ -337,11 +340,6 @@ DefaultFetch<Impl>::initStage() memReq[tid] = NULL; - // Create space to store a cache line. - cacheData[tid] = new uint8_t[cacheBlkSize]; - cacheDataPC[tid] = 0; - cacheDataValid[tid] = false; - stalls[tid].decode = false; stalls[tid].rename = false; stalls[tid].iew = false; @@ -351,6 +349,24 @@ DefaultFetch<Impl>::initStage() template<class Impl> void +DefaultFetch<Impl>::setIcache() +{ + // Size of cache block. + cacheBlkSize = icachePort->peerBlockSize(); + + // Create mask to get rid of offset bits. + cacheBlkMask = (cacheBlkSize - 1); + + for (int tid=0; tid < numThreads; tid++) { + // Create space to store a cache line. + cacheData[tid] = new uint8_t[cacheBlkSize]; + cacheDataPC[tid] = 0; + cacheDataValid[tid] = false; + } +} + +template<class Impl> +void DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt) { unsigned tid = pkt->req->getThreadNum(); diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh index 722ce216b..3e45c85d2 100644 --- a/src/mem/cache/cache.hh +++ b/src/mem/cache/cache.hh @@ -227,6 +227,12 @@ class Cache : public BaseCache BlkType* handleAccess(PacketPtr &pkt, int & lat, PacketList & writebacks, bool update = true); + + /** + *Handle doing the Compare and Swap function for SPARC. + */ + void cmpAndSwap(BlkType *blk, PacketPtr &pkt); + /** * Populates a cache block and handles all outstanding requests for the * satisfied fill request. This version takes an MSHR pointer and uses its diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh index fc4660269..ec0ef1be4 100644 --- a/src/mem/cache/cache_impl.hh +++ b/src/mem/cache/cache_impl.hh @@ -122,12 +122,15 @@ Cache<TagStore,Coherence>::handleAccess(PacketPtr &pkt, int & lat, if (blk != NULL) { if (!update) { + if (pkt->isWrite()){ assert(offset < blkSize); assert(pkt->getSize() <= blkSize); assert(offset+pkt->getSize() <= blkSize); std::memcpy(blk->data + offset, pkt->getPtr<uint8_t>(), pkt->getSize()); + } else if (pkt->isReadWrite()) { + cmpAndSwap(blk, pkt); } else if (!(pkt->flags & SATISFIED)) { pkt->flags |= SATISFIED; pkt->result = Packet::Success; @@ -154,7 +157,8 @@ Cache<TagStore,Coherence>::handleAccess(PacketPtr &pkt, int & lat, } } - if ((pkt->isWrite() && blk->isWritable()) || + if ((pkt->isReadWrite() && blk->isWritable()) || + (pkt->isWrite() && blk->isWritable()) || (pkt->isRead() && blk->isValid())) { // We are satisfying the request @@ -180,13 +184,15 @@ Cache<TagStore,Coherence>::handleAccess(PacketPtr &pkt, int & lat, std::memcpy(blk->data + offset, pkt->getPtr<uint8_t>(), pkt->getSize()); } + } else if (pkt->isReadWrite()) { + cmpAndSwap(blk, pkt); } else { assert(pkt->isRead()); if (pkt->req->isLocked()) { blk->trackLoadLocked(pkt->req); } std::memcpy(pkt->getPtr<uint8_t>(), blk->data + offset, - pkt->getSize()); + pkt->getSize()); } if (write_data || @@ -215,6 +221,44 @@ Cache<TagStore,Coherence>::handleAccess(PacketPtr &pkt, int & lat, } template<class TagStore, class Coherence> +void +Cache<TagStore,Coherence>::cmpAndSwap(BlkType *blk, PacketPtr &pkt){ + uint64_t overwrite_val; + bool overwrite_mem; + uint64_t condition_val64; + uint32_t condition_val32; + + int offset = tags->extractBlkOffset(pkt->getAddr()); + + assert(sizeof(uint64_t) >= pkt->getSize()); + + overwrite_mem = true; + // keep a copy of our possible write value, and copy what is at the + // memory address into the packet + std::memcpy(&overwrite_val, pkt->getPtr<uint8_t>(), pkt->getSize()); + std::memcpy(pkt->getPtr<uint8_t>(), blk->data + offset, + pkt->getSize()); + + if (pkt->req->isCondSwap()) { + if (pkt->getSize() == sizeof(uint64_t)) { + condition_val64 = pkt->req->getExtraData(); + overwrite_mem = !std::memcmp(&condition_val64, blk->data + offset, + sizeof(uint64_t)); + } else if (pkt->getSize() == sizeof(uint32_t)) { + condition_val32 = (uint32_t)pkt->req->getExtraData(); + overwrite_mem = !std::memcmp(&condition_val32, blk->data + offset, + sizeof(uint32_t)); + } else + panic("Invalid size for conditional read/write\n"); + } + + if (overwrite_mem) + std::memcpy(blk->data + offset, + &overwrite_val, pkt->getSize()); + +} + +template<class TagStore, class Coherence> typename Cache<TagStore,Coherence>::BlkType* Cache<TagStore,Coherence>::handleFill(BlkType *blk, PacketPtr &pkt, CacheBlk::State new_state, @@ -244,8 +288,9 @@ Cache<TagStore,Coherence>::handleFill(BlkType *blk, PacketPtr &pkt, blk = NULL; } - if (blk && (target->isWrite() ? blk->isWritable() : blk->isValid())) { - assert(target->isWrite() || target->isRead()); + if (blk && ((target->isWrite() || target->isReadWrite()) ? + blk->isWritable() : blk->isValid())) { + assert(target->isWrite() || target->isReadWrite() || target->isRead()); assert(target->getOffset(blkSize) + target->getSize() <= blkSize); if (target->isWrite()) { if (blk->checkWrite(pkt->req)) { @@ -253,6 +298,8 @@ Cache<TagStore,Coherence>::handleFill(BlkType *blk, PacketPtr &pkt, std::memcpy(blk->data + target->getOffset(blkSize), target->getPtr<uint8_t>(), target->getSize()); } + } else if (target->isReadWrite()) { + cmpAndSwap(blk, target); } else { if (pkt->req->isLocked()) { blk->trackLoadLocked(pkt->req); @@ -332,8 +379,9 @@ Cache<TagStore,Coherence>::handleFill(BlkType *blk, MSHR * mshr, continue; } - if (blk && (target->isWrite() ? blk->isWritable() : blk->isValid())) { - assert(target->isWrite() || target->isRead()); + if (blk && ((target->isWrite() || target->isReadWrite()) ? + blk->isWritable() : blk->isValid())) { + assert(target->isWrite() || target->isRead() || target->isReadWrite() ); assert(target->getOffset(blkSize) + target->getSize() <= blkSize); if (target->isWrite()) { if (blk->checkWrite(pkt->req)) { @@ -341,6 +389,8 @@ Cache<TagStore,Coherence>::handleFill(BlkType *blk, MSHR * mshr, std::memcpy(blk->data + target->getOffset(blkSize), target->getPtr<uint8_t>(), target->getSize()); } + } else if (target->isReadWrite()) { + cmpAndSwap(blk, target); } else { if (target->req->isLocked()) { blk->trackLoadLocked(target->req); diff --git a/src/mem/cache/coherence/coherence_protocol.cc b/src/mem/cache/coherence/coherence_protocol.cc index e8520401d..33a8a4e63 100644 --- a/src/mem/cache/coherence/coherence_protocol.cc +++ b/src/mem/cache/coherence/coherence_protocol.cc @@ -295,9 +295,12 @@ CoherenceProtocol::CoherenceProtocol(const string &name, tt[Invalid][MC::ReadReq].onRequest(MC::ReadReq); // we only support write allocate right now tt[Invalid][MC::WriteReq].onRequest(MC::ReadExReq); + tt[Invalid][MC::SwapReq].onRequest(MC::ReadExReq); tt[Shared][MC::WriteReq].onRequest(writeToSharedCmd); + tt[Shared][MC::SwapReq].onRequest(writeToSharedCmd); if (hasOwned) { tt[Owned][MC::WriteReq].onRequest(writeToSharedCmd); + tt[Owned][MC::SwapReq].onRequest(writeToSharedCmd); } // Prefetching causes a read diff --git a/src/python/m5/objects/O3CPU.py b/src/python/m5/objects/O3CPU.py index 20eef383f..5fba4e96f 100644 --- a/src/python/m5/objects/O3CPU.py +++ b/src/python/m5/objects/O3CPU.py @@ -116,3 +116,8 @@ class DerivO3CPU(BaseCPU): smtROBPolicy = Param.String("SMT ROB Sharing Policy") smtROBThreshold = Param.String("SMT ROB Threshold Sharing Parameter") smtCommitPolicy = Param.String("SMT Commit Policy") + + def addPrivateSplitL1Caches(self, ic, dc): + BaseCPU.addPrivateSplitL1Caches(self, ic, dc) + self.icache.tgts_per_mshr = 20 + self.dcache.tgts_per_mshr = 20 diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini new file mode 100644 index 000000000..75db6656a --- /dev/null +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini @@ -0,0 +1,187 @@ +[root] +type=Root +children=system +dummy=0 + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=TimingSimpleCPU +children=dcache icache l2cache toL2Bus workload +clock=1 +cpu_id=0 +defer_registration=false +function_trace=false +function_trace_start=0 +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +phase=0 +progress_interval=0 +system=system +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=262144 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.port[1] + +[system.cpu.icache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=131072 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.port[0] + +[system.cpu.l2cache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=2097152 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.port[2] +mem_side=system.membus.port[1] + +[system.cpu.toL2Bus] +type=Bus +bus_id=0 +clock=1000 +responder_set=false +width=64 +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side + +[system.cpu.workload] +type=LiveProcess +cmd=gzip input.log 1 +cwd=build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing +egid=100 +env= +euid=100 +executable=/dist/m5/cpu2000/binaries/sparc/linux/gzip +gid=100 +input=cin +output=cout +pid=100 +ppid=99 +system=system +uid=100 + +[system.membus] +type=Bus +bus_id=0 +clock=1000 +responder_set=false +width=64 +port=system.physmem.port system.cpu.l2cache.mem_side + +[system.physmem] +type=PhysicalMemory +file= +latency=1 +range=0:134217727 +zero=false +port=system.membus.port[0] + diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.out b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.out new file mode 100644 index 000000000..11cb72660 --- /dev/null +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.out @@ -0,0 +1,178 @@ +[root] +type=Root +dummy=0 + +[system.physmem] +type=PhysicalMemory +file= +range=[0,134217727] +latency=1 +zero=false + +[system] +type=System +physmem=system.physmem +mem_mode=atomic + +[system.membus] +type=Bus +bus_id=0 +clock=1000 +width=64 +responder_set=false + +[system.cpu.workload] +type=LiveProcess +cmd=gzip input.log 1 +executable=/dist/m5/cpu2000/binaries/sparc/linux/gzip +input=cin +output=cout +env= +cwd=build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing +system=system +uid=100 +euid=100 +gid=100 +egid=100 +pid=100 +ppid=99 + +[system.cpu] +type=TimingSimpleCPU +max_insts_any_thread=0 +max_insts_all_threads=0 +max_loads_any_thread=0 +max_loads_all_threads=0 +progress_interval=0 +system=system +cpu_id=0 +workload=system.cpu.workload +clock=1 +phase=0 +defer_registration=false +// width not specified +function_trace=false +function_trace_start=0 +// simulate_stalls not specified + +[system.cpu.toL2Bus] +type=Bus +bus_id=0 +clock=1000 +width=64 +responder_set=false + +[system.cpu.icache] +type=BaseCache +size=131072 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.dcache] +type=BaseCache +size=262144 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.l2cache] +type=BaseCache +size=2097152 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt new file mode 100644 index 000000000..f83fd185e --- /dev/null +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt @@ -0,0 +1,230 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 531377 # Simulator instruction rate (inst/s) +host_mem_usage 154376 # Number of bytes of host memory used +host_seconds 2803.12 # Real time elapsed on the host +host_tick_rate 1212716 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1489514860 # Number of instructions simulated +sim_seconds 0.003399 # Number of seconds simulated +sim_ticks 3399390003 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 402511688 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 2848.782706 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 1848.782706 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 402318208 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 551182478 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.000481 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 193480 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 357702478 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000481 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 193480 # number of ReadReq MSHR misses +system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.SwapReq_avg_miss_latency 3103.285714 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency 2103.285714 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_hits 1319 # number of SwapReq hits +system.cpu.dcache.SwapReq_miss_latency 21723 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_rate 0.005279 # miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_misses 7 # number of SwapReq misses +system.cpu.dcache.SwapReq_mshr_miss_latency 14723 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_rate 0.005279 # mshr miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_mshr_misses 7 # number of SwapReq MSHR misses +system.cpu.dcache.WriteReq_accesses 166846642 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 3023.717816 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2023.717816 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 166586897 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 785395584 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.001557 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 259745 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 525650584 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.001557 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 259745 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 1255.221220 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 569358330 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 2949.038694 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 1949.038694 # average overall mshr miss latency +system.cpu.dcache.demand_hits 568905105 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 1336578062 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.000796 # miss rate for demand accesses +system.cpu.dcache.demand_misses 453225 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 883353062 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.000796 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 453225 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 569358330 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 2949.038694 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 1949.038694 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 568905105 # number of overall hits +system.cpu.dcache.overall_miss_latency 1336578062 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.000796 # miss rate for overall accesses +system.cpu.dcache.overall_misses 453225 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 883353062 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.000796 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 453225 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 449136 # number of replacements +system.cpu.dcache.sampled_refs 453232 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 4068.114109 # Cycle average of tags in use +system.cpu.dcache.total_refs 568906424 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 33495000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 316447 # number of writebacks +system.cpu.icache.ReadReq_accesses 1489514861 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 3979.992714 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 2979.992714 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1489513763 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 4370032 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 1098 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 3272032 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 1098 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_refs 1356569.911658 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 1489514861 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 3979.992714 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 2979.992714 # average overall mshr miss latency +system.cpu.icache.demand_hits 1489513763 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 4370032 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses +system.cpu.icache.demand_misses 1098 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 3272032 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 1098 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 1489514861 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 3979.992714 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 2979.992714 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 1489513763 # number of overall hits +system.cpu.icache.overall_miss_latency 4370032 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses +system.cpu.icache.overall_misses 1098 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 3272032 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 1098 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 115 # number of replacements +system.cpu.icache.sampled_refs 1098 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 865.251814 # Cycle average of tags in use +system.cpu.icache.total_refs 1489513763 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.l2cache.ReadReq_accesses 454330 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 3215.864263 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1941.261615 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 427145 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 87423270 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.059835 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 27185 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 52773197 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.059835 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 27185 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 316447 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 316438 # number of Writeback hits +system.cpu.l2cache.Writeback_miss_rate 0.000028 # miss rate for Writeback accesses +system.cpu.l2cache.Writeback_misses 9 # number of Writeback misses +system.cpu.l2cache.Writeback_mshr_miss_rate 0.000028 # mshr miss rate for Writeback accesses +system.cpu.l2cache.Writeback_mshr_misses 9 # number of Writeback MSHR misses +system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 27.352695 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 454330 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 3215.864263 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1941.261615 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 427145 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 87423270 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.059835 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 27185 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 52773197 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.059835 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 27185 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 770777 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 3214.799956 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1941.261615 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 743583 # number of overall hits +system.cpu.l2cache.overall_miss_latency 87423270 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.035281 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 27194 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 52773197 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.035270 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 27185 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 2632 # number of replacements +system.cpu.l2cache.sampled_refs 27185 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 23773.580402 # Cycle average of tags in use +system.cpu.l2cache.total_refs 743583 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 2531 # number of writebacks +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 3399390003 # number of cpu cycles simulated +system.cpu.num_insts 1489514860 # Number of instructions executed +system.cpu.num_refs 569359656 # Number of memory references +system.cpu.workload.PROG:num_syscalls 19 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stderr b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stderr new file mode 100644 index 000000000..e74a68c71 --- /dev/null +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stderr @@ -0,0 +1,7 @@ +warn: More than two loadable segments in ELF object. +warn: Ignoring segment @ 0xb4000 length 0x10. +warn: More than two loadable segments in ELF object. +warn: Ignoring segment @ 0x0 length 0x0. +0: system.remote_gdb.listener: listening for remote gdb on port 7000 +warn: Entering event queue @ 0. Starting simulation... +warn: Ignoring request to flush register windows. diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout new file mode 100644 index 000000000..8d54e9042 --- /dev/null +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout @@ -0,0 +1,44 @@ +spec_init +Loading Input Data +Duplicating 262144 bytes +Duplicating 524288 bytes +Input data 1048576 bytes in length +Compressing Input Data, level 1 +Compressed data 108074 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 3 +Compressed data 97831 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 5 +Compressed data 83382 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 7 +Compressed data 76606 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 9 +Compressed data 73189 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Tested 1MB buffer: OK! +M5 Simulator System + +Copyright (c) 2001-2006 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Mar 29 2007 03:54:03 +M5 started Thu Mar 29 03:54:23 2007 +M5 executing on zizzer.eecs.umich.edu +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing tests/run.py long/00.gzip/sparc/linux/simple-timing +Global frequency set at 1000000000000 ticks per second +Exiting @ tick 3399390003 because target called exit() diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/mcf.out b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/mcf.out new file mode 100644 index 000000000..6bbb02cf0 --- /dev/null +++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/mcf.out @@ -0,0 +1,3092 @@ +() +1642 +*** +1759 +() +1641 +*** +1691 +() +1640 +() +1639 +() +1638 +() +1637 +() +1636 +() +1635 +() +1634 +() +1633 +() +1632 +() +1631 +() +1630 +() +1629 +() +1628 +() +1627 +() +1626 +() +1625 +*** +1784 +() +1624 +() +1623 +() +1622 +*** +1688 +() +1621 +() +1618 +() +1617 +*** +1796 +() +1616 +() +1615 +*** +1668 +() +1614 +() +1613 +() +1612 +*** +1700 +() +1611 +() +1610 +() +1608 +() +1606 +() +1605 +() +1604 +() +1603 +() +1602 +() +1601 +() +1599 +() +1598 +*** +1714 +() +1597 +() +1595 +() +1591 +() +1590 +*** +1773 +() +1589 +() +1588 +() +1587 +*** +1710 +() +1586 +() +1585 +() +1584 +*** +1748 +() +1583 +*** +1648 +() +1582 +() +1581 +*** +1757 +() +1579 +() +1578 +*** +1726 +() +1575 +*** +1763 +() +1574 +() +1573 +() +1572 +() +1571 +() +1568 +() +1567 +() +1565 +*** +1643 +() +1564 +() +1563 +() +1562 +() +1559 +() +1557 +() +1556 +() +1555 +() +1554 +() +1553 +*** +1684 +() +1552 +() +1551 +*** +1697 +() +1549 +() +1546 +*** +1768 +() +1544 +*** +1798 +() +1542 +() +1541 +*** +1650 +() +1540 +() +1539 +() +1538 +() +1536 +() +1534 +() +1533 +() +1532 +() +1529 +() +1528 +() +1527 +() +1526 +() +1525 +() +1524 +*** +1736 +() +1523 +() +1522 +*** +1794 +() +1521 +() +1519 +() +1517 +*** +1687 +() +1516 +() +1515 +() +1514 +() +1513 +() +1512 +() +1511 +() +1510 +() +1509 +() +1508 +() +1507 +() +1506 +() +1505 +() +1504 +() +1503 +() +1502 +*** +1746 +() +1501 +*** +1766 +() +1498 +() +1497 +() +1495 +() +1494 +() +1493 +*** +1673 +() +1490 +*** +1774 +() +1486 +() +1485 +() +1482 +() +1481 +() +1480 +() +1479 +() +1477 +() +1476 +() +1475 +() +1473 +() +1472 +() +1471 +*** +1728 +() +1470 +() +1469 +() +1467 +() +1466 +() +1465 +() +1464 +() +1463 +() +1462 +() +1461 +() +1460 +() +1459 +() +1455 +() +1454 +*** +1782 +() +1453 +() +1452 +() +1451 +() +1449 +*** +1732 +() +1448 +() +1445 +() +1444 +() +1442 +() +1441 +() +1440 +() +1438 +() +1437 +() +1435 +() +1433 +() +1432 +*** +1665 +() +1431 +() +1426 +() +1425 +() +1424 +() +1423 +() +1420 +*** +1499 +() +1419 +*** +1457 +*** +1653 +() +1418 +*** +1577 +*** +1664 +() +1417 +*** +1489 +() +1416 +*** +1545 +() +1415 +*** +1430 +() +1414 +*** +1434 +() +1413 +*** +1594 +*** +1735 +() +1412 +*** +1560 +*** +1724 +() +1411 +*** +1428 +() +1404 +*** +1496 +*** +1780 +() +1403 +*** +1561 +() +1402 +*** +1548 +() +1401 +*** +1569 +*** +1792 +() +1400 +*** +1537 +() +1399 +*** +1429 +() +1392 +*** +1580 +() +1391 +*** +1410 +() +1390 +*** +1500 +() +1389 +*** +1483 +() +1388 +*** +1570 +() +1387 +*** +1543 +() +1386 +*** +1558 +() +1385 +() +1384 +() +1382 +*** +1439 +() +1381 +*** +1677 +() +1380 +() +1378 +*** +1397 +() +1377 +*** +1787 +() +1376 +*** +1408 +() +1375 +() +1374 +() +1373 +*** +1671 +() +1372 +() +1370 +*** +1793 +() +1369 +() +1365 +*** +1762 +() +1346 +() +1345 +*** +1566 +() +1344 +*** +1520 +() +1343 +*** +1492 +() +1342 +*** +1576 +*** +1656 +() +1341 +*** +1447 +() +1340 +*** +1550 +() +1339 +() +1338 +() +1337 +() +1329 +*** +1336 +() +1328 +*** +1446 +() +1327 +*** +1607 +() +1325 +() +1324 +() +1323 +() +1317 +() +1315 +() +1311 +*** +1450 +*** +1720 +() +1310 +*** +1619 +() +1309 +*** +1458 +() +1308 +() +1307 +*** +1427 +() +1306 +*** +1364 +*** +1696 +() +1299 +() +1297 +*** +1395 +() +1296 +() +1295 +*** +1326 +() +1294 +*** +1371 +() +1293 +*** +1456 +() +1292 +*** +1312 +() +1291 +() +1290 +*** +1363 +() +1282 +*** +1592 +() +1281 +*** +1379 +() +1280 +*** +1478 +() +1279 +*** +1436 +() +1278 +*** +1620 +() +1277 +*** +1487 +() +1276 +*** +1288 +() +1275 +*** +1596 +() +1274 +*** +1322 +() +1273 +*** +1305 +*** +1699 +() +1272 +() +1271 +*** +1484 +() +1270 +*** +1518 +() +1269 +*** +1289 +() +1268 +*** +1443 +*** +1786 +() +1265 +() +1243 +*** +1368 +() +1242 +() +1241 +*** +1421 +*** +1749 +() +1240 +*** +1260 +*** +1678 +() +1239 +() +1238 +() +1236 +*** +1263 +*** +1767 +() +1235 +() +1234 +() +1233 +() +1232 +*** +1752 +() +1231 +*** +1791 +() +1230 +() +1229 +() +1228 +*** +1702 +() +1227 +() +1226 +() +1225 +() +1224 +() +1223 +() +1216 +*** +1531 +() +1215 +*** +1530 +*** +1797 +() +1214 +*** +1474 +*** +1742 +() +1213 +*** +1488 +() +1212 +*** +1298 +*** +1789 +() +1211 +*** +1491 +() +1210 +*** +1600 +() +1209 +*** +1244 +() +1208 +*** +1609 +*** +1704 +() +1207 +*** +1237 +() +1206 +*** +1468 +() +1205 +*** +1547 +() +1204 +*** +1246 +() +1203 +*** +1593 +*** +1734 +() +1202 +*** +1535 +() +1200 +() +1198 +() +1196 +() +1195 +() +1194 +*** +1302 +() +1192 +() +1191 +() +1189 +() +1188 +() +1187 +() +1186 +() +1183 +() +1181 +*** +1778 +() +1179 +() +1178 +() +1177 +*** +1645 +() +1176 +() +1175 +*** +1318 +*** +1649 +() +1173 +() +1172 +() +1171 +() +1169 +*** +1654 +() +1168 +*** +1692 +() +1167 +() +1164 +() +1163 +() +1162 +*** +1716 +() +1160 +() +1159 +*** +1663 +() +1157 +() +1156 +() +1155 +() +1154 +() +1153 +() +1152 +() +1150 +() +1149 +() +1147 +() +1145 +() +1143 +*** +1711 +() +1142 +() +1141 +() +1140 +() +1139 +*** +1755 +() +1138 +() +1137 +*** +1218 +() +1136 +*** +1248 +*** +1670 +() +1135 +() +1134 +() +1133 +*** +1662 +() +1132 +() +1131 +() +1129 +() +1128 +() +1127 +() +1126 +*** +1301 +() +1125 +() +1124 +() +1123 +() +1122 +() +1120 +*** +1332 +() +1119 +*** +1737 +() +1118 +*** +1718 +() +1117 +*** +1250 +*** +1658 +() +1116 +() +1114 +() +1113 +() +1112 +() +1111 +*** +1772 +() +1110 +*** +1359 +() +1109 +() +1108 +*** +1251 +() +1106 +() +1105 +*** +1771 +() +1104 +() +1102 +() +1101 +() +1100 +() +1099 +*** +1689 +() +1098 +() +1097 +*** +1785 +() +1096 +*** +1685 +() +1095 +() +1094 +() +1093 +() +1092 +() +1091 +() +1090 +() +1089 +() +1088 +() +1087 +() +1086 +() +1085 +() +1084 +*** +1739 +() +1083 +*** +1405 +() +1082 +() +1081 +() +1080 +() +1078 +() +1077 +() +1076 +() +1075 +() +1074 +() +1073 +() +1072 +() +1071 +() +1070 +*** +1707 +() +1069 +*** +1334 +() +1068 +() +1066 +() +1065 +() +1064 +() +1063 +() +1062 +() +1061 +() +1060 +() +1059 +() +1058 +() +1057 +*** +1744 +() +1056 +() +1055 +() +1054 +*** +1335 +() +1052 +*** +1660 +() +1051 +() +1050 +() +1049 +() +1048 +() +1047 +() +1046 +() +1045 +*** +1357 +() +1044 +*** +1659 +() +1043 +() +1041 +() +1040 +() +1039 +() +1038 +() +1037 +() +1036 +() +1035 +() +1034 +() +1033 +*** +1690 +() +1031 +() +1030 +() +1029 +() +1028 +*** +1675 +() +1027 +() +1026 +() +1025 +*** +1257 +() +1024 +() +1023 +() +1022 +() +1021 +() +1020 +() +1019 +*** +1284 +() +1018 +() +1017 +*** +1754 +() +1016 +() +1015 +*** +1247 +() +1014 +() +1013 +() +1012 +*** +1319 +() +1011 +*** +1352 +*** +1651 +() +1010 +() +1009 +*** +1705 +() +1008 +() +1007 +() +1006 +() +1005 +*** +1679 +() +1004 +() +1003 +() +1002 +() +1001 +() +1000 +*** +1731 +() +999 +() +998 +() +996 +() +995 +() +994 +() +993 +() +991 +*** +1799 +() +990 +() +989 +() +987 +() +986 +() +985 +() +984 +() +983 +*** +1745 +() +982 +() +981 +*** +1644 +() +980 +() +979 +() +978 +() +977 +() +976 +() +975 +() +974 +*** +1222 +() +973 +() +972 +() +971 +() +970 +() +968 +() +967 +() +966 +() +965 +*** +1347 +() +964 +() +963 +() +962 +*** +1743 +() +961 +*** +1719 +() +960 +*** +1758 +() +959 +() +958 +*** +1733 +() +957 +*** +1775 +() +956 +() +955 +() +954 +() +953 +() +952 +*** +1393 +() +951 +() +950 +() +949 +*** +1669 +() +948 +() +947 +() +946 +*** +1681 +() +944 +*** +1686 +() +943 +() +942 +() +940 +*** +1783 +() +939 +() +938 +() +937 +() +936 +() +934 +() +933 +() +932 +() +931 +() +930 +() +929 +*** +1713 +() +928 +*** +1725 +() +927 +() +926 +() +925 +() +924 +() +923 +() +922 +() +921 +*** +1394 +() +920 +*** +1741 +() +919 +*** +1708 +() +918 +() +917 +() +916 +*** +1723 +() +915 +() +914 +() +913 +() +912 +() +911 +() +910 +() +909 +*** +1795 +() +908 +() +907 +() +906 +() +905 +() +904 +() +903 +*** +1330 +() +902 +() +901 +() +900 +() +899 +() +898 +() +897 +*** +1790 +() +896 +*** +1652 +() +895 +*** +1761 +() +894 +() +893 +() +892 +() +891 +() +890 +*** +1253 +() +889 +*** +1698 +() +888 +() +887 +() +885 +() +884 +*** +1703 +() +883 +() +882 +() +881 +*** +1747 +() +880 +() +879 +*** +1647 +() +878 +*** +1358 +() +877 +*** +1407 +() +876 +() +875 +() +874 +*** +1283 +() +873 +*** +1682 +() +872 +() +871 +() +870 +() +869 +() +868 +() +867 +*** +1751 +() +866 +() +865 +() +864 +() +863 +() +862 +*** +1753 +() +861 +() +860 +() +859 +() +858 +*** +1348 +() +857 +() +856 +*** +1350 +() +855 +*** +1252 +() +854 +() +853 +*** +1201 +() +852 +() +851 +() +850 +*** +1361 +() +849 +() +848 +() +847 +() +846 +() +845 +() +844 +() +843 +() +842 +() +841 +() +840 +() +839 +*** +1360 +() +838 +() +837 +() +836 +() +835 +() +834 +() +833 +*** +1406 +() +832 +() +831 +() +830 +() +829 +() +827 +() +826 +() +825 +() +824 +() +823 +() +822 +() +821 +*** +1683 +() +820 +*** +1672 +() +819 +() +818 +*** +1693 +() +816 +() +815 +*** +1313 +() +814 +() +813 +() +812 +*** +1727 +() +811 +() +810 +() +809 +() +808 +() +806 +() +805 +*** +1217 +() +804 +() +803 +() +802 +() +801 +() +800 +() +799 +() +798 +() +797 +*** +1220 +() +796 +*** +1788 +() +795 +() +794 +*** +1255 +*** +1674 +() +793 +*** +1740 +() +792 +() +791 +*** +1349 +() +790 +() +789 +() +788 +() +787 +*** +1800 +() +786 +() +785 +() +784 +() +783 +() +782 +() +781 +() +780 +() +779 +() +778 +() +777 +() +776 +() +775 +() +774 +*** +1331 +() +773 +() +772 +*** +1256 +() +771 +() +770 +() +769 +() +768 +() +767 +() +766 +() +765 +() +764 +() +763 +() +762 +() +761 +() +759 +() +758 +*** +1655 +() +757 +() +756 +() +755 +*** +1760 +() +754 +() +753 +() +752 +() +751 +*** +1285 +*** +1680 +() +750 +*** +1261 +() +749 +() +748 +() +747 +() +746 +() +745 +*** +1362 +() +744 +() +743 +() +742 +() +741 +() +740 +() +739 +() +738 +() +737 +() +736 +*** +1729 +() +735 +*** +1769 +() +734 +() +733 +() +732 +*** +1715 +() +731 +() +730 +() +729 +() +728 +() +727 +*** +1721 +() +726 +() +725 +() +724 +() +723 +() +722 +() +721 +() +720 +() +719 +*** +1770 +() +718 +() +717 +() +716 +() +715 +() +714 +() +713 +() +712 +() +711 +*** +1779 +() +710 +*** +1221 +() +709 +() +708 +() +707 +() +706 +() +705 +*** +1661 +() +704 +() +703 +() +702 +() +701 +*** +1722 +() +700 +() +699 +() +698 +() +697 +() +696 +() +695 +() +694 +() +693 +() +692 +*** +1776 +() +690 +*** +1254 +() +689 +*** +1738 +() +688 +() +687 +() +686 +*** +1287 +() +685 +() +684 +() +683 +() +682 +() +681 +*** +1666 +() +680 +() +679 +() +678 +() +677 +() +676 +() +675 +() +674 +*** +1695 +() +673 +*** +1709 +() +672 +() +671 +() +670 +() +669 +() +667 +() +666 +() +665 +() +664 +() +663 +() +662 +() +661 +*** +1730 +() +660 +() +659 +() +658 +() +657 +() +656 +() +655 +() +654 +() +653 +() +652 +() +651 +() +650 +() +649 +() +648 +() +647 +() +594 +610 +622 +() +588 +() +584 +601 +615 +*** +1266 +() +578 +590 +603 +() +574 +592 +607 +*** +1646 +() +568 +() +564 +582 +598 +() +558 +570 +*** +1351 +*** +1712 +() +554 +572 +() +547 +560 +580 +() +543 +562 +() +536 +549 +() +533 +551 +*** +1356 +() +527 +539 +() +524 +541 +() +518 +530 +() +514 +531 +() +508 +521 +*** +1657 +() +503 +523 +() +498 +*** +1383 +() +493 +512 +*** +1422 +() +487 +501 +() +484 +515 +*** +1354 +*** +1701 +() +481 +502 +() +475 +490 +511 +() +472 +504 +538 +566 +589 +613 +629 +() +470 +491 +*** +1303 +() +464 +() +461 +494 +526 +556 +579 +605 +623 +639 +() +450 +*** +1355 +() +438 +483 +516 +545 +569 +596 +616 +633 +() +426 +471 +506 +535 +559 +586 +608 +627 +643 +*** +1259 +() +414 +459 +495 +525 +548 +576 +599 +620 +635 +*** +1765 +() +402 +449 +500 +() +401 +446 +482 +*** +1258 +() +391 +418 +434 +455 +() +388 +435 +469 +() +384 +407 +429 +454 +() +378 +406 +447 +467 +() +376 +423 +457 +*** +1316 +() +373 +394 +416 +442 +() +367 +393 +410 +431 +452 +478 +() +366 +413 +465 +513 +550 +585 +617 +638 +() +364 +*** +1146 +*** +1750 +() +363 +411 +445 +() +359 +396 +*** +1396 +*** +1756 +() +357 +381 +405 +430 +458 +479 +*** +1353 +() +351 +368 +() +350 +389 +*** +1103 +() +349 +397 +433 +() +344 +369 +422 +443 +() +338 +354 +380 +398 +419 +441 +466 +() +335 +385 +421 +() +332 +355 +*** +1320 +() +327 +375 +428 +505 +540 +575 +609 +632 +*** +1321 +() +326 +341 +*** +1182 +() +323 +372 +409 +() +319 +342 +() +318 +331 +343 +356 +370 +382 +395 +408 +420 +432 +444 +456 +468 +480 +492 +() +312 +*** +1161 +() +309 +346 +383 +*** +1366 +() +308 +*** +1262 +() +305 +330 +() +299 +315 +*** +1333 +*** +1676 +() +293 +317 +() +289 +296 +334 +371 +*** +1158 +() +286 +302 +329 +() +281 +303 +*** +1219 +() +280 +292 +304 +316 +*** +1264 +() +275 +290 +() +270 +291 +() +265 +278 +*** +1184 +() +260 +279 +() +255 +268 +*** +1367 +() +250 +269 +*** +1165 +() +245 +*** +1115 +() +240 +259 +*** +1067 +() +235 +248 +*** +1199 +*** +1717 +() +230 +249 +() +225 +238 +*** +1197 +() +220 +239 +() +215 +*** +935 +() +210 +229 +258 +*** +1193 +() +205 +*** +988 +() +200 +219 +() +195 +*** +1166 +*** +1667 +() +190 +209 +*** +1079 +*** +1249 +() +185 +198 +*** +1180 +() +131 +161 +192 +221 +252 +282 +320 +() +118 +151 +182 +211 +242 +271 +306 +*** +1398 +() +112 +127 +140 +*** +1148 +() +105 +141 +172 +201 +232 +261 +294 +() +103 +*** +1144 +() +92 +130 +162 +191 +222 +251 +283 +321 +358 +() +91 +*** +886 +() +80 +136 +174 +216 +254 +301 +348 +404 +473 +520 +555 +591 +619 +() +79 +117 +152 +181 +212 +241 +272 +307 +345 +*** +1267 +() +78 +116 +*** +1042 +*** +1764 +() +74 +87 +100 +114 +126 +() +73 +95 +111 +128 +149 +165 +178 +*** +997 +() +70 +119 +166 +204 +246 +285 +339 +386 +439 +485 +532 +557 +583 +606 +625 +640 +646 +() +66 +104 +142 +171 +202 +231 +262 +295 +333 +*** +1286 +() +62 +86 +108 +124 +139 +159 +175 +188 +*** +1130 +() +61 +72 +88 +113 +134 +148 +160 +179 +208 +228 +*** +1245 +() +57 +106 +157 +193 +236 +273 +328 +374 +427 +474 +519 +552 +() +56 +*** +969 +() +55 +109 +153 +197 +233 +277 +325 +377 +424 +476 +517 +553 +577 +602 +621 +637 +645 +() +54 +110 +154 +196 +234 +276 +324 +379 +425 +477 +522 +561 +595 +624 +642 +() +53 +90 +129 +*** +1190 +() +52 +*** +941 +() +50 +59 +75 +99 +121 +137 +150 +169 +*** +945 +*** +1706 +() +49 +69 +85 +101 +125 +145 +158 +170 +189 +218 +*** +992 +*** +1781 +() +48 +68 +122 +163 +207 +244 +288 +336 +390 +436 +489 +529 +() +45 +96 +143 +187 +223 +267 +310 +360 +*** +1409 +() +41 +60 +82 +98 +115 +138 +155 +168 +180 +199 +() +39 +67 +123 +164 +206 +243 +287 +337 +392 +437 +488 +534 +571 +604 +630 +() +36 +43 +*** +1170 +() +26 +*** +1107 +() +24 +40 +*** +817 +() +20 +46 +97 +144 +186 +224 +266 +311 +365 +412 +463 +507 +542 +567 +593 +614 +631 +() +19 +33 +*** +1185 +*** +1694 +() +18 +44 +94 +146 +184 +226 +263 +314 +361 +415 +460 +509 +546 +573 +597 +618 +634 +644 +() +17 +31 +65 +102 +*** +807 +() +16 +34 +84 +133 +177 +213 +256 +298 +352 +400 +453 +496 +() +14 +37 +81 +135 +173 +217 +253 +300 +347 +403 +448 +499 +537 +563 +587 +611 +628 +641 +() +13 +22 +42 +*** +691 +() +12 +47 +93 +147 +183 +227 +264 +313 +362 +417 +462 +510 +544 +581 +612 +636 +() +11 +29 +*** +760 +() +10 +30 +63 +*** +1121 +() +9 +35 +83 +132 +176 +214 +257 +297 +353 +399 +451 +497 +*** +1304 +() +8 +25 +64 +*** +828 +() +7 +23 +51 +89 +*** +1174 +*** +1300 +() +6 +28 +71 +120 +167 +203 +247 +284 +340 +387 +440 +486 +528 +565 +600 +626 +() +5 +*** +668 +() +4 +32 +77 +*** +1032 +() +3 +15 +38 +76 +*** +1314 +() +2 +27 +*** +1053 +() +1 +21 +58 +107 +156 +194 +237 +274 +322 +*** +1151 +*** +1777 diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini new file mode 100644 index 000000000..dfb81664a --- /dev/null +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini @@ -0,0 +1,187 @@ +[root] +type=Root +children=system +dummy=0 + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=TimingSimpleCPU +children=dcache icache l2cache toL2Bus workload +clock=1 +cpu_id=0 +defer_registration=false +function_trace=false +function_trace_start=0 +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +phase=0 +progress_interval=0 +system=system +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=262144 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.port[1] + +[system.cpu.icache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=131072 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.port[0] + +[system.cpu.l2cache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=2097152 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.port[2] +mem_side=system.membus.port[1] + +[system.cpu.toL2Bus] +type=Bus +bus_id=0 +clock=1000 +responder_set=false +width=64 +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side + +[system.cpu.workload] +type=LiveProcess +cmd=mcf mcf.in +cwd=build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing +egid=100 +env= +euid=100 +executable=/dist/m5/cpu2000/binaries/sparc/linux/mcf +gid=100 +input=/dist/m5/cpu2000/data/mcf/lgred/input/mcf.in +output=cout +pid=100 +ppid=99 +system=system +uid=100 + +[system.membus] +type=Bus +bus_id=0 +clock=1000 +responder_set=false +width=64 +port=system.physmem.port system.cpu.l2cache.mem_side + +[system.physmem] +type=PhysicalMemory +file= +latency=1 +range=0:134217727 +zero=false +port=system.membus.port[0] + diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.out b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.out new file mode 100644 index 000000000..e5ed0b288 --- /dev/null +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.out @@ -0,0 +1,178 @@ +[root] +type=Root +dummy=0 + +[system.physmem] +type=PhysicalMemory +file= +range=[0,134217727] +latency=1 +zero=false + +[system] +type=System +physmem=system.physmem +mem_mode=atomic + +[system.membus] +type=Bus +bus_id=0 +clock=1000 +width=64 +responder_set=false + +[system.cpu.workload] +type=LiveProcess +cmd=mcf mcf.in +executable=/dist/m5/cpu2000/binaries/sparc/linux/mcf +input=/dist/m5/cpu2000/data/mcf/lgred/input/mcf.in +output=cout +env= +cwd=build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing +system=system +uid=100 +euid=100 +gid=100 +egid=100 +pid=100 +ppid=99 + +[system.cpu] +type=TimingSimpleCPU +max_insts_any_thread=0 +max_insts_all_threads=0 +max_loads_any_thread=0 +max_loads_all_threads=0 +progress_interval=0 +system=system +cpu_id=0 +workload=system.cpu.workload +clock=1 +phase=0 +defer_registration=false +// width not specified +function_trace=false +function_trace_start=0 +// simulate_stalls not specified + +[system.cpu.toL2Bus] +type=Bus +bus_id=0 +clock=1000 +width=64 +responder_set=false + +[system.cpu.icache] +type=BaseCache +size=131072 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.dcache] +type=BaseCache +size=262144 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.l2cache] +type=BaseCache +size=2097152 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt new file mode 100644 index 000000000..b11288b2d --- /dev/null +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt @@ -0,0 +1,230 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 446147 # Simulator instruction rate (inst/s) +host_mem_usage 154148 # Number of bytes of host memory used +host_seconds 3854.32 # Real time elapsed on the host +host_tick_rate 13681801 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1719594534 # Number of instructions simulated +sim_seconds 0.052734 # Number of seconds simulated +sim_ticks 52734070003 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 607807189 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 3420.154300 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2420.154300 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 594739458 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 44693656366 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.021500 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 13067731 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 31625925366 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.021500 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 13067731 # number of ReadReq MSHR misses +system.cpu.dcache.SwapReq_accesses 15448 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.SwapReq_avg_miss_latency 3631.818182 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency 2631.818182 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_hits 15437 # number of SwapReq hits +system.cpu.dcache.SwapReq_miss_latency 39950 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_rate 0.000712 # miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_misses 11 # number of SwapReq misses +system.cpu.dcache.SwapReq_mshr_miss_latency 28950 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_rate 0.000712 # mshr miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_mshr_misses 11 # number of SwapReq MSHR misses +system.cpu.dcache.WriteReq_accesses 166970997 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 3255.499606 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2255.499606 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 165264000 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 5557128061 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.010223 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 1706997 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 3850131061 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.010223 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 1706997 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 51.440428 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 774778186 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 3401.130933 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 2401.130933 # average overall mshr miss latency +system.cpu.dcache.demand_hits 760003458 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 50250784427 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.019070 # miss rate for demand accesses +system.cpu.dcache.demand_misses 14774728 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 35476056427 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.019070 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 14774728 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 774778186 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 3401.130933 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 2401.130933 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 760003458 # number of overall hits +system.cpu.dcache.overall_miss_latency 50250784427 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.019070 # miss rate for overall accesses +system.cpu.dcache.overall_misses 14774728 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 35476056427 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.019070 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 14774728 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 14770643 # number of replacements +system.cpu.dcache.sampled_refs 14774739 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 4094.978951 # Cycle average of tags in use +system.cpu.dcache.total_refs 760018895 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 35437000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 4191356 # number of writebacks +system.cpu.icache.ReadReq_accesses 1719594535 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 4032.295228 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 3032.295228 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1719593634 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 3633098 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 901 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 2732098 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 901 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_refs 1908538.994451 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 1719594535 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 4032.295228 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 3032.295228 # average overall mshr miss latency +system.cpu.icache.demand_hits 1719593634 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 3633098 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses +system.cpu.icache.demand_misses 901 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 2732098 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 901 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 1719594535 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 4032.295228 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 3032.295228 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 1719593634 # number of overall hits +system.cpu.icache.overall_miss_latency 3633098 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses +system.cpu.icache.overall_misses 901 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 2732098 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 901 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 31 # number of replacements +system.cpu.icache.sampled_refs 901 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 750.163929 # Cycle average of tags in use +system.cpu.icache.total_refs 1719593634 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.l2cache.ReadReq_accesses 14775639 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 3097.556051 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1926.730191 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 8592784 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 19151739918 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.418449 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 6182855 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 11912693395 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.418449 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 6182855 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 4191356 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 4164131 # number of Writeback hits +system.cpu.l2cache.Writeback_miss_rate 0.006496 # miss rate for Writeback accesses +system.cpu.l2cache.Writeback_misses 27225 # number of Writeback misses +system.cpu.l2cache.Writeback_mshr_miss_rate 0.006496 # mshr miss rate for Writeback accesses +system.cpu.l2cache.Writeback_mshr_misses 27225 # number of Writeback MSHR misses +system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 2.063273 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 14775639 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 3097.556051 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1926.730191 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 8592784 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 19151739918 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.418449 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 6182855 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 11912693395 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.418449 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 6182855 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 18966995 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 3083.976361 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1926.730191 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 12756915 # number of overall hits +system.cpu.l2cache.overall_miss_latency 19151739918 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.327415 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 6210080 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 11912693395 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.325980 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 6182855 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 6150087 # number of replacements +system.cpu.l2cache.sampled_refs 6182855 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 27594.660688 # Cycle average of tags in use +system.cpu.l2cache.total_refs 12756915 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 12316534000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 1069081 # number of writebacks +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 52734070003 # number of cpu cycles simulated +system.cpu.num_insts 1719594534 # Number of instructions executed +system.cpu.num_refs 774793634 # Number of memory references +system.cpu.workload.PROG:num_syscalls 632 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/mcf.out b/tests/long/10.mcf/ref/sparc/linux/simple-timing/mcf.out new file mode 100644 index 000000000..6bbb02cf0 --- /dev/null +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/mcf.out @@ -0,0 +1,3092 @@ +() +1642 +*** +1759 +() +1641 +*** +1691 +() +1640 +() +1639 +() +1638 +() +1637 +() +1636 +() +1635 +() +1634 +() +1633 +() +1632 +() +1631 +() +1630 +() +1629 +() +1628 +() +1627 +() +1626 +() +1625 +*** +1784 +() +1624 +() +1623 +() +1622 +*** +1688 +() +1621 +() +1618 +() +1617 +*** +1796 +() +1616 +() +1615 +*** +1668 +() +1614 +() +1613 +() +1612 +*** +1700 +() +1611 +() +1610 +() +1608 +() +1606 +() +1605 +() +1604 +() +1603 +() +1602 +() +1601 +() +1599 +() +1598 +*** +1714 +() +1597 +() +1595 +() +1591 +() +1590 +*** +1773 +() +1589 +() +1588 +() +1587 +*** +1710 +() +1586 +() +1585 +() +1584 +*** +1748 +() +1583 +*** +1648 +() +1582 +() +1581 +*** +1757 +() +1579 +() +1578 +*** +1726 +() +1575 +*** +1763 +() +1574 +() +1573 +() +1572 +() +1571 +() +1568 +() +1567 +() +1565 +*** +1643 +() +1564 +() +1563 +() +1562 +() +1559 +() +1557 +() +1556 +() +1555 +() +1554 +() +1553 +*** +1684 +() +1552 +() +1551 +*** +1697 +() +1549 +() +1546 +*** +1768 +() +1544 +*** +1798 +() +1542 +() +1541 +*** +1650 +() +1540 +() +1539 +() +1538 +() +1536 +() +1534 +() +1533 +() +1532 +() +1529 +() +1528 +() +1527 +() +1526 +() +1525 +() +1524 +*** +1736 +() +1523 +() +1522 +*** +1794 +() +1521 +() +1519 +() +1517 +*** +1687 +() +1516 +() +1515 +() +1514 +() +1513 +() +1512 +() +1511 +() +1510 +() +1509 +() +1508 +() +1507 +() +1506 +() +1505 +() +1504 +() +1503 +() +1502 +*** +1746 +() +1501 +*** +1766 +() +1498 +() +1497 +() +1495 +() +1494 +() +1493 +*** +1673 +() +1490 +*** +1774 +() +1486 +() +1485 +() +1482 +() +1481 +() +1480 +() +1479 +() +1477 +() +1476 +() +1475 +() +1473 +() +1472 +() +1471 +*** +1728 +() +1470 +() +1469 +() +1467 +() +1466 +() +1465 +() +1464 +() +1463 +() +1462 +() +1461 +() +1460 +() +1459 +() +1455 +() +1454 +*** +1782 +() +1453 +() +1452 +() +1451 +() +1449 +*** +1732 +() +1448 +() +1445 +() +1444 +() +1442 +() +1441 +() +1440 +() +1438 +() +1437 +() +1435 +() +1433 +() +1432 +*** +1665 +() +1431 +() +1426 +() +1425 +() +1424 +() +1423 +() +1420 +*** +1499 +() +1419 +*** +1457 +*** +1653 +() +1418 +*** +1577 +*** +1664 +() +1417 +*** +1489 +() +1416 +*** +1545 +() +1415 +*** +1430 +() +1414 +*** +1434 +() +1413 +*** +1594 +*** +1735 +() +1412 +*** +1560 +*** +1724 +() +1411 +*** +1428 +() +1404 +*** +1496 +*** +1780 +() +1403 +*** +1561 +() +1402 +*** +1548 +() +1401 +*** +1569 +*** +1792 +() +1400 +*** +1537 +() +1399 +*** +1429 +() +1392 +*** +1580 +() +1391 +*** +1410 +() +1390 +*** +1500 +() +1389 +*** +1483 +() +1388 +*** +1570 +() +1387 +*** +1543 +() +1386 +*** +1558 +() +1385 +() +1384 +() +1382 +*** +1439 +() +1381 +*** +1677 +() +1380 +() +1378 +*** +1397 +() +1377 +*** +1787 +() +1376 +*** +1408 +() +1375 +() +1374 +() +1373 +*** +1671 +() +1372 +() +1370 +*** +1793 +() +1369 +() +1365 +*** +1762 +() +1346 +() +1345 +*** +1566 +() +1344 +*** +1520 +() +1343 +*** +1492 +() +1342 +*** +1576 +*** +1656 +() +1341 +*** +1447 +() +1340 +*** +1550 +() +1339 +() +1338 +() +1337 +() +1329 +*** +1336 +() +1328 +*** +1446 +() +1327 +*** +1607 +() +1325 +() +1324 +() +1323 +() +1317 +() +1315 +() +1311 +*** +1450 +*** +1720 +() +1310 +*** +1619 +() +1309 +*** +1458 +() +1308 +() +1307 +*** +1427 +() +1306 +*** +1364 +*** +1696 +() +1299 +() +1297 +*** +1395 +() +1296 +() +1295 +*** +1326 +() +1294 +*** +1371 +() +1293 +*** +1456 +() +1292 +*** +1312 +() +1291 +() +1290 +*** +1363 +() +1282 +*** +1592 +() +1281 +*** +1379 +() +1280 +*** +1478 +() +1279 +*** +1436 +() +1278 +*** +1620 +() +1277 +*** +1487 +() +1276 +*** +1288 +() +1275 +*** +1596 +() +1274 +*** +1322 +() +1273 +*** +1305 +*** +1699 +() +1272 +() +1271 +*** +1484 +() +1270 +*** +1518 +() +1269 +*** +1289 +() +1268 +*** +1443 +*** +1786 +() +1265 +() +1243 +*** +1368 +() +1242 +() +1241 +*** +1421 +*** +1749 +() +1240 +*** +1260 +*** +1678 +() +1239 +() +1238 +() +1236 +*** +1263 +*** +1767 +() +1235 +() +1234 +() +1233 +() +1232 +*** +1752 +() +1231 +*** +1791 +() +1230 +() +1229 +() +1228 +*** +1702 +() +1227 +() +1226 +() +1225 +() +1224 +() +1223 +() +1216 +*** +1531 +() +1215 +*** +1530 +*** +1797 +() +1214 +*** +1474 +*** +1742 +() +1213 +*** +1488 +() +1212 +*** +1298 +*** +1789 +() +1211 +*** +1491 +() +1210 +*** +1600 +() +1209 +*** +1244 +() +1208 +*** +1609 +*** +1704 +() +1207 +*** +1237 +() +1206 +*** +1468 +() +1205 +*** +1547 +() +1204 +*** +1246 +() +1203 +*** +1593 +*** +1734 +() +1202 +*** +1535 +() +1200 +() +1198 +() +1196 +() +1195 +() +1194 +*** +1302 +() +1192 +() +1191 +() +1189 +() +1188 +() +1187 +() +1186 +() +1183 +() +1181 +*** +1778 +() +1179 +() +1178 +() +1177 +*** +1645 +() +1176 +() +1175 +*** +1318 +*** +1649 +() +1173 +() +1172 +() +1171 +() +1169 +*** +1654 +() +1168 +*** +1692 +() +1167 +() +1164 +() +1163 +() +1162 +*** +1716 +() +1160 +() +1159 +*** +1663 +() +1157 +() +1156 +() +1155 +() +1154 +() +1153 +() +1152 +() +1150 +() +1149 +() +1147 +() +1145 +() +1143 +*** +1711 +() +1142 +() +1141 +() +1140 +() +1139 +*** +1755 +() +1138 +() +1137 +*** +1218 +() +1136 +*** +1248 +*** +1670 +() +1135 +() +1134 +() +1133 +*** +1662 +() +1132 +() +1131 +() +1129 +() +1128 +() +1127 +() +1126 +*** +1301 +() +1125 +() +1124 +() +1123 +() +1122 +() +1120 +*** +1332 +() +1119 +*** +1737 +() +1118 +*** +1718 +() +1117 +*** +1250 +*** +1658 +() +1116 +() +1114 +() +1113 +() +1112 +() +1111 +*** +1772 +() +1110 +*** +1359 +() +1109 +() +1108 +*** +1251 +() +1106 +() +1105 +*** +1771 +() +1104 +() +1102 +() +1101 +() +1100 +() +1099 +*** +1689 +() +1098 +() +1097 +*** +1785 +() +1096 +*** +1685 +() +1095 +() +1094 +() +1093 +() +1092 +() +1091 +() +1090 +() +1089 +() +1088 +() +1087 +() +1086 +() +1085 +() +1084 +*** +1739 +() +1083 +*** +1405 +() +1082 +() +1081 +() +1080 +() +1078 +() +1077 +() +1076 +() +1075 +() +1074 +() +1073 +() +1072 +() +1071 +() +1070 +*** +1707 +() +1069 +*** +1334 +() +1068 +() +1066 +() +1065 +() +1064 +() +1063 +() +1062 +() +1061 +() +1060 +() +1059 +() +1058 +() +1057 +*** +1744 +() +1056 +() +1055 +() +1054 +*** +1335 +() +1052 +*** +1660 +() +1051 +() +1050 +() +1049 +() +1048 +() +1047 +() +1046 +() +1045 +*** +1357 +() +1044 +*** +1659 +() +1043 +() +1041 +() +1040 +() +1039 +() +1038 +() +1037 +() +1036 +() +1035 +() +1034 +() +1033 +*** +1690 +() +1031 +() +1030 +() +1029 +() +1028 +*** +1675 +() +1027 +() +1026 +() +1025 +*** +1257 +() +1024 +() +1023 +() +1022 +() +1021 +() +1020 +() +1019 +*** +1284 +() +1018 +() +1017 +*** +1754 +() +1016 +() +1015 +*** +1247 +() +1014 +() +1013 +() +1012 +*** +1319 +() +1011 +*** +1352 +*** +1651 +() +1010 +() +1009 +*** +1705 +() +1008 +() +1007 +() +1006 +() +1005 +*** +1679 +() +1004 +() +1003 +() +1002 +() +1001 +() +1000 +*** +1731 +() +999 +() +998 +() +996 +() +995 +() +994 +() +993 +() +991 +*** +1799 +() +990 +() +989 +() +987 +() +986 +() +985 +() +984 +() +983 +*** +1745 +() +982 +() +981 +*** +1644 +() +980 +() +979 +() +978 +() +977 +() +976 +() +975 +() +974 +*** +1222 +() +973 +() +972 +() +971 +() +970 +() +968 +() +967 +() +966 +() +965 +*** +1347 +() +964 +() +963 +() +962 +*** +1743 +() +961 +*** +1719 +() +960 +*** +1758 +() +959 +() +958 +*** +1733 +() +957 +*** +1775 +() +956 +() +955 +() +954 +() +953 +() +952 +*** +1393 +() +951 +() +950 +() +949 +*** +1669 +() +948 +() +947 +() +946 +*** +1681 +() +944 +*** +1686 +() +943 +() +942 +() +940 +*** +1783 +() +939 +() +938 +() +937 +() +936 +() +934 +() +933 +() +932 +() +931 +() +930 +() +929 +*** +1713 +() +928 +*** +1725 +() +927 +() +926 +() +925 +() +924 +() +923 +() +922 +() +921 +*** +1394 +() +920 +*** +1741 +() +919 +*** +1708 +() +918 +() +917 +() +916 +*** +1723 +() +915 +() +914 +() +913 +() +912 +() +911 +() +910 +() +909 +*** +1795 +() +908 +() +907 +() +906 +() +905 +() +904 +() +903 +*** +1330 +() +902 +() +901 +() +900 +() +899 +() +898 +() +897 +*** +1790 +() +896 +*** +1652 +() +895 +*** +1761 +() +894 +() +893 +() +892 +() +891 +() +890 +*** +1253 +() +889 +*** +1698 +() +888 +() +887 +() +885 +() +884 +*** +1703 +() +883 +() +882 +() +881 +*** +1747 +() +880 +() +879 +*** +1647 +() +878 +*** +1358 +() +877 +*** +1407 +() +876 +() +875 +() +874 +*** +1283 +() +873 +*** +1682 +() +872 +() +871 +() +870 +() +869 +() +868 +() +867 +*** +1751 +() +866 +() +865 +() +864 +() +863 +() +862 +*** +1753 +() +861 +() +860 +() +859 +() +858 +*** +1348 +() +857 +() +856 +*** +1350 +() +855 +*** +1252 +() +854 +() +853 +*** +1201 +() +852 +() +851 +() +850 +*** +1361 +() +849 +() +848 +() +847 +() +846 +() +845 +() +844 +() +843 +() +842 +() +841 +() +840 +() +839 +*** +1360 +() +838 +() +837 +() +836 +() +835 +() +834 +() +833 +*** +1406 +() +832 +() +831 +() +830 +() +829 +() +827 +() +826 +() +825 +() +824 +() +823 +() +822 +() +821 +*** +1683 +() +820 +*** +1672 +() +819 +() +818 +*** +1693 +() +816 +() +815 +*** +1313 +() +814 +() +813 +() +812 +*** +1727 +() +811 +() +810 +() +809 +() +808 +() +806 +() +805 +*** +1217 +() +804 +() +803 +() +802 +() +801 +() +800 +() +799 +() +798 +() +797 +*** +1220 +() +796 +*** +1788 +() +795 +() +794 +*** +1255 +*** +1674 +() +793 +*** +1740 +() +792 +() +791 +*** +1349 +() +790 +() +789 +() +788 +() +787 +*** +1800 +() +786 +() +785 +() +784 +() +783 +() +782 +() +781 +() +780 +() +779 +() +778 +() +777 +() +776 +() +775 +() +774 +*** +1331 +() +773 +() +772 +*** +1256 +() +771 +() +770 +() +769 +() +768 +() +767 +() +766 +() +765 +() +764 +() +763 +() +762 +() +761 +() +759 +() +758 +*** +1655 +() +757 +() +756 +() +755 +*** +1760 +() +754 +() +753 +() +752 +() +751 +*** +1285 +*** +1680 +() +750 +*** +1261 +() +749 +() +748 +() +747 +() +746 +() +745 +*** +1362 +() +744 +() +743 +() +742 +() +741 +() +740 +() +739 +() +738 +() +737 +() +736 +*** +1729 +() +735 +*** +1769 +() +734 +() +733 +() +732 +*** +1715 +() +731 +() +730 +() +729 +() +728 +() +727 +*** +1721 +() +726 +() +725 +() +724 +() +723 +() +722 +() +721 +() +720 +() +719 +*** +1770 +() +718 +() +717 +() +716 +() +715 +() +714 +() +713 +() +712 +() +711 +*** +1779 +() +710 +*** +1221 +() +709 +() +708 +() +707 +() +706 +() +705 +*** +1661 +() +704 +() +703 +() +702 +() +701 +*** +1722 +() +700 +() +699 +() +698 +() +697 +() +696 +() +695 +() +694 +() +693 +() +692 +*** +1776 +() +690 +*** +1254 +() +689 +*** +1738 +() +688 +() +687 +() +686 +*** +1287 +() +685 +() +684 +() +683 +() +682 +() +681 +*** +1666 +() +680 +() +679 +() +678 +() +677 +() +676 +() +675 +() +674 +*** +1695 +() +673 +*** +1709 +() +672 +() +671 +() +670 +() +669 +() +667 +() +666 +() +665 +() +664 +() +663 +() +662 +() +661 +*** +1730 +() +660 +() +659 +() +658 +() +657 +() +656 +() +655 +() +654 +() +653 +() +652 +() +651 +() +650 +() +649 +() +648 +() +647 +() +594 +610 +622 +() +588 +() +584 +601 +615 +*** +1266 +() +578 +590 +603 +() +574 +592 +607 +*** +1646 +() +568 +() +564 +582 +598 +() +558 +570 +*** +1351 +*** +1712 +() +554 +572 +() +547 +560 +580 +() +543 +562 +() +536 +549 +() +533 +551 +*** +1356 +() +527 +539 +() +524 +541 +() +518 +530 +() +514 +531 +() +508 +521 +*** +1657 +() +503 +523 +() +498 +*** +1383 +() +493 +512 +*** +1422 +() +487 +501 +() +484 +515 +*** +1354 +*** +1701 +() +481 +502 +() +475 +490 +511 +() +472 +504 +538 +566 +589 +613 +629 +() +470 +491 +*** +1303 +() +464 +() +461 +494 +526 +556 +579 +605 +623 +639 +() +450 +*** +1355 +() +438 +483 +516 +545 +569 +596 +616 +633 +() +426 +471 +506 +535 +559 +586 +608 +627 +643 +*** +1259 +() +414 +459 +495 +525 +548 +576 +599 +620 +635 +*** +1765 +() +402 +449 +500 +() +401 +446 +482 +*** +1258 +() +391 +418 +434 +455 +() +388 +435 +469 +() +384 +407 +429 +454 +() +378 +406 +447 +467 +() +376 +423 +457 +*** +1316 +() +373 +394 +416 +442 +() +367 +393 +410 +431 +452 +478 +() +366 +413 +465 +513 +550 +585 +617 +638 +() +364 +*** +1146 +*** +1750 +() +363 +411 +445 +() +359 +396 +*** +1396 +*** +1756 +() +357 +381 +405 +430 +458 +479 +*** +1353 +() +351 +368 +() +350 +389 +*** +1103 +() +349 +397 +433 +() +344 +369 +422 +443 +() +338 +354 +380 +398 +419 +441 +466 +() +335 +385 +421 +() +332 +355 +*** +1320 +() +327 +375 +428 +505 +540 +575 +609 +632 +*** +1321 +() +326 +341 +*** +1182 +() +323 +372 +409 +() +319 +342 +() +318 +331 +343 +356 +370 +382 +395 +408 +420 +432 +444 +456 +468 +480 +492 +() +312 +*** +1161 +() +309 +346 +383 +*** +1366 +() +308 +*** +1262 +() +305 +330 +() +299 +315 +*** +1333 +*** +1676 +() +293 +317 +() +289 +296 +334 +371 +*** +1158 +() +286 +302 +329 +() +281 +303 +*** +1219 +() +280 +292 +304 +316 +*** +1264 +() +275 +290 +() +270 +291 +() +265 +278 +*** +1184 +() +260 +279 +() +255 +268 +*** +1367 +() +250 +269 +*** +1165 +() +245 +*** +1115 +() +240 +259 +*** +1067 +() +235 +248 +*** +1199 +*** +1717 +() +230 +249 +() +225 +238 +*** +1197 +() +220 +239 +() +215 +*** +935 +() +210 +229 +258 +*** +1193 +() +205 +*** +988 +() +200 +219 +() +195 +*** +1166 +*** +1667 +() +190 +209 +*** +1079 +*** +1249 +() +185 +198 +*** +1180 +() +131 +161 +192 +221 +252 +282 +320 +() +118 +151 +182 +211 +242 +271 +306 +*** +1398 +() +112 +127 +140 +*** +1148 +() +105 +141 +172 +201 +232 +261 +294 +() +103 +*** +1144 +() +92 +130 +162 +191 +222 +251 +283 +321 +358 +() +91 +*** +886 +() +80 +136 +174 +216 +254 +301 +348 +404 +473 +520 +555 +591 +619 +() +79 +117 +152 +181 +212 +241 +272 +307 +345 +*** +1267 +() +78 +116 +*** +1042 +*** +1764 +() +74 +87 +100 +114 +126 +() +73 +95 +111 +128 +149 +165 +178 +*** +997 +() +70 +119 +166 +204 +246 +285 +339 +386 +439 +485 +532 +557 +583 +606 +625 +640 +646 +() +66 +104 +142 +171 +202 +231 +262 +295 +333 +*** +1286 +() +62 +86 +108 +124 +139 +159 +175 +188 +*** +1130 +() +61 +72 +88 +113 +134 +148 +160 +179 +208 +228 +*** +1245 +() +57 +106 +157 +193 +236 +273 +328 +374 +427 +474 +519 +552 +() +56 +*** +969 +() +55 +109 +153 +197 +233 +277 +325 +377 +424 +476 +517 +553 +577 +602 +621 +637 +645 +() +54 +110 +154 +196 +234 +276 +324 +379 +425 +477 +522 +561 +595 +624 +642 +() +53 +90 +129 +*** +1190 +() +52 +*** +941 +() +50 +59 +75 +99 +121 +137 +150 +169 +*** +945 +*** +1706 +() +49 +69 +85 +101 +125 +145 +158 +170 +189 +218 +*** +992 +*** +1781 +() +48 +68 +122 +163 +207 +244 +288 +336 +390 +436 +489 +529 +() +45 +96 +143 +187 +223 +267 +310 +360 +*** +1409 +() +41 +60 +82 +98 +115 +138 +155 +168 +180 +199 +() +39 +67 +123 +164 +206 +243 +287 +337 +392 +437 +488 +534 +571 +604 +630 +() +36 +43 +*** +1170 +() +26 +*** +1107 +() +24 +40 +*** +817 +() +20 +46 +97 +144 +186 +224 +266 +311 +365 +412 +463 +507 +542 +567 +593 +614 +631 +() +19 +33 +*** +1185 +*** +1694 +() +18 +44 +94 +146 +184 +226 +263 +314 +361 +415 +460 +509 +546 +573 +597 +618 +634 +644 +() +17 +31 +65 +102 +*** +807 +() +16 +34 +84 +133 +177 +213 +256 +298 +352 +400 +453 +496 +() +14 +37 +81 +135 +173 +217 +253 +300 +347 +403 +448 +499 +537 +563 +587 +611 +628 +641 +() +13 +22 +42 +*** +691 +() +12 +47 +93 +147 +183 +227 +264 +313 +362 +417 +462 +510 +544 +581 +612 +636 +() +11 +29 +*** +760 +() +10 +30 +63 +*** +1121 +() +9 +35 +83 +132 +176 +214 +257 +297 +353 +399 +451 +497 +*** +1304 +() +8 +25 +64 +*** +828 +() +7 +23 +51 +89 +*** +1174 +*** +1300 +() +6 +28 +71 +120 +167 +203 +247 +284 +340 +387 +440 +486 +528 +565 +600 +626 +() +5 +*** +668 +() +4 +32 +77 +*** +1032 +() +3 +15 +38 +76 +*** +1314 +() +2 +27 +*** +1053 +() +1 +21 +58 +107 +156 +194 +237 +274 +322 +*** +1151 +*** +1777 diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stderr b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stderr new file mode 100644 index 000000000..9c09fd847 --- /dev/null +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stderr @@ -0,0 +1,7 @@ +warn: More than two loadable segments in ELF object. +warn: Ignoring segment @ 0xa2000 length 0x10. +warn: More than two loadable segments in ELF object. +warn: Ignoring segment @ 0x0 length 0x0. +0: system.remote_gdb.listener: listening for remote gdb on port 7000 +warn: Entering event queue @ 0. Starting simulation... +warn: Ignoring request to flush register windows. diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout new file mode 100644 index 000000000..7d97093d4 --- /dev/null +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout @@ -0,0 +1,33 @@ + +MCF SPEC version 1.6.I +by Andreas Loebel +Copyright (c) 1998,1999 ZIB Berlin +All Rights Reserved. + +nodes : 1800 +active arcs : 8190 +simplex iterations : 6837 +flow value : 12860044181 +new implicit arcs : 300000 +active arcs : 308190 +simplex iterations : 11843 +flow value : 9360043604 +new implicit arcs : 22787 +active arcs : 330977 +simplex iterations : 11931 +flow value : 9360043512 +checksum : 798014 +optimal +M5 Simulator System + +Copyright (c) 2001-2006 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Mar 29 2007 15:41:48 +M5 started Thu Mar 29 15:42:11 2007 +M5 executing on zizzer.eecs.umich.edu +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing tests/run.py long/10.mcf/sparc/linux/simple-timing +Global frequency set at 1000000000000 ticks per second +Exiting @ tick 52734070003 because target called exit() diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini new file mode 100644 index 000000000..770dac1b9 --- /dev/null +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini @@ -0,0 +1,187 @@ +[root] +type=Root +children=system +dummy=0 + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=TimingSimpleCPU +children=dcache icache l2cache toL2Bus workload +clock=1 +cpu_id=0 +defer_registration=false +function_trace=false +function_trace_start=0 +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +phase=0 +progress_interval=0 +system=system +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=262144 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.port[1] + +[system.cpu.icache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=131072 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.port[0] + +[system.cpu.l2cache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=2097152 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.port[2] +mem_side=system.membus.port[1] + +[system.cpu.toL2Bus] +type=Bus +bus_id=0 +clock=1000 +responder_set=false +width=64 +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side + +[system.cpu.workload] +type=LiveProcess +cmd=vortex bendian.raw +cwd=build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing +egid=100 +env= +euid=100 +executable=/dist/m5/cpu2000/binaries/sparc/linux/vortex +gid=100 +input=cin +output=cout +pid=100 +ppid=99 +system=system +uid=100 + +[system.membus] +type=Bus +bus_id=0 +clock=1000 +responder_set=false +width=64 +port=system.physmem.port system.cpu.l2cache.mem_side + +[system.physmem] +type=PhysicalMemory +file= +latency=1 +range=0:134217727 +zero=false +port=system.membus.port[0] + diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.out b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.out new file mode 100644 index 000000000..30db17922 --- /dev/null +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.out @@ -0,0 +1,178 @@ +[root] +type=Root +dummy=0 + +[system.physmem] +type=PhysicalMemory +file= +range=[0,134217727] +latency=1 +zero=false + +[system] +type=System +physmem=system.physmem +mem_mode=atomic + +[system.membus] +type=Bus +bus_id=0 +clock=1000 +width=64 +responder_set=false + +[system.cpu.workload] +type=LiveProcess +cmd=vortex bendian.raw +executable=/dist/m5/cpu2000/binaries/sparc/linux/vortex +input=cin +output=cout +env= +cwd=build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing +system=system +uid=100 +euid=100 +gid=100 +egid=100 +pid=100 +ppid=99 + +[system.cpu] +type=TimingSimpleCPU +max_insts_any_thread=0 +max_insts_all_threads=0 +max_loads_any_thread=0 +max_loads_all_threads=0 +progress_interval=0 +system=system +cpu_id=0 +workload=system.cpu.workload +clock=1 +phase=0 +defer_registration=false +// width not specified +function_trace=false +function_trace_start=0 +// simulate_stalls not specified + +[system.cpu.toL2Bus] +type=Bus +bus_id=0 +clock=1000 +width=64 +responder_set=false + +[system.cpu.icache] +type=BaseCache +size=131072 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.dcache] +type=BaseCache +size=262144 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.l2cache] +type=BaseCache +size=2097152 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt new file mode 100644 index 000000000..78f34213e --- /dev/null +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt @@ -0,0 +1,230 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 473146 # Simulator instruction rate (inst/s) +host_mem_usage 156372 # Number of bytes of host memory used +host_seconds 287.96 # Real time elapsed on the host +host_tick_rate 4801122 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 136246936 # Number of instructions simulated +sim_seconds 0.001383 # Number of seconds simulated +sim_ticks 1382530003 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 37231301 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 3575.086285 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2575.086285 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 37185812 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 162627100 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.001222 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 45489 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 117138100 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.001222 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 45489 # number of ReadReq MSHR misses +system.cpu.dcache.SwapReq_accesses 15916 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.SwapReq_avg_miss_latency 3413.933333 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency 2413.933333 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_hits 15901 # number of SwapReq hits +system.cpu.dcache.SwapReq_miss_latency 51209 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_rate 0.000942 # miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_misses 15 # number of SwapReq misses +system.cpu.dcache.SwapReq_mshr_miss_latency 36209 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_rate 0.000942 # mshr miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_mshr_misses 15 # number of SwapReq MSHR misses +system.cpu.dcache.WriteReq_accesses 20864304 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 4579.703729 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3579.703729 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 20759130 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 481665760 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.005041 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 105174 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 376491760 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.005041 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 105174 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 384.666925 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 58095605 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 4276.384116 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 3276.384116 # average overall mshr miss latency +system.cpu.dcache.demand_hits 57944942 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 644292860 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.002593 # miss rate for demand accesses +system.cpu.dcache.demand_misses 150663 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 493629860 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.002593 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 150663 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 58095605 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 4276.384116 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 3276.384116 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 57944942 # number of overall hits +system.cpu.dcache.overall_miss_latency 644292860 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.002593 # miss rate for overall accesses +system.cpu.dcache.overall_misses 150663 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 493629860 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.002593 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 150663 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 146582 # number of replacements +system.cpu.dcache.sampled_refs 150678 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 4060.510189 # Cycle average of tags in use +system.cpu.dcache.total_refs 57960843 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 33018000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 107279 # number of writebacks +system.cpu.icache.ReadReq_accesses 136246937 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 2909.600795 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 1909.600795 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 136059913 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 544165179 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.001373 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 187024 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 357141179 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.001373 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 187024 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_refs 727.499749 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 136246937 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 2909.600795 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 1909.600795 # average overall mshr miss latency +system.cpu.icache.demand_hits 136059913 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 544165179 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.001373 # miss rate for demand accesses +system.cpu.icache.demand_misses 187024 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 357141179 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.001373 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 187024 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 136246937 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 2909.600795 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 1909.600795 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 136059913 # number of overall hits +system.cpu.icache.overall_miss_latency 544165179 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.001373 # miss rate for overall accesses +system.cpu.icache.overall_misses 187024 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 357141179 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.001373 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 187024 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 184976 # number of replacements +system.cpu.icache.sampled_refs 187024 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 1952.728312 # Cycle average of tags in use +system.cpu.icache.total_refs 136059913 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 1000315000 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.l2cache.ReadReq_accesses 337636 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 3564.034868 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1961.482636 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 202957 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 480000652 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.398888 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 134679 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 264170520 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.398888 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 134679 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 107279 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 106771 # number of Writeback hits +system.cpu.l2cache.Writeback_miss_rate 0.004735 # miss rate for Writeback accesses +system.cpu.l2cache.Writeback_misses 508 # number of Writeback misses +system.cpu.l2cache.Writeback_mshr_miss_rate 0.004735 # mshr miss rate for Writeback accesses +system.cpu.l2cache.Writeback_mshr_misses 508 # number of Writeback MSHR misses +system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 2.299750 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 337636 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 3564.034868 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1961.482636 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 202957 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 480000652 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.398888 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 134679 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 264170520 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.398888 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 134679 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 444915 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 3550.642088 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1961.482636 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 309728 # number of overall hits +system.cpu.l2cache.overall_miss_latency 480000652 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.303849 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 135187 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 264170520 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.302707 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 134679 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 101911 # number of replacements +system.cpu.l2cache.sampled_refs 134679 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 30685.350019 # Cycle average of tags in use +system.cpu.l2cache.total_refs 309728 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 319451000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 82918 # number of writebacks +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 1382530003 # number of cpu cycles simulated +system.cpu.num_insts 136246936 # Number of instructions executed +system.cpu.num_refs 58111522 # Number of memory references +system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/smred.msg b/tests/long/50.vortex/ref/sparc/linux/simple-timing/smred.msg new file mode 100644 index 000000000..0ac2d9980 --- /dev/null +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/smred.msg @@ -0,0 +1,158 @@ + + SYSTEM TYPE... + __ZTC__ := False + __UNIX__ := True + __RISC__ := True + SPEC_CPU2000_LP64 := False + __MAC__ := False + __BCC__ := False + __BORLANDC__ := False + __GUI__ := False + __WTC__ := False + __HP__ := False + + CODE OPTIONS... + __MACROIZE_HM__ := True + __MACROIZE_MEM__ := True + ENV01 := True + USE_HPP_STYPE_HDRS := False + USE_H_STYPE_HDRS := False + + CODE INCLUSION PARAMETERS... + INCLUDE_ALL_CODE := False + INCLUDE_DELETE_CODE := True + __SWAP_GRP_POS__ := True + __INCLUDE_MTRX__ := False + __BAD_CODE__ := False + API_INCLUDE := False + BE_CAREFUL := False + OLDWAY := False + NOTUSED := False + + SYSTEM PARAMETERS... + EXT_ENUM := 999999999L + CHUNK_CONSTANT := 55555555 + CORE_CONSTANT := 55555555 + CORE_LIMIT := 20971520 + CorePage_Size := 384000 + ALIGN_BYTES := True + CORE_BLOCK_ALIGN := 8 + FAR_MEM := False + + MEMORY MANAGEMENT PARAMETERS... + SYSTEM_ALLOC := True + SYSTEM_FREESTORE := True + __NO_DISKCACHE__ := False + __FREEZE_VCHUNKS__ := True + __FREEZE_GRP_PACKETS__ := True + __MINIMIZE_TREE_CACHE__:= True + + SYSTEM STD PARAMETERS... + __STDOUT__ := False + NULL := 0 + LPTR := False + False_Status := 1 + True_Status := 0 + LARGE := True + TWOBYTE_BOOL := False + __NOSTR__ := False + + MEMORY VALIDATION PARAMETERS... + CORE_CRC_CHECK := False + VALIDATE_MEM_CHUNKS := False + + SYSTEM DEBUG OPTIONS... + DEBUG := False + MCSTAT := False + TRACKBACK := False + FLUSH_FILES := False + DEBUG_CORE0 := False + DEBUG_RISC := False + __TREE_BUG__ := False + __TRACK_FILE_READS__ := False + PAGE_SPACE := False + LEAVE_NO_TRACE := True + NULL_TRACE_STRS := False + + TIME PARAMETERS... + CLOCK_IS_LONG := False + __DISPLAY_TIME__ := False + __TREE_TIME__ := False + __DISPLAY_ERRORS__ := False + + API MACROS... + __BMT01__ := True + OPTIMIZE := True + + END OF DEFINES. + + + + ... IMPLODE MEMORY ... + + SWAP to DiskCache := False + + FREEZE_GRP_PACKETS:= True + + QueBug := 1000 + + sizeof(boolean) = 4 + sizeof(sizetype) = 4 + sizeof(chunkstruc) = 32 + + sizeof(shorttype ) = 2 + sizeof(idtype ) = 2 + sizeof(sizetype ) = 4 + sizeof(indextype ) = 4 + sizeof(numtype ) = 4 + sizeof(handletype) = 4 + sizeof(tokentype ) = 8 + + sizeof(short ) = 2 + sizeof(int ) = 4 + + sizeof(lt64 ) = 4 + sizeof(farlongtype) = 4 + sizeof(long ) = 4 + sizeof(longaddr ) = 4 + + sizeof(float ) = 4 + sizeof(double ) = 8 + + sizeof(addrtype ) = 4 + sizeof(char * ) = 4 + ALLOC CORE_1 :: 8 + BHOOLE NATH + + OPEN File ./input/bendian.rnv + *Status = 0 + DB HDR restored from FileVbn[ 0] + DB BlkDirOffset : @ 2030c0 + DB BlkDirChunk : Chunk[ 10] AT Vbn[3146] + DB BlkTknChunk : Chunk[ 11] AT Vbn[3147] + DB BlkSizeChunk : Chunk[ 12] AT Vbn[3148] + DB Handle Chunk's StackPtr = 20797 + + DB[ 1] LOADED; Handles= 20797 + KERNEL in CORE[ 1] Restored @ 1b4750 + + OPEN File ./input/bendian.wnv + *Status = 0 + DB HDR restored from FileVbn[ 0] + DB BlkDirOffset : @ 21c40 + DB BlkDirChunk : Chunk[ 31] AT Vbn[ 81] + DB BlkTknChunk : Chunk[ 32] AT Vbn[ 82] + DB BlkSizeChunk : Chunk[ 33] AT Vbn[ 83] + DB Handle Chunk's StackPtr = 17 + + DB[ 2] LOADED; Handles= 17 + VORTEx_Status == -8 || fffffff8 + + BE HERE NOW !!! + + + + ... VORTEx ON LINE ... + + + ... END OF SESSION ... diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/smred.out b/tests/long/50.vortex/ref/sparc/linux/simple-timing/smred.out new file mode 100644 index 000000000..726b45c60 --- /dev/null +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/smred.out @@ -0,0 +1,258 @@ + CREATE Db Header and Db Primal ... + NEW DB [ 3] Created. + +VORTEX INPUT PARAMETERS:: + MESSAGE FileName: smred.msg + OUTPUT FileName: smred.out + DISK CACHE FileName: NULL + PART DB FileName: parts.db + DRAW DB FileName: draw.db + PERSON DB FileName: emp.db + PERSONS Data FileName: ./input/persons.250 + PARTS Count : 100 + OUTER Loops : 1 + INNER Loops : 1 + LOOKUP Parts : 25 + DELETE Parts : 10 + STUFF Parts : 10 + DEPTH Traverse: 5 + % DECREASE Parts : 0 + % INCREASE LookUps : 0 + % INCREASE Deletes : 0 + % INCREASE Stuffs : 0 + FREEZE_PACKETS : 1 + ALLOC_CHUNKS : 10000 + EXTEND_CHUNKS : 5000 + DELETE Draw objects : True + DELETE Part objects : False + QUE_BUG : 1000 + VOID_BOUNDARY : 67108864 + VOID_RESERVE : 1048576 + + COMMIT_DBS : False + + + + BMT TEST :: files... + EdbName := PartLib + EdbFileName := parts.db + DrwName := DrawLib + DrwFileName := draw.db + EmpName := PersonLib + EmpFileName := emp.db + + Swap to DiskCache := False + Freeze the cache := True + + + BMT TEST :: parms... + DeBug modulo := 1000 + Create Parts count:= 100 + Outer Loops := 1 + Inner Loops := 1 + Look Ups := 25 + Delete Parts := 10 + Stuff Parts := 10 + Traverse Limit := 5 + Delete Draws := True + Delete Parts := False + Delete ALL Parts := after every <mod 0>Outer Loop + + INITIALIZE LIBRARY :: + + INITIALIZE SCHEMA :: + Primal_CreateDb Accessed !!! + CREATE Db Header and Db Primal ... + NEW DB [ 4] Created. + PartLibCreate:: Db[ 4]; VpartsDir= 1 + + Part Count= 1 + + Initialize the Class maps + LIST HEADS loaded ... DbListHead_Class = 207 + DbListNode_Class = 206 + +...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated. + + +...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated. + + Primal_CreateDb Accessed !!! + CREATE Db Header and Db Primal ... + NEW DB [ 5] Created. + DrawLibCreate:: Db[ 5]; VpartsDir= 1 + + Initialize the Class maps of this schema. + Primal_CreateDb Accessed !!! + CREATE Db Header and Db Primal ... + NEW DB [ 6] Created. + + ***NOTE*** Persons Library Extended! + + Create <131072> Persons. + ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ; + + LAST Person Read:: + ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ; + + BUILD <Query0> for <Part2> class:: + + if (link[1].length >= 5) :: + + Build Query2 for <Address> class:: + + if (State == CA || State == T*) + + Build Query1 for <Person> class:: + + if (LastName >= H* && LastName <= P* && Query0(Residence)) :: + + BUILD <Query3> for <DrawObj> class:: + + if (Id >= 3000 + && (Id >= 3000 && Id <= 3001) + && Id >= 3002) + + BUILD <Query4> for <NamedDrawObj> class:: + + if (Nam == Pre* + || (Nam == ??Mid??? || == Pre??Mid?? || == ??Post + || == Pre??Post || == ??Mid???Post || == Pre??Mid???Post) + && Id <= 7) + SEED := 1008; Swap = False; RgnEntries = 135 + + OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10. + + Create 100 New Parts + Create Part 1. Token[ 4: 2]. + + < 100> Parts Created. CurrentId= 100 + + Connect each instantiated Part TO 3 unique Parts + Connect Part 1. Token[ 4: 2] + Connect Part 25. Token[ 4: 26] FromList= 26. + Connect Part 12. Token[ 4: 13] FromList= 13. + Connect Part 59. Token[ 4: 60] FromList= 60. + + SET <DrawObjs> entries:: + 1. [ 5: 5] := <1 >; @[: 6] + Iteration count = 100 + + SET <NamedDrawObjs> entries:: + 1. [ 5: 39] := <14 >; + Iteration count = 12 + + SET <LibRectangles> entries:: + 1. [ 5: 23] := <8 >; @[: 24] + Iteration count = 12 + + LIST <DbRectangles> entries:: + 1. [ 5: 23] + Iteration count = 12 + + SET <PersonNames > entries:: + Iteration count = 250 + + COMMIT All Image copies:: Release=<True>; Max Parts= 100 + < 100> Part images' Committed. + < 0> are Named. + < 50> Point images' Committed. + < 81> Person images' Committed. + + COMMIT Parts(* 100) + + Commit TestObj_Class in <Primal> DB. + ItNum 0. Token[ 0: 0]. TestObj Committed. + < 0> TestObj images' Committed. + + Commit CartesianPoint_Class in <Primal> DB. + ItNum 0. Token[ 0: 0]. CartesianPoint Committed. + < 0> CartesianPoint images' Committed. + + BEGIN Inner Loop Sequence::. + + INNER LOOP [ 1: 1] : + + LOOK UP 25 Random Parts and Export each Part. + + LookUp for 26 parts; Asserts = 8 + <Part2 > Asserts = 2; NULL Asserts = 3. + <DrawObj > Asserts = 0; NULL Asserts = 5. + <NamedObj > Asserts = 0; NULL Asserts = 0. + <Person > Asserts = 0; NULL Asserts = 5. + <TestObj > Asserts = 60; NULL Asserts = 0. + + DELETE 10 Random Parts. + + PartDelete :: Token[ 4: 91]. + PartDisconnect:: Token[ 4: 91] id:= 90 for each link. + DisConnect link [ 0]:= 50; PartToken[ 51: 51]. + DisConnect link [ 1]:= 17; PartToken[ 18: 18]. + DisConnect link [ 2]:= 72; PartToken[ 73: 73]. + DeleteFromList:: Vchunk[ 4: 91]. (* 1) + DisConnect FromList[ 0]:= 56; Token[ 57: 57]. + Vlists[ 89] := 100; + + Delete for 11 parts; + + Traverse Count= 0 + + TRAVERSE PartId[ 6] and all Connections to 5 Levels + SEED In Traverse Part [ 4: 65] @ Level = 4. + + Traverse Count= 357 + Traverse Asserts = 5. True Tests = 1 + < 5> DrawObj objects DELETED. + < 2> are Named. + < 2> Point objects DELETED. + + CREATE 10 Additional Parts + + Create 10 New Parts + Create Part 101. Token[ 4: 102]. + + < 10> Parts Created. CurrentId= 110 + + Connect each instantiated Part TO 3 unique Parts + + COMMIT All Image copies:: Release=<True>; Max Parts= 110 + < 81> Part images' Committed. + < 0> are Named. + < 38> Point images' Committed. + < 31> Person images' Committed. + + COMMIT Parts(* 100) + + Commit TestObj_Class in <Primal> DB. + ItNum 0. Token[ 3: 4]. TestObj Committed. + < 15> TestObj images' Committed. + + Commit CartesianPoint_Class in <Primal> DB. + ItNum 0. Token[ 3: 3]. CartesianPoint Committed. + < 16> CartesianPoint images' Committed. + + DELETE All TestObj objects; + + Delete TestObj_Class in <Primal> DB. + ItNum 0. Token[ 3: 4]. TestObj Deleted. + < 15> TestObj objects Deleted. + + Commit CartesianPoint_Class in <Primal> DB. + ItNum 0. Token[ 3: 3]. CartesianPoint Deleted. + < 16> CartesianPoint objects Deleted. + + DELETE TestObj and Point objects... + + END INNER LOOP [ 1: 1]. + + DELETE All TestObj objects; + + Delete TestObj_Class in <Primal> DB. + < 0> TestObj objects Deleted. + + Commit CartesianPoint_Class in <Primal> DB. + < 0> CartesianPoint objects Deleted. + + DELETE TestObj and Point objects... + STATUS= -201 +V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1! diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr new file mode 100644 index 000000000..c0f1c1fbb --- /dev/null +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr @@ -0,0 +1,569 @@ +warn: More than two loadable segments in ELF object. +warn: Ignoring segment @ 0x1838c0 length 0x10. +warn: More than two loadable segments in ELF object. +warn: Ignoring segment @ 0x0 length 0x0. +0: system.remote_gdb.listener: listening for remote gdb on port 7001 +warn: Entering event queue @ 0. Starting simulation... +warn: Ignoring request to flush register windows. +warn: ignoring syscall time(4026527856, 4026528256, ...) +warn: ignoring syscall time(4026527408, 1375098, ...) +warn: ignoring syscall time(4026527320, 1, ...) +warn: ignoring syscall time(4026527056, 413, ...) +warn: ignoring syscall time(4026527056, 414, ...) +warn: ignoring syscall time(4026527296, 4026527696, ...) +warn: ignoring syscall time(4026526848, 1375098, ...) +warn: Increasing stack size by one page. +warn: ignoring syscall time(4026527056, 409, ...) +warn: ignoring syscall time(4026527056, 409, ...) +warn: ignoring syscall time(4026526968, 409, ...) +warn: ignoring syscall time(4026527048, 409, ...) +warn: ignoring syscall time(4026527008, 409, ...) +warn: ignoring syscall time(4026526992, 409, ...) +warn: ignoring syscall time(4026526992, 409, ...) +warn: ignoring syscall time(4026526880, 409, ...) +warn: ignoring syscall time(4026526320, 19045, ...) +warn: ignoring syscall time(4026526840, 409, ...) +warn: ignoring syscall time(4026526880, 409, ...) +warn: ignoring syscall time(4026526880, 409, ...) +warn: ignoring syscall time(4026526856, 409, ...) +warn: ignoring syscall time(4026526848, 409, ...) +warn: ignoring syscall time(4026526880, 409, ...) +warn: ignoring syscall time(4026526864, 409, ...) +warn: ignoring syscall time(4026526856, 409, ...) +warn: ignoring syscall time(4026526944, 409, ...) +warn: ignoring syscall time(4026527016, 4026527416, ...) +warn: ignoring syscall time(4026526568, 1375098, ...) +warn: ignoring syscall time(4026527192, 18732, ...) +warn: ignoring syscall time(4026526640, 409, ...) +warn: ignoring syscall time(4026526744, 0, ...) +warn: ignoring syscall time(4026527328, 0, ...) +warn: ignoring syscall time(4026527752, 225, ...) +warn: ignoring syscall time(4026527056, 409, ...) +warn: ignoring syscall time(4026526864, 409, ...) +warn: ignoring syscall time(4026526880, 409, ...) +warn: ignoring syscall time(4026527104, 4026527504, ...) +warn: ignoring syscall time(4026526656, 1375098, ...) +warn: ignoring syscall time(4026526832, 0, ...) +warn: ignoring syscall time(4026527328, 0, ...) +warn: ignoring syscall time(4026527192, 1879089152, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall time(4026527480, 1595768, ...) +warn: ignoring syscall time(4026526920, 17300, ...) +warn: ignoring syscall time(4026527480, 0, ...) +warn: ignoring syscall time(4026527480, 0, ...) +warn: ignoring syscall time(4026526920, 19045, ...) +warn: ignoring syscall time(4026527480, 0, ...) +warn: ignoring syscall time(4026527480, 0, ...) +warn: ignoring syscall time(4026527480, 0, ...) +warn: ignoring syscall time(4026527480, 0, ...) +warn: ignoring syscall time(4026527480, 0, ...) +warn: ignoring syscall time(4026527480, 0, ...) +warn: ignoring syscall time(4026527480, 0, ...) +warn: ignoring syscall time(4026527480, 0, ...) +warn: ignoring syscall time(4026527480, 0, ...) +warn: ignoring syscall time(4026526920, 19045, ...) +warn: ignoring syscall time(4026526920, 17300, ...) +warn: ignoring syscall time(4026525976, 20500, ...) +warn: ignoring syscall time(4026525976, 4026526444, ...) +warn: ignoring syscall time(4026526064, 7004192, ...) +warn: ignoring syscall time(4026527520, 4, ...) +warn: ignoring syscall time(4026525768, 0, ...) diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout new file mode 100644 index 000000000..dc2b61804 --- /dev/null +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout @@ -0,0 +1,13 @@ +M5 Simulator System + +Copyright (c) 2001-2006 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Mar 29 2007 03:55:17 +M5 started Thu Mar 29 03:55:38 2007 +M5 executing on zizzer.eecs.umich.edu +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing tests/run.py long/50.vortex/sparc/linux/simple-timing +Global frequency set at 1000000000000 ticks per second +Exiting @ tick 1382530003 because target called exit() diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini new file mode 100644 index 000000000..0e057cbbe --- /dev/null +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini @@ -0,0 +1,187 @@ +[root] +type=Root +children=system +dummy=0 + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=TimingSimpleCPU +children=dcache icache l2cache toL2Bus workload +clock=1 +cpu_id=0 +defer_registration=false +function_trace=false +function_trace_start=0 +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +phase=0 +progress_interval=0 +system=system +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=262144 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.port[1] + +[system.cpu.icache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=131072 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.port[0] + +[system.cpu.l2cache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=2097152 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.port[2] +mem_side=system.membus.port[1] + +[system.cpu.toL2Bus] +type=Bus +bus_id=0 +clock=1000 +responder_set=false +width=64 +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side + +[system.cpu.workload] +type=LiveProcess +cmd=twolf smred +cwd=build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing +egid=100 +env= +euid=100 +executable=/dist/m5/cpu2000/binaries/sparc/linux/twolf +gid=100 +input=cin +output=cout +pid=100 +ppid=99 +system=system +uid=100 + +[system.membus] +type=Bus +bus_id=0 +clock=1000 +responder_set=false +width=64 +port=system.physmem.port system.cpu.l2cache.mem_side + +[system.physmem] +type=PhysicalMemory +file= +latency=1 +range=0:134217727 +zero=false +port=system.membus.port[0] + diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.out b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.out new file mode 100644 index 000000000..5f60c76d0 --- /dev/null +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.out @@ -0,0 +1,178 @@ +[root] +type=Root +dummy=0 + +[system.physmem] +type=PhysicalMemory +file= +range=[0,134217727] +latency=1 +zero=false + +[system] +type=System +physmem=system.physmem +mem_mode=atomic + +[system.membus] +type=Bus +bus_id=0 +clock=1000 +width=64 +responder_set=false + +[system.cpu.workload] +type=LiveProcess +cmd=twolf smred +executable=/dist/m5/cpu2000/binaries/sparc/linux/twolf +input=cin +output=cout +env= +cwd=build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing +system=system +uid=100 +euid=100 +gid=100 +egid=100 +pid=100 +ppid=99 + +[system.cpu] +type=TimingSimpleCPU +max_insts_any_thread=0 +max_insts_all_threads=0 +max_loads_any_thread=0 +max_loads_all_threads=0 +progress_interval=0 +system=system +cpu_id=0 +workload=system.cpu.workload +clock=1 +phase=0 +defer_registration=false +// width not specified +function_trace=false +function_trace_start=0 +// simulate_stalls not specified + +[system.cpu.toL2Bus] +type=Bus +bus_id=0 +clock=1000 +width=64 +responder_set=false + +[system.cpu.icache] +type=BaseCache +size=131072 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.dcache] +type=BaseCache +size=262144 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.l2cache] +type=BaseCache +size=2097152 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt new file mode 100644 index 000000000..2fbdef851 --- /dev/null +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt @@ -0,0 +1,226 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 471554 # Simulator instruction rate (inst/s) +host_mem_usage 155352 # Number of bytes of host memory used +host_seconds 410.21 # Real time elapsed on the host +host_tick_rate 766692 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 193435973 # Number of instructions simulated +sim_seconds 0.000315 # Number of seconds simulated +sim_ticks 314505003 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 57734138 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 3705.925703 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2705.925703 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 57733640 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 1845551 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.000009 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 498 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 1347551 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000009 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 498 # number of ReadReq MSHR misses +system.cpu.dcache.SwapReq_accesses 22406 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.SwapReq_avg_miss_latency 3995 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency 2995 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_hits 22405 # number of SwapReq hits +system.cpu.dcache.SwapReq_miss_latency 3995 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_rate 0.000045 # miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_misses 1 # number of SwapReq misses +system.cpu.dcache.SwapReq_mshr_miss_latency 2995 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_rate 0.000045 # mshr miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_mshr_misses 1 # number of SwapReq MSHR misses +system.cpu.dcache.WriteReq_accesses 18976414 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 3678.678637 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2678.678637 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 18975328 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 3995045 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.000057 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 1086 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 2909045 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.000057 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 1086 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 48410.960883 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 76710552 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 3687.244949 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 2687.244949 # average overall mshr miss latency +system.cpu.dcache.demand_hits 76708968 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 5840596 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.000021 # miss rate for demand accesses +system.cpu.dcache.demand_misses 1584 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 4256596 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.000021 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 1584 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 76710552 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 3687.244949 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 2687.244949 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 76708968 # number of overall hits +system.cpu.dcache.overall_miss_latency 5840596 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.000021 # miss rate for overall accesses +system.cpu.dcache.overall_misses 1584 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 4256596 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.000021 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 1584 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 26 # number of replacements +system.cpu.dcache.sampled_refs 1585 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 1216.403972 # Cycle average of tags in use +system.cpu.dcache.total_refs 76731373 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 23 # number of writebacks +system.cpu.icache.ReadReq_accesses 193435974 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 3138.680633 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 2138.680633 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 193423706 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 38505334 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000063 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 12268 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 26237334 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000063 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 12268 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_refs 15766.523150 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 193435974 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 3138.680633 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 2138.680633 # average overall mshr miss latency +system.cpu.icache.demand_hits 193423706 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 38505334 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000063 # miss rate for demand accesses +system.cpu.icache.demand_misses 12268 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 26237334 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000063 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 12268 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 193435974 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 3138.680633 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 2138.680633 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 193423706 # number of overall hits +system.cpu.icache.overall_miss_latency 38505334 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000063 # miss rate for overall accesses +system.cpu.icache.overall_misses 12268 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 26237334 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000063 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 12268 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 10342 # number of replacements +system.cpu.icache.sampled_refs 12268 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 1567.271345 # Cycle average of tags in use +system.cpu.icache.total_refs 193423706 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.l2cache.ReadReq_accesses 13852 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 2847.598413 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1846.400619 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 8685 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 14713541 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.373015 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 5167 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 9540352 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.373015 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 5167 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 23 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 23 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 1.685311 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 13852 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 2847.598413 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1846.400619 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 8685 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 14713541 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.373015 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 5167 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 9540352 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.373015 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 5167 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 13875 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 2847.598413 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1846.400619 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 8708 # number of overall hits +system.cpu.l2cache.overall_miss_latency 14713541 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.372396 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 5167 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 9540352 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.372396 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 5167 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.sampled_refs 5167 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 3448.701925 # Cycle average of tags in use +system.cpu.l2cache.total_refs 8708 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 314505003 # number of cpu cycles simulated +system.cpu.num_insts 193435973 # Number of instructions executed +system.cpu.num_refs 76732959 # Number of memory references +system.cpu.workload.PROG:num_syscalls 396 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.out b/tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.out new file mode 100644 index 000000000..00387ae5c --- /dev/null +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.out @@ -0,0 +1,276 @@ + +TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 +Standard Cell Placement and Global Routing Program +Authors: Carl Sechen, Bill Swartz + Yale University + + +NOTE: Restart file .rs2 not used + +TimberWolf will perform a global route step +rowSep: 1.000000 +feedThruWidth: 4 + +****************** +BLOCK DATA +block:1 desire:85 +block:2 desire:85 +Total Desired Length: 170 +total cell length: 168 +total block length: 168 +block x-span:84 block y-span:78 +implicit feed thru range: -84 +Using default value of bin.penalty.control:1.000000 +numBins automatically set to:5 +binWidth = average_cell_width + 0 sigma= 17 +average_cell_width is:16 +standard deviation of cell length is:23.6305 +TimberWolfSC starting from the beginning + + + +THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645 +The number of nets with 1 pin is 4 +The number of nets with 2 pin is 9 +The number of nets with 3 pin is 0 +The number of nets with 4 pin is 2 +The number of nets with 5 pin is 0 +The number of nets with 6 pin is 0 +The number of nets with 7 pin is 0 +The number of nets with 8 pin is 0 +The number of nets with 9 pin is 0 +The number of nets with 10 pin or more is 0 + +New Cost Function: Initial Horizontal Cost:242 +New Cost Function: FEEDS:0 MISSING_ROWS:-46 + +bdxlen:86 bdylen:78 +l:0 t:78 r:86 b:0 + + + +THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645 + + + +THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44 + +The rand generator seed was at utemp() : 1 + + + tempfile[0][0] = 0.982500 tempfile[0][1] = 90.000000 + tempfile[1][0] = 0.915000 tempfile[1][1] = 20.000000 + tempfile[2][0] = 0.700000 tempfile[2][1] = 10.000000 + tempfile[3][0] = 0.100000 tempfile[3][1] = 0.000000 + + I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs + 1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40 + 2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46 + 3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.2 0.0 0 46 + 4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48 + 5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46 + 6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52 + 7 449 8 1067 108 190 0.0 0.5 0.5 46.2 53.8 0.0 0 50 + 8 441 8 918 106 171 0.0 0.5 0.5 47.1 40.4 0.0 0 48 + 9 434 8 812 101 197 0.0 0.5 0.5 53.6 21.0 0.0 0 48 + 10 426 8 1038 121 181 0.0 0.5 0.5 43.6 27.1 0.0 0 48 + 11 419 8 898 93 187 0.0 0.5 0.5 45.3 47.8 0.0 0 50 + 12 411 4 857 94 240 0.0 0.5 0.5 62.7 51.6 0.0 0 44 + 13 404 8 1043 88 185 0.0 0.5 0.5 54.0 52.8 0.0 0 50 + 14 397 8 767 94 154 0.0 0.5 0.5 33.8 35.0 0.0 0 50 + 15 390 8 862 89 183 0.0 0.5 0.5 55.6 29.0 0.0 0 46 + 16 383 4 798 79 173 0.0 0.5 0.5 57.5 35.3 0.0 0 52 + 17 376 8 827 100 152 0.0 0.5 0.5 35.3 81.8 0.0 0 50 + 18 370 8 878 101 208 0.0 0.5 0.5 44.7 46.2 0.0 0 48 + 19 363 4 921 67 167 0.0 0.5 0.5 57.1 34.7 0.0 0 48 + 20 357 8 933 93 154 0.0 0.5 0.5 46.5 43.6 0.0 0 52 + 21 351 8 930 89 147 0.0 0.5 0.5 39.4 36.5 0.0 0 52 + 22 345 8 951 79 142 0.0 0.5 0.5 32.8 51.3 0.0 0 50 + 23 339 8 1046 87 207 0.0 0.5 0.5 52.8 61.0 0.0 0 48 + 24 333 4 989 96 185 0.0 0.5 0.5 45.3 43.3 0.0 0 42 + 25 327 4 577 86 157 0.0 0.5 0.5 31.1 55.3 0.0 0 52 + 26 321 8 776 97 174 0.0 0.5 0.5 47.9 62.5 0.0 0 52 + 27 315 8 850 81 188 0.0 0.5 0.5 45.0 55.2 0.0 0 50 + 28 310 8 898 97 148 0.0 0.5 0.5 43.0 45.8 0.0 0 48 + 29 304 8 889 65 173 0.0 0.5 0.5 32.5 41.3 0.0 0 50 + 30 299 8 858 81 153 0.0 0.5 0.5 44.3 29.2 0.0 0 46 + 31 294 8 871 82 187 0.0 0.5 0.5 45.7 47.7 0.0 0 48 + 32 289 8 782 109 173 0.0 0.5 0.5 35.2 57.4 0.0 0 48 + 33 284 8 743 98 189 0.0 0.6 0.5 41.8 64.3 0.0 0 52 + 34 279 8 943 90 147 0.0 0.5 0.5 38.6 32.8 0.0 0 48 + 35 274 8 907 57 166 0.0 0.5 0.5 33.6 51.0 0.0 0 48 + 36 269 8 900 70 148 0.0 0.5 0.5 45.0 41.4 0.0 0 50 + 37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52 + 38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52 + 39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48 + 40 251 8 741 104 159 0.0 0.8 0.5 36.2 47.5 0.0 0 48 + 41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50 + 42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50 + 43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48 + 44 234 8 761 86 129 0.0 0.5 0.5 42.0 36.4 0.0 0 52 + 45 229 8 979 106 137 0.0 0.5 0.5 29.2 55.3 0.0 0 50 + 46 225 8 806 74 130 0.0 0.7 0.5 33.1 65.4 0.0 0 52 + 47 221 8 971 125 114 0.0 0.5 0.5 31.9 45.6 0.0 0 52 + 48 218 8 869 125 104 0.0 0.9 0.5 30.0 56.0 0.0 0 48 + 49 214 8 999 153 140 0.0 0.8 0.5 30.4 46.4 0.0 0 52 + 50 210 8 798 192 139 0.0 1.0 0.5 28.9 50.0 0.0 0 52 + 51 206 8 860 125 157 0.0 1.2 0.5 31.5 26.9 0.0 0 52 + 52 203 8 893 186 127 5.9 0.9 0.5 26.4 42.3 0.0 0 46 + 53 199 8 863 126 141 0.0 1.2 0.5 32.5 44.4 0.0 0 44 + 54 196 8 788 97 133 0.0 0.9 0.5 37.5 40.0 0.0 0 50 + 55 192 8 926 119 116 0.0 0.6 0.5 26.1 55.3 0.0 0 52 + 56 189 8 789 162 107 0.0 0.8 0.5 25.2 40.4 0.0 0 48 + 57 186 8 878 107 128 0.0 1.1 0.5 23.1 34.0 0.0 0 52 + 58 182 8 775 105 122 0.0 0.8 0.5 25.5 57.4 0.0 0 50 + 59 179 8 747 94 129 0.0 0.7 0.5 34.3 37.3 0.0 0 50 + 60 176 8 845 96 138 0.0 0.6 0.5 28.3 41.7 0.0 0 52 + 61 173 8 961 121 110 0.0 0.6 0.5 29.0 52.6 0.0 0 48 + 62 170 4 911 110 109 0.0 0.9 0.5 33.5 33.3 0.0 0 48 + 63 167 8 656 109 109 0.0 0.8 0.5 21.9 44.7 0.0 0 52 + 64 164 8 934 117 105 0.0 0.8 0.5 15.5 50.0 0.0 0 52 + 65 161 8 972 125 95 0.0 0.8 0.5 24.4 50.0 0.0 0 50 + 66 158 8 894 125 101 0.0 0.9 0.5 27.2 35.9 0.0 0 52 + 67 155 8 798 146 129 0.0 1.0 0.5 22.8 58.7 0.0 0 52 + 68 153 8 901 183 92 0.0 1.1 0.5 23.6 34.5 0.0 0 52 + 69 150 8 977 197 103 0.0 1.4 0.5 23.6 36.8 0.0 0 52 + 70 147 8 905 262 93 0.0 1.5 0.5 20.3 63.4 0.0 0 52 + 71 145 8 995 148 122 0.0 1.9 0.5 20.9 35.3 0.0 0 52 + 72 142 8 934 230 99 0.0 1.6 0.5 20.0 65.9 0.0 0 52 + 73 140 8 862 173 100 0.0 1.8 0.5 26.8 46.8 0.0 0 52 + 74 137 8 924 139 90 0.0 1.7 0.5 16.8 42.5 0.0 0 52 + 75 135 8 888 168 113 0.0 1.6 0.5 22.9 40.4 0.0 0 52 + 76 133 8 712 212 84 0.0 1.6 0.5 13.4 46.9 0.0 0 52 + 77 130 8 868 210 91 0.0 1.7 0.5 17.7 51.2 0.0 0 52 + 78 128 8 952 307 92 0.0 1.9 0.5 19.7 44.9 0.0 0 50 + 79 126 8 801 157 107 0.0 2.2 0.5 15.8 39.0 0.0 0 52 + 80 123 8 849 147 93 0.0 2.1 0.5 15.6 51.4 0.0 0 52 + 81 121 8 799 154 86 0.0 1.9 0.5 12.2 50.0 0.0 0 52 + 82 119 8 941 213 82 0.0 1.8 0.5 19.5 41.2 0.0 0 50 + 83 117 8 751 268 94 0.0 2.0 0.5 20.8 42.6 0.0 0 50 + 84 115 8 828 198 102 0.0 2.2 0.5 15.5 59.5 0.0 0 52 + 85 113 8 898 266 123 0.0 2.2 0.5 13.2 85.2 0.0 0 52 + 86 111 8 943 190 93 0.0 2.4 0.5 19.5 45.1 0.0 0 52 + 87 109 8 864 183 65 0.0 2.4 0.5 14.9 31.8 0.0 0 52 + 88 107 8 793 203 93 0.0 2.4 0.5 11.8 35.3 0.0 0 52 + 89 105 8 752 162 74 1.2 2.4 0.5 13.1 21.4 0.0 0 52 + 90 103 8 801 149 77 0.0 2.3 0.5 9.7 58.3 0.0 0 52 + 91 102 8 901 230 99 0.0 2.2 0.5 16.0 25.5 0.0 0 52 + 92 100 8 826 201 87 0.0 2.4 0.5 12.8 45.7 0.0 0 52 + 93 98 8 810 196 83 0.0 2.5 0.5 14.0 24.4 0.0 0 52 + 94 96 8 857 209 68 1.0 2.5 0.5 11.5 27.0 5.1 0 52 + 95 95 8 771 174 91 0.0 2.6 0.5 10.5 26.5 0.0 0 52 + 96 93 8 955 210 59 0.0 2.6 0.5 10.0 36.7 0.7 0 52 + 97 91 8 833 206 53 0.0 2.7 0.5 10.2 19.4 1.4 0 52 + 98 90 8 888 229 86 0.0 2.8 0.5 8.1 36.0 0.0 0 52 + 99 88 8 794 186 91 1.0 2.9 0.5 8.3 25.0 0.5 0 52 +100 81 8 756 170 72 1.0 2.9 0.5 6.0 23.8 7.0 0 52 +101 74 8 791 176 67 0.0 2.9 0.5 4.4 58.3 4.0 0 52 +102 67 8 813 213 43 0.0 3.0 0.5 7.0 150.0 4.2 0 52 +103 62 8 779 245 39 0.0 3.1 0.5 3.2 16.7 13.0 0 52 +104 56 8 767 303 63 0.0 3.2 0.5 4.1 20.0 0.7 0 52 +105 52 8 757 270 57 0.0 3.5 0.5 6.4 3.7 0.5 0 52 +106 47 8 763 283 41 0.0 3.7 0.5 4.5 0.0 0.0 0 52 +107 43 8 768 283 36 0.0 3.7 0.5 2.9 18.2 3.6 0 52 +108 39 8 804 283 25 0.0 3.7 0.5 3.1 0.0 6.2 0 52 +109 36 8 781 283 24 0.0 3.7 0.5 3.6 6.7 6.7 0 52 +110 33 8 738 298 42 0.0 3.7 0.5 3.3 15.4 3.5 0 52 +111 30 8 761 298 36 0.0 3.7 0.5 2.2 0.0 4.3 0 52 +112 27 8 769 298 37 0.0 3.7 0.5 0.9 0.0 2.2 0 52 +113 25 8 745 298 31 0.0 3.7 0.5 1.5 0.0 6.6 0 52 +114 23 8 753 298 16 0.0 3.7 0.5 1.3 0.0 2.8 0 52 +115 21 8 745 298 11 0.0 3.7 0.5 1.5 0.0 14.0 0 52 +116 19 8 747 298 21 0.0 3.7 0.5 2.1 0.0 5.8 0 52 +117 13 8 737 298 12 0.0 3.7 0.5 1.0 0.0 10.0 0 52 +118 9 8 736 298 4 0.0 3.7 0.5 1.5 0.0 18.5 0 52 +119 0 8 739 298 0 0.0 3.7 0.5 1.8 0.0 18.0 0 52 +120 0 8 732 298 0 0.0 3.7 0.5 1.2 0.0 21.8 0 52 +121 0 8 732 19 -1 0.0 0.0 0.5 0.0 100.0 54.8 + +Initial Wiring Cost: 645 Final Wiring Cost: 732 +############## Percent Wire Cost Reduction: -13 + + +Initial Wire Length: 645 Final Wire Length: 732 +************** Percent Wire Length Reduction: -13 + + +Initial Horiz. Wire: 216 Final Horiz. Wire: 147 +$$$$$$$$$$$ Percent H-Wire Length Reduction: 32 + + +Initial Vert. Wire: 429 Final Vert. Wire: 585 +@@@@@@@@@@@ Percent V-Wire Length Reduction: -36 + +Before Feeds are Added: +BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET + 1 82 -20 + 2 86 -16 + +LONGEST Block is:2 Its length is:86 +BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET + 1 86 -16 + 2 86 -16 + +LONGEST Block is:1 Its length is:86 +Added: 1 feed-through cells + +Removed the cell overlaps --- Will do neighbor interchanges only now + +TOTAL INTERCONNECT LENGTH: 994 +OVERLAP PENALTY: 0 + +initialRowControl: 1.650 +finalRowControl: 0.300 +iter T Wire accept + 122 0.001 976 16% + 123 0.001 971 0% + 124 0.001 971 0% +Total Feed-Alignment Movement (Pass 1): 0 +Total Feed-Alignment Movement (Pass 2): 0 +Total Feed-Alignment Movement (Pass 3): 0 +Total Feed-Alignment Movement (Pass 4): 0 +Total Feed-Alignment Movement (Pass 5): 0 +Total Feed-Alignment Movement (Pass 6): 0 +Total Feed-Alignment Movement (Pass 7): 0 +Total Feed-Alignment Movement (Pass 8): 0 + +The rand generator seed was at globroute() : 987654321 + + +Total Number of Net Segments: 9 +Number of Switchable Net Segments: 0 + +Number of channels: 3 + + + +THIS IS THE ORIGINAL NUMBER OF TRACKS: 5 + + +no. of accepted flips: 0 +no. of attempted flips: 0 +THIS IS THE NUMBER OF TRACKS: 5 + + + +FINAL NUMBER OF ROUTING TRACKS: 5 + +MAX OF CHANNEL: 1 is: 0 +MAX OF CHANNEL: 2 is: 4 +MAX OF CHANNEL: 3 is: 1 +FINAL TOTAL INTERCONNECT LENGTH: 978 +FINAL OVERLAP PENALTY: 0 FINAL VALUE OF TOTAL COST IS: 978 +MAX NUMBER OF ATTEMPTED FLIPS PER T: 55 + + +cost_scale_factor:3.90616 + +Number of Feed Thrus: 0 +Number of Implicit Feed Thrus: 0 + +Statistics: +Number of Standard Cells: 10 +Number of Pads: 0 +Number of Nets: 15 +Number of Pins: 46 +Usage statistics not available diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.pin b/tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.pin new file mode 100644 index 000000000..62b922e4e --- /dev/null +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.pin @@ -0,0 +1,17 @@ +$COUNT_1/$AND2_1/$ND2_1$Z 1 $COUNT_1/$AND2_1/$ND2_1 00#Z 17 52 2 1 0 +$COUNT_1/$AND2_1/$ND2_1$Z 1 ACOUNT_1 00#A 15 26 2 -1 0 +B7 2 $COUNT_1/$FJK3_2 00#K 25 78 3 -1 0 +B7 2 $COUNT_1/$FJK3_2 00#J 23 78 3 -1 0 +B7 3 $COUNT_1/$AND2_2/$ND2_1 00#A 9 26 2 -1 0 +B7 3 ACOUNT_1 01#Z 17 26 2 -1 0 +B6 5 $COUNT_1/$FJK3_1 00#K 25 26 2 -1 0 +B6 5 $COUNT_1/$FJK3_1 00#J 23 26 2 -1 0 +B6 5 $COUNT_1/$AND2_3/$IV_1 01#Z 7 26 2 -1 0 +$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$FJK3_1 01#Q 81 26 2 -1 0 +$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$AND2_1/$ND2_1 00#B 19 52 2 1 0 +$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$FJK3_2 00#Q 81 52 2 1 0 +$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$AND2_2/$ND2_1 01#B 11 26 2 -1 0 +$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$ND2_1 00#Z 5 52 2 1 0 +$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$IV_1 00#A 5 26 2 -1 0 +$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$ND2_1 00#Z 7 52 2 1 0 +$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$IV_1 00#A 3 26 2 -1 0 diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.pl1 b/tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.pl1 new file mode 100644 index 000000000..bdc569e39 --- /dev/null +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.pl1 @@ -0,0 +1,11 @@ +$COUNT_1/$AND2_4/$IV_1 0 0 4 26 0 1 +$COUNT_1/$AND2_3/$IV_1 4 0 8 26 2 1 +$COUNT_1/$AND2_2/$ND2_1 8 0 14 26 0 1 +ACOUNT_1 14 0 18 26 2 1 +twfeed1 18 0 22 26 0 1 +$COUNT_1/$FJK3_1 22 0 86 26 0 1 +$COUNT_1/$AND2_3/$ND2_1 0 52 6 78 0 2 +$COUNT_1/$AND2_4/$ND2_1 6 52 12 78 2 2 +$COUNT_1/$AND2_2/$IV_1 12 52 16 78 2 2 +$COUNT_1/$AND2_1/$ND2_1 16 52 22 78 2 2 +$COUNT_1/$FJK3_2 22 52 86 78 0 2 diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.pl2 b/tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.pl2 new file mode 100644 index 000000000..6e2601e82 --- /dev/null +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.pl2 @@ -0,0 +1,2 @@ +1 0 0 86 26 0 0 +2 0 52 86 78 0 0 diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.sav b/tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.sav new file mode 100644 index 000000000..04c8e9935 --- /dev/null +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.sav @@ -0,0 +1,18 @@ +0.009592 +121 +0 +1 +0.000000 +0.500000 +3.906156 +1 +1 1 2 37 13 +2 2 0 34 65 +3 2 2 63 65 +4 1 0 59 13 +5 1 2 32 13 +6 2 0 23 65 +7 1 2 12 13 +8 2 0 6 65 +9 1 0 70 13 +10 2 0 70 65 diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.sv2 b/tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.sv2 new file mode 100644 index 000000000..9dd68ecdb --- /dev/null +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.sv2 @@ -0,0 +1,19 @@ +0.001000 +123 +0 +2 +0.000000 +0.500000 +3.906156 +1 +1 1 2 16 13 +2 2 2 19 65 +3 2 2 14 65 +4 1 0 11 13 +5 1 2 6 13 +6 2 0 3 65 +7 1 0 2 13 +8 2 2 9 65 +9 1 0 50 13 +10 2 0 54 65 +11 1 0 84 13 diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.twf b/tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.twf new file mode 100644 index 000000000..a4c2eac35 --- /dev/null +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.twf @@ -0,0 +1,29 @@ +net 1 +segment channel 2 + pin1 1 pin2 7 0 0 +net 2 +segment channel 3 +pin1 41 pin2 42 0 0 +segment channel 2 +pin1 12 pin2 3 0 0 +net 3 +segment channel 2 +pin1 35 pin2 36 0 0 +segment channel 2 +pin1 19 pin2 35 0 0 +net 4 +segment channel 2 + pin1 5 pin2 38 0 0 +net 5 +net 7 +segment channel 2 + pin1 14 pin2 43 0 0 +net 8 +segment channel 2 + pin1 23 pin2 17 0 0 +net 9 +net 11 +segment channel 2 + pin1 25 pin2 31 0 0 +net 14 +net 15 diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stderr b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stderr new file mode 100644 index 000000000..6e24f6d54 --- /dev/null +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stderr @@ -0,0 +1,8 @@ +warn: More than two loadable segments in ELF object. +warn: Ignoring segment @ 0x11e394 length 0x10. +warn: More than two loadable segments in ELF object. +warn: Ignoring segment @ 0x0 length 0x0. +0: system.remote_gdb.listener: listening for remote gdb on port 7002 +warn: Entering event queue @ 0. Starting simulation... +warn: Ignoring request to flush register windows. +warn: Increasing stack size by one page. diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout new file mode 100644 index 000000000..d50dfc3c4 --- /dev/null +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout @@ -0,0 +1,28 @@ + +TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 +Standard Cell Placement and Global Routing Program +Authors: Carl Sechen, Bill Swartz + Yale University + 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 + 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 + 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 + 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 + 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 + 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 +106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 +122 123 124 M5 Simulator System + +Copyright (c) 2001-2006 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Mar 29 2007 16:12:35 +M5 started Thu Mar 29 16:13:01 2007 +M5 executing on zizzer.eecs.umich.edu +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing tests/run.py long/70.twolf/sparc/linux/simple-timing +Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sav +Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sv2 +Global frequency set at 1000000000000 ticks per second +Exiting @ tick 314505003 because target called exit() |