diff options
| -rw-r--r-- | src/arch/alpha/interrupts.hh | 7 | ||||
| -rwxr-xr-x | src/arch/mips/interrupts.cc | 12 | ||||
| -rwxr-xr-x | src/arch/mips/interrupts.hh | 4 | ||||
| -rw-r--r-- | src/arch/sparc/tlb.cc | 33 | ||||
| -rw-r--r-- | src/arch/x86/interrupts.hh | 6 | ||||
| -rw-r--r-- | src/cpu/base.cc | 6 | ||||
| -rw-r--r-- | src/cpu/base.hh | 1 |
7 files changed, 24 insertions, 45 deletions
diff --git a/src/arch/alpha/interrupts.hh b/src/arch/alpha/interrupts.hh index abfecfb5b..6ae4e4b1d 100644 --- a/src/arch/alpha/interrupts.hh +++ b/src/arch/alpha/interrupts.hh @@ -171,13 +171,6 @@ class Interrupts tc->setMiscRegNoEffect(IPR_INTID, newIpl); newInfoSet = false; } - - uint64_t - get_vec(int int_num) - { - panic("Shouldn't be called for Alpha\n"); - M5_DUMMY_RETURN; - } }; } // namespace AlphaISA diff --git a/src/arch/mips/interrupts.cc b/src/arch/mips/interrupts.cc index c91ee1e99..e04d22631 100755 --- a/src/arch/mips/interrupts.cc +++ b/src/arch/mips/interrupts.cc @@ -156,12 +156,6 @@ static inline void setCauseIP_(ThreadContext *tc, uint8_t val) { return false; } - - uint64_t Interrupts::get_vec(int int_num) - { - panic("MipsISA::Interrupts::get_vec() is not implemented. \n"); - M5_DUMMY_RETURN - } */ void Interrupts::post(int int_num, ThreadContext* tc) { @@ -252,12 +246,6 @@ void Interrupts::updateIntrInfo(ThreadContext *tc) const ; } -uint64_t Interrupts::get_vec(int int_num) -{ - panic("MipsISA::Interrupts::get_vec() is not implemented. \n"); - M5_DUMMY_RETURN - } - bool Interrupts::interruptsPending(ThreadContext *tc) const { //if there is a on cpu timer interrupt (i.e. Compare == Count) diff --git a/src/arch/mips/interrupts.hh b/src/arch/mips/interrupts.hh index f0e928088..99a8f6fa0 100755 --- a/src/arch/mips/interrupts.hh +++ b/src/arch/mips/interrupts.hh @@ -91,8 +91,6 @@ class Interrupts void updateIntrInfoCpuTimerIntr(ThreadContext *tc) const; bool onCpuTimerInterrupt(ThreadContext *tc) const; - uint64_t get_vec(int int_num); - bool check_interrupts(ThreadContext * tc) const{ //return (intstatus != 0) && !(tc->readPC() & 0x3); if (oncputimerintr == false){ @@ -160,8 +158,6 @@ class Interrupts bool interruptsPending(ThreadContext *tc) const; bool onCpuTimerInterrupt(ThreadContext *tc) const; - uint64_t get_vec(int int_num); - bool check_interrupts(ThreadContext * tc) const{ return interruptsPending(tc); } diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc index 125ceba69..61f0985db 100644 --- a/src/arch/sparc/tlb.cc +++ b/src/arch/sparc/tlb.cc @@ -1008,12 +1008,22 @@ DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt) itb->cx_config)); break; case ASI_SWVR_INTR_RECEIVE: - pkt->set(tc->getCpuPtr()->get_interrupts(IT_INT_VEC)); + { + SparcISA::Interrupts * interrupts = + dynamic_cast<SparcISA::Interrupts *>( + tc->getCpuPtr()->getInterruptController()); + pkt->set(interrupts->get_vec(IT_INT_VEC)); + } break; case ASI_SWVR_UDB_INTR_R: - temp = findMsbSet(tc->getCpuPtr()->get_interrupts(IT_INT_VEC)); - tc->getCpuPtr()->clear_interrupt(IT_INT_VEC, temp); - pkt->set(temp); + { + SparcISA::Interrupts * interrupts = + dynamic_cast<SparcISA::Interrupts *>( + tc->getCpuPtr()->getInterruptController()); + temp = findMsbSet(interrupts->get_vec(IT_INT_VEC)); + tc->getCpuPtr()->clear_interrupt(IT_INT_VEC, temp); + pkt->set(temp); + } break; default: doMmuReadError: @@ -1252,11 +1262,16 @@ DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt) } break; case ASI_SWVR_INTR_RECEIVE: - int msb; - // clear all the interrupts that aren't set in the write - while(tc->getCpuPtr()->get_interrupts(IT_INT_VEC) & data) { - msb = findMsbSet(tc->getCpuPtr()->get_interrupts(IT_INT_VEC) & data); - tc->getCpuPtr()->clear_interrupt(IT_INT_VEC, msb); + { + int msb; + // clear all the interrupts that aren't set in the write + SparcISA::Interrupts * interrupts = + dynamic_cast<SparcISA::Interrupts *>( + tc->getCpuPtr()->getInterruptController()); + while(interrupts->get_vec(IT_INT_VEC) & data) { + msb = findMsbSet(interrupts->get_vec(IT_INT_VEC) & data); + tc->getCpuPtr()->clear_interrupt(IT_INT_VEC, msb); + } } break; case ASI_SWVR_UDB_INTR_W: diff --git a/src/arch/x86/interrupts.hh b/src/arch/x86/interrupts.hh index cf9109e22..43675294e 100644 --- a/src/arch/x86/interrupts.hh +++ b/src/arch/x86/interrupts.hh @@ -108,12 +108,6 @@ class Interrupts panic("Interrupts::updateIntrInfo unimplemented!\n"); } - uint64_t get_vec(int int_num) - { - panic("Interrupts::get_vec unimplemented!\n"); - return 0; - } - void serialize(std::ostream & os) { panic("Interrupts::serialize unimplemented!\n"); diff --git a/src/cpu/base.cc b/src/cpu/base.cc index 5a0359e53..1ca0dc14b 100644 --- a/src/cpu/base.cc +++ b/src/cpu/base.cc @@ -396,12 +396,6 @@ BaseCPU::clear_interrupts() interrupts.clear_all(); } -uint64_t -BaseCPU::get_interrupts(int int_num) -{ - return interrupts.get_vec(int_num); -} - void BaseCPU::serialize(std::ostream &os) { diff --git a/src/cpu/base.hh b/src/cpu/base.hh index 7b7ad9be0..c99efa834 100644 --- a/src/cpu/base.hh +++ b/src/cpu/base.hh @@ -119,7 +119,6 @@ class BaseCPU : public MemObject virtual void post_interrupt(int int_num, int index); virtual void clear_interrupt(int int_num, int index); virtual void clear_interrupts(); - virtual uint64_t get_interrupts(int int_num); bool check_interrupts(ThreadContext * tc) const { return interrupts.check_interrupts(tc); } |