diff options
| -rw-r--r-- | src/mem/DRAMCtrl.py | 30 | ||||
| -rw-r--r-- | src/mem/dram_ctrl.cc | 3 | ||||
| -rw-r--r-- | src/mem/dram_ctrl.hh | 2 |
3 files changed, 34 insertions, 1 deletions
diff --git a/src/mem/DRAMCtrl.py b/src/mem/DRAMCtrl.py index 81d0b7581..a1d9e2707 100644 --- a/src/mem/DRAMCtrl.py +++ b/src/mem/DRAMCtrl.py @@ -370,6 +370,12 @@ class DDR3_1600_x64(DRAMCtrl): # <=85C, half for >85C tREFI = '7.8us' + # active powerdown and precharge powerdown exit time + tXP = '6ns' + + # self refresh exit time + tXS = '270ns' + # Current values from datasheet IDD0 = '75mA' IDD2N = '50mA' @@ -591,6 +597,12 @@ class DDR4_2400_x64(DRAMCtrl): # <=85C, half for >85C tREFI = '7.8us' + # active powerdown and precharge powerdown exit time + tXP = '6ns' + + # self refresh exit time + tXS = '120ns' + # Current values from datasheet IDD0 = '70mA' IDD02 = '4.6mA' @@ -659,6 +671,12 @@ class LPDDR2_S4_1066_x32(DRAMCtrl): tRFC = '130ns' tREFI = '3.9us' + # active powerdown and precharge powerdown exit time + tXP = '7.5ns' + + # self refresh exit time + tXS = '140ns' + # Irrespective of speed grade, tWTR is 7.5 ns tWTR = '7.5ns' @@ -815,6 +833,12 @@ class LPDDR3_1600_x32(DRAMCtrl): tRFC = '130ns' tREFI = '3.9us' + # active powerdown and precharge powerdown exit time + tXP = '7.5ns' + + # self refresh exit time + tXS = '140ns' + # Irrespective of speed grade, tWTR is 7.5 ns tWTR = '7.5ns' @@ -1057,3 +1081,9 @@ class HBM_1000_4H_x64(HBM_1000_4H_x128): # Default different rank bus delay to 2 CK, @1000 MHz = 2 ns tCS = '2ns' tREFI = '3.9us' + + # active powerdown and precharge powerdown exit time + tXP = '10ns' + + # self refresh exit time + tXS = '65ns' diff --git a/src/mem/dram_ctrl.cc b/src/mem/dram_ctrl.cc index 55e1cf805..1ef311382 100644 --- a/src/mem/dram_ctrl.cc +++ b/src/mem/dram_ctrl.cc @@ -82,7 +82,8 @@ DRAMCtrl::DRAMCtrl(const DRAMCtrlParams* p) : tCK(p->tCK), tWTR(p->tWTR), tRTW(p->tRTW), tCS(p->tCS), tBURST(p->tBURST), tCCD_L(p->tCCD_L), tRCD(p->tRCD), tCL(p->tCL), tRP(p->tRP), tRAS(p->tRAS), tWR(p->tWR), tRTP(p->tRTP), tRFC(p->tRFC), tREFI(p->tREFI), tRRD(p->tRRD), - tRRD_L(p->tRRD_L), tXAW(p->tXAW), activationLimit(p->activation_limit), + tRRD_L(p->tRRD_L), tXAW(p->tXAW), tXP(p->tXP), tXS(p->tXS), + activationLimit(p->activation_limit), memSchedPolicy(p->mem_sched_policy), addrMapping(p->addr_mapping), pageMgmt(p->page_policy), maxAccessesPerRow(p->max_accesses_per_row), diff --git a/src/mem/dram_ctrl.hh b/src/mem/dram_ctrl.hh index f59528492..98f47edc2 100644 --- a/src/mem/dram_ctrl.hh +++ b/src/mem/dram_ctrl.hh @@ -726,6 +726,8 @@ class DRAMCtrl : public AbstractMemory const Tick tRRD; const Tick tRRD_L; const Tick tXAW; + const Tick tXP; + const Tick tXS; const uint32_t activationLimit; /** |