diff options
| -rw-r--r-- | src/arch/arm/ArmISA.py | 8 | ||||
| -rw-r--r-- | src/arch/arm/isa.cc | 3 | ||||
| -rw-r--r-- | src/arch/arm/isa.hh | 6 | ||||
| -rw-r--r-- | src/arch/arm/isa/formats/aarch64.isa | 14 | ||||
| -rw-r--r-- | src/arch/arm/isa/formats/misc.isa | 20 | ||||
| -rw-r--r-- | src/arch/arm/miscregs.cc | 3 |
6 files changed, 48 insertions, 6 deletions
diff --git a/src/arch/arm/ArmISA.py b/src/arch/arm/ArmISA.py index 7956570bd..78dd04330 100644 --- a/src/arch/arm/ArmISA.py +++ b/src/arch/arm/ArmISA.py @@ -1,4 +1,4 @@ -# Copyright (c) 2012-2013, 2015-2016 ARM Limited +# Copyright (c) 2012-2013, 2015-2016, 2018 ARM Limited # All rights reserved. # # The license below extends only to copyright in the software and shall @@ -111,3 +111,9 @@ class ArmISA(SimObject): # Reserved for future expansion id_aa64mmfr1_el1 = Param.UInt64(0x0000000000000000, "AArch64 Memory Model Feature Register 1") + + # Any access (read/write) to an unimplemented + # Implementation Defined registers is not causing an Undefined Instruction. + # It is rather executed as a NOP. + impdef_nop = Param.Bool(False, + "Any access to a MISCREG_IMPDEF_UNIMPL register is executed as NOP") diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index 296f8eb4a..a4e9c7975 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -61,7 +61,8 @@ ISA::ISA(Params *p) system(NULL), _decoderFlavour(p->decoderFlavour), _vecRegRenameMode(p->vecRegRenameMode), - pmu(p->pmu) + pmu(p->pmu), + impdefAsNop(p->impdef_nop) { miscRegs[MISCREG_SCTLR_RST] = 0; diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh index c8ae5c22d..9158b62aa 100644 --- a/src/arch/arm/isa.hh +++ b/src/arch/arm/isa.hh @@ -90,6 +90,12 @@ namespace ArmISA bool haveLargeAsid64; uint8_t physAddrRange64; + /** + * If true, accesses to IMPLEMENTATION DEFINED registers are treated + * as NOP hence not causing UNDEFINED INSTRUCTION. + */ + bool impdefAsNop; + /** MiscReg metadata **/ struct MiscRegLUTEntry { uint32_t lower; // Lower half mapped to this register diff --git a/src/arch/arm/isa/formats/aarch64.isa b/src/arch/arm/isa/formats/aarch64.isa index 00bd0770f..722cd7415 100644 --- a/src/arch/arm/isa/formats/aarch64.isa +++ b/src/arch/arm/isa/formats/aarch64.isa @@ -377,6 +377,20 @@ namespace Aarch64 return new FailUnimplemented(read ? "mrs" : "msr", machInst, full_mnemonic); + } else if (miscReg == MISCREG_IMPDEF_UNIMPL) { + auto full_mnemonic = + csprintf("%s op0:%d op1:%d crn:%d crm:%d op2:%d", + read ? "mrs" : "msr", + op0, op1, crn, crm, op2); + + if (miscRegInfo[miscReg][MISCREG_WARN_NOT_FAIL]) { + return new WarnUnimplemented(read ? "mrs" : "msr", + machInst, full_mnemonic + " treated as NOP"); + } else { + return new FailUnimplemented(read ? "mrs" : "msr", + machInst, full_mnemonic); + } + } else if (miscRegInfo[miscReg][MISCREG_IMPLEMENTED]) { if (miscReg == MISCREG_NZCV) { if (read) diff --git a/src/arch/arm/isa/formats/misc.isa b/src/arch/arm/isa/formats/misc.isa index 4f1960b95..739741786 100644 --- a/src/arch/arm/isa/formats/misc.isa +++ b/src/arch/arm/isa/formats/misc.isa @@ -220,10 +220,22 @@ let {{ csprintf("miscreg crn:%d opc1:%d crm:%d opc2:%d %s unknown", crn, opc1, crm, opc2, isRead ? "read" : "write")); case MISCREG_IMPDEF_UNIMPL: - return new McrMrcImplDefined( - isRead ? "mrc implementation defined" : - "mcr implementation defined", - machInst, iss, MISCREG_IMPDEF_UNIMPL); + + if (miscRegInfo[miscReg][MISCREG_WARN_NOT_FAIL]) { + auto mnemonic = + csprintf("miscreg crn:%d opc1:%d crm:%d opc2:%d %s", + crn, opc1, crm, opc2, isRead ? "read" : "write"); + + return new WarnUnimplemented( + isRead ? "mrc implementation defined" : + "mcr implementation defined", + machInst, mnemonic + " treated as NOP"); + } else { + return new McrMrcImplDefined( + isRead ? "mrc implementation defined" : + "mcr implementation defined", + machInst, iss, MISCREG_IMPDEF_UNIMPL); + } case MISCREG_CP15ISB: return new Isb(machInst, iss); case MISCREG_CP15DSB: diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc index 31b3580be..8dd56c791 100644 --- a/src/arch/arm/miscregs.cc +++ b/src/arch/arm/miscregs.cc @@ -4008,6 +4008,9 @@ ISA::initializeMiscRegMetadata() .unimplemented() .warnNotFail(); InitReg(MISCREG_UNKNOWN); + InitReg(MISCREG_IMPDEF_UNIMPL) + .unimplemented() + .warnNotFail(impdefAsNop); // Register mappings for some unimplemented registers: // ESR_EL1 -> DFSR |